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P54B
Technical Manual
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GE P4A, P54B, P54E, P54C Technical Manual

GE Energy Connections Grid Solutions
MiCOM P40 Agile
P54A, P54B, P54C, P54E
Technical Manual Single Br
eaker Multi-End Current Differential IED (Non Distance)
Hardware Version: M,P Software Version: 01 Publication Reference: P54xMED-TM-EN-1
Contents
Chapter 1 Introduction 1
1 Chapter Overview 3 2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
2.4 Compliance 5
3 Product Scope 6
3.1 Ordering Options 6
4 Features and Functions 7
4.1 Current Differential Protection Functions 7
4.2 Protection Functions 7
4.3 Control Functions 7
4.4 Measurement Functions 8
4.5 Communication Functions 8
5 Logic Diagrams 9 6 Functional Overview 11
Chapter 2 Safety Information 13
1 Chapter Overview 15 2 Health and Safety 16 3 Symbols 17 4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 22
5 Decommissioning and Disposal 23 6 Regulatory Compliance 24
6.1 EMC Compliance: 2014/30/EU 24
6.2 LVD Compliance: 2014/35/EU 24
6.3 R&TTE Compliance: 2014/53/EU 24
6.4 UL/CUL Compliance 24
6.5 ATEX Compliance: 2014/34/EU 24
Chapter 3 Hardware Design 27
1 Chapter Overview 29 2 Hardware Architecture 30
2.1 Coprocessor Hardware Architecture 30
3 Mechanical Implementation 32
3.1 Housing Variants 32
3.2 List of Boards 33
4 Front Panel 35
4.1 Front Panel 35
4.1.1 Front Panel Compartments 35
4.1.2 Keypad 36
Contents P54A/B/C/E
4.1.3 Front Serial Port (SK1) 36
4.1.4 Front Parallel Port (SK2) 37
4.1.5 Fixed Function LEDs 37
4.1.6 Function Keys 37
4.1.7 Programable LEDs 38
5 Rear Panel 39 6 Boards and Modules 41
6.1 PCBs 41
6.2 Subassemblies 41
6.3 Main Processor Board 42
6.4 Power Supply Board 43
6.4.1 Watchdog 45
6.4.2 Rear Serial Port 46
6.5 Input Module - 1 Transformer Board 47
6.5.1 Input Module Circuit Description 48
6.5.2 Transformer Board 49
6.5.3 Input Board 50
6.6 Standard Output Relay Board 51
6.7 IRIG-B Board 52
6.8 Fibre Optic Board 53
6.9 Rear Communication Board 54
6.10 Ethernet Board 54
6.11 Redundant Ethernet Board 56
6.12 Coprocessor Board 58
6.12.1 Current Differential Inputs 58
6.12.2 Coprocessor board with 1PPS input 58
Chapter 4 Software Design 61
1 Chapter Overview 63 2 Sofware Design Overview 64 3 System Level Software 65
3.1 Real Time Operating System 65
3.2 System Services Software 65
3.3 Self-Diagnostic Software 65
3.4 Startup Self-Testing 65
3.4.1 System Boot 65
3.4.2 System Level Software Initialisation 66
3.4.3 Platform Software Initialisation and Monitoring 66
3.5 Continuous Self-Testing 66
4 Platform Software 68
4.1 Record Logging 68
4.2 Settings Database 68
4.3 Interfaces 68
5 Protection and Control Functions 69
5.1 Acquisition of Samples 69
5.2 Frequency Tracking 69
5.3 Direct Use of Sample Values 69
5.4 System Level Software Initialisation 69
5.5 Fourier Signal Processing 70
5.6 Programmable Scheme Logic 71
5.7 Event Recording 71
5.8 Disturbance Recorder 72
5.9 Fault Locator 72
5.10 Function Key Interface 72
Chapter 5 Configuration 73
ii P54xMED-TM-EN-1
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1 Chapter Overview 75 2 Settings Application Software 76 3 Using the HMI Panel 77
3.1 Navigating the HMI Panel 78
3.2 Getting Started 78
3.3 Default Display 79
3.4 Default Display Navigation 80
3.5 Password Entry 81
3.6 Processing Alarms and Records 81
3.7 Menu Structure 82
3.8 Changing the Settings 83
3.9 Direct Access (The Hotkey menu) 84
3.9.1 Setting Group Selection Using Hotkeys 84
3.9.2 Control Inputs 84
3.9.3 Circuit Breaker Control 85
3.10 Function Keys 85
4 Line Parameters 87
4.1 Tripping Mode 87
4.1.1 CB Trip Conversion Logic Diagram 87
4.2 Residual Compensation 88
4.3 Mutual Compensation 88
5 Date and Time Configuration 90
5.1 Using an SNTP Signal 90
5.2 Using an IRIG-B Signal 90
5.3 Using an IEEE 1588 PTP Signal 90
5.4 Without a Timing Source Signal 91
5.5 Time Zone Compensation 91
5.6 Daylight Saving Time Compensation 92
6 Settings Group Selection 93
Chapter 6 Current Differential Protection 95
1 Chapter Overview 97 2 Current Differential Protection Principle 98
2.1 Numerical Current Differential Protection 98
2.2 Multi-ended Line Differential Protection 99
2.3 Basic Principles and Algorithm Design for Multi-ended Differential Protection 99
2.3.1 Fault Discrimination 99
2.3.2 Differential Characteristics 100
2.3.3 Basic Algorithm 102
2.3.4 Features of Multi-Ended Line Differential 102
2.3.5 Algorithm Overview 102
2.3.6 Communication Requirements 103
3 Charging Current Compensation 104 4 Synchronisation of Current Signals 106
4.1 Time Alignment using Ping-Pong Technique 106
4.2 Remote Terminal Time Alignment 107
4.3 Time Delay Interpolation 108
5 CT Saturation 109 6 CT Compensation 112 7 Current Differential Intertripping 113 8 Stub Bus Differential Protection 114 9 Application Notes 115
9.1 Multi-End Current Differential Protection 115
9.2 Feeder Topology 116
9.3 Configuring the Feeder Topology 116
9.4 Line Parameter Data 117
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9.5 Configuring the Protection Communications 118
9.6 Setting Up the Phase Differential Characteristic 119
9.7 Sensitivity Under Heavy Loads 119
9.8 Permissive Intertripping 121
9.9 CT Ratio Correction Setting Guidelines 121
9.10 Feeders with Small Tapped Loads 122
Chapter 7 Autoreclose 123
1 Chapter Overview 125 2 Introduction to Autoreclose 126 3 Autoreclose Implementation 127
3.1 Autoreclose Logic Inputs from External Sources 128
3.1.1 Circuit Breaker Healthy Input 128
3.1.2 Inhibit Autoreclose Input 128
3.1.3 Block Autoreclose Input 128
3.1.4 Reset Lockout Input 129
3.1.5 Pole Discrepancy Input 129
3.1.6 External Trip Indication 129
3.2 Autoreclose Logic Inputs 129
3.2.1 Trip Initiation Signals 129
3.2.2 Circuit Breaker Status Inputs 129
3.2.3 System Check Signals 129
3.3 Autoreclose Logic Outputs 129
3.4 Autoreclose Operating Sequence 130
3.4.1 AR Timing Sequence - Transient Fault 130
3.4.2 AR Timing Sequence - Evolving/Permanent Fault 130
3.4.3 AR Timing Sequence - Evolving/Permanent Fault Single-phase 131
4 Autoreclose System Map 132
4.1 Autoreclose System Map Diagrams 134
4.2 Autoreclose Internal Signals 139
4.3 Autoreclose DDB Signals 141
5 Logic Modules 147
5.1 Circuit Breaker Status Monitor 147
5.1.1 CB State Monitor Logic diagram 148
5.2 Circuit Breaker Open Logic 149
5.2.1 Circuit Breaker Open Logic Diagram 149
5.3 Circuit Breaker in Service Logic 149
5.3.1 Circuit Breaker in Service Logic Diagram 149
5.3.2 Autoreclose OK Logic Diagram 150
5.4 Autoreclose Enable 150
5.4.1 Autoreclose Enable Logic Diagram 150
5.5 Autoreclose Modes 150
5.5.1 Single-Phase and Three-Phase Autoreclose 151
5.5.2 Autoreclose Modes Enable Logic Diagram 152
5.6 AR Force Three-Phase Trip Logic 152
5.6.1 AR Force Three-Phase Trip Logic Diagram 152
5.7 Autoreclose Initiation Logic 152
5.7.1 Autoreclose Initiation Logic Diagram 154
5.7.2 Autoreclose Trip Test Logic Diagram 154
5.7.3 AR External Trip Initiation Logic Diagram 155
5.7.4 Protection Reoperation and Evolving Fault Logic Diagram 156
5.7.5 Fault Memory Logic Diagram 156
5.8 Autoreclose In Progress 156
5.8.1 Autoreclose In Progress Logic Diagram 157
5.9 Sequence Counter 157
5.9.1 Autoreclose Sequence Counter Logic Diagram 158
5.10 Autoreclose Cycle Selection 158
iv P54xMED-TM-EN-1
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5.10.1 Single-Phase Autoreclose Cycle Selection Logic Diagram 158
5.10.2 3-phase Autoreclose Cycle Selection 159
5.11 Dead Time Control 159
5.11.1 Dead Time Start Enable Logic Diagram 160
5.11.2 1-phase Dead Time Logic Diagram 161
5.11.3 3-phase Dead Time Logic Diagram 162
5.12 Circuit Breaker Autoclose 162
5.12.1 Circuit Breaker Autoclose Logic Diagram 163
5.13 Reclaim Time 163
5.13.1 Prepare Reclaim Initiation Logic Diagram 164
5.13.2 Reclaim Time Logic Diagram 164
5.13.3 Succesful Autoreclose Signals Logic Diagram 165
5.13.4 Autoreclose Reset Successful Indication Logic Diagram 165
5.14 CB Healthy and System Check Timers 165
5.14.1 CB Healthy and System Check Timers Logic Diagram 166
5.15 Autoreclose Shot Counters 166
5.15.1 Autoreclose Shot Counters Logic Diagram 167
5.16 Circuit Breaker Control 168
5.16.1 CB Control Logic Diagram 168
5.17 Circuit Breaker Trip Time Monitoring 169
5.17.1 CB Trip Time Monitoring Logic Diagram 169
5.18 Autoreclose Lockout 169
5.18.1 CB Lockout Logic Diagram 170
5.19 Reset Circuit Breaker Lockout 171
5.19.1 Reset CB Lockout Logic Diagram 171
5.20 Pole Discrepancy 172
5.20.1 Pole Discrepancy Logic Diagram 172
5.21 Circuit Breaker Trip Conversion 172
5.21.1 CB Trip Conversion Logic Diagram 173
5.22 Monitor Checks for CB Closure 173
5.22.1 Check Synchronisation Monitor for CB Closure 174
5.22.2 Voltage Monitor for CB Closure 175
5.23 Synchronisation Checks for CB Closure 175
5.23.1 Three-phase Autoreclose System Check Logic Diagram 177
5.23.2 CB Manual Close System Check Logic Diagram 178
6 Setting Guidelines 179
6.1 De-ionising Time Guidance 179
6.2 Dead Timer Setting Guidelines 179
6.2.1 Example Dead Time Calculation 179
6.3 Reclaim Time Setting Guidelines 180
Chapter 8 CB Fail Protection 181
1 Chapter Overview 183 2 Circuit Breaker Fail Protection 184 3 Circuit Breaker Fail Implementation 185
3.1 Circuit Breaker Fail Timers 185
3.2 Zero Crossing Detection 185
4 Circuit Breaker Fail Logic 187
4.1 Circuit Breaker Fail Logic - Part 1 187
4.2 Circuit Breaker Fail Logic - Part 2 188
4.3 Circuit Breaker Fail Logic - Part 3 189
4.4 Circuit Breaker Fail Logic - Part 4 190
5 Application Notes 191
5.1 Reset Mechanisms for CB Fail Timers 191
5.2 Setting Guidelines (CB fail Timer) 191
5.3 Setting Guidelines (Undercurrent) 192
P54xMED-TM-EN-1 v
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Chapter 9 Current Protection Functions 193
1 Chapter Overview 195 2 Phase Fault Overcurrent Protection 196
2.1 POC Implementation 196
2.2 Directional Element 196
2.3 POC Logic 198
3 Negative Sequence Overcurrent Protection 199
3.1 Negative Sequence Overcurrent Protection Implementation 199
3.2 Directional Element 199
3.3 NPSOC Logic 200
3.4 Application Notes 200
3.4.1 Setting Guidelines (Current Threshold) 200
3.4.2 Setting Guidelines (Time Delay) 200
3.4.3 Setting Guidelines (Directional element) 201
4 Earth Fault Protection 202
4.1 Earth Fault Protection Implementation 202
4.2 IDG Curve 202
4.3 Directional Element 203
4.3.1 Residual Voltage Polarisation 203
4.3.2 Negative Sequence Polarisation 204
4.4 Earth Fault Protection Logic 205
4.5 Application Notes 205
4.5.1 Residual Voltage Polarisation Setting Guidelines 205
4.5.2 Setting Guidelines (Directional Element) 205
5 Sensitive Earth Fault Protection 207
5.1 SEF Protection Implementation 207
5.2 EPATR B Curve 207
5.3 Sensitive Earth Fault Protection Logic 208
5.4 Application Notes 209
5.4.1 Insulated Systems 209
5.4.2 Setting Guidelines (Insulated Systems) 210
6 High Impedance REF 212
6.1 High Impedance REF Principle 212
7 Thermal Overload Protection 214
7.1 Single Time Constant Characteristic 214
7.2 Dual Time Constant Characteristic 214
7.3 Thermal Overload Protection Implementation 215
7.4 Thermal Overload Protection Logic 215
7.5 Application Notes 215
7.5.1 Setting Guidelines for Dual Time Constant Characteristic 215
7.5.2 Setting Guidelines for Single Time Constant Characteristic 217
8 Broken Conductor Protection 219
8.1 Broken Conductor Protection Implementation 219
8.2 Broken Conductor Protection Logic 219
8.3 Application Notes 219
8.3.1 Setting Guidelines 219
Chapter 10 Voltage Protection Functions 221
1 Chapter Overview 223 2 Undervoltage Protection 224
2.1 Undervoltage Protection Implementation 224
2.2 Undervoltage Protection Logic 225
2.3 Application Notes 226
2.3.1 Undervoltage Setting Guidelines 226
3 Overvoltage Protection 227
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3.1 Overvoltage Protection Implementation 227
3.2 Overvoltage Protection Logic 228
3.3 Application Notes 229
3.3.1 Overvoltage Setting Guidelines 229
4 Compensated Overvoltage 230 5 Residual Overvoltage Protection 231
5.1 Residual Overvoltage Protection Implementation 231
5.2 Residual Overvoltage Logic 232
5.3 Application Notes 232
5.3.1 Calculation for Solidly Earthed Systems 232
5.3.2 Calculation for Impedance Earthed Systems 233
5.3.3 Setting Guidelines 234
Chapter 11 Frequency Protection Functions 235
1 Chapter Overview 237 2 Frequency Protection 238
2.1 Underfrequency Protection 238
2.1.1 Underfrequency Protection Implementation 238
2.1.2 Underfrequency Protection logic 239
2.1.3 Application Notes 239
2.2 Overfrequency Protection 239
2.2.1 Overfrequency Protection Implementation 239
2.2.2 Overfrequency Protection logic 240
2.2.3 Application Notes 240
3 Independent R.O.C.O.F Protection 241
3.1 Indepenent R.O.C.O.F Protection Implementation 241
3.2 Independent R.O.C.O.F Protection Logic 241
Chapter 12 Monitoring and Control 243
1 Chapter Overview 245 2 Event Records 246
2.1 Event Types 246
2.1.1 Opto-input Events 247
2.1.2 Contact Events 247
2.1.3 Alarm Events 247
2.1.4 Fault Record Events 248
2.1.5 Maintenance Events 248
2.1.6 Protection Events 248
2.1.7 Security Events 249
2.1.8 Platform Events 249
3 Disturbance Recorder 250 4 Measurements 251
4.1 Measured Quantities 251
4.2 Measurement Setup 251
4.3 Fault Locator 251
4.4 Opto-input Time Stamping 251
5 CB Condition Monitoring 252
5.1 Broken Current Accumulator 253
5.2 CB Trip Counter 253
5.3 CB Operating Time Accumulator 254
5.4 Excessive Fault Frequency Counter 254
5.5 Reset Lockout Alarm 255
5.6 CB Condition Monitoring Logic 256
5.7 Reset Circuit Breaker Lockout 256
5.7.1 Reset CB Lockout Logic Diagram 257
5.8 Application Notes 257
P54xMED-TM-EN-1 vii
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5.8.1 Setting the Thresholds for the Total Broken Current 257
5.8.2 Setting the thresholds for the Number of Operations 258
5.8.3 Setting the thresholds for the Operating Time 258
5.8.4 Setting the Thresholds for Excesssive Fault Frequency 258
6 CB State Monitoring 259
6.1 CB State Monitor Logic diagram 260
7 Circuit Breaker Control 261
7.1 CB Control using the IED Menu 261
7.2 CB Control using the Hotkeys 262
7.3 CB Control using the Function Keys 262
7.4 CB Control using the Opto-inputs 263
7.5 Remote CB Control 263
7.6 CB Healthy Check 264
7.7 Synchronisation Check 264
7.8 CB Control AR Implications 264
7.9 CB Control Logic Diagram 265
8 Pole Dead Function 266
8.1 Pole Dead Logic 266
9 System Checks 267
9.1 System Checks Implementation 267
9.1.1 VT Connections 267
9.1.2 Voltage Monitoring 268
9.1.3 Check Synchronisation 268
9.1.4 Check Syncronisation Vector Diagram 268
9.2 Voltage Monitor for CB Closure 270
9.3 Check Synchronisation Monitor for CB Closure 271
9.4 System Check PSL 272
9.5 Application Notes 272
9.5.1 Predictive Closure of Circuit Breaker 272
9.5.2 Voltage and Phase Angle Correction 272
Chapter 13 Supervision 275
1 Chapter Overview 277 2 Current Differential Supervision 278
2.1 Current Differential Starter Supervision 278
2.1.1 Current Differential Starter Supervision Logic 280
2.1.2 Current Differential Start Logic 281
2.2 Switched Communication Path Supervision 281
2.3 Communications Asymmetry Supervision 282
3 Voltage Transformer Supervision 284
3.1 Loss of One or Two Phase Voltages 284
3.2 Loss of all Three Phase Voltages 284
3.3 Absence of all Three Phase Voltages on Line Energisation 284
3.4 VTS Implementation 285
3.5 VTS Logic 286
4 Current Transformer Supervision 289
4.1 Differential CTS 289
4.2 Differential CTS Logic 290
4.3 CTS Implementation 290
4.4 Standard CTS Logic 291
4.5 CTS Blocking 291
4.6 Application Notes 291
4.6.1 Setting Guidelines 291
4.6.2 Differential CTS Setting Guidelines 292
5 Trip Circuit Supervision 293
5.1 Trip Circuit Supervision Scheme 1 293
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5.1.1 Resistor Values 293
5.1.2 PSL for TCS Scheme 1 294
5.2 Trip Circuit Supervision Scheme 2 294
5.2.1 Resistor Values 295
5.2.2 PSL for TCS Scheme 2 295
5.3 Trip Circuit Supervision Scheme 3 295
5.3.1 Resistor Values 296
5.3.2 PSL for TCS Scheme 3 296
Chapter 14 Digital I/O and PSL Configuration 297
1 Chapter Overview 299 2 Configuring Digital Inputs and Outputs 300 3 Scheme Logic 301
3.1 PSL Editor 302
3.2 PSL Schemes 302
3.3 PSL Scheme Version Control 302
4 Configuring the Opto-Inputs 303 5 Assigning the Output Relays 304 6 Fixed Function LEDs 305
6.1 Trip LED Logic 305
7 Configuring Programmable LEDs 306 8 Function Keys 308 9 Control Inputs 309
Chapter 15 Fibre Teleprotection 311
1 Chapter Overview 313 2 Fibre Teleprotection Implementation 314
2.1 Communication Setup 314
2.2 Protection Communications Channel 315
2.3 1.1.1.Protection Comms Message Slot Allocation for Each Protection Scheme 315
2.4 Error Handling for Protection Communications 319
2.5 Fibre Teleprotection Scheme Terminal Addressing 320
2.6 Physical Connection 320
2.6.1 Direct Connection 321
2.6.2 Indirect Connection 321
3 Communications Supervision 322 4 IM64 Logic 323 5 Application Notes 325
5.1 Scheme Reconfiguration 325
5.2 Alarm Management 325
5.3 Alarm Logic 325
5.4 Two-ended Scheme Extended Supervision 326
5.5 Three-ended Scheme Extended Supervision 327
Chapter 16 Electrical Teleprotection 329
1 Chapter Overview 331 2 Introduction 332 3 Teleprotection Scheme Principles 333
3.1 Direct Tripping 333
3.2 Permissive Tripping 333
4 Implementation 334 5 Configuration 335 6 Connecting to Electrical InterMiCOM 337
6.1 Short Distance 337
P54xMED-TM-EN-1 ix
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6.2 Long Distance 337
7 Application Notes 338
Chapter 17 Communications 341
1 Chapter Overview 343 2 Communication Interfaces 344 3 Serial Communication 345
3.1 EIA(RS)232 Bus 345
3.2 EIA(RS)485 Bus 345
3.2.1 EIA(RS)485 Biasing Requirements 346
3.3 K-Bus 346
4 Standard Ethernet Communication 348
4.1 Hot-Standby Ethernet Failover 348
5 Redundant Ethernet Communication 349
5.1 Supported Protocols 349
5.2 Parallel Redundancy Protocol 350
5.3 High-Availability Seamless Redundancy (HSR) 351
5.3.1 HSR Multicast Topology 351
5.3.2 HSR Unicast Topology 352
5.3.3 HSR Application in the Substation 352
5.4 Rapid Spanning Tree Protocol 353
5.5 Self Healing Protocol 354
5.6 Dual Homing Protocol 355
5.7 Configuring IP Addresses 357
5.7.1 Configuring the IED IP Address 358
5.7.2 Configuring the REB IP Address 358
5.8 PRP/HSR Configurator 361
5.8.1 Connecting the IED to a PC 361
5.8.2 Installing the Configurator 362
5.8.3 Starting the Configurator 362
5.8.4 PRP/HSR Device Identification 363
5.8.5 Selecting the Device Mode 363
5.8.6 PRP/HSR IP Address Configuration 363
5.8.7 SNTP IP Address Configuration 363
5.8.8 Check for Connected Equipment 363
5.8.9 PRP Configuration 363
5.8.10 HSR Configuration 364
5.8.11 Filtering Database 364
5.8.12 End of Session 365
5.9 RSTP Configurator 365
5.9.1 Connecting the IED to a PC 365
5.9.2 Installing the Configurator 366
5.9.3 Starting the Configurator 366
5.9.4 RSTP Device Identification 366
5.9.5 RSTP IP Address Configuration 367
5.9.6 SNTP IP Address Configuration 367
5.9.7 Check for Connected Equipment 367
5.9.8 RSTP Configuration 367
5.9.9 End of Session 368
5.10 Switch Manager 368
5.10.1 Installation 369
5.10.2 Setup 370
5.10.3 Network Setup 370
5.10.4 Bandwidth Used 370
5.10.5 Reset Counters 370
5.10.6 Check for Connected Equipment 370
5.10.7 Mirroring Function 371
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5.10.8 Ports On/Off 371
5.10.9 VLAN 371
5.10.10 End of Session 371
6 Simple Network Management Protocol (SNMP) 372
6.1 SNMP Management Information Bases 372
6.2 Main Processor MIBS Structure 372
6.3 Redundant Ethernet Board MIB Structure 373
6.4 Accessing the MIB 377
6.5 Main Processor SNMP Configuration 377
7 Data Protocols 379
7.1 Courier 379
7.1.1 Physical Connection and Link Layer 379
7.1.2 Courier Database 380
7.1.3 Settings Categories 380
7.1.4 Setting Changes 380
7.1.5 Event Extraction 380
7.1.6 Disturbance Record Extraction 382
7.1.7 Programmable Scheme Logic Settings 382
7.1.8 Time Synchronisation 382
7.1.9 Courier Configuration 383
7.2 IEC 60870-5-103 384
7.2.1 Physical Connection and Link Layer 384
7.2.2 Initialisation 385
7.2.3 Time Synchronisation 385
7.2.4 Spontaneous Events 385
7.2.5 General Interrogation (GI) 385
7.2.6 Cyclic Measurements 385
7.2.7 Commands 385
7.2.8 Test Mode 386
7.2.9 Disturbance Records 386
7.2.10 Command/Monitor Blocking 386
7.2.11 IEC 60870-5-103 Configuration 386
7.3 DNP 3.0 387
7.3.1 Physical Connection and Link Layer 388
7.3.2 Object 1 Binary Inputs 388
7.3.3 Object 10 Binary Outputs 388
7.3.4 Object 20 Binary Counters 389
7.3.5 Object 30 Analogue Input 389
7.3.6 Object 40 Analogue Output 390
7.3.7 Object 50 Time Synchronisation 390
7.3.8 DNP3 Device Profile 390
7.3.9 DNP3 Configuration 398
7.4 IEC 61850 399
7.4.1 Benefits of IEC 61850 400
7.4.2 IEC 61850 Interoperability 400
7.4.3 The IEC 61850 Data Model 400
7.4.4 IEC 61850 in MiCOM IEDs 401
7.4.5 IEC 61850 Data Model Implementation 402
7.4.6 IEC 61850 Communication Services Implementation 402
7.4.7 IEC 61850 Peer-to-peer (GOOSE) communications 402
7.4.8 Mapping GOOSE Messages to Virtual Inputs 402
7.4.9 Ethernet Functionality 403
7.4.10 IEC 61850 Configuration 403
7.4.11 IEC 61850 Edition 2 404
8 Read Only Mode 408
8.1 IEC 60870-5-103 Protocol Blocking 408
8.2 Courier Protocol Blocking 408
8.3 IEC 61850 Protocol Blocking 409
8.4 Read-Only Settings 409
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8.5 Read-Only DDB Signals 409
9 Time Synchronisation 410
9.1 Demodulated IRIG-B 410
9.1.1 IRIG-B Implementation 411
9.2 SNTP 411
9.2.1 Loss of SNTP Server Signal Alarm 411
9.3 IEEE 1588 Precision time Protocol 411
9.3.1 Accuracy and Delay Calculation 411
9.3.2 PTP Domains 412
9.4 Time Synchronsiation using the Communication Protocols 412
Chapter 18 Cyber-Security 413
1 Overview 415 2 The Need for Cyber-Security 416 3 Standards 417
3.1 NERC Compliance 417
3.1.1 CIP 002 418
3.1.2 CIP 003 418
3.1.3 CIP 004 418
3.1.4 CIP 005 418
3.1.5 CIP 006 418
3.1.6 CIP 007 419
3.1.7 CIP 008 419
3.1.8 CIP 009 419
3.2 IEEE 1686-2007 419
4 Cyber-Security Implementation 421
4.1 NERC-Compliant Display 421
4.2 Four-level Access 422
4.2.1 Blank Passwords 423
4.2.2 Password Rules 423
4.2.3 Access Level DDBs 424
4.3 Enhanced Password Security 424
4.3.1 Password Strengthening 424
4.3.2 Password Validation 424
4.3.3 Password Blocking 425
4.4 Password Recovery 426
4.4.1 Password Recovery 426
4.4.2 Password Encryption 427
4.5 Disabling Physical Ports 427
4.6 Disabling Logical Ports 427
4.7 Security Events Management 428
4.8 Logging Out 430
Chapter 19 Installation 431
1 Chapter Overview 433 2 Handling the Goods 434
2.1 Receipt of the Goods 434
2.2 Unpacking the Goods 434
2.3 Storing the Goods 434
2.4 Dismantling the Goods 434
3 Mounting the Device 435
3.1 Flush Panel Mounting 435
3.2 Rack Mounting 436
4 Cables and Connectors 438
4.1 Terminal Blocks 438
4.2 Power Supply Connections 439
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4.3 Earth Connnection 439
4.4 Current Transformers 439
4.5 Voltage Transformer Connections 440
4.6 Watchdog Connections 440
4.7 EIA(RS)485 and K-Bus Connections 440
4.8 IRIG-B Connection 440
4.9 Opto-input Connections 440
4.10 Output Relay Connections 440
4.11 Ethernet Metallic Connections 441
4.12 Ethernet Fibre Connections 441
4.13 RS232 connection 441
4.14 Download/Monitor Port 441
4.15 GPS Fibre Connection 441
4.16 Fibre Communication Connections 441
5 Case Dimensions 442
5.1 Case Dimensions 40TE 442
5.2 Case Dimensions 60TE 443
5.3 Case Dimensions 80TE 444
Chapter 20 Commissioning Instructions 445
1 Chapter Overview 447 2 General Guidelines 448 3 Commissioning Test Menu 449
3.1 Opto I/P Status Cell (Opto-input Status) 449
3.2 Relay O/P Status Cell (Relay Output Status) 449
3.3 Test Port Status Cell 449
3.4 Monitor Bit 1 to 8 Cells 449
3.5 Test Mode Cell 450
3.6 Test Pattern Cell 450
3.7 Contact Test Cell 450
3.8 Test LEDs Cell 450
3.9 Test Autoreclose Cell 450
3.10 Static Test Mode 451
3.11 Loopback Mode 451
3.12 IM64 Test Pattern 452
3.13 IM64 Test Mode 452
3.14 Red and Green LED Status Cells 452
3.15 Using a Monitor Port Test Box 452
4 Commissioning Equipment 453
4.1 Recommended Commissioning Equipment 453
4.2 Essential Commissioning Equipment 453
4.3 Advisory Test Equipment 454
5 Product Checks 455
5.1 Product Checks with the IED De-energised 455
5.1.1 Visual Inspection 456
5.1.2 Current Transformer Shorting Contacts 456
5.1.3 Insulation 456
5.1.4 External Wiring 456
5.1.5 Watchdog Contacts 457
5.1.6 Power Supply 457
5.2 Product Checks with the IED Energised 457
5.2.1 Watchdog Contacts 457
5.2.2 Test LCD 458
5.2.3 Date and Time 458
5.2.4 Test LEDs 459
5.2.5 Test Alarm and Out-of-Service LEDs 459
P54xMED-TM-EN-1 xiii
Contents P54A/B/C/E
5.2.6 Test Trip LED 459
5.2.7 Test User-programmable LEDs 459
5.2.8 Test Opto-inputs 459
5.2.9 Test Output Relays 459
5.2.10 Test Serial Communication Port RP1 460
5.2.11 Test Serial Communication Port RP2 461
5.2.12 Test Ethernet Communication 462
5.3 Secondary Injection Tests 462
5.3.1 Test Current Inputs 462
5.3.2 Test Voltage Inputs 462
6 Electrical Intermicom Communication Loopback 464
6.1 Setting up the Loopback 464
6.2 Loopback Test 464
6.2.1 InterMicom Command Bits 465
6.2.2 InterMicom Channel Diagnostics 465
6.2.3 Simulating a Channel Failure 465
7 Intermicom 64 Communication 466
7.1 Checking the Interface 466
7.2 Setting up the Loopback 466
7.3 Loopback Test 467
8 Setting Checks 468
8.1 Apply Application-specific Settings 468
8.1.1 Transferring Settings from a Settings File 468
8.1.2 Entering settings using the HMI 468
9 IEC 61850 Edition 2 Testing 470
9.1 Using IEC 61850 Edition 2 Test Modes 470
9.1.1 IED Test Mode Behaviour 470
9.1.2 Sampled Value Test Mode Behaviour 470
9.2 Simulated Input Behaviour 471
9.3 Testing Examples 471
9.3.1 Test Procedure for Real Values 472
9.3.2 Test Procedure for Simulated Values - No Plant 472
9.3.3 Test Procedure for Simulated Values - With Plant 473
9.3.4 Contact Test 474
10 Current Differential Protection 475
10.1 Current Differential Bias Characteristic 475
10.1.1 Lower Slope 475
10.1.2 Upper Slope 476
10.2 Current Differential Operation and Contact Assignment 476
11 Protection Timing Checks 478
11.1 Dependency Conditions 478
11.2 Overcurrent Check 478
11.3 Connecting the Test Circuit 478
11.4 Performing the Test 479
11.5 Check the Operating Time 479
12 System Check and Check Synchronism 480
12.1 Check Synchronism Pass 480
12.2 Check Synchronism Fail 480
13 Check Trip and Autoreclose Cycle 481 14 End-to-End Communication Tests 482
14.1 Remove Local Loopbacks 482
14.1.1 Restoring Direct Fibre Connections 482
14.1.2 Restoring C37.94 Fibre Connections 483
14.2 Remove Remote Loopbacks 483
14.3 Verify Communication between IEDs 483
15 Onload Checks 484
15.1 Confirm Voltage Connections 484
15.2 Confirm Current Connections 484
xiv P54xMED-TM-EN-1
P54A/B/C/E Contents
15.3 Measure Capacitive Charging Current 485
15.4 Check Differential Current 485
15.5 Check Current Transformer Polarity 485
15.6 On-load Directional Test 485
16 Final Checks 486
Chapter 21 Maintenance and Troubleshooting 487
1 Chapter Overview 489 2 Maintenance 490
2.1 Maintenance Checks 490
2.1.1 Alarms 490
2.1.2 Opto-isolators 490
2.1.3 Output Relays 490
2.1.4 Measurement Accuracy 490
2.2 Replacing the Device 491
2.3 Repairing the Device 492
2.4 Removing the front panel 492
2.5 Replacing PCBs 493
2.5.1 Replacing the main processor board 493
2.5.2 Replacement of communications boards 494
2.5.3 Replacement of the input module 495
2.5.4 Replacement of the power supply board 495
2.5.5 Replacement of the I/O boards 496
2.6 Recalibration 496
2.7 Changing the battery 496
2.7.1 Post Modification Tests 497
2.7.2 Battery Disposal 497
2.8 Cleaning 497
3 Troubleshooting 498
3.1 Self-Diagnostic Software 498
3.2 Power-up Errors 498
3.3 Error Message or Code on Power-up 498
3.4 Out of Service LED on at power-up 499
3.5 Error Code during Operation 500
3.5.1 Backup Battery 500
3.6 Mal-operation during testing 500
3.6.1 Failure of Output Contacts 500
3.6.2 Failure of Opto-inputs 500
3.6.3 Incorrect Analogue Signals 501
3.7 Coprocessor board failures 501
3.7.1 Signalling failure alarm (on its own) 501
3.7.2 C diff failure alarm (on its own) 501
3.7.3 Signalling failure and C diff failure alarms together 501
3.7.4 Incompatible IED 501
3.7.5 Comms changed 501
3.7.6 IEEE C37.94 fail 502
3.8 PSL Editor Troubleshooting 502
3.8.1 Diagram Reconstruction 502
3.8.2 PSL Version Check 502
3.9 Repair and Modification Procedure 502
Chapter 22 Technical Specifications 505
1 Chapter Overview 507 2 Interfaces 508
2.1 Front Serial Port 508
2.2 Download/Monitor Port 508
P54xMED-TM-EN-1 xv
Contents P54A/B/C/E
2.3 Rear Serial Port 1 508
2.4 Fibre Rear Serial Port 1 508
2.5 Rear Serial Port 2 509
2.6 Optional Rear Serial Port (SK5) 509
2.7 IRIG-B (Demodulated) 509
2.8 IRIG-B (Modulated) 509
2.9 Rear Ethernet Port Copper 510
2.10 Rear Ethernet Port Fibre 510
2.10.1 100 Base FX Receiver Characteristics 510
2.10.2 100 Base FX Transmitter Characteristics 511
2.11 1 PPS Port 511
2.12 Fibre Teleprotection Interface 511
3 Protection Functions 512
3.1 Phase Current Differential Protection 512
3.2 Fibre Teleprotection Transfer Times 512
3.3 Autoreclose and Check Synychronism 512
3.4 Phase Overcurrent Protection 512
3.4.1 Phase Overcurrent Directional Parameters 513
3.5 Earth Fault Protection 513
3.5.1 Earth Fault Directional Parameters 513
3.6 Sensitive Earth Fault Protection 514
3.6.1 Sensitive Earth Fault Protection Directional Element 514
3.7 High Impedance Restricted Earth Fault Protection 514
3.8 Negative Sequence Overcurrent Protection 515
3.8.1 NPSOC Directional Parameters 515
3.9 Circuit Breaker Fail and Undercurrent Protection 515
3.10 Broken Conductor Protection 515
3.11 Thermal Overload Protection 515
4 Monitoring, Control and Supervision 516
4.1 Voltage Transformer Supervision 516
4.2 Standard Current Transformer Supervision 516
4.3 Differential Current Transformer Supervision 516
4.4 CB State and Condition Monitoring 516
4.5 PSL Timers 517
5 Measurements and Recording 518
5.1 General 518
5.2 Disturbance Records 518
5.3 Event, Fault and Maintenance Records 518
5.4 Fault Locator 518
6 Ratings 519
6.1 AC Measuring Inputs 519
6.2 Current Transformer Inputs 519
6.3 Voltage Transformer Inputs 519
6.4 Auxiliary Supply Voltage 519
6.5 Nominal Burden 520
6.6 Power Supply Interruption 520
6.7 Battery Backup 521
7 Input / Output Connections 522
7.1 Isolated Digital Inputs 522
7.1.1 Nominal Pickup and Reset Thresholds 522
7.2 Standard Output Contacts 522
7.3 High Break Output Contacts 523
7.4 Watchdog Contacts 523
8 Mechanical Specifications 524
8.1 Physical Parameters 524
8.2 Enclosure Protection 524
8.3 Mechanical Robustness 524
xvi P54xMED-TM-EN-1
P54A/B/C/E Contents
8.4 Transit Packaging Performance 524
9 Type Tests 525
9.1 Insulation 525
9.2 Creepage Distances and Clearances 525
9.3 High Voltage (Dielectric) Withstand 525
9.4 Impulse Voltage Withstand Test 525
10 Environmental Conditions 526
10.1 Ambient Temperature Range 526
10.2 Temperature Endurance Test 526
10.3 Ambient Humidity Range 526
10.4 Corrosive Environments 526
11 Electromagnetic Compatibility 527
11.1 1 MHz Burst High Frequency Disturbance Test 527
11.2 Damped Oscillatory Test 527
11.3 Immunity to Electrostatic Discharge 527
11.4 Electrical Fast Transient or Burst Requirements 527
11.5 Surge Withstand Capability 527
11.6 Surge Immunity Test 528
11.7 Immunity to Radiated Electromagnetic Energy 528
11.8 Radiated Immunity from Digital Communications 528
11.9 Radiated Immunity from Digital Radio Telephones 528
11.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 528
11.11 Magnetic Field Immunity 529
11.12 Conducted Emissions 529
11.13 Radiated Emissions 529
11.14 Power Frequency 529
12 Regulatory Compliance 530
12.1 EMC Compliance: 2014/30/EU 530
12.2 LVD Compliance: 2014/35/EU 530
12.3 R&TTE Compliance: 2014/53/EU 530
12.4 UL/CUL Compliance 530
12.5 ATEX Compliance: 2014/34/EU 530
Appendix A Ordering Options 533
Appendix B Settings and Signals 535
Appendix C Wiring Diagrams 537
P54xMED-TM-EN-1 xvii
Contents P54A/B/C/E
xviii P54xMED-TM-EN-1
Table of Figures
Figure 1: Key to logic diagrams 10 Figure 2: Functional Overview 11 Figure 3: Hardware architecture 30 Figure 4: Coprocessor hardware architecture 31 Figure 5: Exploded view of IED 32 Figure 6: Front panel (60TE) 35 Figure 7: Rear view of populated case 39 Figure 8: Terminal block types 40 Figure 9: Rear connection to terminal block 41 Figure 10: Main processor board 42 Figure 11: Power supply board 43 Figure 12: Power supply assembly 44 Figure 13: Power supply terminals 45 Figure 14: Watchdog contact terminals 46 Figure 15: Rear serial port terminals 47 Figure 16: Input module - 1 transformer board 47 Figure 17: Input module schematic 48 Figure 18: Transformer board 49 Figure 19: Input board 50 Figure 20: Standard output relay board - 8 contacts 51 Figure 21: IRIG-B board 52 Figure 22: Fibre optic board 53 Figure 23: Rear communication board 54 Figure 24: Ethernet board 54 Figure 25: Redundant Ethernet board 56 Figure 26: Fully populated Coprocessor board 58 Figure 27: Software Architecture 64 Figure 28: Frequency Response (indicative only) 71 Figure 29: Navigating the HMI 78 Figure 30: Default display navigation 80 Figure 31: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 87 Figure 32: Sample multi-ended system 100 Figure 33: Current differential discriminative criterion 101 Figure 34: Overall scheme designed for multi-ended differential protection 103 Figure 35: Two-ended transmission line 104 Figure 36: Ping-pong measurement for alignment of current signals 106 Figure 37: Snapshot of available data for processing at each terminal 108 Figure 38: CT saturation technique 109
Table of Figures P54A/B/C/E
Figure 39: Original current waveforms 110 Figure 40: Ipos and Ineg current waveforms 111 Figure 41: Internal external fault binary 111 Figure 42: CT Compensation 112 Figure 43: Permissive Intertripping example 113 Figure 44: Stub Bus protection 114 Figure 45: Six terminal, four junction topology and ring structure 115 Figure 46: Six terminal ring structure with channel allocation 115 Figure 47: Six terminal, four junction topology 116 Figure 48: Autoreclose sequence for a Transient Fault 130 Figure 49: Autoreclose sequence for an evolving or permanent fault 131 Figure 50: Autoreclose sequence for an evolving or permanent fault - single-phase operation 131 Figure 51: Key to logic diagrams 133 Figure 52: Autoreclose System Map - part 1 134 Figure 53: Autoreclose System Map - part 2 135 Figure 54: Autoreclose System Map - part 3 136 Figure 55: Autoreclose System Map - part 4 137 Figure 56: Autoreclose System Map - part 5 138 Figure 57: CB State Monitor logic diagram (Module 1) 148 Figure 58: Circuit Breaker Open logic diagram (Module 3) 149 Figure 59: CB In Service logic diagram (Module 4) 149 Figure 60: Autoreclose OK logic diagram (Module 8) 150 Figure 61: Autoreclose Enable logic diagram (Module 5) 150 Figure 62: Autoreclose Modes Enable logic diagram (Module 9) 152 Figure 63: Force Three-phase Trip logic diagram (Module 10) 152 Figure 64: Autoreclose Initiation logic diagram (Module 11) 154 Figure 65: Autoreclose Trip Test logic diagram (Module 12) 154 Figure 66: Autoreclose initiation by external trip or evolving conditions (Module 13) 155 Figure 67: Protection Reoperation and Evolving Fault logic diagram (Module 20) 156 Figure 68: Fault Memory logic diagram (Module 15) 156 Figure 69: Autoreclose In Progress logic diagram (Module 16) 157 Figure 70: Autoreclose Sequence Counter logic diagram (Module 18) 158 Figure 71: Single-phase Autoreclose Cycle Selection logic diagram (Module 19) 158 Figure 72: Three-phase Autoreclose Cycle Selection logic diagram (Module 21) 159 Figure 73: Dead time Start Enable logic diagram (Module 22) 160 Figure 74: Single-phase Dead Time logic diagram (Module 24) 161 Figure 75: Three-phase Dead Time logic diagram (Module 25) 162 Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32) 163 Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34) 164 Figure 78: Reclaim Time logic diagram (Module 35) 164
xx P54xMED-TM-EN-1
P54A/B/C/E Table of Figures
Figure 79: Successful Autoreclose Signals logic diagram (Module 36) 165 Figure 80: Autoreclose Reset Successful Indication logic diagram (Module 37) 165 Figure 81: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39) 166 Figure 82: Autoreclose Shot Counters logic diagram (Module 41) 167 Figure 83: CB Control logic diagram (Module 43) 168 Figure 84: Circuit Breaker Trip Time Monitoring logic diagram (Module 53) 169 Figure 85: AR Lockout Logic Diagram (Module 55) 170 Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57) 171 Figure 87: Pole Discrepancy Logic Diagram (Module 62) 172 Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63) 173 Figure 89: Check Synchronisation Monitor for CB closure (Module 60) 174 Figure 90: Voltage Monitor for CB Closure (Module 59) 175 Figure 91: Three-phase Autoreclose System Check Logic Diagram (Module 45) 177 Figure 92: CB Manual Close System Check Logic Diagram (Module 51) 178 Figure 93: Circuit Breaker Fail logic - part 1 187 Figure 94: Circuit Breaker Fail logic - part 2 188 Figure 95: Circuit Breaker Fail logic - part 3 189 Figure 96: Circuit Breaker Fail logic - part 4 190 Figure 97: CB Fail timing 192 Figure 98: Phase Overcurrent Protection logic diagram 198 Figure 99: Negative Phase Sequence Overcurrent Protection logic diagram 200 Figure 100: IDG Characteristic 203 Figure 101: Earth Fault Protection logic diagram 205 Figure 102: EPATR B characteristic shown for TMS = 1.0 208 Figure 103: Sensitive Earth Fault Protection logic diagram 208 Figure 104: Current distribution in an insulated system with C phase fault 209 Figure 105: Phasor diagrams for insulated system with C phase fault 210 Figure 106: Positioning of core balance current transformers 211 Figure 107: High Impedance REF principle 212 Figure 108: High Impedance REF Connection 213 Figure 109: Thermal overload protection logic diagram 215 Figure 110: Spreadsheet calculation for dual time constant thermal characteristic 216 Figure 111: Dual time constant thermal characteristic 216 Figure 112: Broken conductor logic 219 Figure 113: Undervoltage - single and three phase tripping mode (single stage) 225 Figure 114: Overvoltage - single and three phase tripping mode (single stage) 228 Figure 115: Residual Overvoltage logic 232 Figure 116: Residual voltage for a solidly earthed system 233 Figure 117: Residual voltage for an impedance earthed system 234 Figure 118: Underfrequency logic (single stage) 239
P54xMED-TM-EN-1 xxi
Table of Figures P54A/B/C/E
Figure 119: Overfrequency logic (single stage) 240 Figure 120: Rate of change of frequency logic (single stage) 241 Figure 121: Fault recorder stop conditions 248 Figure 122: Broken Current Accumulator logic diagram 253 Figure 123: CB Trip Counter logic diagram 253 Figure 124: Operating Time Accumulator 254 Figure 125: Excessive Fault Frequency logic diagram 254 Figure 126: Reset Lockout Alarm logic diagram 255 Figure 127: CB Condition Monitoring logic diagram 256 Figure 128: Reset Circuit Breaker Lockout Logic Diagram (Module 57) 257 Figure 129: CB State Monitor logic diagram (Module 1) 260 Figure 130: Hotkey menu navigation 262 Figure 131: Default function key PSL 263 Figure 132: Remote Control of Circuit Breaker 264 Figure 133: CB Control logic diagram (Module 43) 265 Figure 134: Pole Dead logic 266 Figure 135: Check Synchronisation vector diagram 269 Figure 136: Voltage Monitor for CB Closure (Module 59) 270 Figure 137: Check Synchronisation Monitor for CB closure (Module 60) 271 Figure 138: System Check PSL 272 Figure 139: Current Differential Starter Supervision Logic 280 Figure 140: Current Differential function Start logic 281 Figure 141: Switched Communication Path supervision 282 Figure 142: Communication Asymmetry Supervision 283 Figure 143: VTS logic 288 Figure 144: Differential CTS 290 Figure 145: Standard CTS 291 Figure 146: TCS Scheme 1 293 Figure 147: PSL for TCS Scheme 1 294 Figure 148: TCS Scheme 2 295 Figure 149: PSL for TCS Scheme 2 295 Figure 150: TCS Scheme 3 296 Figure 151: PSL for TCS Scheme 3 296 Figure 152: Scheme Logic Interfaces 301 Figure 153: Trip LED logic 305 Figure 154: Fibre teleprotection connections for a six-terminal scheme 315 Figure 155: Two terminal single channel scheme 315 Figure 156: Two terminal dual channel scheme 316 Figure 157: Three terminal scheme 316 Figure 158: Four terminal scheme 317
xxii P54xMED-TM-EN-1
P54A/B/C/E Table of Figures
Figure 159: Five terminal scheme 318 Figure 160: Six terminal scheme 319 Figure 161: IM64 channel fail and scheme fail logic 323 Figure 162: IM64 general alarm signals logic 323 Figure 163: IM64 communications mode and IEEE C37.94 alarm signals 324 Figure 164: IM64 two-terminal scheme extended supervision 327 Figure 165: IM64 three-terminal scheme extended supervision 327 Figure 166: Example assignment of InterMiCOM signals within the PSL 336 Figure 167: Direct connection 337 Figure 168: Indirect connection using modems 337 Figure 169: RS485 biasing circuit 346 Figure 170: Remote communication using K-Bus 347 Figure 171: IED attached to separate LANs 350 Figure 172: HSR multicast topology 351 Figure 173: HSR unicast topology 352 Figure 174: HSR application in the substation 353 Figure 175: IED attached to redundant Ethernet star or ring circuit 353 Figure 176: IED, bay computer and Ethernet switch with self healing ring facilities 354 Figure 177: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches 354 Figure 178: Redundant Ethernet ring architecture with IED, bay computer and Ethernet switches
after failur
e
355
Figure 179: Dual homing mechanism 356 Figure 180: Application of Dual Homing Star at substation level 357 Figure 181: IED and REB IP address configuration 358 Figure 182: Connection using (a) an Ethernet switch and (b) a media converter 362 Figure 183: Connection using (a) an Ethernet switch and (b) a media converter 366 Figure 184: Control input behaviour 389 Figure 185: Data model layers in IEC61850 401 Figure 186: Edition 2 system - backward compatibility 405 Figure 187: Edition 1 system - forward compatibility issues 405 Figure 188: Example of Standby IED 406 Figure 189: Standby IED Activation Process 407 Figure 190: GPS Satellite timing signal 410 Figure 191: Timing error using ring or line topology 412 Figure 192: Default display navigation 422 Figure 193: Location of battery isolation strip 435 Figure 194: Rack mounting of products 436 Figure 195: Terminal block types 438 Figure 196: 40TE case dimensions 442 Figure 197: 60TE case dimensions 443
P54xMED-TM-EN-1 xxiii
Table of Figures P54A/B/C/E
Figure 198: 80TE case dimensions 444 Figure 199: RP1 physical connection 460 Figure 200: Remote communication using K-bus 461 Figure 201: InterMicom loopback testing 464 Figure 202: Simulated input behaviour 471 Figure 203: Test example 1 472 Figure 204: Test example 2 473 Figure 205: Test example 3 474 Figure 206: Current Differential Bias Characteristics 475 Figure 207: Possible terminal block types 492 Figure 208: Front panel assembly 494
xxiv P54xMED-TM-EN-1
CHAPTER 1

INTRODUCTION

Chapter 1 - Introduction P54A/B/C/E
2 P54xMED-TM-EN-1
P54A/B/C/E Chapter 1 - Introduction

1 CHAPTER OVERVIEW

This chapter provides some general information about the technical manual and an introduction to the device(s) described in this technical manual.
This chapter contains the following sections: Chapter Overview 3
eword 4
For Product Scope 6 Features and Functions 7 Logic Diagrams 9 Functional Overview 11
P54xMED-TM-EN-1 3
Chapter 1 - Introduction P54A/B/C/E

2 FOREWORD

This technical manual provides a functional and technical description of General Electric's P54A, P54B, P54C, P54E,
ell as a comprehensive set of instructions for using the device. The level at which this manual is written
as w assumes that you are already familiar with protection engineering and have experience in this discipline. The description of principles and theory is limited to that which is necessary to understand the product. For further details on general protection engineering theory, we refer you to Alstom's publication NPAG, which is available online or from our contact centre.
We have attempted to make this manual as accurate, comprehensive and user-friendly as possible. However we cannot guarantee that it is free from errors. Nor can we state that it cannot be improved. We would therefore be very pleased to hear from you if you discover any errors, or have any suggestions for improvement. Our policy is to provide the information necessary to help you safely specify, engineer, install, commission, maintain, and eventually dispose of this product. We consider that this manual provides the necessary information, but if you consider that more details are needed, please contact us.
All feedback should be sent to our contact centre via the following URL:
www.gegridsolutions.com/contact

2.1 TARGET AUDIENCE

This manual is aimed towards all professionals charged with installing, commissioning, maintaining, tr
oubleshooting, or operating any of the products within the specified product range. This includes installation and
commissioning personnel as well as engineers who will be responsible for operating the product. The level at which this manual is written assumes that installation and commissioning engineers have knowledge
of handling electronic equipment. Also, system and protection engineers have a thorough knowledge of protection systems and associated equipment.

2.2 TYPOGRAPHICAL CONVENTIONS

The following typographical conventions are used throughout this manual.
● The names for special k
For example: ENTER
● When describing software applications, menu items, buttons, labels etc as they appear on the screen are
written in bold type. For example: Select Save from the file menu.
● Filenames and paths use the courier font
For example: Example\File.text
● Special terminology is written with leading capitals
For example: Sensitive Earth Fault
● If reference is made to the IED's internal settings and signals database, the menu group heading (column)
text is written in upper case italics For example: The SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the setting cells and DDB signals are
written in bold italics For example: The Language cell in the SYSTEM DATA column
● If reference is made to the IED's internal settings and signals database, the value of a cell's content is
written in the Courier font For example: The Language cell in the SYSTEM DATA column contains the value English
eys appear in capital letters.
4 P54xMED-TM-EN-1
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