GALAX GTX 1060 Schematics
A B
smd.db-x7.ru
D
HGFEC
P45U V10
GP106 8GB/4GB GDDR5, 256b, 256Mx32/128MX32
1
Tall DVI-D + HDMI+ DP
TABLE OF CONTENTS
Page
2
3
4
Description
Table of Contents
1
Block Biagram
2
PCI Express
3
GPU FB_AB
4
MEMORY: FBA[31:0]
5
MEMORY: FBA[63:32]
6
MEMORY: FBB[31:0]
7
MEMORY: FBB[63:32]
8
9
MEM FB_AB PWR
10
GPU FB_CD
MEMORY: FBC[31:0]
11
MEMORY: FBC[63:32]
12
13
MEMORY: FBD[31:0]
MEMORY: FBD[63:32]
14
MEM FB_CD PWR
15
GPU PWR & GND
16
GPU Decoupling
17
IFPAB DVI-D-DL
18
IFPE UNUSED
19
IFPF UNUSED
20
IFPC HDMI
21
IFPD DP
22
MIOA/B Interface and Frame Lock
23
MISC1: Fan, Thermal, JTAG, GPIO,STEREO
24
MISC2: ROM, XTAL,STRAPS
25
Page
Description
PS: 1V8_PLL, 1V8_AON
26
27
PS: 5V, PEX_VDD
PS: NV3V3, NV12V
28
29
PS: FBVDD
30
PS: NVVDD Controller
31
PS: NVVDD Phase 1-4
32
PS:Blank page
33
PS: Input, Filtering, and Monitoring
PS: 12V Power Steering,PSI Control & LED
34
35
PS: Shut Down and Sequencing
36
PS: GC6 MISC
MECH_SN EEPRON
37
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
A B D F H
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
Table of Contents
EC
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Table of Contents
Table of Contents
Table of Contents
Design By:
Design By:
P45U
P45U
P45U
Design By:
Carson V10
Carson V10
Carson V10
1 37Thursday, December 28, 2017
1 37Thursday, December 28, 2017
1 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page2: Block Diagram
1
1
Power Supply:
Power Supply
NVVDD-PH3_BAL
3-WAY SLI
2
FRAME LOCK
2-WAY SLI
DP
D
LO
MEM DMEM
HI
MEM
C
Power Supply
NVVDD-PH3
Power Supply
NVVDD-PH2
Power Supply
NVVDD-PH1
2
EXT_12V 2x3PWR 1
LO
QD:DP
HDMI/
MEM
3
C
3
HI
POWER SUPPLY
GP104/GP106
MEM
DPDP
B
LO
Power Supply
FBVDD/Q-PH1
Power Supply
5V Linear
PEX_12V Finger
MEM
B
PEX_VDD
HI
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
DVI-I
MEM A AMEM
HI
C E
LO
ASSEMBLY
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
Block Biagram
Open_Vreg option
Fan
FDBA
3V3 Finger
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
G
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Block Biagram
Block Biagram
Block Biagram
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
2 37Thursday, December 28, 2017
2 37Thursday, December 28, 2017
2 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page3: PCI Express
12V
CN1
CON_X16
COMMON
@electro_mechanic.con_pci_express(sym_1):page3_i662
B1
+12V
B2
+12V
A2
+12V
A3
+12V
B3
+12V/RSVD
B8
+3V3
A9
+3V3
A10
+3V3
B10
+3V3AUX
A1
PRSNT1
B17
PRSNT2
B12
RSVD
B4
GND
A4
GND
B7
GND
A12
GND
B13
GND
A15
GND
B16
GND
B18
GND
A18
GND
PRSNT2
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PRSNT2
RSVD
RSVD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
PCIE_16X
END OF X1
END OF X4
END OF X8
END OF X16
B31
A19
B30
A32
A20
B21
B22
A23
A24
B25
B26
A27
A28
B29
A31
B32
B48
A33
A34
B35
B36
A37
A38
B39
B40
A41
A42
B43
B44
A45
A46
B47
B49
A49
B81
A50
B82
A51
B52
B53
A54
A55
B56
B57
A58
A59
B60
B61
A62
A63
B64
B65
A66
A67
B68
B69
A70
A71
B72
B73
A74
A75
B76
B77
A78
A79
B80
A82
TRST* JTAG1
TCLK JTAG2
TDI JTAG3
TDO JTAG4
TMS JTAG5
SMCLK
SMDAT
WAKE
PERST
REFCLK
REFCLK
PERP0
PERN0
PETP0
PETN0
PERP1
PERN1
PETP1
PETN1
PERP2
PERN2
PETP2
PETN2
PERP3
PERN3
PETP3
PETN3
PERP4
PERN4
PETP4
PETN4
PERP5
PERN5
PETP5
PETN5
PERP6
PERN6
PETP6
PETN6
PERP7
PERN7
PETP7
PETN7
PERP8
PERN8
PETP8
PETN8
PERP9
PERN9
PETP9
PETN9
PERP10
PERN10
PETP10
PETN10
PERP11
PERN11
PETP11
PETN11
PERP12
PERN12
PETP12
PETN12
PERP13
PERN13
PETP13
PETN13
PERP14
PERN14
PETP14
PETN14
PERP15
PERN15
PETP15
PETN15
R767
0ohm
0402
COMMON
B9
A5
A6
PEX_TDO
A7
A8
PEX_SMCLK
B5
PEX_SMDAT
B6
PEX_WAKE*
B11
PEX_RST* PEX_RST_BUF*
A11
PEX_REFCLK
A13
PEX_REFCLK*
A14
PEX_TXX0
A16
PEX_TXX0*
A17
PEX_RX0
B14
PEX_RX0*
B15
PEX_TXX1
A21
PEX_TXX1*
A22
PEX_RX1
B19
PEX_RX1*
B20
PEX_TXX2
A25
PEX_TXX2*
A26
PEX_RX2
B23
PEX_RX2*
B24
PEX_TXX3
A29
PEX_TXX3*
A30
PEX_RX3
B27
PEX_RX3*
B28
PEX_TXX4
A35
PEX_TXX4*
A36
PEX_RX4
B33
PEX_RX4*
B34
PEX_TXX5
A39
PEX_TXX5*
A40
PEX_RX5
B37
PEX_RX5*
B38
PEX_TXX6
A43
PEX_TXX6*
A44
PEX_RX6
B41
PEX_RX6*
B42
PEX_TXX7
A47
PEX_TXX7*
A48
PEX_RX7
B45
PEX_RX7*
B46
PEX_TXX8
A52
PEX_TXX8*
A53
PEX_RX8
B50
PEX_RX8*
B51
PEX_TXX9
A56
PEX_TXX9*
A57
PEX_RX9
B54
PEX_RX9*
B55
PEX_TXX10
A60
PEX_TXX10*
A61
PEX_RX10
B58
PEX_RX10*
B59
PEX_TXX11
A64
PEX_TXX11*
A65
PEX_RX11
B62
PEX_RX11*
B63
PEX_TXX12
A68
PEX_TXX12*
A69
PEX_RX12
B66
PEX_RX12*
B67
PEX_TXX13
A72
PEX_TXX13*
A73
PEX_RX13
B70
PEX_RX13*
B71
PEX_TXX14
A76
PEX_TXX14*
A77
PEX_RX14
B74
PEX_RX14*
B75
PEX_TXX15
A80
PEX_TXX15*
A81
PEX_RX15
B78
PEX_RX15*
B79
0.05 ohm
3V3 3V3
R754
47k
5 %
0402
COMMON
OUT
OUT
PEX_REFCLK
PEX_REFCLK
PEX_RX0
PEX_RX0
PEX_RX1
PEX_RX1
PEX_RX2
PEX_RX2
PEX_RX3
PEX_RX3
PEX_RX4
PEX_RX4
PEX_RX5
PEX_RX5
PEX_RX6
PEX_RX6
PEX_RX7
PEX_RX7
PEX_RX8
PEX_RX8
PEX_RX9
PEX_RX9
PEX_RX10
PEX_RX10
PEX_RX11
PEX_RX11
PEX_RX12
PEX_RX12
PEX_RX13
PEX_RX13
PEX_RX14
PEX_RX14
PEX_RX15
PEX_RX15
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
C E
{36}
{36}
C970
0.1uF
16V
10%
X7R
0402
COMMON
C978
4.7uF
16V
10%
X5R
0603
COMMON
GPU_EVENT_CONN_R
GC6_FB_EN_CONN_A32
C979
10uF
16V
20%
1
STUFF FOR
TESLA ONLY
UNSTUFF FOR
2
DT/QUADRO
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
X6S
0805LP
COMMON
3V3
C88
4.7uF
6.3V
20%
X5R
0603
COMMON
GND
BI
R892
0ohm/NC
0.05 ohm
0402
DNI
OUT
POWER_BRAKE*
R894
0ohm/NC
0.05 ohm
0402
DNI
OUT
IN
GND
SNN_3V3AUX
SNN_PE_PRSNT2_A
PEX_CONN_B12
GND
SNN_PE_PRSNT2_B
RSVD4_POWER_BRAKE
SNN_PE_PRSNT2_C
GND
SNN_PE_RSVD6
GND
PEX_PRSNT*
SNN_PE_RSVD7
SNN_PE_RSVD8
GND
C980
0.1uF
16V
10%
X7R
0402
COMMON
PEX_TCLK
R755
47k
5 %
0402
COMMON
C946 0.22uF
6.3V 10%
X5R
C0402
C944 0.22uF
6.3V 10%
X5R
C0402
C942
0.22uF
6.3V
X5R
C0402
C939
0.22uF
6.3V 10%
X5R
C0402
C937
0.22uF
6.3V 10%
X5R
C0402
C935
0.22uF
6.3V
X5R
C0402
C932
0.22uF
X5R
C0402
C922
X5R
C0402
C919
0.22uF
6.3V 10%
X5R
C0402
C900
0.22uF
6.3V
X5R
C0402
C913
0.22uF
X5R
C0402
C902
0.22uF
6.3V
X5R
C0402
C898 0.22uF
6.3V
X5R
C0402
C895
0.22uF
6.3V
X5R
C0402
C891 0.22uF
6.3V
X5R
C0402
C887
0.22uF
6.3V
X5R
C0402
0.22uF
10%
10%
10%
10%
10%
10%
10%
10%6.3V
10%6.3V
10%
10%6.3V
OUT
BI
C945
X5R
C943
X5R
C940
X5R
C938 0.22uF
X5R
C936 0.22uF
X5R
C934
X5R
C923 0.22uF
X5R
C921
X5R
C918 0.22uF
X5R
C896
X5R
C912 0.22uF
X5R
C901
X5R
C897
X5R
C892 0.22uF
X5R
C888
X5R
C886 0.22uF
X5R
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
C0402
BI
0.22uF
6.3V
0.22uF
6.3V 10%
0.22uF
6.3V
6.3V 10%
6.3V
0.22uF
6.3V 10%
0.22uF
6.3V
0.22uF
6.3V
6.3V 10%
0.22uF
6.3V
0.22uF
6.3V
6.3V 10%
0.22uF
6.3V 10%
ASSEMBLY
PAGE DETAIL
10%
10%
10%
10%6.3V
10%
10%6.3V
10%
10%
10%
10%6.3V
{36}
{36}
PEX_TX0
PEX_TX0*
PEX_TX1
PEX_TX1*
PEX_TX2
PEX_TX2*
PEX_TX3
PEX_TX3*
PEX_TX4
PEX_TX4*
PEX_TX5
PEX_TX5*
PEX_TX6
PEX_TX6*
PEX_TX7
PEX_TX7*
PEX_TX8
PEX_TX8*
PEX_TX9
PEX_TX9*
PEX_TX10
PEX_TX10*
PEX_TX11
PEX_TX11*
PEX_TX12
PEX_TX12*
PEX_TX13
PEX_TX13*
PEX_TX14
PEX_TX14*
PEX_TX15
PEX_TX15*
{36}
D
3
Q_FET_N_ENH/NC
R756
IN
IN
<ASSEMBLY_DESCRIPTION>
PCI Express
3.3V
NV3V3
5
G
Q524B
@discrete.q_fet_n_enh(sym_7):page3_i968
SOT363
COMMON
S
4
0ohm/NC
DNI0402
0.05 ohm
GPU_PEX_CLKREQ*
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
PEXGEN3_SIGNALS
NV3V3
G
D
6
Q_FET_N_ENH/NC
R758
0402
0.05 ohm
BK26
BL26
BM26
BM27
BG26
BH26
BL27
BK27
BF26
BE26
BK29
BL29
BF27
BG27
BM29
BM30
BG29
BH29
BL30
BK30
BF29
BE29
BK32
BL32
BF30
BG30
BM32
BM33
BG32
BH32
BL33
BK33
BF32
BE32
BK35
BL35
BF33
BG33
BM35
BM36
BG35
BH35
BL36
BK36
BF35
BE35
BK38
BL38
BF36
BG36
BM38
BM39
BG38
BH38
BL39
BK39
BF38
BE38
BK41
BL41
BF39
BG39
BM41
BM42
BH41
BG41
BL42
BK42
3.3V
2
Q524A
@discrete.q_fet_n_enh(sym_7):page3_i970
SOT363
COMMON
S
1
0ohm/NC
DNI
G1A
BGA2152
COMMON
1/23 PCI_EXPRESS
PEX_RST
PEX_CLKREQ
PEX_REFCLK
PEX_REFCLK
PEX_TX0
PEX_TX0
PEX_RX0
PEX_RX0
PEX_TX1
PEX_TX1
PEX_RX1
PEX_RX1
PEX_TX2
PEX_TX2
PEX_RX2
PEX_RX2
PEX_TX3
PEX_TX3
PEX_RX3
PEX_RX3
PEX_TX4
PEX_TX4
PEX_RX4
PEX_RX4
PEX_TX5
PEX_TX5
PEX_RX5
PEX_RX5
PEX_TX6
PEX_TX6
PEX_RX6
PEX_RX6
PEX_TX7
PEX_TX7
PEX_RX7
PEX_RX7
PEX_TX8
PEX_TX8
PEX_RX8
PEX_RX8
PEX_TX9
PEX_TX9
PEX_RX9
PEX_RX9
PEX_TX10
PEX_TX10
PEX_RX10
PEX_RX10
PEX_TX11
PEX_TX11
PEX_RX11
PEX_RX11
PEX_TX12
PEX_TX12
PEX_RX12
PEX_RX12
PEX_TX13
PEX_TX13
PEX_RX13
PEX_RX13
PEX_TX14
PEX_TX14
PEX_RX14
PEX_RX14
PEX_TX15
PEX_TX15
PEX_RX15
PEX_RX15
I2CS_SCL
I2CS_SDA
OUT
BI
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_DVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_HVDD
PEX_PLL_HVDD
PEX_TERMP
FDBA
BB33
BB35
BB36
BC33
BC35
BC36
BD33
BD36
BB26
BB27
BB29
BB32
BC26
BC27
BC29
BC30
BC32
BD27
BD30
BB30
BL44
{24}
PEX_TERMP
{24}
Place under GPU
C831
C855
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
C825
C826
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
1V8
C854
0.1uF
16V
10%
X7R
0402
COMMON
GND
R659
3V3
2.49k
COMMON0402
1 %
12V
GND
C856
1uF
6.3V
10%
X6S
0402
COMMON
C827
1uF
6.3V
10%
X6S
0402
COMMON
GND
NET
GND
G
12V
3V3
VOLTAGE
12V
5.5A 0.406
3.0A 0.400
8.5A0V 0.400
MIN_WIDTHMAX_CURRENT
1
Place between
C830
1uF
6.3V
10%
X6S
0402
COMMON
C773
1uF
6.3V
10%
X6S
0402
COMMON
GPU and PS
C142
4.7uF
6.3V
20%
X6S
0603
COMMON
C815
4.7uF
6.3V
20%
X6S
0603
COMMON
C910
4.7uF
6.3V
20%
X6S
0603
COMMON
C803
4.7uF
6.3V
20%
X6S
0603
COMMON
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
C884
10uF
6.3V
10%
X7R
0805
COMMON
C893
10uF
6.3V
10%
X7R
0805
COMMON
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
PCI Express
PCI Express
PCI Express
P45U
P45U
P45U
H
C841
10uF
6.3V
10%
X7R
0805
COMMON
Design By:
Design By:
Design By:
PEX_VDD
C890
10uF
6.3V
10%
X7R
0805
COMMON
GND
1V8
C813
22uF
6.3V
20%
X6S
0805LP
COMMON
GND
Carson V10
Carson V10
Carson V10
3 37Thursday, December 28, 2017
3 37Thursday, December 28, 2017
3 37Thursday, December 28, 2017
2
3
4
5
A B C D E F G H
smd.db-x7.ru
Page4: MEMORY: GPU Partition A/B
1
FB_DATA
{5,6}
2
3
{5,6}
{5,6}
4
FBA_D[63..0]
BI
FB_DBI
FBA_DBI[7..0]
IN
FB_EDC
FBA_EDC[7..0]
IN
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_D32
32
FBA_D33
33
FBA_D34
34
FBA_D35
35
FBA_D36
36
FBA_D37
37
FBA_D38
38
FBA_D39
39
FBA_D40
40
FBA_D41
41
FBA_D42
42
FBA_D43
43
FBA_D44
44
FBA_D45
45
FBA_D46
46
FBA_D47
47
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_DBI0
0
FBA_DBI1
1
FBA_DBI2
2
FBA_DBI3
3
FBA_DBI4
4
FBA_DBI5
5
FBA_DBI6
6
FBA_DBI7
7
FBA_EDC0
0
FBA_EDC1
1
FBA_EDC2
2
FBA_EDC3
3
FBA_EDC4
4
FBA_EDC5
5
FBA_EDC6
6
FBA_EDC7
7
GND
{4,10}
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
1V8_FB_PLL
IN
C775
0.1uF
16V
10%
X7R
0402
COMMON
C649
0.1uF
16V
10%
X7R
0402
COMMON
GND
AJ44
AG48
AJ45
AG49
AF46
AF47
AF48
AD47
AD49
AD48
AC46
AC47
AA47
AA46
AA45
AW51
BA52
AW50
BA51
BA50
BB50
BA49
AW49
AV48
AT49
AT47
AT48
AT46
AV51
AV52
AV49
AJ48
AJ46
AJ47
AK49
AM47
AM46
AN48
AN49
AM44
AM45
AN45
AN46
AR48
AN47
AR47
AR46
AG47
AC48
BB51
AV50
AM48
AR49
AF44
AA48
BB52
AT50
AK48
AR51
W47
W49
W51
AF42
U51
U48
U50
U49
R51
R50
R47
U46
V46
Y45
Y47
Y46
V50
V47
U52
V51
Y44
U47
Y48
R48
V48
W6
W8
Y14
Y15
Y16
L29
G1B
BGA2152
COMMON
2/23 FBA
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63
FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7
FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7
GND
GND
GND
GND
GND
GND
GND
GND
FB_REFPLL_AVDD0
FB_REFPLL_AVDD1
FB_CMD
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
FBA_CMD32
FBA_CMD33
FBA_CMD34
FBA_CMD35
FBA_DBG_RFU1
FBA_DBG_RFU2
FBA_CLK0
FBA_CLK0
FBA_CLK1
FBA_CLK1
FBA_WCK01
FBA_WCK01
FBA_WCKB01
FBA_WCKB01
FBA_WCK23
FBA_WCK23
FBA_WCKB23
FBA_WCKB23
FBA_WCK45
FBA_WCK45
FBA_WCKB45
FBA_WCKB45
FBA_WCK67
FBA_WCK67
FBA_WCKB67
FBA_WCKB67
FBA_PLL_AVDD
Y51
Y52
Y49
AA52
AA51
AA50
AC50
AC51
AC52
AC49
AD52
AD51
AD50
AF50
AF51
AF52
AN50
AN51
AN52
AM49
AM52
AM51
AM50
AK50
AK51
AK52
AJ49
AJ52
AJ51
AJ50
AG50
AG51
AG52
AF49
Y50
AR50
AA44
AN44
AG45
AG46
AK46
AK45
U45
U44
V45
V44
AC45
AC44
AD46
AD45
AV47
AV46
AW48
AW47
AR45
AR44
AT45
AT44
AN42
FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31
SNN_FBA_CMD<32>
SNN_FBA_CMD<33>
FBA_DEBUG0
FBA_DEBUG1
SNN_FBA_DBG_RFU1
SNN_FBA_DBG_RFU2
FBA_CLK0
FBA_CLK0*
FBA_CLK1
FBA_CLK1*
FBA_WCK01
FBA_WCK01*
SNN_FBA_WCKB01
SNN_FBA_WCKB01*
FBA_WCK23
FBA_WCK23*
SNN_FBA_WCKB23
SNN_FBA_WCKB23*
FBA_WCK45
FBA_WCK45*
SNN_FBA_WCKB45
SNN_FBA_WCKB45*
FBA_WCK67
FBA_WCK67*
SNN_FBA_WCKB67
SNN_FBA_WCKB67*
C645
0.1uF
16V
10%
X7R
0402
COMMON
FBA_CMD[31..0]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
50OHM_NETCLASS1
50OHM_NETCLASS1
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
1V8
LB502
30ohm
COMMON
BEAD_0603
1V8_FB_PLL 1V8_FB_PLL
C903
22uF
6.3V
20%
X6S
0805LP
COMMON
GND
FBA_CMD1
FBA_CMD17
FBA_CMD2
FBA_CMD18
TP508
TP510
R602
10k
5 %
0402
COMMON
R644
10k
5 %
0402
COMMON
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
FBVDD
R645
10k
5 %
0402
COMMON
R601
10k
5 %
0402
COMMON
{7,8}
{7,8}
{7,8}
{4,10}
{5}
{5}
{6}
{6}
{5}
{5}
{5}
{5}
{6}
{6}
{6}
{6}
{5,6}
FBB_CMD1
FBB_CMD17
FBB_CMD2
FBB_CMD18
GDDR5 CMD Mapping
CMD 0..31
CMD0
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
CMD31
GND
ASSEMBLY
PAGE DETAIL
C E
<ASSEMBLY_DESCRIPTION>
GPU FB_AB
CAS*
CKE*
RST*
RAS*
A1_A9
A0_A10
A12_RFU
ABI*
A6_A11
A7_A8
WE*
A5_BA1
A4_BA2
A2_BA0
A3_BA3
CS*
BI
IN
OUT
R568
10k
5 %
0402
COMMON
R581
10k
5 %
0402
COMMON
32..63
CAS*
CKE*
RST*
RAS*
A1_A9
A0_A10
A12_RFU
ABI*
A6_A11
A7_A8
WE*
A5_BA1
A4_BA2
A2_BA0
A3_BA3
CS*
FB_DATA
FBB_D[63..0]
FB_DBI
FBB_DBI[7..0]
FB_EDC
FBB_EDC[7..0]
FBVDD
R570
10k
5 %
0402
COMMON
R580
10k
5 %
0402
COMMON
GND
G1C
BGA2152
COMMON
FBB_D0
0
FBB_D1
1
FBB_D2
2
FBB_D3
3
FBB_D4
4
FBB_D5
5
FBB_D6
6
FBB_D7
7
FBB_D8
8
FBB_D9
9
FBB_D10
10
FBB_D11
11
FBB_D12
12
FBB_D13
13
FBB_D14
14
FBB_D15
15
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_D32
32
FBB_D33
33
FBB_D34
34
FBB_D35
35
FBB_D36
36
FBB_D37
37
FBB_D38
38
FBB_D39
39
FBB_D40
40
FBB_D41
41
FBB_D42
42
FBB_D43
43
FBB_D44
44
FBB_D45
45
FBB_D46
46
FBB_D47
47
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_DBI0
0
FBB_DBI1
1
FBB_DBI2
2
FBB_DBI3
3
FBB_DBI4
4
FBB_DBI5
5
FBB_DBI6
6
FBB_DBI7
7
FBB_EDC0
0
FBB_EDC1
1
FBB_EDC2
2
FBB_EDC3
3
FBB_EDC4
4
FBB_EDC5
5
FBB_EDC6
6
FBB_EDC7
7
H32
D32
B32
E32
G32
H36
G36
D33
G33
E45
D45
G45
D42
E42
H41
E41
E39
D39
E38
D36
E36
M50
P48
M51
M49
P47
P52
R46
P46
M46
M48
M47
A33
J30
F32
J36
F36
F33
J32
F45
F42
F39
F38
L50
L51
L52
L49
L47
D48
C50
C48
C49
E49
E50
F49
F48
F50
D52
J50
H48
H51
J51
H49
H52
C32
E33
E44
G39
P49
L48
D50
H50
B33
E35
G44
H38
P50
J48
D51
F51
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
3/23 FBB
FBB_D0
FBB_D1
FBB_D2
FBB_D3
FBB_D4
FBB_D5
FBB_D6
FBB_D7
FBB_D8
FBB_D9
FBB_D10
FBB_D11
FBB_D12
FBB_D13
FBB_D14
FBB_D15
FBB_D16
FBB_D17
FBB_D18
FBB_D19
FBB_D20
FBB_D21
FBB_D22
FBB_D23
FBB_D24
FBB_D25
FBB_D26
FBB_D27
FBB_D28
FBB_D29
FBB_D30
FBB_D31
FBB_D32
FBB_D33
FBB_D34
FBB_D35
FBB_D36
FBB_D37
FBB_D38
FBB_D39
FBB_D40
FBB_D41
FBB_D42
FBB_D43
FBB_D44
FBB_D45
FBB_D46
FBB_D47
FBB_D48
FBB_D49
FBB_D50
FBB_D51
FBB_D52
FBB_D53
FBB_D54
FBB_D55
FBB_D56
FBB_D57
FBB_D58
FBB_D59
FBB_D60
FBB_D61
FBB_D62
FBB_D63
FBB_DQM0
FBB_DQM1
FBB_DQM2
FBB_DQM3
FBB_DQM4
FBB_DQM5
FBB_DQM6
FBB_DQM7
FBB_DQS_WP0
FBB_DQS_WP1
FBB_DQS_WP2
FBB_DQS_WP3
FBB_DQS_WP4
FBB_DQS_WP5
FBB_DQS_WP6
FBB_DQS_WP7
GND
GND
GND
GND
GND
GND
GND
GND
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
FBB_CMD32
FBB_CMD33
FBB_CMD34
FBB_CMD35
FBB_DBG_RFU1
FBB_DBG_RFU2
FBB_CLK0
FBB_CLK0
FBB_CLK1
FBB_CLK1
FBB_WCK01
FBB_WCK01
FBB_WCKB01
FBB_WCKB01
FBB_WCK23
FBB_WCK23
FBB_WCKB23
FBB_WCKB23
FBB_WCK45
FBB_WCK45
FBB_WCKB45
FBB_WCKB45
FBB_WCK67
FBB_WCK67
FBB_WCKB67
FBB_WCKB67
FBB_PLL_AVDD
GND
FDBA
B35
A35
D35
A36
B36
C36
C38
B38
A38
D38
A39
B39
C39
C41
B41
A41
B49
A49
A48
D47
A47
B47
C47
C45
B45
A45
D44
A44
B44
C44
C42
B42
A42
D41
C35
B50
J35
J41
H42
G42
F47
E47
J33
H33
G35
H35
J39
H39
F41
G41
L46
L45
M44
M45
H47
H46
J47
J46
L38
G
FB_CMD
FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8
FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31
SNN_FBB_CMD<32>
SNN_FBB_CMD<33>
FBB_DEBUG0
FBB_DEBUG1
SNN_FBB_DBG_RFU1
SNN_FBB_DBG_RFU2
FBB_CLK0
FBB_CLK0*
FBB_CLK1
FBB_CLK1*
FBB_WCK01
FBB_WCK01*
SNN_FBB_WCKB01
SNN_FBB_WCKB01*
FBB_WCK23
FBB_WCK23*
SNN_FBB_WCKB23
SNN_FBB_WCKB23*
FBB_WCK45
FBB_WCK45*
SNN_FBB_WCKB45
SNN_FBB_WCKB45*
FBB_WCK67
FBB_WCK67*
SNN_FBB_WCKB67
SNN_FBB_WCKB67*
C652
0.1uF
16V
10%
X7R
0402
COMMON
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
50OHM_NETCLASS1
50OHM_NETCLASS1
IN
FBB_CMD[31..0]
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
{4,10}
TP501
TP504
GND
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
GPU FB_AB
GPU FB_AB
GPU FB_AB
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
Carson V10
Carson V10
Carson V10
4 37Thursday, December 28, 2017
4 37Thursday, December 28, 2017
4 37Thursday, December 28, 2017
{7,8}
{7}
{7}
{8}
{8}
{7}
{7}
{7}
{7}
{8}
{8}
{8}
{8}
1
2
3
4
5
A B C D E F G H
smd.db-x7.ru
Page5: FRAME BUFFER PARTITION A [31:0]
1
FBA_D[31..0]
BI
{4,6}
{4,6}
2
3
{4}
{4}
FBA_EDC[7..0]
IN
FBA_DBI[7..0]
IN
{4}
FBA_D0
0
FBA_D1
1
FBA_D2
2
FBA_D3
3
FBA_D4
4
FBA_D5
5
FBA_D6
6
FBA_D7
7
FBA_EDC0
0
0
1
IN
IN
FBA_DBI0
FBA_D8
8
FBA_D9
9
FBA_D10
10
FBA_D11
11
FBA_D12
12
FBA_D13
13
FBA_D14
14
FBA_D15
15
FBA_EDC1
1
FBA_DBI1
FBA_WCK01
FBA_WCK01*
V11
V13
T11
T13
N11
N13
M11
M13
R13
P13
V4
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
FB_DATA
FB_EDC
FB_EDC
M3D
@memory.u_mem_sd_ddr5_x32(sym_2):page5_i297
BGA170_MIRR
COMMON
MIRRORED
x16x32
DQ0
NC
DQ1
NC
DQ2
NC
DQ3
NC
DQ4
NC
DQ5
NC
DQ6
NC
DQ7
NC
EDC0
NC
DBI0
NC
SNN_FBA_VREFD_M3_0 SNN_FBA_VREFD_M3_1
V10
VREFD
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
EDC1
DBI1
WCK01
WCK01
M3A
@memory.u_mem_sd_ddr5_x32(sym_4):page5_i337
BGA170_MIRR
COMMON
MIRRORED
FBA_D16
16
FBA_D17
17
FBA_D18
18
FBA_D19
19
FBA_D20
20
FBA_D21
21
FBA_D22
22
FBA_D23
23
FBA_EDC2
2
2
3
{4}
{4}
IN
IN
FBA_DBI2
FBA_D24
24
FBA_D25
25
FBA_D26
26
FBA_D27
27
FBA_D28
28
FBA_D29
29
FBA_D30
30
FBA_D31
31
FBA_EDC3
3
FBA_DBI3
FBA_WCK23
FBA_WCK23*
x32 x16
A11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
DBI2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
VREFD
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
A10
R120
931ohm
1 %
0402
COMMON
{4}
{4}
A13
B11
B13
E11
E13
F11
F13
C13
D13
A4
A2
B4
B2
E4
E2
F4
F2
C2
D2
D4
D5
FB_CMD
FBA_CMD[31..0]
IN
R121
1.33k
1 %
0402
COMMON
GND
FBVDD
IN
IN
R122
549ohm
1 %
0402
COMMON
C156
COMMON
{4,6}
FBA_CLK0
FBA_CLK0*
820pF
50V
10%
X7R
0402
R613
40.2ohm
1 %
0402
COMMON
FBA_CLK0_RC
GND
GND
FBA_CMD3
3
FBA_CMD0
0
FBA_CMD10
10
FBA_CMD15
15
FBA_CMD7
7
FBA_CMD5
5
FBA_CMD4
4
FBA_CMD13
13
FBA_CMD14
14
FBA_CMD12
12
FBA_CMD11
11
FBA_CMD8
8
FBA_CMD9
9
FBA_CMD6
6
FBA_CMD2
2
FBA_CMD1
1
R612
40.2ohm
1 %
0402
COMMON
SNN_FBA_RFU1_M1
R614 121ohm
COMMON
0402
1 %
SNN_FBA_RFU2_M1
OUT
FBA_ZQ0
C756
10nF
16V
10%
X7R
0402
COMMON
FBA_VREFC
0.300
GND
M3B
@memory.u_mem_sd_ddr5_x32(sym_5):page5_i342
BGA170_MIRR
COMMON
L3
RAS
G3
CAS
G12
WE
L12
CS
J4
ABI
K4
A0_A10
K5
A1_A9
K11
A2_BA0
K10
A3_BA3
H11
A4_BA2
H10
A5_BA1
H5
A6_A11
H4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
{6}
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
FBA_VREFC_Q
0.300
3
D
Q26
@discrete.q_fet_n_enh(sym_2):page5_i135
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
{7,11,24}
IN
GPIO10_FBVREF_SEL
ASSEMBLY
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
MEMORY: FBA[31:0]
SOT23_1G1D1S
G
1
COMMON
S
2
1G1D1S
GND
50V
0.22A
3500mohm@10V / 3500mohm@4.5V / 3500mohm@2.5V
0.22A
0.35W
20V
FDBA
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBA[31:0]
MEMORY: FBA[31:0]
MEMORY: FBA[31:0]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
5 37Thursday, December 28, 2017
5 37Thursday, December 28, 2017
5 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page6: FRAME BUFFER PARTITION A [63:32]
1
M1B
@memory.u_mem_sd_ddr5_x32(sym_5):page6_i154
FBA_CMD[31..0]
IN
FBA_D[63..32]
BI
{4,5}
{4,5}
2
3
FBA_EDC[7..0]
IN
FBA_DBI[7..0]
IN
{4}
{4}
{4}
32
33
34
35
36
37
38
39
4
4
40
41
42
43
44
45
46
47
5
5
IN
IN
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_EDC4
FBA_DBI4
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_EDC5
FBA_DBI5
FBA_WCK45
FBA_WCK45*
FB_DATA
FB_EDC
FB_DBI
M1D
@memory.u_mem_sd_ddr5_x32(sym_1):page6_i152
BGA170
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
VREFD
x16
x32
A11
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
EDC1
DBI1
WCK01
WCK01
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
A13
B11
B13
E11
E13
F11
F13
C13
D13
D4
D5
M1A
@memory.u_mem_sd_ddr5_x32(sym_3):page6_i153
BGA170
COMMON
N11
N13
M11
M13
R13
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
P13
DBI2
V10
VREFD
x16
x32
V4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
FBA_D48
48
FBA_D49
49
FBA_D50
50
FBA_D51
51
FBA_D52
52
FBA_D53
53
FBA_D54
54
FBA_D55
55
FBA_EDC6
6
SNN_FBA_VREFD_M1_0 SNN_FBA_VREFD_M1_1
A10
{4}
{4}
6
7
IN
IN
FBA_DBI6
FBA_D56
56
FBA_D57
57
FBA_D58
58
FBA_D59
59
FBA_D60
60
FBA_D61
61
FBA_D62
62
FBA_D63
63
FBA_EDC7
7
FBA_DBI7
FBA_WCK67
FBA_WCK67*
{4}
{4}
{5}
IN
IN
IN
{4,5}
FBA_CLK1
FBA_CLK1*
FBA_VREFC
FB_CMD
R619
40.2ohm
1 %
0402
COMMON
FBA_CLK1_RC
GND
GND
C147
820pF
50V
10%
X7R
0402
COMMON
C777
10nF
16V
10%
X7R
0402
COMMON
19
16
26
31
23
21
20
29
30
28
27
24
25
22
18
17
R618
40.2ohm
1 %
0402
COMMON
FBA_CMD19
FBA_CMD16
FBA_CMD26
FBA_CMD31
FBA_CMD23
FBA_CMD21
FBA_CMD20
FBA_CMD29
FBA_CMD30
FBA_CMD28
FBA_CMD27
FBA_CMD24
FBA_CMD25
FBA_CMD22
FBA_CMD18
FBA_CMD17
SNN_FBA_RFU1_M3
SNN_FBA_RFU2_M3
FBA_ZQ2
R620
121ohm
1 %
0402
COMMON
GND GND
BGA170
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
0.300
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
4
5
ASSEMBLY
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
MEMORY: FBA[63:32]
FDBA
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBA[63:32]
MEMORY: FBA[63:32]
MEMORY: FBA[63:32]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
6 37Thursday, December 28, 2017
6 37Thursday, December 28, 2017
6 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page7: FRAME BUFFER PARTITION B [31:0]
1
M7B
@memory.u_mem_sd_ddr5_x32(sym_5):page7_i1383
G12
H11
H10
BGA170_MIRR
COMMON
L3
RAS
G3
CAS
WE
L12
CS
J4
ABI
K4
A0_A10
K5
A1_A9
K11
A2_BA0
K10
A3_BA3
A4_BA2
A5_BA1
H5
A6_A11
H4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
FBB_CMD[31..0]
FBB_D[31..0]
BI
{4,8}
{4,8}
2
FBB_EDC[7..0]
IN
FBB_DBI[7..0]
IN
0
0
1
1
{4}
3
{4}
IN
IN
FB_DATA
{4}
FB_EDC
FB_DBI
M7D
@memory.u_mem_sd_ddr5_x32(sym_2):page7_i1321
BGA170_MIRR
COMMON
MIRRORED
0
FBB_D0
1
FBB_D1
2
FBB_D2
3
FBB_D3
4
FBB_D4
5
FBB_D5
6
FBB_D6
7
FBB_D7
FBB_EDC0
FBB_DBI0
FBB_D8
8
FBB_D9
9
FBB_D10
10
FBB_D11
11
FBB_D12
12
FBB_D13
13
FBB_D14
14
FBB_D15
15
FBB_EDC1
FBB_DBI1
FBB_WCK01
FBB_WCK01*
V11
V13
T11
T13
N11
N13
M11
M13
R13
P13
V4
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EDC0
DBI0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
EDC1
DBI1
WCK01
WCK01
x16x32
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SNN_FBB_VREFD_M7_0 SNN_FBB_VREFD_M7_1
V10
VREFD
{4}
{4}
2
3
IN
IN
FBB_D16
16
FBB_D17
17
FBB_D18
18
FBB_D19
19
FBB_D20
20
FBB_D21
21
FBB_D22
22
FBB_D23
23
FBB_EDC2
2
FBB_DBI2
FBB_D24
24
FBB_D25
25
FBB_D26
26
FBB_D27
27
FBB_D28
28
FBB_D29
29
FBB_D30
30
FBB_D31
31
FBB_EDC3
3
FBB_DBI3
FBB_WCK23
FBB_WCK23*
M7A
@memory.u_mem_sd_ddr5_x32(sym_4):page7_i1378
BGA170_MIRR
COMMON
MIRRORED
x32 x16
A11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
DBI2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
VREFD
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
A13
B11
B13
E11
E13
F11
F13
C13
D13
A4
A2
B4
B2
E4
E2
F4
F2
C2
D2
D4
D5
A10
FBB_VREFC
OUT
R135
931ohm
1 %
0402
COMMON
0.300
IN
{4}
{4}
{8}
R134
1.33k
1 %
0402
COMMON
GND
FBVDD
R136
549ohm
1 %
0402
COMMON
GND
IN
IN
C195
820pF
50V
10%
X7R
0402
COMMON
{4,8}
FBB_CLK0
FBB_CLK0*
FB_CMD
R587
40.2ohm
1 %
0402
COMMON
FBB_CLK0_RC
GND
C563
10nF
16V
10%
X7R
0402
COMMON
FBB_CMD3
3
FBB_CMD0
0
FBB_CMD10
10
FBB_CMD15
15
FBB_CMD7
7
FBB_CMD5
5
FBB_CMD4
4
FBB_CMD13
13
FBB_CMD14
14
FBB_CMD12
12
FBB_CMD11
11
FBB_CMD8
8
FBB_CMD9
9
FBB_CMD6
6
FBB_CMD2
2
FBB_CMD1
1
R591
40.2ohm
1 %
0402
COMMON
SNN_FBB_RFU1_M1
SNN_FBB_RFU2_M1
0.300
R569
0402
1 %
GND
121ohm
COMMON
FBB_ZQ0
1
2
3
{5,11,24}
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
ASSEMBLY
PAGE DETAIL
GPIO10_FBVREF_SEL
IN
<ASSEMBLY_DESCRIPTION>
MEMORY: FBB[31:0]
3
D
Q33
@discrete.q_fet_n_enh(sym_2):page7_i1237
SOT23_1G1D1S
G
1
COMMON
S
2
1G1D1S
GND
FBB_VREFC_Q
50V
0.22A
3500mohm@10V / 3500mohm@4.5V / 3500mohm@2.5V
0.22A
0.35W
20V
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
FDBA
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBB[31:0]
MEMORY: FBB[31:0]
MEMORY: FBB[31:0]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
7 37Thursday, December 28, 2017
7 37Thursday, December 28, 2017
7 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page8: FRAME BUFFER PARTITION B [63:32]
1
M8B
@memory.u_mem_sd_ddr5_x32(sym_5):page8_i155
L12
G12
H11
H10
K11
K10
BGA170
COMMON
G3
RAS
L3
CAS
WE
CS
J4
ABI
H4
A0_A10
H5
A1_A9
A2_BA0
A3_BA3
A4_BA2
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
FBB_CMD[31..0]
FBB_D[63..32]
BI
{4,7}
{4,7}
2
FBB_EDC[7..0]
IN
FBB_DBI[7..0]
IN
{4}
3
FB_DATA
FB_EDC
FB_DBI
M8D
@memory.u_mem_sd_ddr5_x32(sym_1):page8_i157
BGA170
COMMON
32
FBB_D32
33
FBB_D33
34
FBB_D34
35
FBB_D35
36
FBB_D36
37
FBB_D37
38
FBB_D38
39
FBB_D39
FBB_EDC4
4
4
5
IN
IN
FBB_DBI4
FBB_D40
40
FBB_D41
41
FBB_D42
42
FBB_D43
43
FBB_D44
44
FBB_D45
45
FBB_D46
46
FBB_D47
47
FBB_EDC5
5
FBB_DBI5
FBB_WCK45
{4}
FBB_WCK45*
{4}
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
x32
A11
DQ8
A13
DQ9
B11
DQ10
B13
DQ11
E11
DQ12
E13
DQ13
F11
DQ14
F13
DQ15
C13
EDC1
D13
DBI1
D4
WCK01
D5
WCK01
SNN_FBB_VREFD_M8_0 SNN_FBB_VREFD_M8_1
A10
VREFD
x16
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
6
7
IN
IN
FBB_D48
48
FBB_D49
49
FBB_D50
50
FBB_D51
51
FBB_D52
52
FBB_D53
53
FBB_D54
54
FBB_D55
55
FBB_EDC6
6
FBB_DBI6
FBB_D56
56
FBB_D57
57
FBB_D58
58
FBB_D59
59
FBB_D60
60
FBB_D61
61
FBB_D62
62
FBB_D63
63
FBB_EDC7
7
FBB_DBI7
FBB_WCK67
{4}
FBB_WCK67*
{4}
M8A
@memory.u_mem_sd_ddr5_x32(sym_3):page8_i156
BGA170
COMMON
NORMAL
V11
DQ16
V13
DQ17
T11
DQ18
T13
DQ19
N11
DQ20
N13
DQ21
M11
DQ22
M13
DQ23
R13
EDC2
P13
DBI2
VREFD
x16
x32
V4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
V10
IN
{4}
{4}
IN
IN
FB_CMD
{4,7}
FBB_CLK1
FBB_CLK1*
R585
40.2ohm
1 %
0402
COMMON
FBB_CLK1_RC
GND
FBB_VREFC
IN
GND
{7}
C197
820pF
50V
10%
X7R
0402
COMMON
C561
10nF
16V
10%
X7R
0402
COMMON
GND
FBB_CMD19
19
FBB_CMD16
16
FBB_CMD26
26
FBB_CMD31
31
FBB_CMD23
23
FBB_CMD21
21
FBB_CMD20
20
FBB_CMD29
29
FBB_CMD30
30
FBB_CMD28
28
FBB_CMD27
27
FBB_CMD24
24
FBB_CMD25
25
FBB_CMD22
22
FBB_CMD18
18
FBB_CMD17
17
R589
40.2ohm
1 %
0402
COMMON
SNN_FBB_RFU1_M3
SNN_FBB_RFU2_M3
121ohm
COMMON
FBB_ZQ2
R576
0402
1 %
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
ASSEMBLY
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
MEMORY: FBB[63:32]
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
FDBA
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBB[63:32]
MEMORY: FBB[63:32]
MEMORY: FBB[63:32]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
8 37Thursday, December 28, 2017
8 37Thursday, December 28, 2017
8 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page9: FRAME BUFFER PARTITION A/B DECOUPLING
FBVDD
1
2
3
DECOUPLING AROUND FBA MEMORIES (DQ0-DQ31)
C154
C153
C157
C177
C155
1uF
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
C729
22uF
4V
20%
X6S
0603W
COMMON
0603
0402
C168
22uF
4V
20%
X6S
0603W
COMMON
0603
0603
SOE*/MF_VDD
6.3V
10%
X6S
0402
COMMON
C703
22uF
4V
20%
X6S
0603W
COMMON
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C659
22uF
4V
20%
X6S
0603W
COMMON
0603
0603
GND
FBVDD
J1
add 1k to VDD
C10
VDD
C5
VDD
D11
VDD
G1
VDD
G11
VDD
G14
VDD
G4
VDD
L1
VDD
L11
VDD
L14
VDD
L4
VDD
P11
VDD
R10
VDD
R5
VDD
B1
VDDQ
B12
VDDQ
B14
VDDQ
B3
VDDQ
D1
VDDQ
D12
VDDQ
D14
VDDQ
D3
VDDQ
E10
VDDQ
E5
VDDQ
F1
VDDQ
F12
VDDQ
F14
VDDQ
F3
VDDQ
G13
VDDQ
G2
VDDQ
H12
VDDQ
H3
VDDQ
K12
VDDQ
K3
VDDQ
L13
VDDQ
L2
VDDQ
M1
VDDQ
M12
VDDQ
M14
VDDQ
M3
VDDQ
N10
VDDQ
N5
VDDQ
P1
VDDQ
P12
VDDQ
P14
VDDQ
P3
VDDQ
T1
VDDQ
T12
VDDQ
T14
VDDQ
T3
VDDQ
1uF
6.3V
10%
X6S
0402
COMMON
C631
22uF
4V
20%
X6S
0603W
COMMON
C176
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
@memory.u_mem_sd_ddr5_x32(sym_7):page9_i984
BGA170_MIRR
COMMON
Mirrored
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
C740
1uF
6.3V
10%
X6S
0402
COMMON
M3C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B10
B5
D10
G10
G5
H1
H14
K1
K14
L10
L5
P10
T10
T5
A1
A12
A14
A3
C1
C11
C12
C14
C3
C4
E1
E12
E14
E3
F10
F5
H13
H2
K13
K2
M10
M5
N1
N12
N14
N3
R1
R11
R12
R14
R3
R4
V1
V12
V14
V3
0402
FBVDD
0402
C705
1uF
6.3V
10%
X6S
0402
COMMON
C693
1uF
6.3V
10%
X6S
0402
COMMON
C744
C175
C178
C694
C741
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
10uF
4V
20%
X6S
0603
COMMON
0603
0603
10uF
4V
20%
X6S
0603
COMMON
C745
10uF
4V
20%
X6S
0603
COMMON
0603
0603
10uF
4V
20%
X6S
0603
COMMON
C624
C625
10uF
10uF
4V
4V
20%
20%
X6S
X6S
0603
0603
COMMON
COMMON
0603
0603
GND
C626
C672
C664
C663
C658
C629
1uF
1uF
6.3V
10%
X6S
0402
COMMON
0402
Normal
1uF
6.3V
10%
X6S
0402
COMMON
0402
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
6.3V
10%
X6S
0402
COMMON
0402
0402
M1C
@memory.u_mem_sd_ddr5_x32(sym_6):page9_i1290
BGA170
COMMON
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
1uF
6.3V
10%
X6S
0402
COMMON
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
C10
C5
D11
G1
G11
G14
G4
L1
L11
L14
L4
P11
R10
R5
B1
B12
B14
B3
D1
D12
D14
D3
E10
E5
F1
F12
F14
F3
G13
G2
H12
H3
K12
K3
L13
L2
M1
M12
M14
M3
N10
N5
P1
P12
P14
P3
T1
T12
T14
T3
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
FBVDD
1uF
6.3V
10%
X6S
0402
COMMON
C685
1uF
6.3V
10%
X6S
0402
COMMON
0402
GND
FBVDD
DECOUPLING AROUND FBB MEMORIES (DQ0-DQ31)
C188
C211
C201
C208
C537
1uF
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
0402
C228
C226
22uF
22uF
4V
4V
20%
20%
X6S
X6S
0603W
0603W
COMMON
COMMON
0603
0603
0603
6.3V
10%
X6S
0402
COMMON
C601
22uF
4V
20%
X6S
0603W
COMMON
0402
0603
SOE*/MF_VDD
1uF
6.3V
10%
X6S
0402
COMMON
C607
22uF
4V
20%
X6S
0603W
COMMON
0402
0603
GND
FBVDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
1uF
6.3V
10%
X6S
0402
COMMON
C606
22uF
4V
20%
X6S
0603W
COMMON
C10
VDD
C5
VDD
D11
VDD
G1
VDD
G11
VDD
G14
VDD
G4
VDD
VDD
L11
VDD
L14
VDD
VDD
P11
VDD
R10
VDD
R5
VDD
B12
B14
D1
D12
D14
D3
E10
F12
F14
G13
G2
H12
H3
K12
L13
M1
M12
M14
M3
N10
N5
P12
P14
T12
T14
C575
1uF
6.3V
10%
X6S
0402
COMMON
0402
J1
add 1k to VDD
L1
L4
B1
B3
E5
F1
F3
K3
L2
P1
P3
T1
T3
C594
C579
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
FBVDD
C557
C571
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
M7C
@memory.u_mem_sd_ddr5_x32(sym_7):page9_i975
BGA170_MIRR
COMMON
Mirrored
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
B10
B5
D10
G10
G5
H1
H14
K1
K14
L10
L5
P10
T10
T5
A1
A12
A14
A3
C1
C11
C12
C14
C3
C4
E1
E12
E14
E3
F10
F5
H13
H2
K13
K2
M10
M5
N1
N12
N14
N3
R1
R11
R12
R14
R3
R4
V1
V12
V14
V3
C222
C192
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C572
1uF
6.3V
10%
X6S
0402
COMMON
C202
1uF
6.3V
10%
X6S
0402
COMMON
0402
C584
C674
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
M8C
@memory.u_mem_sd_ddr5_x32(sym_6):page9_i1292
BGA170
COMMON
J1
MF_VSS/SOE*
add 1k to VSS
B10
VSS
B5
VSS
D10
VSS
G10
VSS
G5
VSS
H1
VSS
H14
VSS
K1
VSS
K14
VSS
L10
VSS
L5
VSS
P10
VSS
T10
VSS
T5
VSS
A1
VSSQ
A12
VSSQ
A14
VSSQ
A3
VSSQ
C1
VSSQ
C11
VSSQ
C12
VSSQ
C14
VSSQ
C3
VSSQ
C4
VSSQ
E1
VSSQ
E12
VSSQ
E14
VSSQ
E3
VSSQ
F10
VSSQ
F5
VSSQ
H13
VSSQ
H2
VSSQ
K13
VSSQ
K2
VSSQ
M10
VSSQ
M5
VSSQ
N1
VSSQ
N12
VSSQ
N14
VSSQ
N3
VSSQ
R1
VSSQ
R11
VSSQ
R12
VSSQ
R14
VSSQ
R3
VSSQ
R4
VSSQ
V1
VSSQ
V12
VSSQ
V14
VSSQ
V3
VSSQ
0402
Normal
0603
C581
1uF
6.3V
10%
X6S
0402
COMMON
10uF
4V
20%
X6S
0603
COMMON
0402
C528
1uF
6.3V
10%
X6S
0402
COMMON
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
C217
10uF
4V
20%
X6S
0603
COMMON
0603
0603
C550
1uF
6.3V
10%
X6S
0402
COMMON
0402
GND
FBVDD
C10
C5
D11
G1
G11
G14
G4
L1
L11
L14
L4
P11
R10
R5
B1
B12
B14
B3
D1
D12
D14
D3
E10
E5
F1
F12
F14
F3
G13
G2
H12
H3
K12
K3
L13
L2
M1
M12
M14
M3
N10
N5
P1
P12
P14
P3
T1
T12
T14
T3
C591
10uF
4V
20%
X6S
0603
COMMON
C540
C533
10uF
4V
20%
X6S
0603
COMMON
0603
GND
C526
10uF
4V
20%
X6S
0603
COMMON
10uF
4V
20%
X6S
0603
COMMON
0603
0603
1
2
3
GND GND
C880
1uF
6.3V
10%
X6S
0402
COMMON
BGA_0170_P080_140X120
C695
1uF
6.3V
10%
X6S
0402
COMMON
0402
C870
1uF
6.3V
10%
X6S
0402
COMMON
0402
C135
C151
10uF
10uF
4V
4V
20%
20%
X6S
X6S
0603
0603
COMMON
COMMON
0603
C863
C843
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
C E
0603
0603
C844
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C143
10uF
4V
20%
X6S
0603
COMMON
C864
1uF
6.3V
10%
X6S
0402
COMMON
C882
10uF
4V
20%
X6S
0603
COMMON
0603
C840
1uF
6.3V
10%
X6S
0402
COMMON
0402
GND
C138
1uF
6.3V
10%
X6S
0402
COMMON
0603
BGA_0170_P080_140X120
C148
1uF
6.3V
10%
X6S
0402
COMMON
0402
C833
22uF
4V
20%
X6S
0603W
COMMON
0603
GND
0402
C139
1uF
6.3V
10%
X6S
0402
COMMON
C883
22uF
4V
20%
X6S
0603W
COMMON
C794
C795
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
FBVDD
0402
0402
C860
1uF
6.3V
10%
X6S
0402
COMMON
C792
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
4
FBVDD
C150
C149
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C857
22uF
4V
20%
X6S
0603W
COMMON
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
0603
0603
1uF
6.3V
10%
X6S
0402
COMMON
C877
22uF
4V
20%
X6S
0603W
COMMON
C137
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C865
22uF
4V
20%
X6S
0603W
COMMON
0603
0603
ASSEMBLY
PAGE DETAIL
C789
10uF
4V
20%
X6S
0603
COMMON
0603
GND
C881
10uF
4V
20%
X6S
0603
COMMON
FBVDD
<ASSEMBLY_DESCRIPTION>
MEM FB_AB PWR
GND GND
BGA_0170_P080_140X120
BGA_0170_P080_140X120
4
DECOUPLING AROUND FBB MEMORIES (DQ32-DQ63)DECOUPLING AROUND FBA MEMORIES (DQ32-DQ63)
C189
C193
C204
C210
C596
1uF
1uF
1uF
6.3V
6.3V
10%
10%
X6S
X6S
0402
0402
COMMON
COMMON
0402
0402
C230
22uF
4V
20%
X6S
0603W
COMMON
0603
0402
C521
22uF
4V
20%
X6S
0603W
COMMON
0603
0603
6.3V
10%
X6S
0402
COMMON
C522
22uF
4V
20%
X6S
0603W
COMMON
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C523
22uF
4V
20%
X6S
0603W
COMMON
0603
0603
1uF
6.3V
10%
X6S
0402
COMMON
C520
22uF
4V
20%
X6S
0603W
COMMON
C215
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
GND
FDBA
C595
1uF
6.3V
10%
X6S
0402
COMMON
FBVDD
0402
0402
C555
1uF
6.3V
10%
X6S
0402
COMMON
C580
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C566
1uF
6.3V
10%
X6S
0402
COMMON
C547
1uF
6.3V
10%
X6S
0402
COMMON
C586
1uF
6.3V
10%
X6S
0402
COMMON
0402
C686
C587
1uF
6.3V
10%
X6S
0402
COMMON
C532
1uF
6.3V
10%
X6S
0402
COMMON
0402
G
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
C559
C604
10uF
10uF
4V
4V
20%
20%
X6S
X6S
0603
0603
COMMON
COMMON
0603
Custom
Custom
Custom
C552
1uF
6.3V
10%
X6S
0402
COMMON
0603
C576
1uF
6.3V
10%
X6S
0402
COMMON
0402
GND
0603
C568
1uF
6.3V
10%
X6S
0402
COMMON
0402
0402
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
C564
C534
10uF
10uF
4V
4V
20%
20%
X6S
X6S
0603
0603
COMMON
COMMON
0603
0603
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEM FB_AB PWR
MEM FB_AB PWR
MEM FB_AB PWR
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
C536
10uF
4V
20%
X6S
0603
COMMON
0603
GND
Carson V10
Carson V10
Carson V10
9 37Thursday, December 28, 2017
9 37Thursday, December 28, 2017
9 37Thursday, December 28, 2017
C214
10uF
4V
20%
X6S
0603
COMMON
5
A B C D E F G H
smd.db-x7.ru
Page10: MEMORY: GPU Partition C/D
1
FB_DATA
{11,12}
2
3
{11,12}
{11,12}
4
FBC_D[63..0]
BI
FB_DBI
FBC_DBI[7..0]
OUT
FB_EDC
FBC_EDC[7..0]
OUT
FBC_D0
0
FBC_D1
1
FBC_D2
2
FBC_D3
3
FBC_D4
4
FBC_D5
5
FBC_D6
6
FBC_D7
7
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_D32
32
FBC_D33
33
FBC_D34
34
FBC_D35
35
FBC_D36
36
FBC_D37
37
FBC_D38
38
FBC_D39
39
FBC_D40
40
FBC_D41
41
FBC_D42
42
FBC_D43
43
FBC_D44
44
FBC_D45
45
FBC_D46
46
FBC_D47
47
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_DBI0
0
FBC_DBI1
1
FBC_DBI2
2
FBC_DBI3
3
FBC_DBI4
4
FBC_DBI5
5
FBC_DBI6
6
FBC_DBI7
7
FBC_EDC0
0
FBC_EDC1
1
FBC_EDC2
2
FBC_EDC3
3
FBC_EDC4
4
FBC_EDC5
5
FBC_EDC6
6
FBC_EDC7
7
GND
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
F18
G18
E18
H18
D15
E15
G17
H17
H15
E14
F14
H11
G11
F11
E11
F30
H29
G30
B30
A30
H30
C30
D27
F27
G27
C27
B27
A27
G29
H20
D18
G20
E20
F23
E21
D21
E23
G24
H26
F24
G26
F26
D26
B26
C26
F12
D29
E27
F20
E26
E17
E12
E30
B29
G21
E24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
Y32
C6
D6
A6
B6
B4
A4
B3
C4
D9
C9
E9
B9
B8
A8
F6
E6
J15
J29
J26
A5
C8
J18
D5
D8
G1D
BGA2152
COMMON
4/23 FBC
FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63
FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7
FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7
GND
GND
GND
GND
GND
GND
GND
GND
FB_CMD
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31
FBC_CMD32
FBC_CMD33
FBC_CMD34
FBC_CMD35
FBC_DBG_RFU1
FBC_DBG_RFU2
FBC_CLK0
FBC_CLK0
FBC_CLK1
FBC_CLK1
FBC_WCK01
FBC_WCK01
FBC_WCKB01
FBC_WCKB01
FBC_WCK23
FBC_WCK23
FBC_WCKB23
FBC_WCKB23
FBC_WCK45
FBC_WCK45
FBC_WCKB45
FBC_WCKB45
FBC_WCK67
FBC_WCK67
FBC_WCKB67
FBC_WCKB67
FBC_PLL_AVDD
C11
B11
A11
D11
A12
B12
C12
C14
B14
A14
D14
A15
B15
C15
C17
B17
B24
A24
D23
A23
B23
C23
C21
B21
A21
D20
A20
B20
C20
C18
B18
A18
D17
A17
A9
C24
J14
J23
G15
F15
H21
J21
F8
G8
G9
F9
H12
G12
G14
H14
J27
H27
E29
F29
G23
H23
H24
J24
L17
FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8
FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30
FBC_CMD31
SNN_FBC_CMD<32>
SNN_FBC_CMD<33>
FBC_DEBUG0
FBC_DEBUG1
SNN_FBC_DBG_RFU1
SNN_FBC_DBG_RFU2
FBC_CLK0
FBC_CLK0*
FBC_CLK1
FBC_CLK1*
FBC_WCK01
FBC_WCK01*
SNN_FBC_WCKB01
SNN_FBC_WCKB01*
FBC_WCK23
FBC_WCK23*
SNN_FBC_WCKB23
SNN_FBC_WCKB23*
FBC_WCK45
FBC_WCK45*
SNN_FBC_WCKB45
SNN_FBC_WCKB45*
FBC_WCK67
FBC_WCK67*
SNN_FBC_WCKB67
SNN_FBC_WCKB67*
1V8_FB_PLL 1V8_FB_PLL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
50OHM_NETCLASS1
50OHM_NETCLASS1
C728
0.1uF
16V
10%
X7R
0402
COMMON
FBC_CMD[31..0]
IN
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
TP503
TP502
GND
R574
10k
5 %
0402
FBC_CMD1
FBC_CMD17
FBC_CMD2
FBC_CMD18
C E
COMMON
R583
10k
5 %
0402
COMMON
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
{4,10}
ASSEMBLY
PAGE DETAIL
FBVDD
GND
R575
10k
5 %
0402
COMMON
R582
10k
5 %
0402
COMMON
{11,12}
GDDR5 CMD Mapping
CMD
CMD1
CMD2
CMD3
CMD4
CMD5
CMD6
CMD7
CMD8
CMD9
CMD10
CMD11
CMD12
CMD13
CMD14
CMD15
CMD16
CMD17
CMD18
CMD19
CMD20 A1_A9
CMD21
CMD22
CMD23
CMD24
CMD25
CMD26
CMD27
CMD28
CMD29
CMD30
{11}
{11}
{12}
{12}
{11}
{11}
{11}
{11}
{12}
{12}
{12}
{12}
FBD_CMD1
FBD_CMD17
FBD_CMD2
FBD_CMD18
<ASSEMBLY_DESCRIPTION>
GPU FB_CD
CAS*CMD0
CKE*
RST*
RAS*
A1_A9
A0_A10
A12_RFU
ABI*
A6_A11
A7_A8
WE*
A5_BA1
A4_BA2
A2_BA0
A3_BA3
CS*
R626
10k
5 %
0402
COMMON
R599
10k
5 %
0402
COMMON
G1E
BGA2152
AK8
AK4
AK2
AK3
AK5
AK6
AK9
AK7
AG4
AF9
AG6
AG7
AG5
AA6
AA5
AC5
AC4
AD7
AC6
AF6
AD6
AF7
AF8
AF2
AF3
AG1
AA7
AD5
AG2
AA9
AF4
AJ4
AJ5
AJ6
Y6
Y5
V5
Y4
F4
E1
F3
F5
D2
D1
C3
C2
J5
J4
L8
J2
F1
F2
H4
H5
V7
V8
V6
V9
U4
R5
R6
U8
P6
R9
P4
P5
L7
L6
L4
L5
AJ1
D3
H3
U5
M9
AJ3
E3
H2
U6
M5
Y33
Y34
Y35
Y36
Y37
Y38
Y39
Y9
COMMON
5/23 FBD
FBD_D0
FBD_D1
FBD_D2
FBD_D3
FBD_D4
FBD_D5
FBD_D6
FBD_D7
FBD_D8
FBD_D9
FBD_D10
FBD_D11
FBD_D12
FBD_D13
FBD_D14
FBD_D15
FBD_D16
FBD_D17
FBD_D18
FBD_D19
FBD_D20
FBD_D21
FBD_D22
FBD_D23
FBD_D24
FBD_D25
FBD_D26
FBD_D27
FBD_D28
FBD_D29
FBD_D30
FBD_D31
FBD_D32
FBD_D33
FBD_D34
FBD_D35
FBD_D36
FBD_D37
FBD_D38
FBD_D39
FBD_D40
FBD_D41
FBD_D42
FBD_D43
FBD_D44
FBD_D45
FBD_D46
FBD_D47
FBD_D48
FBD_D49
FBD_D50
FBD_D51
FBD_D52
FBD_D53
FBD_D54
FBD_D55
FBD_D56
FBD_D57
FBD_D58
FBD_D59
FBD_D60
FBD_D61
FBD_D62
FBD_D63
FBD_DQM0
FBD_DQM1
FBD_DQM2
FBD_DQM3
FBD_DQM4
FBD_DQM5
FBD_DQM6
FBD_DQM7
FBD_DQS_WP0
FBD_DQS_WP1
FBD_DQS_WP2
FBD_DQS_WP3
FBD_DQS_WP4
FBD_DQS_WP5
FBD_DQS_WP6
FBD_DQS_WP7
GND
GND
GND
GND
GND
GND
GND
GND
GP104
FBD
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30
FBD_CMD31
FBD_CMD32
FBD_CMD33
FBD_CMD34
FBD_CMD35
FBD_DBG_RFU1
FBD_DBG_RFU2
FBD_CLK0
FBD_CLK0
FBD_CLK1
FBD_CLK1
FBD_WCK01
FBD_WCK01
FBD_WCKB01
FBD_WCKB01
FBD_WCK23
FBD_WCK23
FBD_WCKB23
FBD_WCKB23
FBD_WCK45
FBD_WCK45
FBD_WCKB45
FBD_WCKB45
FBD_WCK67
FBD_WCK67
FBD_WCKB67
FBD_WCKB67
FBD_PLL_AVDD
GP106
UNUSED
AD2
AD1
AD4
AC1
AC2
AC3
AA3
AA2
AA1
AA4
Y1
Y2
Y3
V3
V2
V1
L3
L2
L1
M4
M1
M2
M3
P3
P2
P1
R4
R1
R2
R3
U3
U2
U1
V4
AD3
J3
AC9
P9
Y8
Y7
R8
R7
AJ8
AJ7
AG8
AG9
AD8
AD9
AC7
AC8
J6
J7
H7
H6
P8
P7
M7
M8
V11
FBD_CMD0
FBD_CMD1
FBD_CMD2
FBD_CMD3
FBD_CMD4
FBD_CMD5
FBD_CMD6
FBD_CMD7
FBD_CMD8
FBD_CMD9
FBD_CMD10
FBD_CMD11
FBD_CMD12
FBD_CMD13
FBD_CMD14
FBD_CMD15
FBD_CMD16
FBD_CMD17
FBD_CMD18
FBD_CMD19
FBD_CMD20
FBD_CMD21
FBD_CMD22
FBD_CMD23
FBD_CMD24
FBD_CMD25
FBD_CMD26
FBD_CMD27
FBD_CMD28
FBD_CMD29
FBD_CMD30
FBD_CMD31
SNN_FBD_CMD<32>
SNN_FBD_CMD<33>
FBD_DEBUG0
FBD_DEBUG1
SNN_FBD_DBG_RFU1
SNN_FBD_DBG_RFU2
FBD_CLK0
FBD_CLK0*
FBD_CLK1
FBD_CLK1*
FBD_WCK01
FBD_WCK01*
SNN_FBD_WCKB01
SNN_FBD_WCKB01*
FBD_WCK23
FBD_WCK23*
SNN_FBD_WCKB23
SNN_FBD_WCKB23*
FBD_WCK45
FBD_WCK45*
SNN_FBD_WCKB45
SNN_FBD_WCKB45*
FBD_WCK67
FBD_WCK67*
SNN_FBD_WCKB67
SNN_FBD_WCKB67*
GND
C681
0.1uF
16V
10%
X7R
0402
COMMON
FB_DATA
FBD_D[63..0]
BI
32..630..31
CAS*
CKE*
RST*
RAS*
A0_A10
A12_RFU
ABI*
A6_A11
A7_A8
WE*
A5_BA1
A4_BA2
A2_BA0
A3_BA3
CS*CMD31
FB_DBI
FBD_DBI[7..0]
OUT
FB_EDC
FBD_EDC[7..0]
OUT
FBVDD
R600
10k
5 %
0402
COMMON
R627
10k
5 %
0402
COMMON
FBD_D0
0
FBD_D1
1
FBD_D2
2
FBD_D3
3
FBD_D4
4
FBD_D5
5
FBD_D6
6
FBD_D7
7
FBD_D8
8
FBD_D9
9
FBD_D10
10
FBD_D11
11
FBD_D12
12
FBD_D13
13
FBD_D14
14
FBD_D15
15
FBD_D16
16
FBD_D17
17
FBD_D18
18
FBD_D19
19
FBD_D20
20
FBD_D21
21
FBD_D22
22
FBD_D23
23
FBD_D24
24
FBD_D25
25
FBD_D26
26
FBD_D27
27
FBD_D28
28
FBD_D29
29
FBD_D30
30
FBD_D31
31
FBD_D32
32
FBD_D33
33
FBD_D34
34
FBD_D35
35
FBD_D36
36
FBD_D37
37
FBD_D38
38
FBD_D39
39
FBD_D40
40
FBD_D41
41
FBD_D42
42
FBD_D43
43
FBD_D44
44
FBD_D45
45
FBD_D46
46
FBD_D47
47
FBD_D48
48
FBD_D49
49
FBD_D50
50
FBD_D51
51
FBD_D52
52
FBD_D53
53
FBD_D54
54
FBD_D55
55
FBD_D56
56
FBD_D57
57
FBD_D58
58
FBD_D59
59
FBD_D60
60
FBD_D61
61
FBD_D62
62
FBD_D63
63
FBD_DBI0
0
FBD_DBI1
1
FBD_DBI2
2
FBD_DBI3
3
FBD_DBI4
4
FBD_DBI5
5
FBD_DBI6
6
FBD_DBI7
7
FBD_EDC0
0
FBD_EDC1
1
FBD_EDC2
2
FBD_EDC3
3
FBD_EDC4
4
FBD_EDC5
5
FBD_EDC6
6
FBD_EDC7
7
GND
GND
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
FDBA
G
property to Galaxy Microsystems (HK) Ltd.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
50OHM_NETCLASS1
50OHM_NETCLASS1
IN
FB_CMD
FBD_CMD[31..0]
P45U
P45U
P45U
OUT
TP509
TP506
FB_CLK
FB_CLK
FB_CLK
FB_CLK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
FB_WCK
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
{4,10}
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
GPU FB_CD
GPU FB_CD
GPU FB_CD
Design By:
Design By:
Design By:
Carson V10
Carson V10
Carson V10
10 37Thursday, December 28, 2017
10 37Thursday, December 28, 2017
10 37Thursday, December 28, 2017
H
1
2
3
4
5
A B C D E F G H
smd.db-x7.ru
Page11: Frame Buffer Partition C [31:0]
1
M5B
@memory.u_mem_sd_ddr5_x32(sym_5):page11_i1415
FBC_CMD[31..0]
IN
FBC_D[31..0]
BI
{10,12}
{10,12}
2
3
FBC_EDC[7..0]
IN
FBC_DBI[7..0]
IN
{10}
{10}
{10}
0
FBC_D0
1
FBC_D1
2
FBC_D2
3
FBC_D3
4
FBC_D4
5
FBC_D5
6
FBC_D6
7
FBC_D7
0
0
1
IN
IN
FBC_EDC0
FBC_DBI0
FBC_D8
8
FBC_D9
9
FBC_D10
10
FBC_D11
11
FBC_D12
12
FBC_D13
13
FBC_D14
14
FBC_D15
15
FBC_EDC1
1
FBC_DBI1
FBC_WCK01
FBC_WCK01*
FB_DATA
FB_EDC
FB_DBI
M5D
@memory.u_mem_sd_ddr5_x32(sym_2):page11_i1353
BGA170_MIRR
COMMON
MIRRORED
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
EDC0
DBI0
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
EDC1
DBI1
WCK01
WCK01
x16x32
VREFD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
N11
N13
M11
M13
R13
V4
V2
T4
T2
N4
N2
M4
M2
R2
P2
V11
V13
T11
T13
P13
P4
P5
V10
SNN_FBA_VREFD_M5_0
M5A
@memory.u_mem_sd_ddr5_x32(sym_4):page11_i1412
BGA170_MIRR
COMMON
MIRRORED
FBC_D16
16
FBC_D17
17
FBC_D18
18
FBC_D19
19
FBC_D20
20
FBC_D21
21
FBC_D22
22
FBC_D23
23
FBC_EDC2
2
2
3
{10}
{10}
IN
IN
FBC_DBI2
FBC_D24
24
FBC_D25
25
FBC_D26
26
FBC_D27
27
FBC_D28
28
FBC_D29
29
FBC_D30
30
FBC_D31
31
FBC_EDC3
3
FBC_DBI3
FBC_WCK23
FBC_WCK23*
{5,7,24}
x32 x16
A11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
EDC2
DBI2
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
VREFD
IN
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
SNN_FBA_VREFD_M5_1
A10
GPIO10_FBVREF_SEL
OUT
FBC_VREFC_Q
3
D
Q32
@discrete.q_fet_n_enh(sym_2):page11_i1237
SOT23_1G1D1S
G
1
COMMON
S
2
1G1D1S
GND
{10}
{10}
FBC_VREFC
{12}
R133
931ohm
1 %
0402
COMMON
0.300
50V
0.22A
3500mohm@10V / 3500mohm@4.5V / 3500mohm@2.5V
0.22A
0.35W
20V
GND
FBVDD
R132
1.33k
1 %
0402
COMMON
IN
IN
R131
549ohm
1 %
0402
COMMON
A13
B11
B13
E11
E13
F11
F13
C13
D13
A4
A2
B4
B2
E4
E2
F4
F2
C2
D2
D4
D5
{10,12}
GND
FBC_CLK0
FBC_CLK0*
C194
820pF
50V
10%
X7R
0402
COMMON
FB_CMD
R586
40.2ohm
1 %
0402
COMMON
FBC_CLK0_RC
GND
C562
10nF
16V
10%
X7R
0402
COMMON
FBC_CMD3
3
FBC_CMD0
0
FBC_CMD10
10
FBC_CMD15
15
FBC_CMD7
7
FBC_CMD5
5
FBC_CMD4
4
FBC_CMD13
13
FBC_CMD14
14
FBC_CMD12
12
FBC_CMD11
11
FBC_CMD8
8
FBC_CMD9
9
FBC_CMD6
6
FBC_CMD2
2
FBC_CMD1
1
R590
40.2ohm
1 %
0402
COMMON
R577 121ohm
0402 COMMON
GND
1 %
SNN_FBC_RFU1_M1
SNN_FBC_RFU2_M1
FBC_ZQ0
BGA170_MIRR
COMMON
L3
RAS
G3
CAS
G12
WE
L12
CS
J4
ABI
K4
A0_A10
K5
A1_A9
K11
A2_BA0
K10
A3_BA3
H11
A4_BA2
H10
A5_BA1
H5
A6_A11
H4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
0.300
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
CONTAIN KNOWN AND UNKNOWN VIOLATIONS OR DEVIATIONS OF INDUSTRY STANDARDS AND SPECIFICATIONS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY OR OTHERWISE WITH RESPECT TO THE MATERIALS OR OTHERWISE, AND EXPRESSLY DISCLAIMS ALL
IMPLIED WARRANTIES INCLUDING, WITHOUT LIMITATION, THE WARRANTIES OF DESIGN, OF NONINFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, OR ARISING FROM A COURSE OF DEALING, TRADE USAGE, TRADE PRACTICE, OR INDUSTRY STANDARDS.
C E
ASSEMBLY
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
MEMORY: FBC[31:0]
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
FDBA
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBC[31:0]
MEMORY: FBC[31:0]
MEMORY: FBC[31:0]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
11 37Thursday, December 28, 2017
11 37Thursday, December 28, 2017
11 37Thursday, December 28, 2017
A B C D E F G H
smd.db-x7.ru
Page12: FRAME BUFFER PARTITION C [63:32]
1
M6B
FBC_CMD[31..0]
IN
FBC_D[63..32]
BI
{10,11}
2
{10,11}
FBC_EDC[7..0]
IN
FBC_DBI[7..0]
IN
{10}
32
33
34
35
36
37
38
39
4
4
40
41
42
43
44
45
46
47
3
{10}
{10}
5
5
IN
IN
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_EDC4
FBC_DBI4
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_EDC5
FBC_DBI5
FBC_WCK45
FBC_WCK45*
FB_DATA
FB_EDC
FB_DBI
M6D
@memory.u_mem_sd_ddr5_x32(sym_1):page12_i155
BGA170
COMMON
NORMAL
A4
DQ0
A2
DQ1
B4
DQ2
B2
DQ3
E4
DQ4
E2
DQ5
F4
DQ6
F2
DQ7
C2
EDC0
D2
DBI0
VREFD
x16
x32
A11
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
EDC1
DBI1
WCK01
WCK01
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
A13
B11
B13
E11
E13
F11
F13
C13
D13
D4
D5
M6A
@memory.u_mem_sd_ddr5_x32(sym_3):page12_i156
BGA170
COMMON
FBC_D48
48
FBC_D49
49
FBC_D50
50
FBC_D51
51
FBC_D52
52
FBC_D53
53
FBC_D54
54
FBC_D55
55
FBC_EDC6
6
SNN_FBA_VREFD_M6_0 SNN_FBA_VREFD_M6_1
A10
{10}
{10}
6
7
IN
IN
FBC_DBI6
FBC_D56
56
FBC_D57
57
FBC_D58
58
FBC_D59
59
FBC_D60
60
FBC_D61
61
FBC_D62
62
FBC_D63
63
FBC_EDC7
7
FBC_DBI7
FBC_WCK67
FBC_WCK67*
V11
V13
N11
N13
M11
M13
NORMAL
DQ16
DQ17
T11
DQ18
T13
DQ19
DQ20
DQ21
DQ22
DQ23
R13
EDC2
P13
DBI2
V10
VREFD
x16
x32
V4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
EDC3
DBI3
WCK23
WCK23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V2
T4
T2
N4
N2
M4
M2
R2
P2
P4
P5
{10}
{10}
IN
IN
IN
{10,11}
FBC_CLK1
FBC_CLK1*
FBC_VREFC
FB_CMD
R584
40.2ohm
1 %
0402
COMMON
FBC_CLK1_RC
GND
{11}
GND
C560
10nF
16V
10%
X7R
0402
COMMON
C196
820pF
50V
10%
X7R
0402
COMMON
FBC_CMD19
19
FBC_CMD16
16
FBC_CMD26
26
FBC_CMD31
31
FBC_CMD23
23
FBC_CMD21
21
FBC_CMD20
20
FBC_CMD29
29
FBC_CMD30
30
FBC_CMD28
28
FBC_CMD27
27
FBC_CMD24
24
FBC_CMD25
25
FBC_CMD22
22
FBC_CMD18
18
FBC_CMD17
17
R588
40.2ohm
1 %
0402
COMMON
SNN_FBC_RFU1_M3
SNN_FBC_RFU2_M3
0.300
GND
FBC_ZQ2
R578
121ohm
1 %
0402
COMMON
@memory.u_mem_sd_ddr5_x32(sym_5):page12_i157
BGA170
COMMON
G3
RAS
L3
CAS
L12
WE
G12
CS
J4
ABI
H4
A0_A10
H5
A1_A9
H11
A2_BA0
H10
A3_BA3
K11
A4_BA2
K10
A5_BA1
K5
A6_A11
K4
A7_A8
J5
RFU_A12
J2
RESET
J3
CKE
J12
CLK
J11
CLK
A5
NC_RFU_A5
V5
NC_RFU_V5
J14
VREFC
J13
ZQ
J10
SEN
1
2
3
4
5
ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS OR INFORMATION (TOGETHER AND SEPARATELY, 'MATERIALS') ARE BEING PROVIDED 'AS IS'. THE MATERIALS MAY
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C E
ASSEMBLY
PAGE DETAIL
<ASSEMBLY_DESCRIPTION>
MEMORY: FBC[63:32]
4
5
Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
Page Name:
Page Name:
Page Name:
Size Project Name: Rev
Size Project Name: Rev
Size Project Name: Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
PROPERTY NOTE: This document contains information confidential and
property to Galaxy Microsystems (HK) Ltd.
property to Galaxy Microsystems (HK) Ltd.
FDBA
G
property to Galaxy Microsystems (HK) Ltd.
Galaxy Microsystems (HK) Ltd.
MEMORY: FBC[63:32]
MEMORY: FBC[63:32]
MEMORY: FBC[63:32]
Design By:
Design By:
P45U
P45U
P45U
Design By:
H
Carson V10
Carson V10
Carson V10
12 37Thursday, December 28, 2017
12 37Thursday, December 28, 2017
12 37Thursday, December 28, 2017
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