FUJITSU SIEMENS XI1546, XI1547 Schematics
5
D D
Model : P72IA0
4
3
2
Revision History
09/2005
10/2005
RA
RB
1
Intel Yonah CPU + 945PM / ICH7-M Chipset
PG01 INDEX
PG02 SYSTEM BLOCK DIAGRAM
C C
PG03 POWER DIAGRAM & SEQUENCE
PG04 GPIO & POWER CONSUMPTION
PG05 CPU Yonah-1/2
PG06 CPU Yonah-2/2
PG07 CLOCK GEN ICS9LPR310
PG08 NB 945PM-HOST -1/5
PG09 NB 945PM VGA_PCIEXPR-2/5
PG10 NB 945PM DDR_MEM SYSTEM-3/5
PG11 NB 945PM POWER-4/5
PG12 NB 945PM VSS_NCTF-5/5
PG13 DDR2 CHANNELA,B
PG14 Terminatation / SMP / DC IN
B B
PG15 PWR S/W& LCD/INVERTOR/CRT/TV
PG16 SB ICH7-MDH -1/3
PG20 WIRELESS / NEW CARD / EMI
PG21 I/O PORT CON
PG22 AUD PWR / FAN CTL
PG23 GIGA LAN RTL8110SBL
PG24 IEEE1394A TSB43AB22A
PG25 EC IT8510E / BIOS / TP CON
PG26 VGA MXM CON
PG27 CPU_CORE ( ISL6262 )
PG28 1.05V/1.5V/1.8V/2.5V/0.9V
PG29 +3.3V/+5V/+12V
PG30 VCC SW/+1.05VS/+1.5VS
PG31 BATT IN / Charger
PG32 RAID IC VT6421
PG33 Appendix A. Ver. History
PG17 SB ICH7-MDH -2/3
PG18 SB ICH7-MDH -3/3
PG19 HDD / CD-ROM
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
UNIWILL COMPUTER CORP.
P72IA0
3220
INDEX
1
133Wednesday, October 19, 2005
B
of
5
4
3
2
1
SATA
P72IA0
D D
C C
Amplifier
LM4991
WOOFER
SPK
B B
BLOCK DIAGRAM
CRYSTAL
14.318MHz
Clock Gen
ICS
9LPR310-CLK
AUDIO CODEC
ALC880
AMPLIFIER
TPA6011A4
INTERNAL SPK
EARPHONE
JACK(SPDIF) X 1
MICPHONE JACK X
1
DDR2 RAM BUS
SODIMM1
+1.8VS
SODIMM0
+1.8VS
IEEE-1394A
TSB43AB22
533/667MHZ
AZALIA
MDC
RJ11
PCI BUS
SATA HDD X2
2.5"
CPU
Yonah
Socket 478
HOST BUS
667
MHZ
North Bridge
INTEL
945PM
DMI
South Bridge
INTEL
ICH7-M
RTC
THERMAL
ADM1032
PCIE
x16
IDE
PCIE X1
PCIE X1
PCIE X1
USBX8
USB CONN x3
ATI
M58
CD-ROM
Vidalia
GIGA LAN
(82573L)
Mini
Card
NEW CARD
SATA
EC
LVDS
TMDS&CRT
+5V
CRYSTAL
Buletooth
MASTER HDD
SECONDARY HDD
S-Video
LCD
DVI
RJ45
25M HZ
CARD READER
+5V
+5V
DC_IN BD X2
CRYSTAL
24.576M HZ
SMBus Diagram
LPC BUS
CRYSTAL
MASTER
EC
K/B CONTROLLER
ITE8510
PS/2 & GPIO
A A
FLASH ROM
5
4
T/PINT K/B
3
CHARGERFAN
32.768K
PS/2 & GPIO
REMOTE IR
BATTERY
2
South
Bridge
SMBus 1
KBC
SMBus 2
Title
Size Document Number Rev
Date: Sheet
UNIWILL COMPUTER CORP.
SYSTEM BLOCK DIAGRAM
3220
DDR DIMM
Clock Gen
Thermal Sensor for CPU
BATTERY
P72IA0
1
233Wednesday, October 19, 2005
B
of
5
4
3
2
1
POWER BLOCK DIAGRAM
VID0
VID1
D D
VID2
VID3
ISL 6262
VID4
VIN
RQA130
RQW220
CPU_CORE
OZ818 RSS090N03
VIN
VID5
+1.8VS
RT9173B
AO4422
+0.9VS
+1.8V
VID6
VIN
RSS090N03
C C
SC1404
+12VA
SI2301
VIN
RSS090N03
B B
VIN
OZ813
RSS090N03
VIN
RSS090N03
A A
+5VA
+3.3VA
+1.5VS
+1.05VS
SI4835
+12VS
AO4422
AO4422
SI4835
AO4422
AO4422
+5VS
+5V
+3.3VS
+3.3V
RT9173B
+1.5V
+2.5VS
+1.05V
POWER Sequence
+3VA,+5VA,+12VA
PWRSW
.
+3.3VS_ON
+5VS,+12VS
+3.3VS
+1.5VS_ON
.
+1.05VS_ON
.
+1.8V_DDR_ON
.
+1.5VS
+1.05VS
+1.8VS
RSMRST#
.
.
PWRBTN#
.
+5V_ON
+5V
+3.3V
+2.5V
+1.8V_ON
.
+1.8V
+1.05V
+1.5V
.
Vcore_ON
Vcore
PWROK
.
H_PWRGD
PCIRST#/PLTRST#
CPURST#
+3.3VS_ON
+3.3VS_ON
+5V_ON
+5V_ON
+1.8V_ON
+1.8V_ON
+1.8V_ON
120ms
60ms
20ms
100ms
?ms
EC debouns 100ms
880ms
?ms
?ms
5ms
300ms
.
EC Control Pin
5
4
3
2
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
C
3220
Date: Sheet
P72IA0
POWER DIAGRAM
1
of
333Wednesday, October 19, 2005
B
5
4
3
2
1
ICH6-M
GPIO
BM_BUSY#
GPI0
GP7
EC_EXTSMI#
GP8
SMB_ALERT#
GPI11
D D
C C
B B
GPI12
GPI13
GPO18
GPO19
GPO20
GPO21
GPO23
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
PM_STPPCI_ICH#
PM_STPCPU_ICH#
TPM_EN
SATA0_GP
PNLSW1
PNLSW2
PNLSW0
PM_CLKRUN#
ITE8510E
GPIO
GPCF0
RF_SW#
GPCF1
SILENT#/
GPCF2
IR_PS2CLK1
GPCF3
IR_PS2DAT1
GPCF4
TP_CLK
GPCF5
TP_DATA
MAIL#
GPCF6
BROWSER#
GPCF7
GPI0
SCROLL#
GPI1
CAPS#
GPI2
NUM#
GPI3
CHG_R_LED#
CHG_G_LED#
GPI4
GPI5
SUSLED_LED#
GPI6
VOLMAX
GPH0
+1.8V_DDR_ON
+1.8V_ON
GPH1
GPH2
+1.05VS_ON
GPH3
+3.3VS_ON
+5V_ON
GPH4
GPH5
SET_V
GPH6
+1.5VS_ON
VCORE_ON
GPH7
GPG4
TP_DISABLE
LCDSW
GPG5
GPG6
MUTE#
GPG7
EXTTS#0
CELERON_VO_DET
GPB0
GPB1
CPPE#
PM_RSMRST#
GPB2
GPB3
BAT_SMBCLK
GPB4
BAT_SMBDAT
H_A20GATE
GPB5
H_RCIN#
GPB6
GPB7
RFLED_ON#
GPE0
NA
CPU_BSEL0
GPE1
GPE2
NA
GPE3
NA
GPE4
PWRSW
GPE5
LID#
GPE6
PCM#
PM_SLP_S3#
GPE7
GPD0
ADAP_IN
GPD1
REMOTE_ON#
PCI_RST#/PLT_RST#
GPD2
GPD3
EC_EXTSMI#
GPD4
PM_SLP_S4#
GPD5
PM_THROTTLING#
FAN_SPD#
GPD6
EC_PREST#
GPD7
BTL_BEEP
GPA0
EC_VID1
GPA1
GPA2
EC_VID2
GPA3
EC_VID3
GPA4
EC_VID4
GPA5
SMP1_EN#
GPA6
SMP2_EN#
GPA7
PWRBTN#
GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
ADC0
ADC1
ADC2
ADC3
DAC0
DAC1
DAC2
DAC3
ITE8510E
GPIO
PWROK
BAT2_SMBCLK
BAT2_SMBDAT
SB_ALERT#1
SB_ALERT#2
TP_LED#
CHG_ON
SILENT_LED#
BAT_TEMP
ADAPTOR_I
DDR2_TEMP
VGA_TEMP
BRIGHTADJ
CHG_I
FAN_CTRL0
NA
CPU CORE(V)
2.0G
2.2G
2.26G
2.4G
2.5G
2.53G
2.6G
2.66G
2.8G
3.06G
VCC
+3.3V
+3.3VA
+2.5V
+1.5V
+VCCP
+VCC_GMCH_CORE
VCC
+3.3V
+3.3VA
+1.5V
+1.5VA
+3.3VA_RTC
CPU
ICC(mA)
1.525
1.525
1.525
1.525
1.525
1.525
1.525
1.525
1.525
1.525
35.7
37.5
38.1
39.3
40
40.4
41.05
43.35
44.86
55.9
MCHE
ICC(mA)
108.19
501.3
1390
33.4
10
266
ICH6-M
ICC(mA) W
275
487
27
0.003
W
0.357
1.254
2.502
0.084
0.018
0.452
0.315
0.909
0.876
0.049
0.00001
W
54.3
57.1
58.0
59.8
61.0
61.5
62.6
66.1
68.4
85.2
TEMP( )
70
TEMP( )
70
TEMP( )
℃
69
70
70
71
72
72
72
74
75
81
℃
℃
VCC
+3.3V
VCC
+3.3V
VCC
+3.3V(DVDD)
VCC
3.3V9630
VCC
+3.3V
ITE8510E
ICC(mA)
300
W
1
CLOCK GENERATOR
ICC(mA)
180
W
0.594
ALC880
ICC(mA)
W
0.234
71
TPA6011A4
ICC(mA)
W
0.099W
ADM1032
ICC
170uA
W
0.56mW
TEMP( )
℃
70
℃
TEMP( )
70
℃
TEMP( )
70
TEMP( )
℃
85
TEMP( )
℃
150
A A
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
C
3220
5
4
3
2
Date: Sheet
P72IA0
GPIO & POWER CONSU
1
B
of
433Wednesday, October 19, 2005
5
H_A#[31:3]8
D D
H_ADSTB#08
H_REQ#[4:0]8
H_A#[31:3]8
C C
B B
H_ADSTB#18
H_A20M#16
H_FERR#16
H_STPCLK#16
H_IGNNE#16
H_INTR16
H_NMI16
H_SMI#16
R26 0
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
Z0505
AA1
AA4
AB2
AA3
B25
J4
L4
M3
K5
M1
N2
J1
N3
P5
P2
L1
P4
P1
R1
L2
K3
H2
K2
J3
L5
Y2
U5
R3
W6
U4
Y5
U2
R4
T5
T3
W3
W5
Y4
W2
Y1
V4
A6
A5
C4
D5
C6
B4
A3
M4
N5
T2
V3
B2
C3
U4-1
A{3}#
A{4}#
A{5}#
A{6}#
A{7}#
A{8}#
A{9}#
A{10}#
A{11}#
A{12}#
A{13}#
A{14}#
A{15}#
A{16}#
ADSTB{0}#
REQ{0}#
REQ{1}#
REQ{2}#
REQ{3}#
REQ{4}#
A{17}#
A{18}#
A{19}#
A{20}#
A{21}#
A{22}#
A{23}#
A{24}#
A{25}#
A{26}#
A{27}#
A{28}#
A{29}#
A{30}#
A{31}#
ADSTB{1}#
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
RSVD{01}
RSVD{02}
RSVD{03}
RSVD{04}
RSVD{05}
RSVD{06}
RSVD{07}
RSVD{08}
RSVD{09}
RSVD{10}
RSVD{11}
I24074326
ADDR GROUP 0 ADDR GROUP 1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
CONTROL
LOCK#
RESET#
RS{0}#
RS{1}#
RS{2}#
TRDY#
HITM#
BPM{0}#
BPM{1}#
BPM{2}#
BPM{3}#
PRDY#
PREQ#
XDP/ITP SIGNALS
TRST#
DBR#
PROCHOT#
THERMDA
THERMDC
THERM
THERMTRIP#
BCLK{0}
BCLK{1}
H CLK
RSVD{12}
RSVD{13}
RSVD{14}
RSVD{15}
RSVD{16}
RSVD{17}
RESERVED
RSVD{18}
RSVD{19}
RSVD{20}
HIT#
TCK
TDO
TMS
H1
E2
G5
H5
F21
E1
F1
H_IERR#
D20
B3
H4
H_CPURST#
B1
H_RS#0
F3
H_RS#1
F4
H_RS#2
G3
G2
G6
E4
AD4
AD3
AD1
AC4
AC2
Z0506
AC1
TCK
AC5
TDI
AA6
TDI
TDO
AB3
TMS
AB5
TRST#
AB6
C20
H_PROCHOT#
D21
H_THERMDA
A24
H_THERMDC
A25
PM_THRMTRIP#
C7
A22
A21
T22
D2
F6
D3
C1
AF1
D22
C23
C24
CPU Thermal Sensor
+3.3V
R412 200_1
2.2U_6.3V_X5R
H_THERMDA
H_THERM#
C451
H_THERMDC
2200p
A A
C459
Z0511
1
U22
2
D+
4
THERM#
3
D-
5
VDD
GND
ADM1032
5
ADATA
SCLK
ALERT
7
8
6
SMBDAT_EC 7,25
SMBCLK_EC 7,25
PSB533
PSB667
4
H_ADS# 8
H_BNR# 8
H_BPRI# 8
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
H_BREQ#0 8
H_INIT# 16
H_LOCK# 8
H_CPURST# 8
H_TRDY# 8
H_HIT# 8
H_HITM# 8
PM_THRMTRIP# 9,16
CLK_CPU_BCLK 7
CLK_CPU_BCLK# 7
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
4
H_RS#[2:0]
+1.05V
R18
56_OP
R55 0
R56 0
R66 0
BSEL2
H_RS#[2:0] 8
Close to NB
+1.05V
R96
1K
R100 1K
+1.05V
R111
1K
R110 1K
+1.05V
R107
1K
R108 1K
BSEL1 BSEL0
0
0
11
3
H_D#[63:0]8
H_DSTBN#08
H_DSTBP#08
H_DINV#08
+1.05V
R407
1K_1
R408
2K_1
CLK_BSEL0 7
MCH_BSEL0 9
MCH_BSEL1 9
CLK_BSEL1 7
MCH_BSEL2 9
CLK_BSEL2 7
MHZ
10
133
DK_MXM_THERM#26
H_DSTBN#18
H_DSTBP#18 H_DSTBP#3 8
H_DINV#18
Layout note: 0.5"
max length.
CPU_BSEL125
PM_THRMTRIP#
H_THERM#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_GTLREF
R70 1K_OP
R69 51_1
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
R386 1K
R375 0
R374 0
TEST1
TEST2
U4-2
E22
D{0}#
F24
D{1}#
E26
D{2}#
H22
D{3}#
F23
D{4}#
G25
D{5}#
E25
D{6}#
E23
D{7}#
K24
D{8}#
G24
D{9}#
J24
D{10}#
J23
D{11}#
H26
D{12}#
F26
D{13}#
K22
D{14}#
H25
D{15}#
H23
DSTBN{0}#
G22
DSTBP{0}#
J26
DINV{0}#
N22
D{16}#
K25
D{17}#
P26
D{18}#
R23
D{19}#
L25
D{20}#
L22
D{21}#
L23
D{22}#
M23
D{23}#
P25
D{24}#
P22
D{25}#
P23
D{26}#
T24
D{27}#
R24
D{28}#
L26
D{29}#
T25
D{30}#
N24
D{31}#
M24
DSTBN{1}#
N25
DSTBP{1}#
M26
DINV{1}#
AD26
GTLREF
C26
TEST1
D25
TEST2
B22
BSEL{0}
B23
BSEL{1}
C21
BSEL{2}
I24075270
H_DPRSTP# Layout
routing is
ICH-7 -> CPU -> IMVP-6
sequency
CPU_CORE
Z0507
B
C433
0.1u_Y5V
+3.3V
R373
100K
Z0509
B
C419
0.1u_Y5V
166
3
E C
E C
R385
100K
Z0508
Q55
2N3904
R369
100K
Z0510
Q50
2N3904
2
D{32}#
D{33}#
D{34}#
D{35}#
D{36}#
DATA GRP 3
DATA GRP 2
D{37}#
D{38}#
D{39}#
D{40}#
D{41}#
D{42}#
D{43}#
D{44}#
D{45}#
D{46}#
D{47}#
DSTBN{2}#
DSTBP{2}#
DINV{2}#
D{48}#
D{49}#
D{50}#
D{51}#
D{52}#
D{53}#
D{54}#
D{55}#
D{56}#
D{57}#
D{58}#
D{59}#
D{60}#
D{61}#
D{62}#
D{63}#
DSTBN{3}#
DSTBP{3}#
DINV{3}#
COMP{0}
COMP{1}
COMP{2}
COMP{3}
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PS1#
DATA GRP 0
DATA GRP 1
MISC
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20
R26
U26
U1
V1
E5
B5
D24
D6
D7
AE6
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
COMP0
COMP1
COMP2
COMP3
R413 27.4_1
R414 54.9_1
R359 27.4_1
R360 54.9_1
H_D#32
AA23
H_D#[63:0] 8
H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[63:0] 8H_D#[63:0]8
H_DSTBN#3 8
H_DINV#3 8
H_DPRSTP# 16,27
H_DPSLP# 16
H_DPWR# 8
H_PWRGD 16
H_CPUSLP# 8,16
H_PSI# 27
1
For current return path
+1.05V
C74
C70
1000P
AUX_OFF# 29
Q54
B
2N3904
E C
C432
1u/10V
Q51
B
2N3904
E C
C401
1u/10V
Title
Size Document Number Rev
3220
2
Date: Sheet
H_IERR#
H_PROCHOT#
H_STPCLK#
TDO
TMS
TDI
H_CPURST#
TRST#
TCK
UNIWILL COMPUTER CORP.
CPU Yonah-1/2
1000P
P72IA0
C90
1000P_0402
Close
CPU
R61 56
R62 56
R366 150_1
R20 54.9_1_OP
R35 39.2_1_OP
R36 150_1_OP
R23 54.9_1_OP
R38 680
R32 27.4_1
1
+1.05V
533Wednesday, October 19, 2005
B
of
5
4
3
2
1
CPU_CORE
U4-3
A7
VCC001
A9
VCC002
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AC10
AB10
AB12
AB14
AB15
AB17
AB18
A10
A12
A13
A15
A17
A18
A20
B10
B12
B14
B15
B17
B18
B20
C10
C12
C13
C15
C17
C18
D10
D12
D14
D15
D17
D18
E10
E12
E13
E15
E17
E18
E20
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AB9
B7
B9
C9
D9
E7
E9
F7
F9
VCC003
VCC004
VCC005
VCC006
VCC007
VCC008
VCC009
VCC010
VCC011
VCC012
VCC013
VCC014
VCC015
VCC016
VCC017
VCC018
VCC019
VCC020
VCC021
VCC022
VCC023
VCC024
VCC025
VCC026
VCC027
VCC028
VCC029
VCC030
VCC031
VCC032
VCC033
VCC034
VCC035
VCC036
VCC037
VCC038
VCC039
VCC040
VCC041
VCC042
VCC043
VCC044
VCC045
VCC046
VCC047
VCC048
VCC049
VCC050
VCC051
VCC052
VCC053
VCC054
VCC055
VCC056
VCC057
VCC058
VCC059
VCC060
VCC061
VCC062
VCC063
VCC064
VCC065
VCC066
VCC067
I24088053
D D
C C
B B
VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099
VCC100
VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCSENSE
VSSSENSE
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
B26
AD6
AF5
AE5
AF4
AE3
AF2
AE2
AF7
AE7
CPU_CORE
Z0601
+1.05V
H_VID0 14
H_VID1 14
H_VID2 14
H_VID3 14
H_VID4 14
H_VID5 14
H_VID6 14
+1.5V
B4
0
Close to Pin
C73
C75
4.7U_10V_0805
VCORE_VCCSENSE 27 VCORE_C- 27
VCORE_VSSSENSE 27
0.01u
CPU_CORE
C417
+
C28
4.7U_10V_0805
C411
4.7U_10V_0805
C439
1u/10V
C37
1u/10V
C45
1000P
C425
0.1u_Y5V
+
220U_2V_POS_OP
4.7U_10V_0805
C408
1u/10V
C430
1u/10V
0.1u_Y5V
C429
220U_2V_POS
C414
4.7U_10V_0805
C55
C30
1u/10V
C32
1u/10V
C423
1000p
C427
4.7U_10V_0805
C44
1u/10V
C436
C438
1000p
C397
0.1u_Y5V
JP5 CLOSE
JP6 CLOSE
C20
4.7U_10V_0805
C412
C48
1u/10V
1u/10V
1u/10V
C406
1000p
C399
0.1u_Y5V
12
12
4.7U_10V_0805
4.7U_10V_0805
C43
1u/10V
C442
C29
1000P
0.1u_Y5V
C54
C409
C407
1u/10V
C448
1u/10V
C416
1000p
C395
0.1u_Y5V
VCORE_C+ 27
C40
4.7U_10V_0805
4.7U_10V_0805
C47
1u/10V
C62
0.1u_Y5V
C437
1000p
C410
C46
1u/10V
C50
C435
4.7U_10V_0805
C24
4.7U_10V_0805
C21
1u/10V
C413
C25
1000p
1000P
more than P71
C65
0.1u_Y5V
C31
1000P
Modify 10
QT1608GRL600 = 200mA
QT1608RL120 = 200mA
QT1608RL600 = 200 mA
QT1608RL030 = 500mA
QT1608RL060 = 500mA
G23
G26
H21
H24
K23
K26
M22
M25
N23
N26
A11
A14
A16
A19
A23
A26
B11
B13
B16
B19
B21
B24
C11
C14
C16
C19
C22
C25
D11
D13
D16
D19
D23
D26
E11
E14
E16
E19
E21
E24
F11
F13
F16
F19
F22
F25
J22
J25
L21
L24
A4
A8
B6
B8
C5
C8
C2
D1
D4
D8
E3
E6
E8
F5
F8
F2
G4
G1
H3
H6
J2
J5
K1
K4
L3
L6
M2
M5
N1
N4
P3
U4-4
VSS001
VSS002
VSS003
VSS004
VSS005
VSS006
VSS007
VSS008
VSS009
VSS010
VSS011
VSS012
VSS013
VSS014
VSS015
VSS016
VSS017
VSS018
VSS019
VSS020
VSS021
VSS022
VSS023
VSS024
VSS025
VSS026
VSS027
VSS028
VSS029
VSS030
VSS031
VSS032
VSS033
VSS034
VSS035
VSS036
VSS037
VSS038
VSS039
VSS040
VSS041
VSS042
VSS043
VSS044
VSS045
VSS046
VSS047
VSS048
VSS049
VSS050
VSS051
VSS052
VSS053
VSS054
VSS055
VSS056
VSS057
VSS058
VSS059
VSS060
VSS061
VSS062
VSS063
VSS064
VSS065
VSS066
VSS067
VSS068
VSS069
VSS070
VSS071
VSS072
VSS073
VSS074
VSS075
VSS076
VSS077
VSS078
VSS079
VSS080
VSS081
I24089147
VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098
VSS099
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24
A A
5
4
+1.05V
C183
0.1u_Y5V
C181
0.1u_Y5V
C57
0.1u_Y5V
C58
0.1u_Y5V
C14
0.1u_Y5V
3
C59
0.1u_Y5V
C15
0.1u_Y5V
C16
0.1u_Y5V
C17
0.1u_Y5V
C60
0.1u_Y5V
C19
4.7U_10V_0805
4.7U_10V_0805
C56
C53
4.7U_10V_0805
2
C18
4.7U_10V_0805
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P72IA0
CPU Yonah-2/2
1
633Wednesday, October 19, 2005
of
B
5
4
3
2
+3.3V
1
Reserved FOR EMI
C213
33p
PCI4
PCI3
PCI2
CLK_BSEL1
CLKBSEL0
PCICLK_1394_A24
TEST_PCI25
CLK_PCI_LPC25
CLK_PCI17
PCICLK_LAN23
PCICLK_RAID32
CLK_ICH1417
CLK_USB4817
CLKBSEL2
CLKBSEL1
XTAL_OUT
XTAL_IN
SATA_CLKP16
SATA_CLKN16
MINICARD_CLK_REQ#20
Ce = 2*CL - ( Cs + Ci )
CL = Crystal Load Cap = 20P
Ci = IC internal Cap = 5P
Cs = 2P
Ce = Crystal external Cap = 33P
C194
0.1u_Y5V
R176 33
R168 33
C206 10p_OP
D D
SELDOT , 1= Pin 14/15 DOT 96MHZ , Pin 17/18 LCDCLK
0= Pin 14/15 27MHZ Fix/SS Pin 17/18 PCIEX
C C
CLK_BSEL25
CLK_BSEL15
CLK_BSEL05
C598 10p_OP
C208 10p_OP
C201 10p_OP
C198 10p_OP
Bsel [0,2]
Vil = 0.3
Vih = 0.7
R513 2.2K
R510 2.2K
R175 2.2K_OP
R171 100
+3.3V
Modify 8
B B
Y2
14.318MHz_DIP
R185 10M_OP
C212
33p
CLK_VDDA
R161
2.2
VDD_A_CR
C195
4.7U_10V_0805
R512 33
R639 33
R528 33
R179 33
R1059 33
R1060 33
R151 22
R152 22
C187
C185
0.1u_Y5V
0.1u_Y5V
PCI-E
Power
42 56
50 45
PCI4
Z0702
PCI3
PCI2
64
CLKBSEL2
CLKBSEL1
CLKBSEL0
CLKGEN_DATA
CLKGEN_CLK
XTAL_OUT
XTAL_IN
REQ1# = PCI-E 0,6
REQ2# = PCI-E 1,8
REQ3# = PCI-E 2,4
REQ4# = PCI-E 3,5,7
Z0711
Z0712
IREF
R487
4.3K_1
61
60
12
55
54
17
18
26
27
33
32
34
16
57
58
47
C186
0.1u_Y5V
0.1u_Y5V
U29
VDDPCIEX VDDREF
VDDCPU VDDA
5
PCICLK3
4
PCICLK2_2X
3
PCICLK1_2X
PCICLK0_2X
9
SELDOT/ PCICLK_F1
8
PCICLK_F0
FLSC/REF1
FLSB/REF0
FLSA/USB_48M_2X
SDATA
SCLK
LCD_SSCGT/PCIEXOT
LCD_SSCGC/PCIEXOC
SATACLKT
SATACLKC
PEREQ4#
PEREQ3#
PEREQ2#
PEREQ1#
X2_OUT
X1_IN
VREF
9LPR310-CLK
261321293753
GND
7
VDDPCI1
GND
GND
C190
GND
PCI
Power
1
VDDPCI0
GND
GND
C188
4.7U_10V_0805
VDD48VDDPCIEX
PLL
Power
PCI/PCIEX_STOP#
CPU_STOP#
CPUCLKT1
CPUCLKC1
CPUCLKT0
CPUCLKC0
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
PCIEXT3
PCIEXC3
PCIEXT4
PCIEXC4
PCIEXT5
PCIEXC5
PCIEXT6
PCIEXC6
PCIEXT7
PCIEXC7
PCIEXT8
PCIEXC8
DOTT_96M
DOTC_96M
VTT_PWRGD#/PD
GND
GND
59
GNDA
Z0703
Z0704
R180
0.1u_Y5V
2.2
1128
46
63
62
49
48
52
51
19
20
22
23
24
25
30
31
36
35
39
38
41
40
44
43
14
15
10
VDD_REF_CR
CLK_VDDA
Z0705
Z0706
CPU1
CPU#1
CPU0
CPU#0
PCIE5
PCIE#5
PCIE4
PCIE#4
PCIE3
PCIE#3
PCIE2
PCIE#2
Z0707
Z0708
Z0709
Z0710
GCLK => PCI-E & DMI (100MHZ)
DREFCLK => Dispaly PLLA ( nun- ss 96MHZ)
DRESSFCLK => Display LVDS PLLB ( ss 100MHZ)
C203
C199
4.7U_10V_0805_OP
Xtal
Power
R530 0
R523 0_OP
R497 22
R494 22
R165 22
R163 22
R160 22
R159 22
R493 22
R486 22
R483 22
R481 22
R479 22
R471 22
R480 22
R472 22
R484 22
R482 22
0.1u_Y5V
R178
1
Modify 3
C202 0.1u_Y5V
PM_STPPCI# 17
PM_STPCPU# 17
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5
GCLK 9
GCLK# 9
CLK_PCIE_NEW_CARD 20
CLK_PCIE_NEW_CARD# 20
CLK_PCIE_ICH 17
CLK_PCIE_ICH# 17
CLK_PCIE_MXM 26
CLK_PCIE_MXM# 26
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_Mini card 20
CLK_PCIE_Mini card# 20
C593
0.1u_Y5V
C603
200mA
B9
QT1608RL600
200mA
B10
QT1608RL600
C209
4.7U_10V_0805
+3.3V
R502
10K
6262CLK_EN# 27
BSEL2
A A
PSB533
PSB667
PSB533
PSB667
FS3FS4
00
0
00
01
01
FSLB
FSLC
0
01
0
01
1
01
FS3 , FS 4 SEETING BY I2C BUS ??????
5
FSLA
1
1
CPU
MHZ
133
166
133
166
PCI
MHZ
33 100
33
PCI-E
MHZ
100
SPREAD %
0.5% DOWN
+/- 0.25%
CENTER
4
SB_SMB_DATA13,17
SMBDAT_EC5,25
SMBCLK_EC5,25
SB_SMB_CLK13,17
R173 0_OP
R172 0
R169 0
R170 0_OP
3
CLKGEN_DATA
CLKGEN_CLK
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
2
Date: Sheet
P72IA0
CLOCK GEN ICS9LPR310
1
733Wednesday, October 19, 2005
B
of
BSEL0
BSEL1
5
4
3
2
1
U24J
AT23
VSS_180
AN23
VSS_181
AM23
VSS_182
AH23
VSS_183
AC23
VSS_184
W23
VSS_185
K23
VSS_186
J23
AA22
BA21
AV21
AR21
AN21
AL21
AB21
AW20
AR20
AM20
AA20
AN19
AC19
AH18
AY17
AR17
AP17
AM17
AK17
AV16
AN16
AL16
AN15
AM15
AK15
BA14
AT14
AK14
AD14
AA14
AV13
AR13
AN13
AM13
AL13
AG13
AY12
AC12
AD11
AA11
W19
M15
F23
C23
K22
G22
F22
E22
D22
A22
Y21
P21
K21
J21
H21
C21
K20
B20
A20
K19
G19
C19
P18
H18
D18
A18
J16
F16
C16
N15
L15
B15
A15
U14
K14
H14
E14
P13
F13
D13
B13
K12
H12
E12
Y11
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
CALISTOGA
VSS
D D
C C
B B
A A
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
VSS_351
VSS_352
VSS_353
VSS_354
VSS_355
VSS_356
VSS_357
VSS_358
VSS_359
VSS_360
J11
D11
B11
AV10
AP10
AL10
AJ10
AG10
AC10
W10
U10
BA9
AW9
AR9
AH9
AB9
Y9
R9
G9
E9
A9
AG8
AD8
AA8
U8
K8
C8
BA7
AV7
AP7
AL7
AJ7
AH7
AF7
AC7
R7
G7
D7
AG6
AD6
AB6
Y6
U6
N6
K6
H6
B6
AV5
AF5
AD5
AY4
AR4
AP4
AL4
AJ4
Y4
U4
R4
J4
F4
C4
AY3
AW3
AV3
AL3
AH3
AG3
AF3
AD3
AC3
AA3
G3
AT2
AR2
AP2
AK2
AJ2
AD2
AB2
Y2
U2
T2
N2
J2
H2
F2
C2
AL1
FSB I/O slew rate compensation
+1.05V
54.9_1
+1.05V
R87
R422
54.9_1
H_YSCOMPH_XSCOMP
Reference Voltage for RCOMP
+1.05V
R91
221_1
H_XSWING
C112
R92
0.1u_Y5V
100_1
+1.05V
R421
221_1
H_YSWING
C510
R420
0.1u_Y5V
100_1
Calibration FSB I/O Buffer
H_XRCOMP
R424
24.9_1
24.9_1
H_YRCOMP
R419
H_D#[63:0]5
CLK_MCH_BCLK7
CLK_MCH_BCLK#7
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
W11
AA10
AC9
AB11
AC11
AC2
AD1
AD9
AC1
AD7
AC6
AD10
AD4
AC8
AG2
AG1
F1
J1
H1
J6
H3
K2
G1
G2
K9
K1
K7
J8
H4
J3
K11
G4
T10
T3
U7
U9
U11
T11
W9
T1
T8
T4
W7
U5
T9
W6
T5
AB7
AA9
W4
W3
Y3
Y7
W5
Y10
AB8
W2
AA4
AA7
AA2
AA6
Y8
AA1
AB4
AB3
AB5
E1
E2
E4
Y1
U1
W1
U24A
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING
H_CLKIN
H_CLKIN#
CALISTOGA
H9
H_A#_3
C9
H_A#_4
E11
H_A#_5
G11
H_A#_6
F11
H_A#_7
G12
H_A#_8
F9
H_A#_9
H11
H_A#_10
J12
H_A#_11
G14
H_A#_12
D9
H_A#_13
J14
H_A#_14
H13
H_A#_15
J15
H_A#_16
F14
H_A#_17
D12
H_A#_18
A11
H_A#_19
C11
H_A#_20
A12
H_A#_21
A13
H_A#_22
E13
H_A#_23
G13
H_A#_24
F12
H_A#_25
B12
H_A#_26
B14
H_A#_27
C12
H_A#_28
A14
H_A#_29
C14
H_A#_30
D14
H_A#_31
E8
H_ADS#
H_VREF
H_BNR#
H_BPRI#
H_BREQ#0
H_CPURST#
H_DBSY#
H_DEFER#
H_DPWR#
H_DRDY#
H_VREF
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_HIT#
H_HITM#
H_LOCK#
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
H_RS#_0
H_RS#_1
H_RS#_2
H_SLPCPU#
H_TRDY#
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13
J7
W8
U3
AB10
K4
T7
Y5
AC4
K3
T6
AA5
AC5
D3
D4
B3
D8
G8
B8
F8
A8
B4
E6
D6
H_CPUSLP#_GMCH
E3
E7
H_ADSTB#_0
H_ADSTB#_1
HOST
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5
H_BNR# 5
H_BPRI# 5
H_BREQ#0 5
H_CPURST# 5
H_DBSY# 5
H_DEFER# 5
H_DPWR# 5
H_DRDY# 5
H_DINV#[3:0] 5
H_DSTBN#[3:0] 5
H_DSTBP#[3:0] 5
H_HIT# 5
H_HITM# 5
H_LOCK# 5
H_REQ#[4:0] 5
H_RS#[2:0] 5
R90 0
H_TRDY# 5
H_A#[31:3] 5
H_VREF
0.1u_Y5V_0402
p71 not mout ,
they mount SB
side
+1.05V
C129
H_CPUSLP# 5,16
R101
100_1
R98
200_1
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
5
4
3
2
Date: Sheet
P72IA0
NB_945PM-1/5
1
833Wednesday, October 19, 2005
B
of
5
DMI_RXP[3:0]17
D D
C C
B B
DMI_RXN[3:0]17
DMI_TXP[3:0]17
DMI_TXN[3:0]17
R468 0
R470 0
R438 0
R441 0
GCLK7
GCLK#7
as short as
possible
R106
R97
40.2_1_OP
40.2_1_OP
+1.8VS
R89
150_1
0.05A
R88
150_1
0.1u_Y5V
MB_CK#313
MB_CK#413
MA_CK#113
MA_CK#013
M_VREF_MCH
C169
MB_ODT313,14
MB_ODT213,14
MA_ODT113,14
MA_ODT013,14
MB_CS#313,14
MB_CS#213,14
MA_CS#113,14
MA_CS#013,14
MB_CKE313,14
MB_CKE213,14
MA_CKE113,14
MA_CKE013,14
MB_CK313
MB_CK413
MA_CK113
MA_CK013
M_OCDCOMP1
M_OCDCOMP0
C105
0.1u_Y5V
DMI_RXP3
DMI_RXP2
DMI_RXP1
DMI_RXP0
DMI_RXN3
DMI_RXN2
DMI_RXN1
DMI_RXN0
DMI_TXP3
DMI_TXP2
DMI_TXP1
DMI_TXP0
DMI_TXN3
DMI_TXN2
DMI_TXN1
DMI_TXN0
Z0901
Z0902
Z0906
Z0912
M_VREF_MCH
M_RCOMPP
M_RCOMPN
U24B
AG41
DMI_TXP_3
AF37
DMI_TXP_2
AE41
AC37
AH41
AG37
AF41
AE37
AG39
AF35
AE39
AC35
AH39
AG35
AF39
AE35
D41
C40
AG33
AF33
AK41
AK1
AT9
AV9
AU21
AY20
BA12
BA13
AF10
AL20
AW21
AY21
AW12
AW13
AY29
BA29
AT20
AU20
AY40
AY7
AT1
AW35
AW40
AW7
AR1
AY35
A26
A27
DMI_TXP_1
DMI_TXP_0
DMI_TXN_3
DMI_TXN_2
DMI_TXN_1
DMI_TXN_0
DMI_RXP_3
DMI_RXP_2
DMI_RXP_1
DMI_RXP_0
DMI_RXN_3
DMI_RXN_2
DMI_RXN_1
DMI_RXN_0
D_REFSSCLKIN
D_REFSSCLKIN#
D_REFCLKIN
D_REFCLKIN#
G_CLKIN
G_CLKIN#
SM_VREF_1
SM_VREF_0
SM_RCOMP
SM_RCOMP#
SM_ODT_3
SM_ODT_2
SM_ODT_1
SM_ODT_0
SM_OCDCOMP_1
SM_OCDCOMP_0
SM_CS#_3
SM_CS#_2
SM_CS#_1
SM_CS#_0
SM_CKE_3
SM_CKE_2
SM_CKE_1
SM_CKE_0
SM_CK#_3
SM_CK#_2
SM_CK#_1
SM_CK#_0
SM_CK_3
SM_CK_2
SM_CK_1
SM_CK_0
CALISTOGA
DMI CLK
DDR MUXING
Only Base on Discreted VGA
VCCA_DPLLA , VCCA_DPLLB => NC
DREF_CLKP / DREF_SSCLKP = GND
DREF_CLKN / DREF_SSCLKN = GND
VCCA_DPLLA , VCCA_DPLLB =>1.5V
DREF_CLKP / DREF_SSCLKP = 1.5V
DREF_CLKN / DREF_SSCLKN = GND
+1.8VS
R95
R94
80.6_1
80.6_1
M_RCOMPN
M_RCOMPP
A A
For MEN bus throttling
+3.3V
R114 10K
R115 10K
Check with S/W
5
4
NC
SDVO_CTRLDATA
SDVO_CTRLCLK
MISC
PM_THRMTRIP#
PM_EXTTS#_1
PM_EXTTS#_0
PM
PM_BMBUSY#
CFG
RSVD
PM_EXTTS#1
PM_EXTTS#0
4
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
CLK_REQ#
LT_RESET#
RSTIN#
PWROK
CFG_20
CFG_19
CFG_18
CFG_17
CFG_16
CFG_15
CFG_14
CFG_13
CFG_12
CFG_11
CFG_10
CFG_9
CFG_8
CFG_7
CFG_6
CFG_5
CFG_4
CFG_3
CFG_2
CFG_1
CFG_0
RSVD_13
RSVD_12
RSVD_11
RSVD_10
RSVD_9
RSVD_8
RSVD_7
RSVD_6
RSVD_5
RSVD_4
RSVD_3
RSVD_2
RSVD_1
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
NC0
A3
A39
A4
A40
AW1
GCLK => PCI-E & DMI (100MHZ)
AW41
DREFCLK => Dispaly PLLA ( nun- ss 96MHZ)
AY1
AY41
DRESSFCLK => Display LVDS PLLB ( ss 100MHZ)
B2
B41
SDVODATA has internal pull down
BA1
0= no DVO device
BA2
BA3
1= DVO device present
BA39
SDVOCLK has internal pull
BA40
down .
BA41
C1
C41
D1
Asserted to control the raw PCI-E clock
Z0907
H32
K28
H27
H28
AH34
AH33
G6
H26
F25
G28
J26
K27
J25
H15
G18
H16
C15
K15
G15
D15
E16
G16
D16
D19
E18
F15
E15
F18
J18
K18
K16
D27
D28
A34
A35
A41
J19
H7
AF11
AG11
F7
F3
R32
T32
R117 0_OP
Asserted to synchronize with ICH on fault
Z0911
DELAY_VR_PWRGOOD
ICH7_THRMTRIP#
PM_EXTTS#1
PM_EXTTS#0
R157 100
R112 0
GHCH integrated graphics busy
Z0903
R104 1K_OP
Z0904
R105 1K_OP
CFG0
CFG10CFG2
1
1
1
NB_SYNC# 17
BM_BUSY# 17
CFG19 12
CFG18 12
CFG16 12
CFG9 12
CFG5 12
MCH_BSEL2 5
MCH_BSEL1 5
MCH_BSEL0 5
Base on
RSTIN#
0
0
+1.5V
A C
Host
Clock
frequency
PLT_RST# 17,19,20,25,26
DELAY_VR_PWRGOOD 17
BAT54D6
533
667
Reserve for NB THRMTRIP# ( O/D Vccp )
IPU
PM_EXTTS#0 13
ICH7_THRMTRIP#
AC
BAT54_OPD5
3
PM_DPRSLPVR 17,27
EXTTS#0 14,25
+1.05V
C196
1000P
PM_THRMTRIP# 5,16
3
+1.05V
+1.5V
Colse to NB
U24C
D32
L_BKLTCTL
J30
L_BKLTEN
H30
L_CLKCTLA
H29
L_CLKCTLB
G26
L_DDC_CLK
G25
L_DDC_DATA
B38
L_IBG
C35
L_VBG
F32
L_VDDEN
C33
L_VREFH
C32
L_VREFL
A33
LA_CLK#
A32
LA_CLK
E27
LB_CLK#
E26
LB_CLK
C37
LA_DATA#_0
B35
LA_DATA#_1
A37
LA_DATA#_2
B37
LA_DATA_0
B34
LA_DATA_1
A36
LA_DATA_2
G30
LB_DATA#_0
D30
LB_DATA#_1
F29
LB_DATA#_2
F30
LB_DATA_0
D29
LB_DATA_1
F28
LB_DATA_2
A16
TV_DACA_OUT
C18
TV_DACB_OUT
A19
TV_DACC_OUT
J20
TV_IREF
B16
TV_IRTNA
B18
TV_IRTNB
B19
TV_IRTNC
K30
TV_DCONSEL0
J29
O/A
TV_DCONSEL1
E23
CRT_BLUE
D23
CRT_BLUE#
C22
CRT_GREEN
B22
CRT_GREEN#
A21
CRT_RED
B21
CRT_RED#
C26
CRT_DDC_CLK
C25
CRT_DDC_DATA
G23
CRT_HSYNC
J22
CRT_IREF
H23
CRT_VSYNC
DELAY_VR_PWRGOOD
C193
0.1u_Y5V
CALISTOGA
2
LVDS
TV
VGA
2
1
PEG_COMP
EXP_A_COMPI
EXP_A_COMPO
EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9
EXP_A_RXN_10
EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15
EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8
EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15
EXP_A_TXN_0
EXP_A_TXN_1
EXP_A_TXN_2
EXP_A_TXN_3
EXP_A_TXN_4
EXP_A_TXN_5
EXP_A_TXN_6
EXP_A_TXN_7
EXP_A_TXN_8
EXP_A_TXN_9
EXP_A_TXN_10
EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15
EXP_A_TXP_0
EXP_A_TXP_1
EXP_A_TXP_2
PCI-EXPRESS GRAPHICS
EXP_A_TXP_3
EXP_A_TXP_4
EXP_A_TXP_5
EXP_A_TXP_6
EXP_A_TXP_7
EXP_A_TXP_8
EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15
CFG20 ( IPD ) => 1= Only SDVO or PCI-E
0 = SDVO and PCI-E
CFG7 ( IPU ) => 1= Mobility CPU
0 = Reverse
D40
D38
F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38
D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38
F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40
D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
R469 24.9_1
PEG_RXN[15..0] 26
PEG_RXP[15..0] 26
PEG_TXN[15..0] 26
+1.5V
PEG_TXP[15..0] 26
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P72IA0
NB NB DDRCLK_VGA_PCIEXPR-2/5
1
933Wednesday, October 19, 2005
of
B
5
4
3
2
1
MA_DQ[63:0]13
D D
C C
B B
MA_DQ0
MA_DQ1
MA_DQ2
MA_DQ3
MA_DQ4
MA_DQ5
MA_DQ6
MA_DQ7
MA_DQ8
MA_DQ9
MA_DQ10
MA_DQ11
MA_DQ12
MA_DQ13
MA_DQ14
MA_DQ15
MA_DQ16
MA_DQ17
MA_DQ18
MA_DQ19
MA_DQ20
MA_DQ21
MA_DQ22
MA_DQ23
MA_DQ24
MA_DQ25
MA_DQ26
MA_DQ27
MA_DQ28
MA_DQ29
MA_DQ30
MA_DQ31
MA_DQ32
MA_DQ33
MA_DQ34
MA_DQ35
MA_DQ36
MA_DQ37
MA_DQ38
MA_DQ39
MA_DQ40
MA_DQ41
MA_DQ42
MA_DQ43
MA_DQ44
MA_DQ45
MA_DQ46
MA_DQ47
MA_DQ48
MA_DQ49
MA_DQ50
MA_DQ51
MA_DQ52
MA_DQ53
MA_DQ54
MA_DQ55
MA_DQ56
MA_DQ57
MA_DQ58
MA_DQ59
MA_DQ60
MA_DQ61
MA_DQ62
MA_DQ63
AJ35
AJ34
AM31
AM33
AJ36
AK35
AJ32
AH31
AN35
AP33
AR31
AP31
AN38
AM36
AM34
AN33
AK26
AL27
AM26
AN24
AK28
AL28
AM24
AP26
AP23
AL22
AP21
AN20
AL23
AP24
AP20
AT21
AR12
AR14
AP13
AP12
AT13
AT12
AL14
AL12
AK9
AN7
AK8
AK7
AP9
AN9
AT5
AY2
AW2
AP1
AN2
AV2
AT3
AN1
AG7
AF9
AG4
AF6
AG9
AH6
AF4
AF8
U24D
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ3
SA_DQ4
SA_DQ5
SA_DQ6
SA_DQ7
SA_DQ8
SA_DQ9
SA_DQ10
SA_DQ11
SA_DQ12
SA_DQ13
SA_DQ14
SA_DQ15
SA_DQ16
SA_DQ17
SA_DQ18
SA_DQ19
SA_DQ20
SA_DQ21
SA_DQ22
SA_DQ23
SA_DQ24
SA_DQ25
SA_DQ26
SA_DQ27
SA_DQ28
SA_DQ29
SA_DQ30
SA_DQ31
SA_DQ32
SA_DQ33
SA_DQ34
SA_DQ35
SA_DQ36
SA_DQ37
SA_DQ38
SA_DQ39
SA_DQ40
SA_DQ41
SA_DQ42
SA_DQ43
SA_DQ44
SA_DQ45
SA_DQ46
AL5
SA_DQ47
SA_DQ48
SA_DQ49
SA_DQ50
SA_DQ51
SA_DQ52
SA_DQ53
SA_DQ54
AL2
SA_DQ55
SA_DQ56
SA_DQ57
SA_DQ58
SA_DQ59
SA_DQ60
SA_DQ61
SA_DQ62
SA_DQ63
Value
DDR SYSTEM MEMORY A
SA_BS_0
SA_BS_1
SA_BS_2
SA_CAS#
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
MA_BA1
AV14
MA_BA2
BA20
AY13
MA_DM0
AJ33
MA_DM1
AM35
MA_DM2
AL26
MA_DM3
AN22
MA_DM4
AM14
MA_DM5
AL9
MA_DM6
AR3
MA_DM7
AH4
MA_DQS0
AK33
MA_DQS1
AT33
MA_DQS2
AN28
MA_DQS3
AM22
MA_DQS4
AN12
MA_DQS5
AN8
MA_DQS6
AP3
MA_DQS7
AG5
MA_DQS#0
AK32
MA_DQS#1
AU33
MA_DQS#2
AN27
MA_DQS#3
AM21
MA_DQS#4
AM12
MA_DQS#5
AL8
MA_DQS#6
AN3
MA_DQS#7
AH5
MAA_A0
AY16
MAA_A1
AU14
MAA_A2
AW16
MAA_A3
BA16
MAA_A4
BA17
MAA_A5
AU16
MAA_A6
AV17
MAA_A7
AU17
MAA_A8
AW17
MAA_A9
AT16
MAA_A10
AU13
MAA_A11
AT17
MAA_A12
AV20
MAA_A13
AV12
AW14
Z1001
AK23
AK24
AY14
TP3
Z1002 Z1003
TP4 TP1
MA_BA0
AU12
MA_BA[2:0] 13,14
MA_CAS# 13,14
MA_DM[7:0] 13
MA_DQS[7:0] 13
MA_DQS#[7:0] 13
MAA_A[13:0] 13,14
MA_RAS# 13,14
MA_WE# 13,14
MB_DQ[63:0]13
MB_DQ0
MB_DQ1
MB_DQ2
MB_DQ3
MB_DQ4
MB_DQ5
MB_DQ6
MB_DQ7
MB_DQ8
MB_DQ9
MB_DQ10
MB_DQ11
MB_DQ12
MB_DQ13
MB_DQ14
MB_DQ15
MB_DQ16
MB_DQ17
MB_DQ18
MB_DQ19
MB_DQ20
MB_DQ21
MB_DQ22
MB_DQ23
MB_DQ24
MB_DQ25
MB_DQ26
MB_DQ27
MB_DQ28
MB_DQ29
MB_DQ30
MB_DQ31
MB_DQ32
MB_DQ33
MB_DQ34
MB_DQ35
MB_DQ36
MB_DQ37
MB_DQ38
MB_DQ39
MB_DQ40
MB_DQ41
MB_DQ42
MB_DQ43
MB_DQ44
MB_DQ45
MB_DQ46
MB_DQ47
MB_DQ48
MB_DQ49
MB_DQ50
MB_DQ51
MB_DQ52
MB_DQ53
MB_DQ54
MB_DQ55
MB_DQ56
MB_DQ57
MB_DQ58
MB_DQ59
MB_DQ60
MB_DQ61
MB_DQ62
MB_DQ63
AK39
AJ37
AP39
AR41
AJ38
AK38
AN41
AP41
AT40
AV41
AU38
AV38
AP38
AR40
AW38
AY38
BA38
AV36
AR36
AP36
BA36
AU36
AP35
AP34
AY33
BA33
AT31
AU29
AU31
AW31
AV29
AW29
AM19
AL19
AP14
AN14
AN17
AM16
AP15
AL15
AJ11
AH10
AN10
AK13
AH11
AK10
BA10
AW10
BA4
AW4
AY10
AY9
AW5
AY5
AV4
AR5
AK4
AK3
AT4
AK5
AJ9
AJ8
AJ5
AJ3
U24H
SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63
CALISTOGA
TP2
MB_BA[2:0] 13,14
MB_CAS# 13,14
MB_DM[7:0] 13
MB_DQS[7:0] 13
MB_DQS#[7:0] 13
MBA_A[13:0] 13,14
MB_RAS# 13,14
MB_WE# 13,14
SB_BS_0
SB_BS_1
SB_BS_2
SB_CAS#
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_RAS#
DDR SYSTEM MEMORY B
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
AV23
AY28
AR24
AK36
AR38
AT36
BA31
AL17
AH8
BA5
AN4
AM39
AT39
AU35
AR29
AR16
AR10
AR7
AN5
AM40
AU39
AT35
AP29
AP16
AT10
AT7
AP5
AY23
AW24
AY24
AR28
AT27
AT28
AU27
AV28
AV27
AW27
AV24
BA27
AY27
AR23
AU23
AK16
AK18
AR27
MB_BA1
MB_BA2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS0
MB_DQS1
MB_DQS2
MB_DQS3
MB_DQS4
MB_DQS5
MB_DQS6
MB_DQS7
MB_DQS#0
MB_DQS#1
MB_DQS#2
MB_DQS#3
MB_DQS#4
MB_DQS#5
MB_DQS#6
MB_DQS#7
MBA_A0
MBA_A1
MBA_A2
MBA_A3
MBA_A4
MBA_A5
MBA_A6
MBA_A7
MBA_A8
MBA_A9
MBA_A10
MBA_A11
MBA_A12
MBA_A13
Z1004
MB_BA0
AT24
AK34
AG34
AF34
AE34
AC34
C34
AW33
AV33
AR33
AE33
AB33
Y33
V33
T33
R33
M33
H33
G33
F33
D33
B33
AH32
AG32
AF32
AE32
AC32
AB32
G32
B32
AY31
AV31
AN31
AJ31
AG31
AB31
Y31
AB30
E30
AT29
AN29
AB29
T29
N29
K29
G29
E29
C29
B29
A29
BA28
AW28
AU28
AP28
AM28
AD28
AC28
W28
J28
E28
AP27
AM27
AK27
J27
G27
F27
C27
B27
AN26
M26
K26
F26
D26
AK25
P25
K25
H25
E25
D25
A25
BA24
AU24
AL24
AW23
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_49
VSS_50
AB37
VSS_51
AA37
Y37
VSS_52
VSS_53
W37
VSS
VSS_54
VSS_55
V37
T37
R37
VSS_56
VSS_57
P37
N37
VSS_58
VSS_59
M37
L37
VSS_60
VSS_61
J37
H37
3
VSS_62
VSS_63
G37
VSS_64
F37
D37
VSS_65
VSS_66
AY36
AW36
VSS_67
VSS_68
AN36
VSS_69
AH36
AG36
VSS_70
VSS_71
AF36
VSS_72
AE36
AC36
VSS_73
VSS_74
C36
VSS_75
B36
BA35
VSS_76
VSS_77
AV35
AR35
VSS_78
VSS_79
AH35
VSS_80
AB35
AA35
VSS_81
VSS_82
Y35
VSS_83
W35
V35
VSS_84
VSS_85
T35
VSS_86
R35
P35
VSS_87
VSS_88
N35
VSS_89
M35
L35
VSS_90
VSS_91
J35
A A
VSS_0
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
AC41
AA41
W41
T41
P41
M41
J41
F41
AV40
AP40
AN40
AK40
AJ40
AH40
AG40
AF40
AE40
B40
AY39
AW39
AV39
AR39
AN39
AJ39
AC39
AB39
AA39
Y39
W39
V39
T39
R39
P39
N39
M39
L39
J39
H39
G39
F39
D39
AT38
AM38
AH38
AG38
AF38
AE38
C38
AK37
AH37
5
4
VSS_92
H35
VSS_93
G35
F35
VSS_94
VSS_95
D35
VSS_96
AN34
2
U24I
CALISTOGA
UNIWILL COMPUTER CORP.
Title
Size Document Number Rev
3220
Date: Sheet
P72IA0
NB DDR_MEM SYSTEM-3/5
1
10 33Wednesday, October 19, 2005
of
B
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