FUJITSU SIEMENS S6010 Schematics

1

Laurel Main Board REV.02

Index

2

System Block

PAGE CONTENTS

01

02

03

04

05

06

07

08

09

10

11

12

13

14

15

16

17

18

19

20

TOP PAGE

Block Diagram

R-C for EMI

PLL

CPU(Tualatin)

CPU(Tualatin)

PassC for CPU

Pull up for CPU

BLANK

BLANK

GMCH(Almador-M)

GMCH(Almador-M)

GMCH(Almador-M),STRAP

PassC for GMCH(Almador-M)

Thermister, FAN

ICH3-M

ICH3-M

Pullup for ICH3-M

Pullup for AGP,PCI,LPC

FWH(BIOS)

PAGE CONTENTS

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

3

BLANK

SDRAM Dumping

DIMM CN

VCH

VCH

S-VIDEO

BLANK

IEEE1394

BLANK

PCIC

PCIC

PCIC POW

PCMCIA SLOT

CODEC

Audio AMP

MIC AMP

BLANK

Super-IO

KBC

HOOP

4

5

6

7

8

9

Version History

PAGE

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

CONTENTS

HOOP

Pullup for HOOP

LAN

LAN

BLANK

RESET

S-OUT CN

KBD/POINTING/LCD CN

APPLI CN/LID SW/MAIN SW

USB/IEEE1394 CN

MiniPCI CN

BLANK

FingerPrint CN

P-R CN

AUDIO CN

DOCK CN

HDD CN

ConnectorBoard CN

Power Interface require

Version Date

01-01 2001/Jul/18 First Edition for PCB placement

2001/Aug/24

First Edition for PCB desgin01-02

02-01

Description

Power Block

PAGE CONTENTS

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

Proprietary & Confidential

Power/TopPage

Power /DDC/CPU Core

Power/DDC/CPU Bus

Power/DDC/3V,5V

Power/DDC/Charger

Power/LDO/System

Power/LDO/Audio

Power/LDO/PMU

Power/Node/DCIn

Power/Node/Battery

Power/PMU/Etc3

Power/Node/Switch1

Power/Node/Switch2

Power/PMU/PMU

Power/PMU/AmMeter

Power/PMU/VolMeter

Power/PMU/Etc1

Power/PMU/Etc2

1

PCI REQ#/GNT#

PAGE CONTENTS

81

82

Power/PMU/Etc2

Power/Reserved

USB CHANEL

PCIINT#

USB1

USB2

USB3

USB4

USB5

USB6

Device

USB CN1

USB CN2 / Port Replicator

BAY USB

Blue-Tooth / TachPAD

Finger-P

Unused

REQ#/GNT# Device

REQ#0

REQ#1

REQ#2

REQ#3

REQ#4

REQ#5

IEEE1394 (Programable arbitration latency)

PCIC

MiniPCI

On Board LAN

Unused

Unused

PCI INTERRUPT

PCIINT#

INT#0

INT#1

INT#2

INT#3

INT#4

INT#5

INT#6

INT#7

Device

PCIC

PCIC

Mini-PCI

Mini-PCI

IEEE1394

On Board LAN

Unused

Unused

ICH-LAN /

SMBus / AC97-0,1

USB-0

USB-1

SMBus

PLL,ADM1030,KBC0,0,0

0,0,1

0,1,0

0,1,1

2

3

4

5

007,DOCK,PMU

DIMM Slot 1

DIMM Slot 2

6

PCI BUS NUMBER = #0

IDSEL

AD16

AD17

AD18

PCI BUS NUMBER = #2

IDSEL Device

AD24

AD26 0Ah

AD28 0Ch

AD29SMBCNT[2:0] Device

Rev.

DATE Design

2001.02.15

7

00h

01h

02h

1Fh

Dev.ID

08h ICH2_M(LAN)

0Dh

Appr.

CheckDesign

Konaka

DeviceDev.ID

GMCH(HOST/DRAM BRIDGE)

GMCH(AGP BRIDGE)

GMCH(INTERNAL GRAPHICS)

ICH2M(HUB IF)1Eh

ICH2-M(LPC,IDE,USB,SMBUS,AC97)

OnBoard LAN09hAD25

OZ711

IEEE1394

MiniPCI

Description

Fuchida Fukuda

Appr.

8

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

1 82

1

2

3

4

5

6

7

8

9

Laurel system block diagram

P28 LCD CN

LVDS

P29 CRT

ITP

Thermal
Sensor

VGA

P24
P25
P26

IDE0 ATA66/100

HDD

P40

IDE1 ATA66/100

BAY0

P41

P10

P15

AGPx4 1.5V

USB

Moblle

Tualatin

Coppermine-T

Micro-FCPGA
479pin

P5,P6

PSB 1.2V 133MHz

Almador-M

625
BGA

P11,P12,P13

Hublink 1.8V 266MHz

ICH3-M

421 BGA

P16,P17

PLL

SDRAM 3.3V 133MHz

PCI 3.3V 33MHz

LAN

AC97

Audio
CODEC

P35

P4

P23 P23

SODIMM0

INT_MIC

OZ711E1Mini PCI

P34 P30,P31 P56 P57

MIC
AMP

P37

Audio
AMP

P36

Audio
CN

P38

PHONE,MIC

LINE-IN

SODIMM1

CRT

USB4,USB5

PCI_D

Q-SW

FDD
Serial
Parallel
PS/2

LPC 3.3V 33MHz

DOCK

CN

P58

USB3

Bluetooth

P52

System
DC/DC
Module

USB2

FingerPrint

P52

Battery
Module

USB0USB1

P51 P51

FDD

SIO

P42

KBC

P43

ISA

FIR

I/O_CN

P46

DMC

P45

KB

P44

HOOP

P47,P48

80PORT

P20

Power
Controler

P77

FWH

P61-P82 P61-P82

1

2

3

4

5

P20

Resource

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

2 82

1

2

3

4

5

6

7

8

9

CLK

BUS

本コンデンサは電源/グランド層に発生するベタプレーン同士を接続するためのものである。
そのため、上記のようなベタ構成であれば、ポイントとなる個所にコンデンサ
を配置する。
‑クロックがベタをまたいで引く場合
‑Bus系がベタをまたいで引く場合(数本毎に1個間隔で)

個数については、適宜増やすこと。

1

2

3

PWR_1

PWR_5VMAIN

12

CC1

680pF 25V

PWR_5VMAIN PWR_5VMAIN PWR_3VSTD PWR_1.8VMAIN

CC10

2 1

680pF 25V

4

PWR_5VMAIN PWR_1 PWR_DCIN

12

CC2

680pF 25V

CC11

680pF 25V

12

CC12

680pF 25V

5

12

PWR_3VSUSPWR_3VMAINPWR_3VMAIN

12

CC3

680pF 25V

PWR_3VSUSPWR_3VMAINPWR_5VSUSPWR_3VMAIN

12

CC13

680pF 25V

12

CC4

680pF 25V

6

PWR_3VSUS PWR_3VSUS PWR_5VSUS PWR_5VSUS PWR_3VSUS

12

Rev.

DATE Design

2001.01.16 Komahara

CC5

680pF 25V

7

12

CC6

680pF 25V

Appr.

CheckDesign

Yoshida Aoki

12

Description

CC7

680pF 25V

PWR_5VMAIN

12

CC8

Appr.

8

680pF 25V

PWR_3VMAINPWR_3VMAINPWR_5VSUSPWR_3VMAIN

12

CC9

680pF 25V

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

PWR_1

21

PWR_5VSUS

CC21

680pF 25V

SHEET

9

EMI

CAST

3 82

PWR_3VSUS

1

CPU_BSEL15,8

SMB_CLK_ICH17,23,25,50
SMB_DATA_ICH17,23,25,50

CLK_GBO6612

SUSB#

STP_CPU#16

STP_PCI#16

VTTPWRGD#76

FL3

2 1

BLM21P300S
FL4

1 2

BLM21P300S

12

+

C6

10uF 6.3V (TA)

GND1

1 2

C7 0.1uF 16V 20%

2

Placecyrstalwithin500milsofClkTITAN
(byALMADOR-MCHIPSET/MOBILETUALATIN
PROCESSOR
CUSTMERREFERENCEBOARDSCHEMATICS
rev.0.80)

2 1

10k 1/16W 5%

1 2

1 2

C8 0.1uF 16V 20%

C9 0.1uF 16V 20%

3

X1

12

14.31818MHz

C1

16pF 25V

2 1

Reserve

GND1 GND1

12

2 1

C11 1uF 10V 20%

C10 0.1uF 16V 20%

PWR_3VSUS

R11

1 2

C2

16pF 25V

1 2

Reserve

2 1

2 1

C12 0.1uF 16V 20%

C13 0.1uF 16V 20%

1 2

240k 1/16W 5%

GND1

PLL_VCCA_33
PLL_VCC_33

C14 0.1uF 16V 20%

GND1

R12

4

FL1

<FILTER>

BLM10B750B
FL2

<FILTER>

BLM10B750B

R22

330 1/16W 1%

5

M1

1

21

12

12

XTAL_IN

2

XTAL_OUT

46

S1

36

S2

26

SCLK

25

SDATA

20

66MHz_IN/3V66_5

21

PWR_DWN#

45

CPU_STOP#

30

PCI_STOP#

24

PWR_DG#

22

VDD_CORE

33

VDD48

48

VDD_REF

11

VDD_PCI

28

VDD_3V66_1

15

VDD_3V66_2

44

VDD_CPU1

40

VDD_CPU2

37

IREF

23

GND_CORE

7

GND_PCI

16

GND_3V66_1

27

GND_3V66_2

3

GND_REF

32

GND_48MHZ

41

GND_CPU

CY28322

本ページのコンデンサは、PLLの近傍に
配置すること。

Place these capacitors near PLL.

CPU1

CPU#1

CPU2

CPU#2

3V66_0

3V66_1/VCH

66BUFF0/3V66_2

66BUFF1/3V66_3

66BUFF2/3V66_4

PCI_F0

PCI_F1

PCI_F2

REF0

PCI0

PCI1

PCI2

PCI3

PCI4

PCI5

DOT

USB

6

※のパターンのライン・インピーダンスは、５５Ωで引くこと。(5mil幅)
また、各対のクロックライン同士の間隔(CPUCLK0,CPUCLK0#間など３対)
は、信号線間インピーダンス１００Ωで引くこと。(９mil幅)

Control the impedance of signals that "*" are marked are 55 ohm. (the width is 5mil)
Control the impedance between the pair of clock (CPUCLK0 & CPCLK0#, etc) 100 ohm.
(the width is 9mil)

※

43

※

42

39

※

38

※

R2 62 1/16W 1%

R4 62 1/16W 1%

GND1

R7 62 1/16W 1%

R9 62 1/16W 1%

GND1

7

R1 33 1/16W 1%

R3

470 1/16W 1%

R8

470 1/16W 1%

12

R5 33 1/16W 1%

12

R6 33 1/16W 1%

12

12

12

12

12

12

21

12

8

R10 33 1/16W 1%

#B 枠内部品は、M2(CPU)裏面 PAD直裏に配置のこと。
#C枠内部品は、M3(GMCH)裏面PAD直裏に配置のこと。

29

31

17

18

19

8

9

10

12

13

14

4

5

6

34

35

47

R13 BLM15AG700

12

R14 BLM15AG700

12

R15 BLM15AG700

12

R16 BLM15AG700

12

R17 BLM15AG700

12

R18 BLM15AG700

12

R19 BLM15AG700

12

R20 BLM15AG700

12

R449 BLM15AG700

12

R21 BLM15AG700

12

R23 47 1/16W 5%

12

R24 BLM15AG700

12

R25 BLM15AG700

21

R26 BLM15AG700

21

R27 BLM15AG700

21

R28 BLM15AG700

21

R29 BLM15AG700

21

R30 BLM15AG700

21

R31 BLM15AG700

21

R490 0 1/16W

12

C4

1 2

5pF 25V

GND1

C5

1 2

5pF 25V

GND1

#B

#C

9

CPUCLK1 5

CPUCLK1# 5

CPUCLK2 11

CPUCLK2# 11

CLK_ICH66 16

CLK_GBI66 12

CLK_FWH33 20

CLK_71133 29

CLK_SIO33 37

CLK_ASIC33 39

CLK_MINI33 50

CLK_1394 27

CLK_LAN33 42

CLK_ICH33 16

CLK_CPUAPIC33 5

CLK_ICHAPIC33 17

CLK_MCH_DREF48 12

CLK_ASIC48 39

CLK_ICH48 16

CLK_ICH14 16

CLK_SIO14 37

CLK_VCH14 24

CLK_TVO14 26

12

2 1

2 1

1 2

2 1

1 2

1 2

1 2

1 2

1 2

1 2

1 2

2 1

2 1

C1710pF 25V

C1810pF 25V

C1910pF 25V

C2010pF 25V

C2110pF 25V

Appr.

C2218pF 25V

CheckDesign

C1610pF 25V

C1510pF 25V

各クロックのダンピング抵抗はチップから
1cm以内に配置すること。

Place each dumping resistor of clock line near PLL as
possible.(less than 10mm)

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

7

1 2

C2310pF 25V

C2510pF 25V

C2610pF 25V

C2410pF 25V

Description

Yoshida Aoki

C2710pF 25V

Appr.

8

C2810pF 25V

1 2

C2910pF 25V

C3010pF 25V

TITLE

Lauurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

1 2

C65910pF 25V

GND1

9

SHEET

PLL

CAST

4 82

1

2

3

4

5

6

7

8

9

M2A

CPU_D#[0:63]11

CPU_D#0
CPU_D#1
CPU_D#2
CPU_D#3
CPU_D#4
CPU_D#5
CPU_D#6
CPU_D#7
CPU_D#8
CPU_D#9
CPU_D#10
CPU_D#11
CPU_D#12
CPU_D#13
CPU_D#14
CPU_D#15
CPU_D#16
CPU_D#17
CPU_D#18
CPU_D#19
CPU_D#20
CPU_D#21
CPU_D#22
CPU_D#23
CPU_D#24
CPU_D#25
CPU_D#26
CPU_D#27
CPU_D#28
CPU_D#29
CPU_D#30
CPU_D#31
CPU_D#32
CPU_D#33
CPU_D#34
CPU_D#35
CPU_D#36
CPU_D#37
CPU_D#38
CPU_D#39
CPU_D#40
CPU_D#41
CPU_D#42
CPU_D#43
CPU_D#44
CPU_D#45
CPU_D#46
CPU_D#47
CPU_D#48
CPU_D#49
CPU_D#50
CPU_D#51
CPU_D#52
CPU_D#53
CPU_D#54
CPU_D#55
CPU_D#56
CPU_D#57
CPU_D#58
CPU_D#59
CPU_D#60
CPU_D#61
CPU_D#62
CPU_D#63

M24
U26

R24
R26
M25

M26

AA26

U24

W26

AB25

W24

AB24
AA24

A16
B17
A17
D23
B19
C20
C16
A20
A22
A19
A23
A24
C18
D24
B24
A18
E23
B21
B23
E26
C24
F24
D25
E24
B25
G24
H24
F26
L24
H25
C26
K24
G26
K25

J24
K26
F25
N26

J26

P25
L26

V25
T24

P24

T26

Y25

V26

T25
Y24

Y26

V24

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

CopperMine-T

A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

DEP#0
DEP#1
DEP#2
DEP#3
DEP#4
DEP#5
DEP#6
DEP#7

FERR#

BREQ0#

HITM#

HIT#

AP#0

AP#1
LOCK#
PRDY#

PICD0
PICD1

ADS#

K1
J1
G2
K3
J2
H3
G1
A3
J3
H1
D3
F3
G3
C2
B5
B11
C6
B9
B7
C8
A8
A10
B3
A13
A9
C3
C12
C10
A6
A15
A14
B13
A12

AE24
AD25
AE25
AC24
AF24
AD26
AC26
AD24

AF6

A7
U2

AA2

AB3
P3
V3
AE22
AD19
AD17
AA3

CPU_A#3
CPU_A#4
CPU_A#5
CPU_A#6
CPU_A#7
CPU_A#8
CPU_A#9
CPU_A#10
CPU_A#11
CPU_A#12
CPU_A#13
CPU_A#14
CPU_A#15
CPU_A#16
CPU_A#17
CPU_A#18
CPU_A#19
CPU_A#20
CPU_A#21
CPU_A#22
CPU_A#23
CPU_A#24
CPU_A#25
CPU_A#26
CPU_A#27
CPU_A#28
CPU_A#29
CPU_A#30
CPU_A#31

CPU_BREQ0#

12

R33

10 1/16W 5%

GND1

CPU_HLOCK# 11
ITP_PRDY# 8
CPU_APICD0 8,17
CPU_APICD1 8,17
CPU_ADS# 11

A#3
A#4
A#5
A#6
A#7
A#8
A#9

CPU_A#[3:31] 11

CLK_CPUAPIC334

R32はM2.AF20の近くに置くこと

CPU_FERR# 8,16

CPU_HITM# 11

CPU_HIT# 11

GND1

R32
68 1/16W 5%

CPUCLK1,CPUCLK1#
のビアのうち、
本CPUに一番近いビアに対し、
シルクで表示すること。

CPUCLK14
CPUCLK1#4

CPU_A20M#16
CPU_INTR8,16
CPU_NMI8,16
CPU_IGNNE#16
CPU_FLUSH#8
CPU_RST#8,11
CPU_INIT#8,16,20
CPU_SMI#8,16
CPU_RS#[0:2]11

TP1RS#P

CPU_STPCLK#16
CPU_DEFER#11

CPU_BPRI#11
ITP_PREQ#8

21

PWR_CPUBUS

GND1

CPU_PWRGD8,16
CPU_DPSLP#8,16,60

GLO/HI#16

CPU_THMDA15 CPU_THMDC 15

ITP_TRST#8
CPU_TRDY#11
ITP_TCK8
ITP_TMS8
ITP_TDI8

CPU_BSEL08
CPU_BSEL14,8

R36 1k 1/16W 5%

12

R37 1k 1/16W 5%

12

R39 1k 1/16W 5%

21

R40 1k 1/16W 5%

2 1

M2B

AC1

BCLK

AD1

BCLK#

AC3

A20M#

AD15

INTR/LINT0

AE14

NMI/LINT1

AD9

IGNNE#

AF5

FLUSH#

B15

RESET#

AE6

INIT#

AD3

SMI#

Y3

CPU_RS#0
CPU_RS#1
CPU_RS#2

☆ ☆

AE4

AF20

AF19

AB4
AF8

AF13

AF15

AD10

AF7
AD7

AE12
AF10

AF11

V1
U3
M5

T3

R2

L5

W1

E2

M1

Y4

RS#0
RS#1
RS#2
RS#P

STPCLK#
DEFER#
PICCLK
BPRI#
PREQ#
PWRGOOD
DPSLP#

GHI#

THERMDA

TRST#
TRDY#
TCK
TMS
TDI

BSEL0
BSEL1

TESTHI
TESTHI
TESTLO
TESTLO

THERMDC

RTTIMPEDP

EDGECTRLP

VTTPWRGD

IERR#
AERR#
BERR#

BINIT#

BNR#

BPM#0
BPM#1

BP#2
BP#3

DBSY#
DRDY#

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

RP#

TDO

NCTRL

VID0
VID1
VID2
VID3
VID4

AF4
W2
C14
AF23
L2

AD22
AD21
AF22
AE20

W3
Y1

R1
L3
T1
U1
L1

T4

AF14

AD11

AE16

AF16

AD16

E3

AB1
AC2
AE2
AF3
R3

CPU_REQ#0
CPU_REQ#1
CPU_REQ#2
CPU_REQ#3
CPU_REQ#4

CPU_RTTIMPEDP

CPU_EDGECTRLP

CPU_IERR# 8

CPU_BNR# 11

CPU_DBSY# 11
CPU_DRDY# 11
CPU_REQ#[0:4] 11

ITP_TDO 8

R34

12

56 1/16W 1%

R38

1 2

110 1/16W 1%

VTTPWRGD 8,76

GND1

PWR_CPUBUS

21

R35 14 1/16W 1%

CopperMine-T

BSEL0

PSB Freq.

100MHz

BSEL1

0

1133MHz

1

1

☆印のついた信号線はGND1で両側をガードすること。

M2

Cuppermine GMCH

M2からM3への信号線は上記の条件を厳守すること。

1

2

3

4

Total Trace Length:50.8-101.6mm

Trace Width:5mils
Spacing to Other Traces:10mils

5

M6

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

DRAW. No.

FUJITSU
LTD.

CPU-1

Laurel

C1CPxxxxxx-X1

SHEET

9

CAST

5 82

1

2

3

4

5

6

7

8

9

PWR_CPUBUS

R44

2K 1/16W 0.5%

1 2

12

GND1

PWR_CPUBUS

R41

1K 1/16W 0.5%

2 1

2 1

C691 1uF 6.3V

M2C

L1

12

4.7uH

C694

VGTLREF

2 1

C35 0.1uF 10V R12C36 0.1uF 10V R12C37 0.1uF 10V R12C38 0.1uF 10V R

C692 1uF 6.3V

C693 1uF 6.3V

◎のついた信号線は25mil以上の太さで配線し、
周りをベタのGNDで配線すること。

10uF 6.3V (TA)

12

+

C695

10uF 6.3V (TA)

N3

PLL1

12

+

N2

PLL2

A4

VREF

A21

VREF

N1

VREF

AF9

VREF

AF21

VREF

AA1

VREF

AB26

VREF

H26

VREF

12

CopperMine-T

CMOSREF
CMOSREF

AD5
AF12

このページの抵抗・キャパシタ・インダクタはCPUの近傍に置くこと

12

C32

0.1uF 10V R

C34 0.1uF 10V R

PWR_1.5VMAIN

1 2

12

12

GND1

R42

560 1/16W 0.5%

R43

1.1K 1/16W 0.5%

PWR_CPUCORE

W21

AA11
AA13
AA15
AA17
AA19
AA21

AB10
AB12
AB14
AB16
AB18
AB20
AB22

AC5
AC7

AC9
AC11
AC13
AC15
AC17
AC19
AC21

D10
D12
D14
D16
D18
D20
D22

E11
E13
E15
E17
E19
E21

F10
F12
F14
F16
F18
F20
F22

G21

H22

K22

M22

N21

P22

R21

T22

U21

V22

Y22
AA5
AA7
AA9

AB6
AB8

PWR_CPUBUS

M2D

D6

VCC

D8

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

E5

VCC

E7

VCC

E9

VCC
VCC
VCC
VCC
VCC
VCC
VCC

F6

VCC

F8

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

G5

VCC
VCC

H6

VCC
VCC

J5

VCC

J21

VCC

K6

VCC
VCC

L21

VCC

M6

VCC
VCC

N5

VCC
VCC

P6

VCC
VCC

R5

VCC
VCC

T6

VCC
VCC

U5

VCC
VCC

V6

VCC
VCC

W5

VCC
VCC

Y6

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT
VCCT

A26
C5
C7
C9
C11
C13
C15
C17
C19
C21
D5
E4
E6
G4
G23
J4
J23
L4
L23
N23
R23
U23
V4
W23
AA4
AA23
AC4
AC23
AD6
AD8
AD12
AD14
AD18
AD20
AE3
AE18
AF1
AF2

A2

NC

A5

NC

A11

NC

B1

NC

C1

NC

C4

NC

C22

NC

D1

NC

D26

NC

E1

NC

F1

NC

N4

NC

N24

NC

P1

NC

P4

NC

P5

NC

P26

NC

AD4

NC

AD13

NC

AD23

NC

AE8

NC

AE10

NC

AF17

NC

AF18

NC

M21
M23

N22
N25

A25

B10
B12
B14
B16
B18
B20
B22
B26
C23
C25

D11
D13
D15
D17
D19
D21

E10
E12
E14
E16
E18
E20
E22
E25

F11
F13
F15
F17
F19
F21
F23

G22
G25

H21
H23

J22
J25

K21
K23

L22
L25

B2
B4
B6
B8

D2
D4
D7
D9

E8

F2
F4
F5
F7
F9

G6

H2
H4
H5

J6

K2
K4
K5

L6

M2
M3
M4

N6

M2E

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

CopperMine-T

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P2
P21
P23
R4
R6
R22
R25
T2
T5
T21
T23
U4
U6
U22
U25
V2
V5
V21
V23
W4
W6
W22
W25
Y2
Y5
Y21
Y23
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB2
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AC6
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AC25
AD2
AE1
AE5
AE7
AE9
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE26
AF25
AF26

GND1GND1

CopperMine-T

TITLE

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

FUJITSU
LTD.

CPU-2

Laurel

C1CPxxxxxx-X1

SHEET

9

CAST

6 82

1

2

MOBILE
Coppermine-T
Tualatin

3

At least x24 0.47uF & x10 10uF CPUCOREVCC(PWR_CPUCORE)
decoupling capacitors.
At least x10 1.0uF CPUBUSVCC(PWR_CPUBUS) de capaciters.
(by Tualatin / Coppermine-T SpecSheet)

21

C39 0.22uF 10V

C40 0.22uF 10V12C41 0.22uF 10V12C42 0.22uF 10V21C43 0.22uF 10V12C44 0.22uF 10V12C45 0.22uF 10V21C46 0.22uF 10V21C47 0.22uF 10V12C48 0.22uF 10V12C49 0.22uF 10V12C50 0.22uF 10V21C51 0.22uF 10V12C52 0.22uF 10V12C53 0.22uF 10V12C54 0.22uF 10V21C55 0.22uF 10V21C56 0.22uF 10V21C57 0.22uF 10V21C58 0.22uF 10V12C59 0.22uF 10V12C60 0.22uF 10V21C61 0.22uF 10V12C62 0.22uF 10V

1 2

2 1

2 1

C63 10uF 6.3V B

C64 10uF 6.3V B

C65 10uF 6.3V B

1 2

1 2

C66 10uF 6.3V B

4

1 2

C67 10uF 6.3V B

1 2

C68 10uF 6.3V B

1 2

C69 10uF 6.3V B

5

PWR_CPUCORE

C70 10uF 6.3V B

GND1

PWR_CPUBUS

6

7

8

PWR_CPUCORE

12

GND1

9

1 2

1 2

2 1

1 2

2 1

1 2

1 2

1 2

C75 1uF 6.3V

C76 1uF 6.3V

C77 1uF 6.3V

C78 1uF 6.3V

C79 1uF 6.3V

C80 1uF 6.3V

C81 1uF 6.3V

C82 1uF 6.3V

上記のコンデンサはM2(CPU)の各電源ピンの近傍に均等に配置すること
複数の種類のコンデンサは、容量の小さいものを優先的に、
M2の電源PINの直近に配置すること

上記コンデンサ

0.47uF10VR(C36‑C59),10uF6.3VB(C60‑C71)はCPU裏の中央に配置し、

1.0uF10V(C72‑C84)はCPUBUS電源(VCCT)のPIN近くに均等に配置すること。

2 1

2 1

C86 10uF 6.3V B

C87 10uF 6.3V B

GND1

1.0uF10V

10uF6.3V B

0.47uF10VR

PassC for CPU

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

7 82

1

ITP_TCK5

ITP_TDI5

ITP_TMS5

ITP_TRST#5

VTTPWRGD5,76

CPU_APICD05,17

CPU_APICD15,17

ITP_TDO5

ITP_PREQ#5

CPU_FLUSH#5

CPU_FERR#5,16

CPU_IERR#5

CPU_INTR5,16

CPU_NMI5,16

CPU_DPSLP#5,16,60

CPU_SMI#5,16

CPU_INIT#5,16,20

CPU_RST#5,11

ITP_PRDY#5

2

R45 10 1/16W 5%

1 2

R46 10 1/16W 5%

1 2

R47 10 1/16W 5%

1 2

R48 10 1/16W 5%

1 2

GND1

3

R49 1.5k 1/16W 5%

1 2

R50 150 1/16W 5%

R51 150 1/16W 5%

R52 150 1/16W 5%

1 2

R53 10 1/16W 5%

1 2

R54 3k 1/16W 5%

1 2

R55 1.5k 1/16W 5%

1 2

R56 1.5k 1/16W 5%

1 2

R58 10k 1/16W 5% Reserve

1 2

R59 56 1/16W 5%

2 1

R61 56 1/16W 5%

PWR_CPUBUS

21

21

21

4

PWR_1.5VMAIN

ITP_PREQ# Pull-up signal change to 10ohm from 200ohm for ESD protection

PWR_CPUBUS

5

CPU_PWRGD5,16

CPU_BSEL05

CPU_BSEL14,5

6

2 1

GND1

R57 1.5k 1/16W 5%

C696

100pF 25V

R60 10k 1/16W 5%

R62 10k 1/16W 5%

1 2

1 2

1 2

7

PWR_1.8VMAIN

PWR_3VMAIN

8

9

21

12

C89

C88

2 1

100pF 25V

100pF 25V

CPURST#は上記抵抗までの分岐配線を0.1inch以下にすること。

C90

100pF 25V

21

C92

C91

2 1

100pF 25V

100pF 25V

GND1

本ページの抵抗・コンデンサはCPUの近くに配置すること

1

2

3

Pullup for CPU

Rev.

DATE Design

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

8 82

1

2

3

4

5

GMCHA24,GMCHC24間の信号<CLKSYSMEM>は0.15inch(+/‑50mil)で配線すること。
またコンデンサはその信号線の中間に配置すること。

6

7

8

PAD(A24)

9

M3A

Almador-M

HOST I/F

3

CPURST#

BPRI#

DEFER#

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8

HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

R6
L4
J4

U4

CPU_D#0

P1

CPU_D#1

W6

CPU_D#2

U2

CPU_D#3

U6

CPU_D#4

R1

CPU_D#5

N3

CPU_D#6

W5

CPU_D#7

V4

CPU_D#8

P3

CPU_D#9
CPU_D#10

R3
U1

CPU_D#11

V6

CPU_D#12

W4

CPU_D#13

T3

CPU_D#14

P2

CPU_D#15

V3

CPU_D#16

R2

CPU_D#17

T1

CPU_D#18

W3

CPU_D#19

U3

CPU_D#20

Y4

CPU_D#21

AA3

CPU_D#22

W1

CPU_D#23

V1

CPU_D#24

Y1

CPU_D#25

Y6

CPU_D#26

AD3

CPU_D#27

AB4

CPU_D#28

AB5

CPU_D#29

V2

CPU_D#30

Y3

CPU_D#31

Y2

CPU_D#32

AA4

CPU_D#33

AA1

CPU_D#34

AA6

CPU_D#35

AB1

CPU_D#36

AC4

CPU_D#37

AA2

CPU_D#38

AB3

CPU_D#39

AD2

CPU_D#40

AD1

CPU_D#41

AC2

CPU_D#42

AB6

CPU_D#43

AC6

CPU_D#44

AC1

CPU_D#45

AF3

CPU_D#46

AD4

CPU_D#47

AD6

CPU_D#48

AC3

CPU_D#49

AH3

CPU_D#50

AE5

CPU_D#51

AE3

CPU_D#52

AG2

CPU_D#53

AF4

CPU_D#54

AF2

CPU_D#55

AJ3

CPU_D#56

AE4

CPU_D#57

AG1

CPU_D#58

AE1

CPU_D#59

AG4

CPU_D#60

AH4

CPU_D#61

AG3

CPU_D#62

AF1

CPU_D#63

R82,R83,R84の抵抗はGMCH(M6)から0.5inch以内に置き、
※のついた信号線は10mil幅以上で配線すること。

Place R82,R83,R84 near GMCH (within 0.5 inch) and
the width of patterns must be more than 10 mil.

4

C699 22pF 25V Reserve

1 2

C700 22pF 25V Reserve

1 2

C701 22pF 25V Reserve

1 2

C702 22pF 25V Reserve

1 2

GND1

CPU_RST# 5,8
CPU_BPRI# 5
CPU_DEFER# 5

CPUCLK24
CPUCLK2#4
PCI_RST#

CPU_A#[3:31]5 CPU_D#[0:63] 5

CPU_ADS#5
CPU_DBSY#5
CPU_DRDY#5
CPU_HIT#5
CPU_HITM#5
CPU_HLOCK#5
CPU_TRDY#5
CPU_BNR#5

CPU_REQ#[0:4]5

CPU_RS#[0:2]5

GTL_RCOMP must be pulled down
to GND with 80.6 ohm resistor.

12

R67

160 1/16W 1%

12

CPU_A#3
CPU_A#4
CPU_A#5
CPU_A#6
CPU_A#7
CPU_A#8
CPU_A#9
CPU_A#10
CPU_A#11
CPU_A#12
CPU_A#13
CPU_A#14
CPU_A#15
CPU_A#16
CPU_A#17
CPU_A#18
CPU_A#19
CPU_A#20
CPU_A#21
CPU_A#22
CPU_A#23
CPU_A#24
CPU_A#25
CPU_A#26
CPU_A#27
CPU_A#28
CPU_A#29
CPU_A#30
CPU_A#31

CPU_REQ#0
CPU_REQ#1
CPU_REQ#2
CPU_REQ#3
CPU_REQ#4

CPU_RS#0
CPU_RS#1
CPU_RS#2

R68

160 1/16W 1%

AJ4

HTCLK

AH5

HTCLK#

AB24

RESET#

H2

HA#3

E3

HA#4

G3

HA#5

N4

HA#6

M6

HA#7

F1

HA#8

F2

HA#9

J3

HA#10

F3

HA#11

P6

HA#12

G1

HA#13

N5

HA#14

H1

HA#15

P4

HA#16

T4

HA#17

M2

HA#18

J2

HA#19

L2

HA#20

R4

HA#21

K1

HA#22

L3

HA#23

L1

HA#24

J1

HA#25

N1

HA#26

T5

HA#27

H3

HA#28

M3

HA#29

M1

HA#30

K3

HA#31

C1

ADS#

G5

DBSY#

F4

DRDY#

D3

HIT#

D1

HITM#

J6

HLOCK#

G4

HTRDY#

E1

BNR#

K6

HREQ#0

M4

HREQ#1

K5

HREQ#2

K4

HREQ#3

L6

HREQ#4

H6

RS#0

H4

RS#1

G6

RS#2

C2

※

GTL_RCOMP

※

GND1

1

2

MEM_D[0:63]23

5

CLK_DIMM0 23

CLK_DIMM1 23

CLK_DIMM2 23

CLK_DIMM3 23

21

C93

GND1

CLK_SYSMEM

M3B

22pF 25V

Reserve

Memory I/F

C24

SM_RCLK

SM_OCLK

A24

下記の抵抗はGMCHの各PINから0.25inch以内に配置すること。

Place these resistors near GMCH. (within 0.25inch)

MEM_D0
MEM_D1
MEM_D2
MEM_D3
MEM_D4
MEM_D5
MEM_D6
MEM_D7
MEM_D8
MEM_D9
MEM_D10
MEM_D11
MEM_D12
MEM_D13
MEM_D14
MEM_D15
MEM_D16
MEM_D17
MEM_D18
MEM_D19
MEM_D20
MEM_D21

MEM_D23
MEM_D24
MEM_D25
MEM_D26
MEM_D27
MEM_D28
MEM_D29
MEM_D30
MEM_D31
MEM_D32
MEM_D33
MEM_D34
MEM_D35
MEM_D36
MEM_D37
MEM_D38
MEM_D39
MEM_D40

MEM_D42
MEM_D43
MEM_D44
MEM_D45
MEM_D46
MEM_D47
MEM_D48
MEM_D49
MEM_D50
MEM_D51
MEM_D52
MEM_D53
MEM_D54
MEM_D55
MEM_D56
MEM_D57
MEM_D58
MEM_D59
MEM_D60
MEM_D61
MEM_D62
MEM_D63

D29

SM_MD0

C29

SM_MD1

D27

SM_MD2

C27

SM_MD3

A27

SM_MD4

B26

SM_MD5

E24

SM_MD6

C25

SM_MD7

E23

SM_MD8

B25

SM_MD9

C23

SM_MD10

F22

SM_MD11

B23

SM_MD12

C22

SM_MD13

E21

SM_MD14

B22

SM_MD15

C12

SM_MD16

D10

SM_MD17

C11

SM_MD18

A10

SM_MD19

C10

SM_MD20

C8

SM_MD21

A7

SM_MD22

E9

SM_MD23

C7

SM_MD24

E8

SM_MD25

A5

SM_MD26

F8

SM_MD27

C5

SM_MD28

D6

SM_MD29

B4

SM_MD30

C4

SM_MD31

E27

SM_MD32

C28

SM_MD33

B28

SM_MD34

E26

SM_MD35

C26

SM_MD36

D25

SM_MD37

A26

SM_MD38

D24

SM_MD39

F23

SM_MD40

A25

SM_MD41

G22

SM_MD42

D22

SM_MD43

A23

SM_MD44

F21

SM_MD45

D21

SM_MD46

A22

SM_MD47

F11

SM_MD48

A11

SM_MD49

B11

SM_MD50

F10

SM_MD51

B10

SM_MD52

B8

SM_MD53

D9

SM_MD54

B7

SM_MD55

F9

SM_MD56

A6

SM_MD57

C6

SM_MD58

D7

SM_MD59

B5

SM_MD60

E6

SM_MD61

A4

SM_MD62

D4

SM_MD63

Almador-M

SM_CLK0
SM_CLK1
SM_CLK2
SM_CLK3

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_RAS#
SM_CAS#

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8

SM_MA9
SM_MA10
SM_MA11
SM_MA12

SM_BA0
SM_BA1

SM_WE#

SM_RCOMP

1 2

A15

2 1

B2
B14

1 2

A3

1 2

E17

MEM_CS#0

F16

MEM_CS#1

D16

MEM_CS#2

D15

MEM_CS#3

F18

MEM_DQM0

D18

MEM_DQM1

D13

MEM_DQM2

D12

MEM_DQM3

E18

MEM_DQM4

F17

MEM_DQM5

F14

MEM_DQM6

F13

MEM_DQM7MEM_D22

A13

MEM_CKE0

C9

MEM_CKE1

C13

MEM_CKE2

A9

MEM_CKE3

C20

MEM_RAS#

D19

MEM_CAS#

A20

MEM_AA0

B20

MEM_AA1

B19

MEM_AA2MEM_D41

C19

MEM_AA3

A18

MEM_AA4

A19

MEM_AA5

C17

MEM_AA6

C18

MEM_AA7

B17

MEM_AA8

A17

MEM_AA9

A16

MEM_AA10

C15

MEM_AA11

C14

MEM_AA12

B16

MEM_BA0

C16

MEM_BA1

A21

MEM_WE#

F6

MEM_COMPA

SM_RCOMP must be pulled down
to GND with 27.5 ohm resistor.

Memoryの配線条件については、回路図Page22を参照すること。

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

0.15inch

+/-50mil

PAD(C24)

R63 10 1/16W 5%
R64 10 1/16W 5%
R65 10 1/16W 5%
R66 10 1/16W 5%

R69

※ ※

27.4 1/16W 1%

Appr.

8

12

C

Board trace

CLK_DIMM0 23
CLK_DIMM1 23
CLK_DIMM2 23
CLK_DIMM3 23

MEM_CS#[0:3] 23

MEM_DQM[0:7] 23

MEM_CKE[0:3] 23

MEM_RAS# 22
MEM_CAS# 22

MEM_AA[0:12] 22

MEM_BA[0:1] 22

MEM_WE# 22

GND1

GMCH-M-1

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

Connect to
GND

SHEET

11 82

9

CAST

1

CLK_GBI664

DVOB_CLKIN[0:1]24

VCH_GMBSCL_B24

VCH_GMBSDA_B24

DVOB_DATA[0:11]24

DVOB_BLANK#24

R85

330 1/16W 5%

1 2

GND1

-NOTE
G_PAR/DVO_DETECT signal use for DVO B/C detection.
Rx Unprpurated : AGP or Internal graphics with DVOA
Rx Popurated : DVO B/C selected.
This G_PAR/DVO_DETECT pin had internall pull up resister.

PWR_1.5VMAIN

RM2

8
7
6
5

SMT8

10kx4 1/32W 5%
RM4

1
2
3
4

10kx4 1/32W 5%

下記抵抗（R85）はM6‑AD24から0.5inch以内に配置すること。

R71

DVOB_CLKIN0
DVOB_CLKIN1

Open
Intel confermed

DDC2_B_CLK_PU15
VCH_GMBSCL_B
DDC2_B_DATA_PU15

VCH_GMBSDA_B

Open
Intel confermed

Open
Intel confermed

1

DVOA_PCLK

2
3

DVOB_CLKINT_PU15

4

8

DDC2_B_CLK_PU15

7

VCH_GMBSDA_B

6

DDC2_B_DATA_PU15

5

VCH_GMBSCL_B

12

GND1

DVOB_DATA7

CTM_PDGND
CTM#_PDGND

AG26

L29
L28

U29
U28

AA27
AA28

AB25
AB29

AB26

AA29
AA24
AA25

Y24
Y27
Y26

W24

Y28

R29
P26
P27
N25
R28
P28

L27
P29
R27
T25

AC27

AH15

AJ15

AG17

AJ17

AG18

AJ18

AG19

AJ19

AG20

AJ20

AJ11

AH10

AJ10

AG10

AJ9

AG9

AJ8

AG8

DVOB_INT# 24

VCH_GMBSDA_B 24

VCH_GMBSCL_B 24

r240k 1/16W 5%

SMT8

1

2

M3C

GBIN

AD_STB0/DVOB_CLK
AD_STB#0/DVOB_CLK#

AD_STB1/DVOC_CLK
AD_STB#1/DVOC_CLK#

SB_STB/ZV_D4
SB_STB#/ZV_D3

RBF#/ZV_D11
WBF#/ZV_D9

PIPE#/ZV_D10

SBA0/ZV_D8(UV0)
SBA1/ZV_D7(Y7)
SBA2/ZV_D6
SBA3/ZV_D5
SBA4/ZV_D2
SBA5/ZV_D1
SBA6/ZV_D0(Y0)
SBA7/ZV_HREF

G_AD30/DVOBC_INTR#/DPMS_CLK

G_FRAME#/M_DDC2_DATA
G_IRDY#/M_I2C_CLK
G_TRDY#/M_DDC2_CLK
G_STOP#
G_DEVSEL#/M_I2C_DATA
G_PAR/DVO_DETECT

G_C/BE#0/DVOB_D7
G_C/BE#1/DVOB_BLANK#
G_C/BE#2/ZV_VSYNC
G_C/BE#3/DVOC_D5

G_REQ#/ZV_CLK

RDRAM I/F

CTM
CTM#

DQ_A0
DQ_A1
DQ_A2
DQ_A3
DQ_A4
DQ_A5
DQ_A6
DQ_A7

DQ_B0
DQ_B1
DQ_B2
DQ_B3
DQ_B4
DQ_B5
DQ_B6
DQ_B7

Almador-M

PWR_3VMAIN

GND1

2

3

AGP I/F

G_AD13/DVOB_CLKINT#
G_AD14/DVOB_FLD/STL

G_AD16/DVOC_VSYNC
G_AD17/DVOC_HSYNC

G_AD18/DVOC_BLOCK#

G_AD31/DVOC_FLD/STL

AGP_RCOMP/DVOBC_RCOMP

R491
10K 1/16W 5%

2 1

RM3

1
2
3
4

10kx4 1/32W 5%

RM5

4
3
2
1

10kx4 1/32W 5%

GBOUT

G_AD0/DVOB_HSYNC
G_AD1/DVOB_VSYNC

G_AD2/DVOB_D0
G_AD3/DVOB_D0
G_AD4/DVOB_D3
G_AD5/DVOB_D2
G_AD6/DVOB_D5
G_AD7/DVOB_D4
G_AD8/DVOB_D6
G_AD9/DVOB_D9

G_AD10/DVOB_D8
G_AD11/DVOB_D11
G_AD12/DVOB_D10

G_AD15

G_AD19/DVOC_D0

G_AD20/DVOC_D1

G_AD21/DVOC_D2

G_AD22/DVOC_D3

G_AD23/DVOC_D4

G_AD24/DVOC_D7

G_AD25/DVOC_D6

G_AD26/DVOC_D9

G_AD27/DVOC_D8
G_AD28/DVOC_D11
G_AD29/DVOC_D10

AGP_BUSY#

ST0/ZV_D14
ST1/ZV_D13
ST2/ZV_D12

G_GNT#/ZV_D15(UV7)

GM_GCLK
GM_RCLK

CFM#

AGP_BUSY_PU33

8

DDC2_A_DATA_PU33

7
6

DDC2_A_CLK_PU33

5

SMT8

SMT8

5
6

CTM_PDGND

7

CTM#_PDGND

8

3

AD24

J29
J28
K26
K25
L26
J27
K29
K27
M29
M28
L24
M27
N29
M25
N26
N27
R25
R24
T29
T27
T26
U27
V27
V28
U26
V29
W29
V25
W26
W25
W27
Y29

AC24

AC28
AC29
AB27

AD29

K24

AGP_RCOMP

AG6
AJ6

AJ16

CFM

AH16

AG11

RQ0

AJ12

RQ1

AG12

RQ2

AH13

RQ3

AG13

RQ4

AJ13

RQ5

AG14

RQ6

AJ14

RQ7

AH7

CMD

AF7

SCK

AJ7

SIO

VCH_GMBSDA_A

VCH_GMBSCL_A

DVOA_FIELD_PDGND
DVOC_FIELD_PDGND

4

R70

C94

47 1/16W 5%

0.01uF 16V R

1 2

1 2

1 2

DVOB_DATA1
DVOB_DATA0
DVOB_DATA3
DVOB_DATA2
DVOB_DATA5
DVOB_DATA4
DVOB_DATA6
DVOB_DATA9
DVOB_DATA8
DVOB_DATA11
DVOB_DATA10

DVOB_CLKINT_PU15

Open
Intel confermed

DVOC_FIELD_PDGND

AGP_BUSY_PU33

Open
Intel confermed

AGP_RCOMP must be pulled down
to GND with 55 ohm resistor.

Open
Intel confermed

VCH_GMBSDA_A 26

VCH_GMBSCL_A 26

1 2

R72 47 1/16W 5%

R73 47 1/16W 5%

R84 54.9 1/16W 1%

4

AGP_BUSY_PU33 16

21

PWR_CPUBUS

FL5

BLM21P300S

CLK_GBO66 4

DVOB_HSYNC 24

DVOB_VSYNC 24

DVOB_DATA[0:11] 24

DVOB_STALL 24

DVOB_INT# 24

GND1

21

5

CLK_MCH_DREF484

DVOA_PCLK26

DVOA_RCOMP must be pulled down

GND1

to GND with 55 ohm resistor.

CRT_DDC1_CLK25

CRT_DDC1_CLK/DATA pullup had
CRT connector sections via Q-SW.

12

+

10uF 6.3V (TA)

C96

CRT_DDC1_DATA25

VCH_GMBSCL_A26
VCH_GMBSDA_A26

GND1

HL_STRB16
HL_STRB#16

GND1

FL6

BLM11B102S
FL8

BLM11B102S

FL10

BLM11B102S

6

PWR_1.5VMAIN

DVOA_PCLK

DVOA_FIELD_PDGND

R76 54.9 1/16W 1%

HL_RCOMP must be pulled down
to GND with 55 ohm resistor.

12

CRT_DDC1_CLK

CRT_DDC1_DATA

DDC2_A_CLK_PU33
DDC2_A_DATA_PU33

VCH_GMBSCL_A
VCH_GMBSDA_A

R77 255 1/16W 1%

1 2

R86 54.9 1/16W 1%

21

21

2 1

C98 1uF 10V12C99 1uF 10V

C725 0.1uF 16V 20%

GND1GND1

21

12

C101

GND1

C95,C96はGMCHF25,GMCHAC20ピンの近くに配置すること。

R87,R88,R90,R91,R92,R93,R94は、GMCH(M6)
から0.5inch以内に置き、配線は10mil以上にすること

Place R87,R88,R90,R91,R92,R93,R94 near GMCH (within 0.5 inch) and
the width of patterns must be more than 10 mil.

5

6

12

21

1uF 10V

2 1

C726 0.1uF 16V 20%

12

+

10uF 6.3V (TA)

C97

AC19

AE21

AD20

AE22

AC22

AE27
AD27

AE26
AD26

AD25
AC25

AJ27

AC20

AE20

G29

G24

AE6

AD7

F28

J23

F25

Rev.

7

M3D

DREFCLK

DVOA_INTR#

DVOA_CLKINT

DVOA_FLD/STL

DVOA_RCOMP

DVOA I/F

Analog Display I/F

DDC1_CLK
DDC1_DATA

DDC2_CLK
DDC2_DATA

I2C_CLK
I2C_DATA

REFSET

HUB I/F

HLSTRB
HLSTRB#

HL_RCOMP

Analogue Power

VCCA_DPLL0
VCCA_DPLL1

VSSA_DPLL0
VSSA_DPLL1

VCCA_HPLL

VSSA_HPLL

Almador-M

DATE Design

2001.01.16 Komahara

7

DVOA_CLK

DVOA_CLK#

DVOA_D0
DVOA_D1
DVOA_D2
DVOA_D3
DVOA_D4
DVOA_D5
DVOA_D6
DVOA_D7
DVOA_D8

DVOA_D9
DVOA_D10
DVOA_D11

DVOA_HSYNC
DVOA_VSYNC

DVOA_BLANK#

HSYNC
VSYNC

RED

GREEN

BLUE

RED#

GREEN#

BLUE#

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9

HL10

VCCA_CPLL

VSSA_CPLL

VCCA_DAC
VCCA_DAC

VSSA_DAC

Appr.

CheckDesign

Yoshida Aoki

AJ24
AG24

AJ22
AH22
AG22
AJ23
AH23
AG23
AE23
AE24
AJ25
AH25
AG25
AJ26

AF22
AF23

AD21

AD28
AE29

AF29
AG29
AH28

AF28
AG28
AH27

G26
H28
H29
H27
F29
F27
E29
E28
G25
G27
H26

G7

G8

AF26
AG27

AH26

Description

8

DVOA_CLKIN0
DVOA_CLKIN1

DVOA_DATA0
DVOA_DATA1
DVOA_DATA2
DVOA_DATA3
DVOA_DATA4
DVOA_DATA5
DVOA_DATA6
DVOA_DATA7
DVOA_DATA8
DVOA_DATA9
DVOA_DATA10
DVOA_DATA11

R74 47 1/16W 5%

1 2

R75 47 1/16W 5%

2 1

CRT_HSYNC
CRT_VSYNC

CRT_RED
CRT_GREEN
CRT_BLUE

CRT_RED#
CRT_GREEN#
CRT_BLUE#

HL[0:10] 16

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

FL7

21

BLM11B102S

C95

1uF 10V

GND1

FL9

12

BLM11B102S

12

+

C100

1uF 10V

C686

10uF 6.3V (TA)

GND1

Appr.

8

DVOA_CLKIN[0:1] 26

DVOA_DATA[0:11] 13,26

DVOA_HSYNC 26
DVOA_VSYNC 26

CRT_HSYNC 25
CRT_VSYNC 25

1 2

2 1

2 1

1 2

1 2

2 1

R79 75 1/16W 1%

R80 75 1/16W 1%

R81 37.4 1/16W 1%

R82 37.4 1/16W 1%

R78 75 1/16W 1%

12

PWR_1.8VMAIN

12

GMCH-M-2

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

CRT_RED 53,57
CRT_GREEN 53,57
CRT_BLUE 53,57

GND1

R83 37.4 1/16W 1%

SHEET

12 82

9

CAST

1

PWR_1.5VMAIN

PWR_1.8VMAIN

GND1

C108

GND1

12

0.01uF 16V R

◎

VGTLREF

SM_VREF14

HL_REF14,16

1

2

C99,C100はGMCHA8,GMCHA12に直接接続すること。
A8,A12pinは可能な限り広い電源ベタに貫通VIAで接続すること。（電源層が望ましい）
またGNDへの接続も貫通VIAで接続すること。
コンデンサはGMCHA8,GMCHA12の90mil(2.286mm)以内に配置すること。

PWR_CPUBUS PWR_3VSUS

M3E

Digital Power

N6

VCC

T6

VCC

H7

VCC

K7

VCC

L7

VCC

W7

VCC

Y7

VCC

AB7

VCC

P12

VCC

R12

VCC

T12

VCC

M14

VCC

M15

VCC

M16

VCC

P18

VCC

R18

VCC

T18

VCC

H23

VCC

K23

VCC

Y23

VCC

M24

VCC

P24

VCC

T24

VCC

V24

VCC

AC21

VCC_DVO

AF21

VCC_DVO

AF24

VCC_DVO

L23

VCC_AGP

U24

VCC_AGP

J26

VCC_AGP

M26

VCC_AGP

R26

VCC_AGP

V26

VCC_AGP

AA23

VCC_AGP

AA26

VCC_AGP

W23

VCCQ_AGP

N24

VCCQ_AGP

J24

VCC_HUB

F26

VCC_HUB

AC8

VCC_CMOS

AC9

VCC_CMOS

AE7

VCC_CMOS

AF6

VCC_CMOS

E11

NC

E20

21

C106 0.1uF 10V R21C107 0.1uF 10V R

◎

◎

21

GND1

◎のついた信号線は25mil以上の太さで配線し、
周りをベタのGNDで配線すること。

Thewidthofsignalsthatmarked"◎"mustbelaidout
morethan25milandguardatthebothsides,topand
bottombyGND1pattern.

NC

F12

NC

F20

NC

REF Voltage

E5

SM_REFA

F24

SM_REFB

H24

HLREF

J7

GTL_REFA

AA7

GTL_REFB

12

Almador-M

C103,C104,C105,C106,C107は各PINの近くに配置すること。

C110 0.1uF 10V R

C109 0.1uF 10V R

2

3

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM
VCC_LM

VCC_GPIO
VCC_GPIO

VCCQ_SM
VCCQ_SM
VCCQ_SM
VCCQ_SM
VCCQ_SM

VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM
VDD_LM

RAM_REFA
RAM_REFB

AGPREF

3

4

GND1

21

12

0.1uF 10V R

C102

D5
D8
D11
G11
D14
D17
D20
D23
G23
D26
G10
E12
A8
A12

AC10
AC11
AD11
AD12
AD13
AD17
AD18
AD19
AE18

AD23
AE25

E15
F7
F15
G19
G20

V14
V15
V16
AD15
AD16
AE15
AE16

E2

VTT

F5

VTT

J5

VTT

M5

VTT

R5

VTT

V5

VTT

AA5

VTT

AD5

VTT

AG5

VTT

AD14
AE14

J25

0.1uF 10V R

C103

PWR_3VSUS

PWR_CPUBUS

PWR_CPUBUS

◎

RAM_REF 14

◎

AGP_MCHREF 14,24,26

21

C105

4

PWR_1.8VMAIN

GND1

68pF 25V

5

12

68pF 25V

C104

GND1

C102はAE15,AE16の近くに配置すること。

Place C102 near AE15 and AE16 on
GMCH.

5

GND1

6

AD10
AE10
AF10
AE11
AF11
AH11

AE12
AF12
AH12

AE13
AF13

6

C21

AH2

AC5
AF5

AH6

AC7
AG7
AD8
AE8
AF8
AH8

AD9
AE9
AF9
AH9

M12
N12
U12

M13
N13

R13

U13

N14

R14

U14

7

M3F

A14

VSS

B13

VSS

C3

VSS
VSS

E14

VSS

F19

VSS

D2

VSS

G2

VSS

K2

VSS

N2

VSS

T2

VSS

W2

VSS

AB2

VSS

AE2

VSS
VSS

B3

VSS

E4

VSS

H5

VSS

L5

VSS

P5

VSS

U5

VSS

Y5

VSS
VSS
VSS

AJ5

VSS

B6

VSS
VSS

E7

VSS
VSS
VSS
VSS
VSS
VSS
VSS

B9

VSS

G9

VSS
VSS
VSS
VSS
VSS

E10

VSS
VSS
VSS
VSS
VSS
VSS
VSS

B12

VSS
VSS
VSS
VSS

V12

VSS
VSS
VSS
VSS

E13

VSS
VSS
VSS

P13

VSS
VSS

T13

VSS
VSS

V13

VSS
VSS
VSS
VSS

P14

VSS
VSS

T14

VSS
VSS

Almador-M

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

Rev.

DATE Design

2001.01.16 Komahara

AF14
AH14
B15
N15
P15
R15
T15
U15
AF15
AG15
E16
N16
P16
R16
T16
U16
AF16
AG16
M17
N17
P17
R17
T17
U17
V17
AE17
AF17
AH17
B18
M18
N18
U18
V18
AF18
AH18
E19
AE19
AF19
AH19
AF20
AH20
B21
G21
AG21
AH21
AJ21
E22
AD22
AB23
AC23
B24
AH24
E25
H25
L25
P25
U25
Y25
AF25
AC26
B27
AF27
D28
G28
K28
N28
T28
W28
AB28
AE28

7

Almador-M Strapping Options

GND1

Appr.

CheckDesign

Yoshida Aoki

8

DVOA_DATA012,26

DVOA_DATA112,26

DVOA_DATA512,26

DVOA_DATA612,26

R87 2.2k 1/16W 5% Reserve

R88 2.2k 1/16W 5%

R89 2.2k 1/16W 5%

R90 2.2k 1/16W 5% Reserve

21

12

PWR_1.5VMAIN

21

21

9

Reserve

GND1

Signal Notes

DVOA_D0

DVOA_D1

DVOA_D5

DVOA_D6

DVOA_D7

DVOA_D8

G_PAR 0=DVO B/C Device connected.

Description

0=Reserved
1=133MHz(default)

0=IOQD1
1=IOQD8(default)

0=Desktop(default)
1=Mobile

0=dual ended termination(default)
1=single ended termination

0=Normal opration (default)
1=XOR Chain test mode

0=Normal operation(default)
1=Tri-state all i830M outputs

1=AGP Device (Default)

GMCH-M-3,STRAP

Appr.

8

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

SHEET

9

CAST

13 82

1

PWR_3VSUS

21

R91

240 1/16W 1%

C138

2 1

470pF 25V

C158

1 2

470pF 25V

◎

12

R97

82 1/16W 1%

12

R100

82 1/16W 1%

◎

12

R93

47 1/16W 1%

GND1

上記信号<SMVREF>は配線が最短になるように部品を
GMCHの近くに配置すること。

PWR_1.5VMAIN

21

R96

1K 1/16W 1%

21

R99

1K 1/16W 1%

GND1

上記信号<AGPVGAREF>は配線が最短になるように部品を
GMCH(M6)の近くに配置すること。

2

SM_VREF 13

AGP_MCHREF 13,24,26

3

PWR_1.8VMAIN

12

R92

300 1/16W 1%

12

R94

300 1/16W 1%

GND1

上記抵抗とコンデンサは、極力GMCHとICH3の
中間になるよう配置し、それぞれの配線長は10cm
以内とすること

PWR_1.8VMAIN

21

R95

300 1/16W 1%

21

R98

300 1/16W 1%

GND1

上記信号<HUBVSWG>は配線が最短になるように部品を
ICH3の近くに配置すること。

◎

◎

4

HL_REF 13,16

HUBVSWG 16

5

21

C687 0.22uF 10V

PWR_CPUBUS

GND1

21

GND1

21

H

GND1

21

C159

J JKK

21

C127 0.1uF 16V

C139 0.1uF 16V

1uF 10V

21

C688 0.22uF 10V

21

21

Reserve

6

21

C689 0.22uF 10V

A

C128 0.1uF 16V

D

21

Reserve

C140 0.1uF 16V

PWR_3VSUS

C690 0.22uF 10V

Reserve

C141 0.1uF 16V

C160

GND1

21

12

21

21

C142 82pF 25V

1uF 10V

12

21

C113

C111 0.1uF 16V

C112 0.1uF 16V

B B

21

21

C131

C129 0.1uF 16V

C130 0.1uF 16V

21

21

C144 0.1uF 16V

C143 0.1uF 16V

21

C161 0.1uF 16V

GND1GND1

7

12

21

1uF 10V

C114 0.1uF 16V

C132 0.1uF 16V

21

Reserve

C145 0.1uF 16V

21

C162 0.1uF 16V

21

C133

21

C146 82pF 25V

21

C164

C163 0.1uF 16V

21

82pF 25V

E F

21

Reserve

21

12

C116

C115 0.1uF 16V

21

82pF 25V

C147 0.1uF 16V

82pF 25V

1uF 10V

C134 0.1uF 16V

21

21

21

21

C148 0.1uF 16V

Reserve

21

C165 0.1uF 16V

8

21

C117 0.1uF 16V

12

C135

21

C150

C149 0.1uF 16V

12

C167

C166 0.1uF 16V

PWR_1.5VMAINPWR_3VSUS

21

C118 0.1uF 16V

12

C136

0.1uF 10V R

21

82pF 25V

82pF 25V

21

C120 0.1uF 16V

C119 0.1uF 16V

PWR_1.8VMAIN

12

C137

0.1uF 10V R

G

21

C152 0.1uF 16V

C151 0.1uF 16V

Reserve

21

L

C168 0.1uF 16V

21

1uF 10V

21

21

9

21

C122 0.1uF 16V

C121 0.1uF 16V

21

C154 0.1uF 16V

C153 0.1uF 16V

PWR_1.5VMAIN

12

C170

1uF 10V

C169 0.1uF 16V

PWR_CPUBUS

21

C123 0.1uF 16V

PWR_3VSUS

21

Reserve

C155 0.1uF 16V

12

C124 0.1uF 16V

C

21

C156 82pF 25V

PWR_1.8VMAIN

12

R101

160 1/16W 5%

◎

12

R102

560 1/16W 5%

GND1

上記信号<RAMREF>は配線が最短になるように部品を
GMCH(M6)の近くに配置すること。

◎のついた信号線BGAPAD横に貫通THを空け
その裏面直下に部品を搭載、配線すること。

1

RAM_REF 13

2

A

1

Topview

C

12

C171

1uF 10V

J

J

GND1

H

J

J

2 1

Reserve

C706 10uF 6.3V B

H

12

C173

C172 0.1uF 16V

C174

82pF 25V

21

1uF 10V

12

M

GND1

G

B B

C

A A

L

PassC for GMCH-M

E

AJ

3

4

D

F

M

Rev.

DATE Design

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

14 82

1

ADD
pin
GND01

0

N.C
VCC

☆印の付いた信号線(CPUTHMDA,CPUTHMDC)は、
GND1で両側をガードすること
（下図参照）

10mil

10mil

10mil

10mil

GND1

CPUTHMDA

CPUTHMDC

GND1

2

A0

Address

01011,100
0A101011,00
1 01011,01

3

コンデンサは本ICの近くに配置

10mil

10mil

10mil

4

FAN_TACH

SMBCLK38,50,52
SMBDATA38,50,52

CPU_THMDA5 FANFAULT# 41

CPU_THMDC5

5

M4

2

TACH

16

SMBCLK
SMBDATA15INT#

10

DX+

9

DX-

3

NC

4

NC0

11

NC1

12

NC2

13

ADD

124

875

PWM_OUT

FANFAULT#

ADM1030_Rev3

PWR_5VMAIN

12

R103
10k 1/16W 5%

TP2
TACK

☆

12

C175

2200pF 25V

Reserve

☆

GND1

本ICはCPUの近くに配置願います。

6

PWR_3VMAIN

3

SMT8

6

THERM#

VCC

GND0

RM6

10kx4 1/32W 5%

1

14

7

8

PWR_3VMAIN

6

5

GND1

12

C176

0.1uF 16V

7

ADFANON

ATFINT# 38

THLTL# 16

8

9

TP95
FAN

FAN_TACH

GND1

Description

CheckDesign

Yoshida Aoki

CN22

01

TP96

TACK

21

C177

4.7uF 10V

8

Appr.

-

02

+

03

NC

FAN CN

Thermister,FAN

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

15 82

21

R105
47k 1/16W 5%

32

Q2
2SK3019

6

Q1

Si2305DS

1

32

Rev.

DATE Design

2001.01.16 Komahara

Appr.

7

PWR_5VSUS

12

R104
470k 1/16W 5%

ADFANON

1

2

3

4

5

2 1

C178

1000pF 25V

1

GND1

1

CLK_ICH144
CLK_ICH484
CLK_ICH664

HUBVSWG14
HL[0:10]12

C158はM8‑L19pinの
近くに配置すること。

HL1118

LPC_DRQ#019,37
LPC_DRQ#119

BSRBTN#40

THLTL#15

AGP_BUSY_PU3312

RIOUT#39

VGATE45

ICHPWROK17,25,40

RSMRST#40,45

CPU_FERR#5,8

EXTSMI#19,39
KBCSCI38
EXTSCI#39
BLUE_RI17,57
BLID40

PWR_RTC

R124はM8‑Y6pinの
近くに配置すること。

KBINIT#38
KBA20G38

1

21

GND1

GND1

R112

2 1

100k 1/16W 5%

GND1

C179

1uF 10V

PLLB#

2 1

C187

2 1

1000pF 25V

HL0

HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

J23
F20
T19

L19

L22

M21
M23

N20
P21
R22
R20
T23

M19

P19
N19
R19

AB1

AA1

AB3

V19

AA6

AA7

J22
U22
Y22

W2

C188

1000pF 25V

C9

C8

A8
A9

Y5

D8

T2

U4

U5

V4

C4

V2

Y4
Y2

Y6

2

M5A

CLK14
CLK48
CLK66

HITERM

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11

LAN_CLK

LAN_RXD0
LAN_RXD1
LAN_RXD2

LAN_RST#

EE_DIN

LDRQ#0
LDRQ#1

PWRBTN#

THRM#

AGPBUSY#

RI#

BATLOW#

VGATE/VRMPWRGD

PWROK

RSMRST#

FERR#
RCIN#
A20GATE

GPIO0/REQ#A
GPIO7
GPIO8
GPIO12
GPIO13

INTRUDER#

ICH3-M

SMLINK0_PU33
SMLINK1_PU33

2

HI_STB
HI_STB#
HICOMP

HIREF

LAN_RSTSYNC

LAN_TXD0
LAN_TXD1
LAN_TXD2

EE_SHCLK

EE_DOUT

EE_CS

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME#

SLP_S1#
SLP_S3#
SLP_S5#

SUS_STAT#/LPCPD#

C3_STAT#/GPIO21

STP_PCI#

STP_CPU#

DPRSLPVR

CPUPERF#

SSMUXSEL

A20M#

CPUSLP#

IGNNE#

INIT#
INTR

SMI#

STPCLK#

CPUPWRGD

DPSLP#

SUSCLK

SMLINK0
SMLINK1

RM7

8
7
5
6

SMT8

10kx4 1/32W 5%

3

◎のついた信号線は25mil以上の太さで配線し、
左右と下をベタのGND線で囲むこと

※抵抗R117はM8から0.5inch以内に置き、
10mil幅以上で配線すること。

N22
P23
K19

HL_COMPIAHL1

L20

◎

D7

B9
C10
A10

D10
E8
E9

V1
U3
T3
U2
U1

W20
AA5
AA2

AB4
V5
U21
V21
AB21

Y20
U20

V23
W21
AA21
AB23
AA23
Y21

NMI

Y23
U23

W23
AB22

AA4

CLK_32K_STD

AC3

SMLINK0_PU33
SMLINK1_PU33

AB2

PWR_5VMAIN

1
2
4
3

3

2 1

R106 36.5 1/16W 1%

12

C180

1uF 10V

GND1

Intel Checking!!!Intel Checking!!!

PWR_3VSTD

4

HL_STRB 12
HL_STRB# 12

GND1

HL_REF 13,14

C159はM8‑L20pinの
近くに配置すること。

LPC_AD0 20,37,39
LPC_AD1 20,37,39
LPC_AD2 20,37,39
LPC_AD3 20,37,39
LPC_FRAME# 19,20,37,39

SUSA# 71
SUSB# 4,37,40,42,45,60,61,62,69,76
SUSC# 50,62,70,71

SUSTAT# 37,40

STP_PCI# 4
STP_CPU# 4
DPRSLPVR 60

GLO/HI# 5
VR_HI/LO# 60

CPU_A20M# 5

CPU_IGNNE# 5
CPU_INIT# 5,8,20
CPU_INTR 5,8
CPU_NMI 5,8
CPU_SMI# 5,8
CPU_STPCLK# 5

CPU_PWRGD 5,8
CPU_DPSLP# 5,8,60

CLK_32K_STD 50

PWR_RTCBATT

12

C186

0.1uF 16V

GND1

4

PWR_RTCBATT

PWR_PMU

R110

1k 1/16W 5%

TP3
PWR_RTCBATT

CN20

1

2

RTC BAT CN

5

PCI_AD[0:31]27,29,42,50

PWR_3VMAIN

PWR_RTC

1SS400

D60

2 1

D61 1SS400

21

2 1

R113

1 2

1k 1/16W 5%

2 1

R114
15k 1/16W 5%

+

-

上記振動子(X2)は、ICH3(M7)の近傍に配置すること。
また、振動子両端のパターンに隣接して、
高速な信号を走らせてはならない。（層構成も考慮のこと）

5

C184 0.047uF 10V

2 1

RTCRST#

21

GND1

C181

GND1

C185 1uF 10V

12

1uF 10V

CL1

CL2

IRQ1456
IRQ1555,56

PCI_REQ#019,27
PCI_REQ#119,25
PCI_REQ#219,25

ICH_GPI117

PCI_SERR#19,27,29,42,50
WAKEOUT#39

USB_OC#049
USB_OC#149

USB_OC#549

4
1

2

CLK_ICH334

X2

VDD
VIO

GND

32.768KHz

GND1

6

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

1 2

R108

33K 1/16W 1%

PWR_RTC

R504 150K 1/16W 5%

3

OUT

6

2 1

1 2

R111 10M 1/16W 5%

1

T5

PCICLK

J2

AD0

K1

AD1

J4

AD2

K3

AD3

H5

AD4

K4

AD5

H3

AD6

L1

AD7

L2

AD8

G2

AD9

L4

AD10

H4

AD11

M4

AD12

J3

AD13

M5

AD14

J1

AD15

F5

AD16

N2

AD17

G4

AD18

P2

AD19

G1

AD20

P1

AD21

F2

AD22

P3

AD23

F3

AD24

R1

AD25

E2

AD26

N4

AD27

D1

AD28

P4

AD29

E1

AD30

P5

AD31

AB14

IRQ14

W19

IRQ15

D3

REQ#0

F4

REQ#1

A3

REQ#2

R4

REQ#3

E4

REQ#4

D4

REQ#5/REQ#B/GPIO1

L5

SERR#

W1

PME#

E12

OC#0/GPIO32

D12

OC#1/GPIO33

C12

OC#2/GPIO34

B12

OC#3/GPIO35

A12

OC#4/GPIO36

A11

OC#5/GPIO37

B21

USBRBIAS

AB6

VCCRTC

AC7

RTCX1

2 1

AC6

RTCX2

R503

10M 1/16W 5%

Reserve

AB7

VBIAS

Y7

RTCRST#

32

Q58
2SK3019

GND1

Rev.

7

M5B

ICH3-M

DATE Design

2001.01.16 Komahara

7

PIRQ#E/GPIO2

PIRQ#F/GPIO3
PIRQ#G/GPIO4
PIRQ#H/GPIO5

GNT#5/GNT#B/GPIO17

USBLEDA#0/GPIO32
USBLEDA#1/GPIO33
USBLEDA#2/GPIO34
USBLEDA#3/GPIO35
USBLEDA#4/GPIO36
USBLEDA#5/GPIO37
USBLEDG#0/GPIO38
USBLEDG#1/GPIO39
USBLEDG#2/GPIO40
USBLEDG#3/GPIO41
USBLEDG#4/GPIO42
USBLEDG#5/GPIO43

CLK_PMU32K 39,71

Appr.

CheckDesign

Yoshida Aoki

PCIRST#

C/BE#0
C/BE#1
C/BE#2
C/BE#3

DEVSEL#

FRAME#

IRDY#
TRDY#
STOP#

PAR

PLOCK#

PERR#

CLKRUN#

SERIRQ

PIRQ#A
PIRQ#B

PIRQ#C
PIRQ#D

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4

USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N

Description

PLLB40,71

8

Y1

K2

PCI_C/BE#0

K5

PCI_C/BE#1

N1

PCI_C/BE#2

R2

PCI_C/BE#3

M3
F1
N3
H1
H2
G5
M1

M2

AC2
H22

R107 22 1/16W 5%

B1
C1
B2
A2

A6
B5
C5
A5

A4
E3
D2
D5
B4
B3

D19
D18
A19
A18
E17
E16
B17
B16
D15
D14
A15
A14

H20
G22
F21
G19
E22
E21
H21
G23
F23
G21
D23
E23

Appr.

8

9

PCI_RST# 11,19,20,24,26,27,37,40

PCI_C/BE#[0:3] 27,29,42,50

PCI_DEVSEL# 19,27,29,42,50
PCI_FRAME# 19,27,29,42,50
PCI_IRDY# 19,27,29,42,50
PCI_TRDY# 19,27,29,42,50
PCI_STOP# 19,27,29,42,50
PCI_PAR 27,29,42,50
PCI_LOCK# 19,29

PCI_PERR# 19,27,29,42,50

PCI_CLKRUN# 19,27,29,37,42,50

21

SERIRQ 19,29,37

R118はM8‑H22pinの
近くに配置すること。

PCI_INT#0 19,29
PCI_INT#1 19,29
PCI_INT#2 19,50
PCI_INT#3 19,50

PCI_INT#4 19,27
PCI_INT#5 19,42
PCI_INT#6 19
PCI_INT#7 19

PCI_GNT#0 27
PCI_GNT#1 29
PCI_GNT#2 50
PCI_GNT#3 42PCI_REQ#319,42

USB_P0P 49
USB_P0N 49
USB_P1P 49,53
USB_P1N 49,53
USB_P2P 55
USB_P2N 55
USB_P5P 52
USB_P5N 52
USB_P4P 52
USB_P4N 52
USB_P3P 57
USB_P3N 57

FR_USBON 52

ICH_GPIO42 18
ICH_GPIO43 18

PWR_3VSTD

21

R115

100k 1/16W 5%

PLLB#

32

Q3
2SK3019

1

GND1

ICH3-M-1

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

SHEET

9

CAST

16 82

1

2

3

4

5

6

7

8

PWR_3VMAIN

9

M5C

IDE_PDD[0:15]56

IDE_PDDREQ56
IDE_PDIORDY56

IDE_SDD[0:15]55,56

IDE_SDDREQ55,56
IDE_SDIORDY56

AC97_BITCLK50

AC97_SDIN033
AC97_SDIN150

CLK_ICHAPIC334 CPU_APICD0 5,8

R120
330 1/16W 5%

1 2

GND1

Reserve

PCICACT#40
SERB_SIN137

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

C175はM8‑B7pinの近くに配置すること。

C195

GND1

W12

PDD0

AB11

PDD1

AA10

PDD2

AC10

PDD3

W11

PDD4

Y9

PDD5

AB9

PDD6

AA9

PDD7

AC9

PDD8

Y10

PDD9

W9

PDD10

Y11

PDD11

AB10

PDD12

AC11

PDD13

AA11

PDD14

AC12

PDD15

AB12

PDDREQ

AB13

PIORDY

Y17

SDD0

W17

SDD1

AC17

SDD2

AB16

SDD3

W16

SDD4

Y14

SDD5

AA13

SDD6

W15

SDD7

W13

SDD8

Y16

SDD9

Y15

SDD10

AC16

SDD11

AB17

SDD12

AA17

SDD13

Y18

SDD14

AC18

SDD15

AB18

SDDREQ

AB19

SIORDY

AC_BIT_CLKB7AC_SYNC

B11

AC_SDIN0

C11

AC_SDIN1

J19

APICCLK

AC5

SMBALERT#/GPIO11

W3

GPIO25

W4

GPIO27

Y3

GPIO28

ICH3-M

12

10pF 25V Reserve

GPIO16/GNT#A

PDCS#1
PDCS#3

PDA0
PDA1
PDA2

PDDACK#

PDIOR#

PDIOW#

SDCS#1
SDCS#3

SDA0
SDA1
SDA2

SDDACK#

SDIOR#

SDIOW#

SPKR

AC_SDOUT

AC_RST#

APICD0
APICD1

SMBCLK

SMBDATA

AC15
AB15

AA14
AC14
AA15

Y13

AC13

Y12

AC21
AC22

AC20
AA19
AB20

Y19

AC19

AA18

H23

B6

R118 0 1/16W

A7

R119 0 1/16W

C7

D11

J20
J21

AC4
AB5

C2

N/C

E7

N/C

T21

N/C

D6

N/C

T1

N/C

ICHPWROK16,25,40

ICHSMBALT#71

BLUE_RI16,57

SMB_CLK_ICH1

ICH_GPI1

12

21

SMB_CLK_ICH1

IDE_PDCS#1 56
IDE_PDCS#3 56

IDE_PDA0 56
IDE_PDA1 56
IDE_PDA2 56

IDE_PDDACK# 56

IDE_PDIOR# 56

IDE_PDIOW# 56

IDE_SDCS#1 55
IDE_SDCS#3 55

IDE_SDA0 55
IDE_SDA1 55
IDE_SDA2 55

IDE_SDDACK# 55

IDE_SDIOR# 56

IDE_SDIOW# 56

SPKSYS 18,39

R130,R131はM8(ICH3)の
近くに配置すること。

AC97_SYNC 33,50

AC97_SDOUT 18,33,50

AC_RST# 33,50

CPU_APICD1 5,8

3 2

RM8

1
2
3

16

4

10kx4 1/32W 5%

Q4

2SK3019

1

SMT8

8
7
6
5

PWR_1.8VSTD

PWR_1.8VMAIN

SMB_CLK_ICH 4,23,25,50ICHSMBALT#71

SMB_DATA_ICH 4,23,25,50

PWR_3VMAIN

PWR_3VSTD

PWR_1.5VMAIN

GND1

U18

C23

M14

R18

U19

C14
C15
C16
C17
C18
C19
C20
C21
C22

D13
D16
D17
D20
D21
D22

G20
H19

P14

V22

B23

E13
F14
F15
F16
K12
P10

E11

J18

K18

P18

T18

V10
V14

K10

A13
A16
A17
A20
A23

B10
B13
B14
B15
B18
B19
B20
B22

C3
C6

F19

D9

E14
E15
E18
E19
E20
F22

G3

K11
K13
K20
K21
K22
K23
A21

V6
V7

K6

P6

F7
F8

A1

B8

E5

J5

M5D

V_CPU_IO
V_CPU_IO
V_CPU_IO

VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

VCCLAN1_8
VCCLAN1_8
VCCLAN1_8

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

ICH3-M

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

VCCLAN3_3
VCCLAN3_3

V5REF1
V5REF2

V5REF_SUS1
V5REF_SUS2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

PWR_3VMAIN

F6
G6
G18
H6
H18
J6
M10
P12
R6
T6
U6
V15
V16
V17

PWR_3VSTD GND1

V18

E10
F17
F18
K14
V8
V9

F9
F10

E6
W8

C13
W5

L3
L10
L11
L12
L13
L14
L21
L23
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N21
N23
P11
P13
P20
P22
R3
R5
R21
R23
T4
T20
T22
V3
AA22
V20
W6
W7
W10
W14
W18
W22
Y8
AA3
AA8
AA12
AA16
AA20
AB8
AC1
AC8
AC23
A22

PWR_3VMAIN

GND1

21

C190

C189

1 2

1000pF 25V

PWR_5VREF_MAIN

21

D3

RB521S-30

R116
1k 1/16W 5%

C191

1 2

1uF 10V

PWR_5VREF_STD

1 2

GND1

GND1

PWR_5VMAIN

12

PWR_3VSTD

21

D4

C194
1uF 10V

0.1uF 16V

C192

1 2

RB521S-30

R117
1k 1/16W 5%

上記部品はM8(ICH3)の近くに配置すること。

21

C193

1000pF 25V

GND1

PWR_5VSUS

21

0.1uF 16V

ICH3-M-2

TITLE

◎のついた信号線は25mil以上の太さで配線し、
左右と下をベタのGND線で囲むこと

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

17 82

1

2

3

4

5

6

7

8

9

PWR_3VMAIN

Thise ressister use for strap signal.

R121 1k 1/16W 5% Reserve

SPKSYS17,39

AC97_SDOUT17,33,50

2 1

R122 1k 1/16W 5% Reserve

2 1

SPKSYS

AC97_SDOUT

Configuration Table

0=Nomal mode (Default)
1=NO REBOOT

0=Nomall mode (Deflault)
1=SAFE MODE

下記のICH3のコンデンサは、各電源ピンの近くに均等に配置すること。
また複数種類のコンデンサがある場合は、容量の小さいコンデンサを優先的に各電源ピンの近くに配置すること。

PWR_3VMAIN

ICH3

21

C196 0.1uF 10V R12C197 0.1uF 10V R21C198 47pF 25V12C199 0.1uF 10V R21C200 0.1uF 10V R12C201 47pF 25V

R124 10k 1/16W 5%

HL1116

USB_OC#549

2 1

R489 10k 1/16W 5%

2 1

PWR_1.8VMAIN

2001.01.31
DeletePart
R137を削除

PWR_5VSUS

12

12

C209 0.1uF 10V R

C208 0.1uF 10V R

12

12

12

C210 0.1uF 10V R

PWR_3VSTD PWR_1.8VSTD

C217 0.1uF 10V R

C218 1uF 10V21C219 0.1uF 10V R

12

C211 0.1uF 10V R12C213 47pF 25V

C212 0.1uF 10V R

12

12

C202 0.1uF 10V R12C203 47pF 25V

PWR_1.8VMAIN

12

C214 0.1uF 10V R

C220 0.1uF 10V R21C221 0.1uF 10V R21C222 0.1uF 10V R

12

12

C204 0.1uF 10V R

2001.01.23
PartChange

12

C191を47pF25V‑>0.1uF10VRに変更
Reserve‑>Mount
C190をMountに変更

C215 0.1uF 10V R

GND1

12

GND1

C205 47pF 25V

12

C206 0.1uF 10V R21C207 0.1uF 10V R

GND1

R125 10k 1/16W 5%

ICH_GPIO4216

ICH_GPIO4316

1 2

R126 10k 1/16W 5%

1 2

PWR_3VMAIN

C223 1uF 10V21C224 0.1uF 10V R12C225 0.1uF 10V R

PWR_1.5VMAIN

12

GND1

Pullup & PassC for ICH3-M

本ページの部品はM8(ICH3)の近くに配置すること。

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

18 82

1

2

3

4

5

6

7

PWR_3VMAIN

8

9

RM9

PCI_INT#316,50
PCI_INT#016,29
PCI_INT#216,50
PCI_INT#116,29

PCI_INT#416,27
PCI_INT#716
PCI_INT#516,42
PCI_INT#616

PCI_PERR#16,27,29,42,50
PCI_TRDY#16,27,29,42,50
PCI_IRDY#16,27,29,42,50
PCI_SERR#16,27,29,42,50

PCI_FRAME#16,27,29,42,50
PCI_STOP#16,27,29,42,50
PCI_LOCK#16,29
PCI_DEVSEL#16,27,29,42,50

8
7
6
5

8.2kx4 1/32W 5%

RM10

4
3
2
1

8.2kx4 1/32W 5%

RM11

1
2
3
4

8.2kx4 1/32W 5%

RM12

8
7
6
5

8.2kx4 1/32W 5%

SMT8

SMT8

SMT8

SMT8

1
2
3
4

5
6
7
8

8
7
6
5

1
2
3
4

1 2

330pF 50V

Reserve

RM13

8
7
6
5

SMT8

8.2kx4 1/32W 5%

RM15

1

11,16,20,24,26,27,37,40

3
2
4

8.2kx4 1/32W 5%

C227

0.1uF 16V

Reserve

SMT8

1
2
3
4

8
6
7
5

GND1

PWR_3VMAIN

RM14

LPC_DRQ#116
LPC_DRQ#016,37

LPC_FRAME#16,20,37,39

1
2
3
4

10kx4 1/32W 5% res

Reserve

1 2

SMT8

R127

10k 1/16W 5%

Reserve

8
7
6
5

枠内は自由にピンスワップ可

PCI_REQ#216,25
PCI_REQ#016,27
PCI_REQ#116,25
PCI_REQ#316,42

PCI_CLKRUN#16,27,29,37,42,50

PCI_RST#

SERIRQ16,29,37

EXTSMI#16,39

21

C226

GND1

本枠内の部品は、ICH3‑Mの近くに配置すること。

Pullup for AGP,PCI,LPC

本ページの部品はM8(ICH3)の近くに配置すること。

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

19 82

1

2

3

4

5

6

M6

7

8

9

CLK_FWH334

FWHTBL#40

FWHWP#40

PCI_RST#11,16,19,24,26,27,37,40

LCDID024,57
LCDID124,57

PWR_1.5VMAIN

1

CPU_INIT#5,8,16

RM16

LCDID124,57
LCDID024,57

FWHINIT#

FWHWP#

8
7
6

40

5

SMT8

10kx4 1/32W 5%

2 3

1
2
3
4

FWHINIT#

Q5

DTC143TEA

PWR_3VMAIN

GND1

GND1

FWHINIT#

9

CLK

20

TBL#

19

WP#

37

INIT#

12

RST#

18

FGPI0

17

FGPI1

16

FGPI2

15

FGPI3

7

FGPI4

2

IC

1

NC0

3

NC1

4

NC2

5

NC3

6

NC4

8

NC5

13

NC6

14

NC7

FWH1-8MB

25

FWH0

26

FWH1

27

FWH2

28

FWH3

38

FWH4

24

ID0

23

ID1

22

ID2

21

ID3

32

RFU0

33

RFU1

34

RFU2

35

RFU3

36

RFU4

10

VCC0

31

VCC1

39

VCCA

11

VPP

29

GND0

30

GND1

40

GNDA

LPC_AD016,37,39

LPC_AD116,37,39

LPC_AD216,37,39

LPC_AD316,37,39

LPC_FRAME#16,19,37,39

CLK_FWH334

PCI_RST#11,16,19,24,26,27,37,40

本枠内のTPは一列に配置すること

LPC_AD0 16,37,39
LPC_AD1 16,37,39
LPC_AD2 16,37,39
LPC_AD3 16,37,39
LPC_FRAME# 16,19,37,39

PWR_3VMAIN

21

C228

0.1uF 16V

GND1

PWR_5VMAIN

PWR_3VMAIN

GND1

TP4
DEBUG09
TP5
DEBUG00
TP6
DEBUG01
TP7
DEBUG02
TP8
DEBUG03
TP9
DEBUG04
TP10
DEBUG05
TP11
DEBUG06
TP12
DEBUG07
TP13
DEBUG08

FWH(BIOS)

TITLE

本ページの部品はM10(FWH)の近くに配置すること。

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

20 82

1

2

3

4

5

6

7

8

9

MEMAA[0:12],MEMRAS#,MEMCAS#,MEMWE#,MEMBA[0:1]の配線条件

L0 L1 L2

SO-DIMM
PAD

MEM_RAS#D 23
MEM_CAS#D 23
MEM_BA0D 23
MEM_BA1D 23

MEM_WE#D 23

slot_0slot_1

GMCH

Section

L0

L0+L1

L0+L1+L2

MEM_AA[0:12]11 MEM_ADA[0:12] 23

MEM_RAS#11
MEM_CAS#11
MEM_BA011
MEM_BA111

MEM_WE#11

Mnimum

Maximum

0.8inch

N/A

N/A

N/A

6.0inch

RM17

4
3
2
1

10x4 1/32W 5%

RM18

8
7
6
5

SMT8

10x4 1/32W 5%
RM19

1
2
3
4

10x4 1/32W 5%
R128

10 1/16W 5%

RM20

1
2
3
4

10x4 1/32W 5%

R129

10 1/16W 5%

SMT8

SMT8

SMT8

5

MEM_ADA0

6

MEM_ADA1

7

MEM_ADA3

8

MEM_ADA2

1

MEM_ADA4

2

MEM_ADA5

3

MEM_ADA7

4

MEM_ADA6

8

MEM_ADA8

7

MEM_ADA9

6

MEM_ADA10

5

MEM_ADA11

12

8
7
6
5

12

1.5inch

MEM_AA0
MEM_AA1
MEM_AA3
MEM_AA2

MEM_AA4
MEM_AA5
MEM_AA7
MEM_AA6

MEM_AA8
MEM_AA9
MEM_AA10
MEM_AA11

MEM_AA12 MEM_ADA12

枠内は自由にピンスワップ可

CLKDIMM[0:3]の配線条件

L0 L1

GMCH

SO-DIMM
PAD

SectionL0Mnimum Maximum

N/A

0.25inch

L0+L1 4.9inch 5.1inch

CLKDIMM[0:3]のお互いの線長を+/‑100milにすること。

MEMCS#[0:3],MEMCKE[0:3]の配線条件

L0

GMCH

SO-DIMM
PAD

MaximumSection

L0

CLKDIMM[0:3]の配線長より‑0.2inch+/‑100milで
配線すること。

1.5inch

Mnimum

5.0inch

MEMD[0:63],MEMDQM[0:7]の配線条件

GMCH

SO-DIMM
PAD

Section

L0+L1

L1

MEMD[0:63],MEMDQM[0:7]の全信号線は
お互いの配線長誤差を+/‑0.5inchにすること。

Mnimum

1.5inch

N/A

Maximum

4.0inch

0.7inch

L1L0

slot_0slot_1

SDRAM Dumping
System Memory Design Guideline

TITLE

Rickwood Main Board

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

22 82

1

MEM_D[0:63]11

MEM_DQM[0:7]11

MEM_ADA022
MEM_ADA122
MEM_ADA222

MEM_D[0:63]11

CLK_DIMM011

MEM_RAS#D22
MEM_WE#D22
MEM_CS#011
MEM_CS#111

MEM_D[0:63]11

MEM_ADA622

MEM_ADA822

MEM_ADA922
MEM_ADA1022
MEM_DQM[0:7]11

MEM_D[0:63]11 MEM_D[0:63] 11

SMB_DIMM_DATA0

CLK_DIMM211

MEM_CS#2

MEM_CS#311

SMB_DIMM_DATA1

2

MEM_D31
MEM_D30
MEM_D29
MEM_D28

MEM_D27
MEM_D26
MEM_D25
MEM_D24

MEM_DQM3
MEM_DQM2

MEM_ADA0
MEM_ADA1
MEM_ADA2

MEM_D23
MEM_D22
MEM_D21
MEM_D20

MEM_D19
MEM_D18
MEM_D17
MEM_D16

MEM_D15
MEM_D14
MEM_D13
MEM_D12

MEM_D11
MEM_D10
MEM_D9
MEM_D8

MEM_ADA6
MEM_ADA8

MEM_ADA9
MEM_ADA10

MEM_DQM1

MEM_D7
MEM_D6
MEM_D5
MEM_D4

MEM_D3
MEM_D2
MEM_D1
MEM_D0

11

PWR_3VSUS

141B

141A

3

CN11

LOWER_SLOT

1

GND1

3

DQ0

5

DQ1

7

DQ2

9

DQ3

11

VDD1

13

DQ4

15

DQ5

17

DQ6

19

DQ7

21

GND2

23

DQM0

25

DQM1

27

VDD2

29

A0

31

A1

33

A2

35

GND3

37

DQ8

39

SQ9

41

DQ10

43

DQ11

45

VDD3

47

DQ12

49

DQ13

51

DQ14

53

DQ15

55

GND4

57

NC1

59

NC2

61B

CLK0

63

VDD4

65

RAS0

67

WE

69B

CS0

71B

CS1

73

GND5

75

GND6

77

NC3

79

NC4

81

VDD5

83

DQ16

85

DQ17

87

DQ18

89

DQ19

91

GND7

93

DQ20

95

DQ21

97

DQ22

99

DQ23

101

VDD6

103

A6

105

A8

107

GND8

109

A9

111

A10

113

VDD7

115

DQM2

117

DQM3

119

GND9

121

DQ24

123

DQ25

125

DQ26

127

DQ27

129

VDD8

131

DQ28

133

DQ29

135

DQ30

137

DQ31

139

GND10
IIS_DATA0

143

VDD9

61A

CLK2

69A

CS2

71A

CS3
IIS_DATA1

UPPER_SLOT

144_PIN

GND11

DQ32
DQ33
DQ34
DQ35

VDD10

DQ36
DQ37
DQ38
DQ39

GND12

DQM4
DQM5

VDD11

GND13

DQ40
DQ41
DQ42
DQ43

VDD12

DQ44
DQ45
DQ46
DQ47

GND14

CKE0

VDD13

CAS0
CKE1

GND15

CLK1

GND16

VDD14

DQ48
DQ49
DQ50
DQ51

GND17

DQ52
DQ53
DQ54
DQ55

VDD15

GND18

VDD16

DQM7
DQM8

GND19

DQ56
DQ57
DQ58
DQ59

VDD17

DQ60
DQ61
DQ62
DQ63

GND20

IIS_CLK0

VDD18

CKE2
CKE3

CLK3

IIS_CLK1

NC5
NC6

NC7
NC8

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

A3

32

A4

34

A5

36
38
40
42
44
46
48
50
52
54
56
58
60
62A
64
66
68A
70

A12

72
74A
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104

A7

106

BA0

108
110

BA1

112

A11

114
116
118
120
122
124
126
128
130
132
134
136
138
140
142A
144

62B
68B
74B
142B

GND1GND1

4

MEM_D63
MEM_D62
MEM_D61
MEM_D60

MEM_D59
MEM_D58
MEM_D57
MEM_D56

MEM_DQM7
MEM_DQM6

MEM_ADA3
MEM_ADA4
MEM_ADA5

MEM_D55
MEM_D54
MEM_D53
MEM_D52

MEM_D51
MEM_D50
MEM_D49
MEM_D48

MEM_ADA12

MEM_D47
MEM_D46
MEM_D45
MEM_D44

MEM_D43
MEM_D42
MEM_D41
MEM_D40

MEM_ADA7

MEM_ADA11

MEM_DQM5
MEM_DQM4MEM_DQM0

MEM_D39
MEM_D38
MEM_D37
MEM_D36

MEM_D35
MEM_D34
MEM_D33
MEM_D32

11

5

MEM_D[0:63] 11

注意：
MEMD56‑D63等、各破線ｸﾞﾙｰﾌﾟ内であれば自由にﾋﾟﾝｽﾜｯﾌﾟが可能。
例：MDMD56,MDMD53をｽﾜｯﾌﾟ
補足事項：
破線単位での他信号を含めたｽﾜｯﾌﾟについても可能ではあるが
実施する場合は、ネットの一時戻しOrCADからの再生成を条件

MEM_DQM[0:7] 11

とします。
例：MEMD56‑D63とMEMD48,D55をｸﾞﾙﾌﾟ単位で丸々ｽﾜｯﾌﾟ

MEM_ADA3 22
MEM_ADA4 22
MEM_ADA5 22
MEM_D[0:63] 11

MEM_CKE0 11

MEM_CAS#D 22
MEM_CKE1 11
MEM_ADA12 22

CLK_DIMM1 11

MEM_D[0:63] 11

MEM_ADA7 22
MEM_BA0D 22

MEM_BA1D 22
MEM_ADA11 22
MEM_DQM[0:7] 11

SMB_CLK_ICH 4,17,25,50

MEM_CKE2 11
MEM_CKE3
CLK_DIMM3 11

PWR_3VSUS

6

SMB_CLK_ICH

SMB_DATA_ICH4,17,25,50

4,17,25,50

7

4,17,25,50

PWR_3VSUS

BLEN

SMB_CNCT140

3VMAINOK#40

8

PWR_3VSUS

123

4

GND1

876

5

M7

2

1A

5

2A

9

3A

12

4A

1

1OE#

4

2OE#

10

3OE#

13

4OE#

CBT3125PW,PI5C3125L,FST3125MTC

VCC

GND

3

1B

6

2B

8

3B

24

11

4B

14

7

RM21

ARRAY

10Kx4 1/32W 5%

PWR_5VSUS

21

C229

0.1uF 16V

GND1

9

SMB_DIMM_DATA0

SMB_DIMM_DATA1

GBLEN

12

12

C230 0.1uF 16V12C231 0.1uF 16V21C232 0.1uF 16V12C233 0.1uF 16V12C234 0.1uF 16V

GND1

本コンデンサは、コネクタの電源PINの近傍に配置すること。

1

コンデンサは、0.1uFを優先的に各電源ピンの近くに配置すること。

2

3

C235 0.1uF 16V

21

C236 0.1uF 16V

12

4

C237 0.1uF 16V

21

C239

C238 0.1uF 16V

12

4.7uF 6.3V R

DIMM CN

TITLE

Rickwood Main Board

DRAW. No.

Rev.

DATE Design

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

23 82

1

D5

PCI_RST#11,16,19,20,26,27,37,40

SUSB#11,16,19,20,26,27,37,40

PWR_1.5VMAIN

VCH_GMBSDA_B12

1

1SS400

DVOCLKIN0,1のビアはシルクで表示

Mark via of DVO_CLKIN0,1 with silk.

1

1

D56
1SS400

21

12

GND1

2

C240

1000pF 25V

Reserve

21

AGP_MCHREF13,14,26

Q6

DTC143TEA

2 3

2

VCH_PCIRST#_PU25

DVOB_DATA[0:11]12

DVOB_CLKIN[0:1]12

Q8

DTC143TEA

2 3

3

CLK_VCH144

DVOB_DATA0
DVOB_DATA1
DVOB_DATA2
DVOB_DATA3
DVOB_DATA4
DVOB_DATA5
DVOB_DATA6
DVOB_DATA7
DVOB_DATA8
DVOB_DATA9
DVOB_DATA10
DVOB_DATA11

GND1

DVOB_CLKIN0
DVOB_CLKIN1

DVOB_HSYNC12
DVOB_VSYNC12

DVOB_BLANK#12

VCH_PD#_PU25

VCH_BAL

VCH_COLOR
VCH_EDGE

VCH_TEST2

C241

2 1

0.1uF 10V

GND1 GND1

PWR_1.5VMAIN

VCH_GMBSCL_B12

3

4

M8A

18

CLK_REF

61

RESET#

17

DVO_D0

16

DVO_D1

15

DVO_D2

14

DVO_D3

13

DVO_D4

12

DVO_D5

9

DVO_D6

8

DVO_D7

7

DVO_D8

6

DVO_D9

5

DVO_D10

4

DVO_D11

32

DVO_D12

31

DVO_D13

30

DVO_D14

29

DVO_D15

28

DVO_D16

27

DVO_D17

26

DVO_D18

25

DVO_D19

24

DVO_D20

23

DVO_D21

22

DVO_D22

21

DVO_D23

10

DVO_CLKINP

11

DVO_CLKINM

2

DVO_HSYNC

1

DVO_VSYNC

3

DE

99

PD#

97

BAL

35

DUAL

34

COLOR

36

EDGE

83

VREF

19

TST1

20

TST2

85

TST3

DS90C2501

GMBus Address : 70h ( 0,1,1,1, A2,A1,A0,x )

1

ENAVDD/GPIO0

ENABLK/GPIO1

PWM/GPIO2

VSTALL/GPIO3

HIRQ/GPIO4

RESERVED1
RESERVED2
RESERVED3
RESERVED4

Q7

DTC143TEA

2 3

72

SCLK

71

SDAT

117

A2

116

A1

115

A0

37

CLK2P

38

CLK2M

39

A7P

40

A7M

41

A6P

42

A6M

43

A5P

44

A5M

45

A4P

46

A4M

49

CLK1P

50

CLK1M

47

A3P

48

A3M

51

A2P

52

A2M

53

A1P

54

A1M

55

A0P

56

A0M

69
68
67
66

65
64

GPIO5

63

GPIO6

62

GPIO7

57

LID0

58

LID1

59

LID2

60

LID3

98

MSEN

114
70
113
100

DVO_GMBSCL_B25DVO_GMBSDA_B25

VCH_LD0_PU33
VCH_LD1_PU33

VCH_RSVD1

GND1

5

VCH_GPIO5
VCH_GPIO6
VCH_GPIO7

このページの部品はVCHの近くに置くこと

Place all components in this page near VCH.

4

5

DVO_GMBSCL_B25
DVO_GMBSDA_B25

GND1

DVOB_STALLV

VCH_MSEN_PU15

LVDS_LC+ 47
LVDS_LC- 47

LVDS_L2+ 47
LVDS_L2- 47
LVDS_L1+ 47
LVDS_L1- 47
LVDS_L0+ 47
LVDS_L0- 47

LCDEN 40
BLEN 40

6

6

R137

2 1

0 1/16W 5%

Reserve

R132

0 1/16W 5%

Reserve

12

R138

10K 1/16W 5%

GND1

21

DVOB_STALL 12

DVOB_INT# 12

Rev.

DATE Design

2001.01.16 Komahara

7

VCH_RSVD4

VCH_RSVD1

VCH_RSVD1

VCH_GPIO5
VCH_GPIO6

VCH_GPIO7

VCH_MSEN_PU15

VCH_COLOR

VCH_BAL

VCH_EDGE

VCH_EDGE
VCH_COLOR
VCH_BAL
VCH_TEST2

DVO_GMBSCL_B25
DVO_GMBSDA_B25
VCH_LD1_PU33
VCH_LD0_PU33

VCH_PCIRST#_PU25

VCH_PD#_PU25

Appr.

CheckDesign

7

Yoshida Aoki

8

If PullUped

Scalar Bypass enable

CLKINx invert

R130 10k 1/16W 5% Reserve

R131 10k 1/16W 5%

R134

2 1

R135

2 1

R136

2 1

VCH_BAL

VCH_EDGE

VCH_COLOR

VCH_DUAL

R133

R482

Description

Appr.

8

21

21

GND1

RM22

8
7
6
5

10kx4 1/32W 5%

0 1/16W 5% Reserve

0 1/16W 5% Reserve

0 1/16W 5% Reserve

RM23

8
7
6
5

10kx4 1/32W 5%

SMT8

SMT8

1
2
3
4

1
2
3
4

Configuration Table

0=DC Balanced disabled
1=DC Balanced enabled

0=Falling edge
1=Rising egde

0=conventional color mapping
1=non-conventional color mapping
0=single pixel
1/2V=single pixel to dual pixel
1=dual pixel to dual pixel

RM24

SMT8

5
6
7
8

10kx4 1/32W 5%

21

21

4
3
2
1

10k 1/16W 5%

10k 1/16W 5%

VCH

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

PWR_2.5VSUS

GND1

PWR_3VSUS

PWR_2.5VSUS

SHEET

9

PWR_1.5VMAIN

GND1

CAST

24 82

1

2

3

NOTE for LDO
Input:PWR_3VSUS
Output:PWR_VCH2.5/500mA(max)
Output contl

4

5

6

7

8

9

下記コンデンサはVCHの各電源ピンの近くに１個づつ配置のこと。

4.7uFのｺﾝﾃﾞﾝｻは電源ﾌﾟﾚｰﾝ接続位置付近に配置する。
PWR2.5VMAIN-PWR3VMAIN間ｺﾝﾃﾞﾝｻは、Pin
107-105間に最短距離で実装すること。

GND1

PWR_VCHPLLPWR_2.5VSUS

M8B

87

SPLLVCC

89

SPLLVCC

92

PLLVCC

94

PLLVCC

75

VCC2.5

77

VCC2.5

81

VCC2.5

82

VCC2.5

96

VCC2.5

119

VCC2.5

123

VCC2.5

125

VCC2.5

86

SPLLGND

88

SPLLGND

90

SPLLGND

91

PLLGND

93

PLLGND

95

PLLGND

33

GND2.5

73

GND2.5

74

GND2.5

76

GND2.5

78

GND2.5

79

GND2.5

80

GND2.5

84

GND2.5

118

GND2.5

122

GND2.5

124

GND2.5

DS90C2501

VCC3V
VCC3V

VCCLVDS3V
VCCLVDS3V
VCCLVDS3V
VCCLVDS3V

VCCLVDS
VCCLVDS

GND3V
GND3V
GND3V

GNDLVDS3V
GNDLVDS3V
GNDLVDS3V
GNDLVDS3V

GNDLVDS
GNDLVDS

121
127

101
103
107
111

105
109

120
126
128

102
106
110
112

104
108

GND1

PWR_3VSUS PWR_2.5VSUS

PWR_5VMAIN

21

876

123

D6

1SS400

5

4

SMT8

RM25

10kx4 1/32W 5%

PWR_3VSUS

PWR_2.5VSUS

21

C242 0.1uF 10V

FL11

2 1

BLM21A601SPB

21

21

C243 0.1uF 10V

21

C259

C244 0.1uF 10V

21

12

C249 0.1uF 10V12C250 0.1uF 10V

4.7uF 6.3V R

1 2

C251 0.1uF 10V

C248

GND1

C252 0.1uF 10V

PWR_VCHPLL

12

C261 0.1uF 10V

21

4.7uF 6.3V R

12

C258

4.7uF 6.3V R

GND1

12

C262 0.1uF 10V

GND1

Description

VCH

8

Appr.

TITLE

DRAW. No.

FUJITSU
LTD.

VGA-2

Rickwood Main Board

C1CPxxxxxx-X1

9

SHEET

CAST

25 82

M9

CBT3345

GND1

2
3
4
5
6
7
8
9

1

19

CBT3345PW

3

A1
A2
A3
A4
A5
A6
A7
A8

OE

OE#

SMB_CLK_ICH4,17,23,50
SMB_DATA_ICH4,17,23,50
MPCI_REQ#250

PCIC_REQ#129
CRT_HSYNC12
CRT_VSYNC12
CRT_DDC1_CLK12

ICHPWROK16,17,40

1

2

VCC

GND

18

B1

17

B2

16

B3

15

B4

14

B5

13

B6

12

B7

11

B8

20

10

PWR_5VSUS

C263

0.1uF 16V

2 1

GND1

4

SMB_CLK_PMU
SMB_DATA_PMU
PCI_REQ#2 16,19
PCI_REQ#1 16,19
CRT_Q_HSYNC 53,57
CRT_Q_VSYNC 53,57
CRT_Q_DDCCLK 53,57
CRT_Q_DDCDAT 53,57CRT_DDC1_DATA12

5

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

CheckDesign

7

Yoshida Aoki

1

2

3

4

5

※※S-OUT無しモデルが発生するならば、空きピン処理等の検討が必要!!

C1450はTVEncoderの近くに配置すること

Place C1450 near TVEncoder

振動子および周辺部品は、M165-42,43pin付近に配置，配線すること。 また、パターン下にバス等の高速な信号は走らせないこと。 すべてのクロックは、内層を走らせること(GND層の隣がベスト) 。

Place oscillator near M165-42,43 pins. Don't
route high speed bus under oscillator. All
clock lines should be routed in internal layer,
layer under GND is best.

PCI_RST#11,16,19,20,24,27,37,40

AGP_MCHREF13,14,24

1

CLK_TVO144

21

GND1

GND1

C264
1000pF 25V

Reserve
S-OUT

TVE_VREF

21

C268

0.1uF 16V

S-OUT

2

DVOA_DATA[0:11]12,13

DVOA_CLKIN[0:1]12

DVOA_HSYNC12
DVOA_VSYNC12

R142

1 2

27.4 1/16W 1%

S-OUT

GND1

PWR_3VMAINPWR_1.5VMAIN

12

S-OUT

12

C269 0.1uF 10V

S-OUT

DVOA_DATA0
DVOA_DATA1
DVOA_DATA2
DVOA_DATA3
DVOA_DATA4
DVOA_DATA5
DVOA_DATA6
DVOA_DATA7
DVOA_DATA8
DVOA_DATA9
DVOA_DATA10
DVOA_DATA11

DVOA_CLKIN0
DVOA_CLKIN1

R143

2 1

110 1/16W 1%

S-OUT

PWR_TVEPLL

21

C270 0.1uF 10V

S-OUT

3

TVE_ISET

PWR_TVEPLL2

2 1

C271 0.1uF 10V

S-OUT

GND1

M10

42

X1/14M_FIN

43

XO

13

RESET#

63

DVO_D0

62

DVO_D1

61

DVO_D2

60

DVO_D3

59

DVO_D4

58

DVO_D5

55

DVO_D6

54

DVO_D7

53

DVO_D8

52

DVO_D9

51

DVO_D10

50

DVO_D11

57

DVO_CLKINP

56

DVO_CLKINM

4

DVO_HSYNC

5

DVO_VSYNC

2

DE

3

VREF

35

ISET

18

PLLVDD

44

PLLVDD

33

DACVDD

1

VDD

12

VDD

49

VDD

45

VDDV

23

NC

29

NC

CH7011A

S-OUT

C272 0.1uF 10V

※本ライブラリには22pin(NC)が無いので注意

SCLK
SDAT

SAS

GPIO0
GPIO1

P-OUT

BCO

CVBS

CVBS/B

C/H SYNC

SWING

PLLGND
PLLGND
PLLGND

DACGND
DACGND

GND
GND
GND

15
14
10

8

TVE_GPIO0

7

TVE_GPIO1

46
47

36

38

C/R

37

Y/G

39

48

19

9

NC

21

NC

24

NC

25

NC

27

NC

28

NC

30

NC

31

NC

16
17
41

34
40

6
11
64

20

NC
NC
NC

GND1

26
32

GMBus Address : EAh ( 1,1,1,0, 1,SA#,SA,x )

4

VCH_GMBSCL_A 12
VCH_GMBSDA_A 12

DVOA_PCLK 12

2 1

75 1/16W 1% 1005

S-OUT

GND1

5

R141

3

GND1

2

D10

1SS302

1

6

7

8

TV_MODESEL

TVE_GPIO0

Pullup

PWR_3VMAIN

R507

2 1

10K 1/16W 5%

S-OUT

R508

2 1

PWR_3VMAIN

10K 1/16W 5%

S-OUT

Pullup presents internally

R139 10k 1/16W 5% Reserve

TVE_GPIO0

TVE_GPIO1

TV_S_C 46
TV_S_Y 46

PWR_3VMAIN

2

D11

PWR_3VMAIN

1SS302

3

1

GND1

FL12

1 2

BLM21A601SPB

S-OUT

R509

2 1

10 1/16W 1%

S-OUT

12

S-OUT

C265 0.1uF 10V

12

S-OUT

C720 0.1uF 10V

S-OUT

PWR_TVEPLL

12

C266 0.22uF 10V

GND1

PWR_TVEPLL2

12

C721 0.22uF 10V

GND1

21

R140 10k 1/16W 5% Reserve

12

S-OUT

このページの部品はTVEncoderの各電源ピンの近くに置くこと。

Place all components in this page near TVEncoder.

TITLE

DRAW. No.

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

FUJITSU
LTD.

9

NTSC

PALPulldown

GND1

TVEncoder
Crontel

Rickwood Main Board

C1CPxxxxxx-X1

9

SHEET

26 82

CAST

1

PCI_AD[0:31]16,29,42,50

2

M12A

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

16

PCI_CLK

22

PCI_AD31

24

PCI_AD30

25

PCI_AD29

26

PCI_AD28

28

PCI_AD27

29

PCI_AD26

31

PCI_AD25

32

PCI_AD24

37

PCI_AD23

38

PCI_AD22

40

PCI_AD21

41

PCI_AD20

42

PCI_AD19

43

PCI_AD18

45

PCI_AD17

46

PCI_AD16

61

PCI_AD15

63

PCI_AD14

65

PCI_AD13

66

PCI_AD12

67

PCI_AD11

69

PCI_AD10

70

PCI_AD9

71

PCI_AD8

74

PCI_AD7

76

PCI_AD6

77

PCI_AD5

79

PCI_AD4

80

PCI_AD3

81

PCI_AD2

82

PCI_AD1

84

PCI_AD0

TSB43AB21

下記のコンデンサはTSB43AA21の
VDDPxピン近傍に配置

CLK_13944

3

C/D

PCI_FRAME#

PCI_DEVSEL#

PWR_3VSUS PWR_3VSUS PWR_3VSUS

12

C279 0.1uF 16V

C278 0.1uF 16V

C/D

C/D

GND1 GND1GND1

PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0

PCI_IRDY#

PCI_TRDY#

PCI_STOP#

PCI_PERR#
PCI_SERR#

PCI_PAR

PCI_PME#

PCI_IDSEL

PCI_GNT#
PCI_REQ#
PCI_INTA#

CLKRUN#

PCI_RST#

12

C280 0.1uF 16V

C/D

34
47
60
73

49
50
52
53
54

56
57
58

21
36

18
19
13

12

85

21

PCI_FRAME# 16,19,29,42,50
PCI_IRDY# 16,19,29,42,50
PCI_TRDY# 16,19,29,42,50
PCI_DEVSEL# 16,19,29,42,50
PCI_STOP# 16,19,29,42,50

PCI_PERR# 16,19,29,42,50
PCI_SERR# 16,19,29,42,50
PCI_PAR 16,29,42,50

R148 100 1/16W 5%

PCI_GNT#0 16
PCI_REQ#0 16,19
PCI_INT#4 16,19

PCI_CLKRUN# 16,19,29,37,42,50

PCI_RST# 11,16,19,20,24,26,37,40

4

PCI_C/BE#3 16,29,42,50
PCI_C/BE#2 16,29,42,50
PCI_C/BE#1 16,29,42,50
PCI_C/BE#0 16,29,42,50

PCI_AD28

21

C/D

下記のコンデンサはTSB43AA21の
AVDDxピン近傍に配置

C281 0.1uF 16V

C/D

12

C282 0.1uF 16V

C/D

2 1

1 2

C283 0.1uF 16V

C/D

21

C284 0.1uF 16V

C/D

5

下記のコンデンサはTSB43AA21の
DVDDxピン近傍に配置

1 2

C285 0.1uF 16V

C/D

12

C286 0.1uF 16V

C/D

1 2

C287 0.1uF 16V

C/D

6

GND1

C274 10pF 25V C/D

PME_1394# 39,41

C273

10pF 25V

2 1

R

C/D

12

X3

24.576MHz

1 2

C/D

PWR_3VSUS

PWR_3VSUS

12

L2

1.5uH(NLC322522T-1R5M)

C/D

C276

1 2

r 4.7uF 6.3V

GND1

R144

1 2

0 1005 C/D

C/D

C275 0.1uF 10V R

C/D

TPBIAS49

TPA+49
TPA-49
TPB+49
TPB-49

IEEE1394_PU33_1
IEEE1394_PU33_2

IEEE1394_PD_5

C277

1 2

0.1uF 16V

C/D

7

1 2

R146

1 2

6.34K 1/16W 0.5%

IEEE1394_PD_5
IEEE1394_PU33_1
IEEE1394_PU33_2
IEEE1394_PU33_3

IEEE1394_PD_1
IEEE1394_PD_2
IEEE1394_PD_4
IEEE1394_PD_3

118

119

116
115
114
113
112

106

87
86

96

30
93

20
35
48
62
78

15
27
39
51
59
72
88

100

107
108
120

M12B

6

XO

5

XI

3

FILTER0

4

FILTER1

R0

R1

TPBIAS0
TPA0+
TPA0­TPB0+
TPB0-

CPS

CYCLEIN
CYCLEOUT

CNA

REG18A
REG18B

VDDP0
VDDP1
VDDP2
VDDP3
VDDP4

DVDD0
DVDD1
DVDD2
DVDD3
DVDD4
DVDD5
DVDD6
DVDD7

7

PLLVDD

1

AVDD0

2

AVDD1
AVDD2
AVDD3
AVDD4

TSB43AB21

C/D

RM26

1
2
3
4

4.7Kx4 1/32W 5%

C/D

RM27

1
2
3
4

220x4 1/32W 5%

C/D

G_RST#

NC(TPBIAS1)

NC(TPA1+)

NC(TPA1-)

NC(TPB1+)

NC(TPB1-)

REG_EN#

PLLGND

SMT8

SMT8

8

TEST17
TEST16

TEST9
TEST8

TEST3
TEST2
TEST1
TEST0

GPIO3
GPIO2

DGND0
DGND1
DGND2
DGND3
DGND4
DGND5
DGND6
DGND7
DGND8
DGND9

AGND0
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6

8
7
6
5

8
7
6
5

PC0
PC1
PC2

SDA
SCL

10
11

94
95

101
102
104
105

14

125
124
123
122
121

99
98
97

92
91

89
90

9

17
23
33
44
55
64
68
75
83
103

8

109
110
111
117
126
127
128

GND1

PWR_3VSUS

IEEE1394_PU33_3

GND1

R145

1 2

0 1005
R147

1 2

r 0 1005 R

49

TPBIAS_PR

49

TPA_PR+

49

TPA_PR-

49

TPB_PR+

49

TPB_PR-

GND1

IEEE1394_PD_1
IEEE1394_PD_2

IEEE1394_PD_3
IEEE1394_PD_4

GND1

9

C/D

3VSUSOK 29,40,45

PCI_RST# 11,16,19,20,24,26,37,40

IEEE1394

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

28 82

1

2

3

4

PWR_3VSUS

5

6

7

8

9

M13A

CLK_711334

CLK_32K_SUS31,50

VGARST#40,41

PCI_FRAME#16,19,27,42,50
PCI_IRDY#16,19,27,42,50
PCI_GNT#116

PCI_AD26

3VSUSOK27,40,45

1 2

100 1/16W 5%

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

R152

PCI_AD[0:31]16,27,42,50

PCI_C/BE#[0:3]16,27,42,50

PCI_AD[0:31]16,27,42,50

E3

K14

D1

N18

P7
U5
R6

W4

T1
R3
R2

P6
N5

P3

P1
N6
N3
N1
N2
M5

K2

K1

J6
J3
J2

J1
H1
H2
G2
G3
H6
G5

F1
F3
E2
E1

R1
M3

K3

G1

H5

K6
L1
F5

PCLK

SCLK/A_VCC_5#

PRST#

G_RST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C/BE#0
C/BE#1
C/BE#2
C/BE#3

IDSEL
FRAME#
IRDY#
GNT#

SDATA/B_VCC_3#

SLATCH/B_VCC_5#

IRQ3/A_VCC_3#
IREQ9/A_VPP_VCC_PGM
IOQ10/B_VPP_VCC_PGM

IRQ7/B_VPP_PGM/A_ZV_SEL#

INTB#/IRQ4/A_VPP_PGM

IRQ5/SERIRQ#

LEDO#/SKTA_ACTV

IRQ11/SKTB_ACTV

IRQ12/PME#

IRQ15/RI_OUT#

SPKROUT#

INTA#

DEVSEL#

TRDY#

PERR#
SERR#
STOP#

REQ#

LOCK#

CLKRUN#

AUX_VCC

PCI_VCC
PCI_VCC
PCI_VCC
PCI_VCC

CORE_VCC
CORE_VCC
CORE_VCC

PAR

K15
K17
W12
P19
F19
E6

K19

B5
F6
C5
J19
E8

L3
L2
M2
L6
M1
L5
G6
V5
A4
B14
V9

L15

F2
J5
M6
P5

R10
J18
B10

R150

1 2

R151

1 2

10k 1/16W 5%

GND1

10k 1/16W 5%

SDATA 31
SLATCH 31

SPKPCM 39

PCI_INT#0 16,19
PCI_INT#1 16,19
SERIRQ 16,19,37
PCICLED0 40
PCICLED1 40

PCI_DEVSEL# 16,19,27,42,50
PCI_TRDY# 16,19,27,42,50
PCI_PAR 16,27,42,50
PCI_PERR# 16,19,27,42,50
PCI_SERR# 16,19,27,42,50
PCI_STOP# 16,19,27,42,50
PCIC_REQ#1 25
PCI_LOCK# 16,19
PCI_CLKRUN# 16,19,27,37,42,50
PME_711# 39,41

PCM_RI# 39,41

PWR_3VSUS

2 1

0.1uF 16V

C292

0.1uF 16V

21

C295

1 2

C294

1 2

C293

0.1uF 16V

0.1uF 16V

GND1

0.1uF 16V

RM28

JCE1A#30,32
JCE2A#30,32
JCE2B#30,55
JCE1B#30,55

4
3
2
1

10kx4 1/32W 5%

ARRAY

5
6
7
8

PCIC-1[O2Micro-Tarzan]

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

PWR_CARD1

PWR_CARD0

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

30 82

H3

GND

B15

NC1

E5

NC2

OZ711E1_CSP

1

2

3

GND
GND
GND
GND
GND
GND

K5
P2
W5
V15
K18
E11

12

C291

2 1

C289

2 1

C288

0.1uF 16V

4

1 2

0.1uF 16V

C290

0.1uF 16V

5

1

2

3

4

5

6

7

8

9

JDA[0:15]32

JDA0
JDA1JDA1
JDA2JDA2JDA2
JDA3JDA3JDA3JDA3
JDA4JDA4JDA4JDA4JDA4
JDA5JDA5JDA5JDA5JDA5JDA5
JDA6JDA6JDA6JDA6JDA6JDA6JDA6
JDA7JDA7JDA7JDA7JDA7JDA7JDA7JDA7
JDA8JDA8JDA8JDA8JDA8JDA8JDA8JDA8JDA8
JDA9JDA9JDA9JDA9JDA9JDA9JDA9JDA9JDA9JDA9
JDA10JDA10JDA10JDA10JDA10JDA10JDA10JDA10JDA10JDA10JDA10
JDA11JDA11JDA11JDA11JDA11JDA11JDA11JDA11JDA11JDA11JDA11JDA11
JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12JDA12
JDA13
JDA14
JDA15

JBVD1A32
JBVD2A32

JCD1A#32

JCD2A#32

JINPACKA#32

JBSYA#32,40

JWAITA#32

JWPA32

JVS1A#32
JVS2A#32

M13B

M17

A_AD27/A_D0

M18

A_AD29/A_D1

L19

A_RSVD/A_D2/SC_RVD4

U6

A_AD0/A_D3

P8

A_AD1/A_D4

U7

A_AD3/A_D5

W7

A_AD5/A_D6

U8

A_AD7/A_D7

M15

A_AD28/A_D8

M19

A_AD30/A_D9

L18

A_AD31/A_D10

W6

A_AD2/A_D11

V7

A_AD4/A_D12

R8

A_AD6/A_D13

V8

A_RSVD/A_D14/SC_RVD8

W9

A_AD8/A_D15

N19

A_STSCHG/A_BVD1

M14

A_AUDIO/A_BVD2/SC_DET

V6

A_CD1#/A_CD1#

L14

A_CD2#/A_CD2#

P17

A_REQ#/A_INPACK#

P12

A_INT#/A_READY/SC_IO

R18

A_SERR#/A_WAIT#

L17

A_CLKRUN#/A_WP

W10

A_CVS1/A_VS1#

W16

A_CVS2/A_VS2#

A_AD26/A_A0
A_AD25/A_A1
A_AD24/A_A2
A_AD23/A_A3
A_AD22/A_A4
A_AD21/A_A5
A_AD20/A_A6
A_AD18/A_A7

A_C/BE1#/A_A8

A_AD14/A_A9
A_AD9/A_A10

A_AD12/A_A11

A_C/BE2#/A_A12

A_PAR/A_A13

SEL_CLK/A_PERR#/A_A14

A_IRDY#/A_A15

A_CLK/A_A16

A_AD16/A_A17

SC_CLK/A_RSVD/A_A18

EXTCLK/A_BLOCK#/A_A19

A_STOP#/A_A20

A_DEVSEL#/A_A21

A_TRDY#/A_A22

A_FRAME#/A_A23

A_AD17/A_A24
A_AD19/A_A25

A_C/BE0#/A_CE1#

A_AD10/A_CE2#

A_AD13/A_IORD#

A_AD15/A_IOWR#

A_AD11/A_OE#

A_C/BE3#/A_REG#

SC_RST/A_RST#/A_RESET

A_GNT#/A_WE#

VCCA
VCCA

N17
P18
R19
N14
R17
T19
R14
P14
V11
W11
U9
V10
V14
R11
V12
P13
V13
U11
P11
U12
W13
U13
W14
U14
W15
U15

W8
R9

U10
P10
P9
N15
P15
R12

R13
R7

JAA0
JAA1
JAA2
JAA3
JAA4
JAA5
JAA6
JAA7
JAA8
JAA9
JAA10
JAA11
JAA12
JAA13
JAA14
JAA15

JAA17
JAA18
JAA19
JAA20
JAA21
JAA22
JAA23
JAA24
JAA25

2 1

C296

0.1uF 16V

JAA[0:25] 32

GNDガード GNDガード

JAA16

R153

12

22 1/16W 5%

本抵抗はICに近接して実装すること。 本抵抗はICに近接して実装すること。

JCE1A# 29,32
JCE2A# 29,32

JIORDA# 32
JIOWRA# 32
JOEA# 32
JREGA# 32
JRSTA 32
JWEA# 32

PWR_CARD0 PWR_CARD1

C297

0.1uF 16V

2 1

JDB[0:15]55

JDB0
JDB1
JDB2
JDB3
JDB4
JDB5
JDB6
JDB7
JDB8
JDB9
JDB10
JDB11
JDB12
JDB13
JDB14
JDB15

JBVD1B55
JBVD2B55

JCD1B#55
JCD2B#55

JINPACKB#55

JBSYB#40,55

JWAITB#55

JWPB55

JVS1B#55

JVS2B#55

M13C

A7

B_AD27/B_D0

B7

B_AD29/B_D1

F7

B_RSVD/B_D2/SC_RVD4

J17

B_AD0/B_D3

J14

B_AD1/B_D4

H18

B_AD3/B_D5

H14

B_AD5/B_D6

G18

B_AD7/B_D7

C7

B_AD28/B_D8

A6

B_AD30/B_D9

B6

B_AD31/B_D10

H19

B_AD2/B_D11

H17

B_AD4/B_D12

H15

B_AD6/B_D13

G17

B_RSVD/B_D14/SC_RVD8

F17

B_AD8/B_D15

F8

B_STSCHG/B_BVD1

C8

B_AUDIO/B_BVD2/SC_DET

J15

B_CD1#/B_CD1#

C6

B_CD2#/B_CD2#

C9

B_REQ#/B_INPACK#

F12

B_INT#/B_READY/SC_IO

A9

B_SERR#/B_WAIT#

A5

B_CLKRUN#/B_WP

E18

B_CVS1/B_VS1#

A10

B_CVS2/B_VS2#

B_AD26/B_A0
B_AD25/B_A1
B_AD24/B_A2
B_AD23/B_A3
B_AD22/B_A4
B_AD21/B_A5
B_AD20/B_A6
B_AD18/B_A7

B_C/BE1#/B_A8

B_AD14/B_A9
B_AD9/B_A10

B_AD12/B_A11

B_C/BE2#/B_A12

B_PAR/B_A13

SEL_CLK/B_PERR#/B_A14

B_IRDY#/B_A15

B_CLK/B_A16

B_AD16/B_A17

SC_CLK/B_RSVD/B_A18

EXTCLK/B_BLOCK#/B_A19

B_STOP#/B_A20

B_DEVSEL#/B_A21

B_TRDY#/B_A22

B_FRAME#/B_A23

B_AD17/B_A24
B_AD19/B_A25

B_C/BE0#/B_CE1#

B_AD10/B_CE2#

B_AD13/B_IORD#

B_AD15/B_IOWR#

B_AD11/B_OE#

B_C/BE3#/B_REG#

SC_RST/B_RST#/B_RESET

B_GNT#/B_WE#

VCCB
VCCB
VCCB

JAB[0:25] 55

B8

JAB0

A8

JAB1

E9

JAB2

B9

JAB3

F10

JAB4

E10

JAB5

F11

JAB6

B11

JAB7

A16

JAB8

F15

JAB9

F18

JAB10

F14

JAB11

A12

JAB12
JAB13
JAB14
JAB15

JAB17
JAB18
JAB19
JAB20
JAB21
JAB22
JAB23
JAB24
JAB25

21

0.1uF 16V

C298

JAB16JAB16

R154

22 1/16W 5%

JCE1B# 29,55
JCE2B# 29,55

JIORDB# 55
JIOWRB# 55
JOEB# 55
JREGB# 55
JRSTB 55
JWEB# 55

12

0.1uF 16V

C299

12

12

C15
A15
C12
E12
E14
C14
A14
C13
B13
A13
B12
A11
C11

G14
E19

E17
D19
G15
F9
C10
E13

G19
F13
E7

C300

0.1uF 16V

OZ711E1_CSP

【注意】
JAA16,JAB16はCardBus時クロック信号になるのでGND1にてガードを行うこと。

JWPA32

JWPB55

1

2

R155 43k 1/16W 5%

R156 43k 1/16W 5%

PWR_CARD0

21

PWR_CARD1

12

3

GND1

4

5

OZ711E1_CSP

PCIC-2[O2Micro-Tarzan]

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

GND1

TITLE

Rickwood Main Board

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

31 82

1

2

3

4

5

6

7

8

9

PWR_3VSUS

21

C303

0.1uF 16V

PWR_5VSUS

12

12

C302

C301

0.1uF 16V

1uF 10V

GND1 GND1

21

C304

1uF 10V

GND1GND1

SDATA29

CLK_32K_SUS29,50

SLATCH29

3VSUSOK40

M14

18

VPPIN

19

VPPIN

1

VCC5IN

3

VCC5IN

10

VCC5IN

12

VCC5IN

14

VCC3IN

23

VCC3IN

5

SDA

6

SCL

8

SLA

7

RST#

MIC2564A-1BTS

AVCCOUT
AVCCOUT
AVCCOUT

BVCCOUT
BVCCOUT
BVCCOUT

AVPPOUT

BVPPOUT

AFLAG
BFLAG

GND
GND

PWR_CARD0

2
22
24

PWR_CARD1

11
13
15

PWR_CARDP0

20

PWR_CARDP1

17

4
9

16
21

GND1

PCIC POW

TITLE

Rickwood Main Board

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

32 82

1

2

3

4

5

6

7

8

9

CN17-1

PCMCIA CN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

PWR_CARDP0

21

GND1

PWR_CARD0

0.1uF 16V

C305

1 2

JDA3

JDA4

JDA5

JDA6

JDA7

JDA0

JDA1

JDA2

0.1uF 16V

C306

21

JAA10

JAA11

JAA9

JAA8

JAA13

JAA14

JAA16

JAA15

JAA12

JAA7

JAA6

JAA5

JAA4

JAA3

JAA2

JAA1

JAA0

C307 2.2uF 16V

JDA[0:15] 30

JAA[0:25] 30

JCE1A# 29,30

JOEA# 30

JWEA# 30

JBSYA# 30,40

JWPA 30

CN17-2

PCMCIA CN

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

FG1

FG2

PWR_CARDP0

GND1

PWR_CARD0

JDA11

JDA12

JDA13

JDA14

JDA15

JDA10

JDA8

JDA9

JAA17

JAA18

JAA19

JAA20

JAA21

JAA22

JAA23

JAA24

JAA25

JDA[0:15] 30

JCD1A# 30

JAA[0:25] 30

JCE2A# 29,30

JVS1A# 30

JIORDA# 30

JIOWRA# 30

JVS2A# 30

JRSTA 30

JWAITA# 30

JINPACKA# 30

JREGA# 30

JBVD2A 30

JBVD1A 30

JCD2A# 30

TITLE

Rickwood Main Board

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

33 82

1

本項中★印のついたパターンは、AUDIOGNDでガードし、その上下はAUDIOGNDのベタパターンで覆うこと。

2

全項AUDIOAREA

X4

1 2

24.576MHz

Reserve

21

C309

5pF 25V

Reserve

GND1

CLK_ICH1434,39

GSPKOUT34,39

注)CDL,CDRは、基板端面より、CDGND,CDL,CDGND,CDR,
CDGND順にｶﾞｰﾄﾞして布線し、その上下層はGNDAUDにて
CDL,CDR,CDGNDをｶﾊﾞｰする幅にて布線必ず実施のこと。

R170

CDL55

CDGND55

CDR55

LINEIN_L54

LINEIN_R54

MODEM50

MIC_CODEC_IN35

1 2

4.7K 1/16W 5%

*

1 2

4.7K 1/16W 5%

*

1 2

4.7K 1/16W 5%

*

100 1/16W 5%

1 2

R171

R172

R180

R476

0 1005

21

R176

27K 1/16W 5%

R181

2 1

R

R177

GND_AUD

C342

GND_AUD

AC97CODEC

1

21

C310

GND1

21

21

R179

1 2

27K 1/16W 5%

27K 1/16W 5%

GND_AUD

r 10K 1/16W 5%

C328

2 1

1 2

C343

2 1

1000pF 25V

2

R160

0 1005

0 1005

1000pF 25V

1000pF 25V

*

C344

12

*

2 1

1000pF 25V

12

R158
1M 1/16W 5%

Reserve

C313 4.7uF 10V

2 1

C314 4.7uF 10V

12

C315 4.7uF 10V

12

C316 4.7uF 10V

12

C318

12

4.7uF 10V

C319

21

0.1uF 16V

C345

2 1

1000pF 25V

3

AC_RST#17,50

17,50

R166

2 1

10K 1/16W 5%

Reserve

*
**

GND1

3

*

FL14
0 1005

<FILTER>

AC97_SYNC

AC97_SDOUT17,18,50

R167

2 1

Reserve

1K 1/16W 5%

1 2

C320 100pF 25V

GND_AUD

12

12

GND_AUD

21

C321 100pF 25V

C312

0.1uF 16V

21

C322 100pF 25V

C335

1 2

GND_AUD

FL13
BLM10B750B

Reserve

<FILTER>

12

C323 100pF 25V

C336

1uF 10V

CM3

6
7
8

0.1uFx4 16V

4

R157

0 1005

12

12

C324 100pF 25V

1 2

0.1uF 16V

45
3
2
1

4

21

C308

GND1

21

C325 100pF 25V

FL15

2

12

C337

TERM1
TERM2
TERM3
TERM4

5

21

R

r 0.1uF 16V

*
*
*
*
*

TERM1

TERM2

TERM3

TERM4

12

12

C326 100pF 25V

<FILTER>

BLM11A121S

PWR_AUD

C327 100pF 25V

112

12

C338

0.1uF 16V
1000pF 25V

GND_AUD

本項中★印のついたパターンは、GNDAUDでガードし、
その上下はGNDAUDのベタパターンで覆うこと。

11

02

03

10

05

43

44

34

33

12

18

19

20

23

24

14

15

16

17

13

21

22

25
38

26
42

M15

RESET#

XTL_IN

XTL_OUT

SYNC

SDATA_OUT

GPIO0

GPIO1

NC1

NC2

PC_BEEP

CD_L

CD_GND

CD_R

LINEIN_L

LINEIN_R

AUX_L

AUX_R

VIDEO_L

VIDEO_R

PHONE

MIC1

MIC2

AVDD1
AVDD2

AVSS1
AVSS2

STAC9767T

5

BIT_CLK

SDATA_IN

SPDIF

EAPD

LINEOUT_L

LINEOUT_R

MONOOUT

HP_OUT_L

HP_COMM

HP_OUT_R

VREFOUT

VREF

AFILT1

AFILT2

CAP2

DVDD1
DVDD2

DVSS1
DVSS2

PWR_3VMAIN

NC3

ID0

ID1

6

R506

10K 1/16W 5%

Reserve

1 2

R161

33 1/16W 5%

1 2

06

08

48

2 1

GND1

47

35

36

37

39

40

41

28

27

29

30

31

32

45

46

01
09

04
07

6

R162

1 2

33 1/16W 5%

R164
0 1005

12

SPDIFO 54

R474

1K 1/16W 5%

R168

12

0 1005

R

GND1

EAPD 40

*
* *

R178

* *
*

2 1

0 1005

Reserve

*
*

*

C339

21

C340

0.1uF 16V

FL16

<FILTER>

112

BLM11A121S

21

0.1uF 16V

PWR_3VMAIN

2

10uF 10V

C341

1 2

GND1

Rev.

DATE Design

2001.01.16 Komahara

7

AC97_BITCLK

AC97_SDIN0 17

R

C311

2 1

R165

r 0.1uF 16V

1 2

r 10K 1/16W 5%

OUT_L 34

*

OUT_R 34

21

21

Reserve

R173

1M 1/16W 5%

Reserve

R174

1M 1/16W 5%

8

AC97_SYNC17,50

PWR_AUD

Reserve

R169

2 1

27K 1/16W 5%

R175

27K 1/16W 5%

1 2

21

R159

GND1

21

10K 1/16W 5%

C317

0.1uF 16V

9

VREFO 35

GND_AUD

GND_AUD

C329

21

C330

1 2

0.1uF 16V

1uF 6.3V

C331

21

1000pF 25V

C332

21

21

C333

1000pF 25V

C334

1 2

0.1uF 16V

1uF 6.3V

GND_AUD

TITLE

Laurel

DRAW. No.

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

34 82

1

OUT_L33

OUT_R33

GSPKOUT33,39

VOLUME_5V40

PWR_3VMAIN

Q63
DTC143TEA

1

SP_HP#54

EAPD40

40

EAPD_EN#

2

G=24.1dB

fc=3.38Hz(10K,4.7u)

R184

10k 1/16W 5%

R191

2 3

6

1

3

4

4
3
2
1

Q60A
UM6K1N

Q60B
UM6K1N

12

R185

10k 1/16W 5%

RM29

10kx4 1/32W 5%

*
*

2 1

10k 1/16W 5%

MUTE40

2

5

12

SMT8

5
6
7
8

*
*

C364

0.1uF 16V

PWR_AUD

C348

2 1

1uF 10V

12

C349

2 1

1uF 10V

2 1

C360 1uF 10V

R190 39k 1/16W 5%

3

12

R492 39k 1/16W 5%

2 1

*
*

C350

0.1uF 16V12C351

0.1uF 16V

C352

2 1

12

C710

2 1

0.1uF 16VReserved

4

C711

0.1uF 16VReserved

2 1

*
*

C361

0.1uF 16VReserved

5

R182

2 1

27k 1/16W 5%

R183

12

27k 1/16W 5%

M16

1

SP_IN_L

12

SP_IN_R

5

HP_IN_L

8

HP_IN_R

7

BEEP_IN

11

SUSPEND#

10

MUTE#

4

BASS

3

ST/MONO#

2

SP/HP#

9

DCVOL

6

RBEEP

BH7884

12

1uF 10V

RIGHTOUTP

RIGHTOUTM

RIGHT BASS

HP_OUT_L

HP_OUT_R

LEFTOUTP

LEFTOUTM

LEFT BASS

VDD1
VDD2

GND1
GND2

24

13

20

21

17

16

22

15

14
23

18
19

AMP_HP_OUT_L

AMP_HP_OUT_R

*
*
*
*

ALG_BASS_L

ALG_BASS_R

6

SPKOUTL-

SPKOUTR-

C355

+

150uF 10V(TAN)

PWR_AUDPWR_AUD

12

C356

C357

1 2

0.01uF 16V R

GND_AUD

C354

+

150uF 10V(TAN)

0.1uF 16V

7

R479

2 1

27k 1/16W 5%

4700pF 25V
R480

1 2

27k 1/16W 5%

C346

1 2

4700pF 25V

C347

ALG_BASS_L

12

ALG_BASS_R

R495 100 1/16W 5%

2 1

100 1/16W 5%

R496

2 1

C708

2 1

0.1uF 16V

GND_AUD

8

12

R188 1k 1/16W 5%12R189 1k 1/16W 5%

GND_AUD

SPKOUTL+ 54

SPKOUTL- 54

SPKOUTR+ 54

SPKOUTR- 54

C709

2 1

0.1uF 16V

9

HPOUTL 54

HPOUTR 54

G=-8.8dB

GND1

GND_AUD

本IC下部は、GNDAUDベタとすること。

印はAnalog

*

Lineのため、0.25mm以上の幅で配線し、
極力GNDAUDでガード(上下層を含む)すること。

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

Audio AMP

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

SHEET

9

CAST

35 82

1

PWR_MIC

2 1

INTMIC_IN57

※ ※

fc=72.3Hz(22K,0.1uF)

INTMIC_RTN57

パターン接続指定（エディタ）

R194

2.2k 1/16W 5%

C366

2 1

0.1uF 16V

PWR_AUD

R196

1 2

2

R473

0 1005

Resrve

27k 1/16W 5%

R195

1 2

22k 1/16W 5%

VREFO_2

21

※

3

fc=7.23KHz(22K,1000pF)

C365

12

1000pF 25V

R193

2 1

22k 1/16W 5%

PWR_AUD

M17A

84

TS972IPT(DOCK)

2

-

3

+

GND_AUD

1

G=0dB

※

※

VREFO_2

4

※

INTMIC_OUT 54

5

6

7

8

9

C367

2 1

27k 1/16W 5%

0.1uF 16V

本抵抗分割はM19の近くに配置すること。

C368 100pF 25V

1 2

fc=15.9KHz(100K,100pF)

C370

1 2

MICIN54

※ ※

0.47uF 10V R

R199

2 1

10k 1/16W 5%

VREFO33

※

※

TS972IPT(DOCK)

R198

1 2

100k 1/16W 5%

PWR_AUD

M17B

84

6

-

5

+

C369

7

1 2

0.1uF 16V

fc(min)=72.3Hz(10K,0.22uF)

C371

2 1

* *

0.22uF 25V

MIC_CODEC_IN 33

R197

2 1

GND_AUD

印はAnalog

*

Lineのため、0.25mm以上の幅で配線し、
極力GNDAUDでガード(上下層を含む)すること。

fc=72.3Hz(10K,0.22uF)

※印は微小なAnalog
Lineのため、0.25mm以上の幅で配線し、
GNDAUDでガード(上下層を含む)すること。

1

2

3

4

G=20dB

5

GND_AUD

MIC AMP

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

36 82

FDCHG#

FRDDT#53
FWP#53
FINDEX#53
FTRK0#53

FDSELO#53

ISA_IOR#38

ISA_IOW#38

S_IRQ138

S_IRQ1238

FDIR#53
FSIDE#53
FMOTOR#53
FSTEP#53

FWG#53

FWD#53

DTR2#

KOKO_IO_A

PWR_3VSUS

GND1

1

枠内ｸﾞﾙｰﾌﾟｽﾜｯﾌﾟ可

RTS2#

1

RM31

ARRAY

8
7
6
5

1kx4 1/32W 5%

RM33

7
8
5
6

1Kx4 1/32W 5%

RM35

4
3
2
1

1Kx4 1/32W 5%

RM37

ARRAY

8
7
6
5

1kx4 1/32W 5%

R472 1K 1/16W 5%

RM38

8
7
6
5

SMT8

10kx4 1/32W 5%

Floating check

GPIO15,16,17,20,24,12,23

IR_TX

CM5

45
3

6

2

7

1

8

0.1uFx4 25V

SERB_RI39

SMT8

SMT8

21

1
2
3
4

CTSA53

SINA#53
DCDA53

DSRA53

SERB_RI

1
2
3
4

2
1
4
3

5
6
7
8

1
2
3
4

SUSB#4,16,40,42,45,60,61,62,69,76

RIA53

2

PWR_3VMAIN

PWR_5VMAIN

PWR_5VMAIN

PWR_3VMAIN

GND1

SERB_RTS1#
SERB_DTR1#
SERB_SOUT1

2

PWR_5VMAIN

21

D7
RB521S-30

22
23

14
13
12

4
5
6
7
8

28
24

21
20

1
2

27

3

3

枠内ｸﾞﾙｰﾌﾟｽﾜｯﾌﾟ可

RM32

4
3
2
1

ARRAY

10Kx4 1/32W 5%

RM34

5
6
7
8

10Kx4 1/32W 5%

RM36

4
3
2
1

ARRAY

10Kx4 1/32W 5%

12

R200 10K 1/16W 5%

RM39

4
3
2
1

ARRAY

4.7Kx4 1/32W 5%

M19

[RS-232]

FORCEOFF#
FORCEON

DIN1
DIN2
DIN3

RIN1
RIN2
RIN3
RIN4
RIN5

C1+
C1-

INVALID#
ROUT2B

C2+
C2-

V+

V-

MAX3243

3

ARRAY

DOUT1
DOUT2
DOUT3

ROUT1
ROUT2
ROUT3
ROUT4
ROUT5

VCC

GND

5
6
7
8

4
3
2
1

5
6
7
8

5
6
7
8

9
10
11

19
18
17
16
15

26

C375

25

PRD6
PRD4
PRD1
PRD0

PRD7
PRD5
PRD3
PRD2

PPE 53
PBUSY 53
PACK# 53
PPERR# 53

PSLCT 53

PSLIN# 53
PINIT# 53
PAFD# 53
PSTB# 53

RTSA 53
DTRA 53
SOUTA# 53

SERB_CTS1#
SERB_RIRS232A#

SERB_DCD1#
SERB_DSR1#

PWR_3VSUS

12

12

0.1uF 16V
C376

GND1

4

SERB_SIN1 17

Reserve

1000pF 25V

4

PRD[0:7] 53

PWR_3VMAIN

SERB_SIN117

CLK_SIO144

LPC_FRAME#16,19,20,39
LPC_DRQ#016,19
PCI_RST#11,16,19,20,24,26,27,40
SUSTAT#16,40
PCI_CLKRUN#16,19,27,29,42,50
CLK_SIO334
SERIRQ16,19,29

PACK#53
PPERR#53
PSLCT53
PPE53
PBUSY53

S_IRQ138
S_IRQ1238

FRDDT#53
FTRK0#53
FINDEX#53
FDCHG#53
FWP#53

IR_MODE45

PWR_3VMAIN

C372 0.1uF 16V

2 1

GND1

5

C373 0.1uF 16V

2 1

5

SERB_CTS1#
SERB_DSR1#
SERB_DCD1#
SERB_RIRS232A#

C374 0.1uF 16V

1 2

M18

19

CLOCKI

24

LFRAME#

25

LDREQ#

26

PCIRST#

27

LPCPD#

28

CLKRUN#

29

PCICLK

30

SERIRQ

17

IOPME#

80

ACK#

81

ERROR#

77

SLCT

78

PE

79

BUSY

64

GPIO23/FDC_PP

52

GPIO14/IRQIN2

51

GPIO13/IRQIN1

50

GPIO12/IO_SMI#

95

RXD2

99

CTS2#

97

DSR2#

94

DCD2#

92

RI2#

84

RXD1

88

CTS1#

86

DSR1#

91

DCD1#

90

RI1#

16

RDATA#

14

TRK0#

13

INDEX#

4

DSKCHG#

15

WRTPRT#

63

IRMODE/IRRX3

18

VTR

93

VCC

65

VCC

53

VCC

76

VSS

60

VSS

31

VSS

7

VSS

KOKO@smsc

6

6

LAD0
LAD1
LAD2
LAD3

STROBE#
AUTOFD#

SLCTIN#

INIT#

GPIO15/PME/SMI
GPIO16/PME/SMI
GPIO17/PME/SMI

GPIO20/PME
GPIO21/PME
GPIO22/PME

GPIO24/PME/SMI

GPIO30/SD0
GPIO31/SD1
GPIO32/SD2
GPIO33/SD3
GPIO34/SD4
GPIO35/SD5
GPIO36/SD6
GPIO37/SD7
GPIO40/CS0
GPIO41/CS1
GPIO42/CS2

GPIO43/RD

GPIO44/WT
GPIO45/SA0
GPIO46/SA1
GPIO47/SA2
GPIO10/SA3

TXD1
RTS1#
DTR1#

TXD2
RTS2#
DTR2#

HDSEL#

WGATE#

WDATA#

STEP#

DIR#

DS0#
MTR0#

DRVDEN1
DRVDEN0

IRTX2
IRRX2

GPIO11/SYSOPT

20
21
22
23

68

PD0

69

PD1

70

PD2

71

PD3

72

PD4

73

PD5

74

PD6

75

PD7

83
82
67
66

54
55
56
57
58
59

6

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

85
87
89

96
98
100

12
11
10
9
8
5
3
2
1

62
61

49

Rev.

DATE Design

2001.01.16 Komahara

IR_TX

7

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

PRD0
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7

RTS2#
DTR2#

7

8

LPC_AD[0:3] 16,20,39

PRD[0:7] 53

PSTB# 53
PAFD# 53
PSLIN# 53
PINIT# 53

ISA_D0 38
ISA_D1 38
ISA_D2 38
ISA_D3 38
ISA_D4 38
ISA_D5 38
ISA_D6 38
ISA_D7 38
KBCCS# 38
MCCS# 38

ISA_IOR# 38
ISA_IOW# 38

ISA_A2 38

SERB_SOUT1
SERB_RTS1#
SERB_DTR1#

FSIDE# 53
FWG# 53
FWD# 53
FSTEP# 53
FDIR# 53
FDSELO# 39,53
FMOTOR# 53

IR_TX 45
IR_RXA# 45

KOKO_IO_A

LPC SuperI/O[Smsc-KOKO]

Appr.

CheckDesign

Yoshida Aoki

1:IndexBaseI/Oaddress
04Eh
0:IndexBaseI/Oaddress
02Eh

Description

Appr.

8

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

9

SHEET

CAST

38 82

1

HL1

HL2

GND1

2

ATFINT#15

KSHIPID047
KSHIPID147

CLK_KBC439

PWR_5VMAIN

876

5

123

4

3

RM42

100kx4 1/32W 5%

SMT8

4

2001.01.31
C458.1をCLKKBC4‑>RSTDRV#に変更

21

PWR_5VMAIN

12

C378

0.1uF 16V

GND1

GND1

PCI_RST#
ISA_IOR#37
ISA_IOW#37

KBCCS#37
ISA_A237

21

C379

1uF 10V

KBC_P40

GND1

C377

Reserve

1000pF 25V

5

M20

28

XIN

29

XOUT

25

RST-

15

RD#

14

WR#

16

S0

17

A0

27

P40

26

P41

13

P54

12

P55

11

P56

10

P57

1

P60

80

P61

79

P62

78

P63

77

P64

76

P65

75

P66

74

P67

24

CNVSS

72

VREF

73

AVSS

71

VCC

30

VSS

M38867

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

70
69
68
67
66
65
64
63

54

P00

53

P01

52

P02

51

P03

50

P04

49

P05

48

P06

47

P07

46

P10

45

P11

44

P12

43

P13

42

P14

41

P15

40

P16

39

P17

38

P20

37

P21

36

P22

35

P23

34

P24

33

P25

32

P26

31

P27

62

P30

61

P31

60

P32

59

P33

58

P34

57

P35

56

P36

55

P37

23

P42

22

P43

21

P44

20

P45

19

P46

18

P47

9

P70

8

P71

7

P72

6

P73

5

P74

4

P75

3

P76

2

P77

ROW#0
ROW#1
ROW#2
ROW#3
ROW#4
ROW#5
ROW#6
ROW#7

KSMBALT#

ISA_D0
ISA_D1
ISA_D2
ISA_D3
ISA_D4
ISA_D5
ISA_D6
ISA_D7

6

ISA_D[0:7] 37

CLM#0
CLM#1
CLM#2
CLM#3
CLM#4
CLM#5
CLM#6
CLM#7
CLM#8
CLM#9
CLM#10
CLM#11
CLM#12
CLM#13
CLM#14
CLM#15

HTKYSMI 39

CAPS 39
NUM 39
SCRL 39
ROW#[0:7] 47

S_IRQ1 37
S_IRQ12 37
KBINIT# 16
KBA20G 16
KBCSCI 16
MCCS# 37
PADDATA 47
PADCLK 47

MDATA 53
MCLOCK 53

KDATA 53
KCLOCK 53

SMBDATA 15,50,52
SMBCLK 15,50,52

7

CLM#[0:15] 47

MCLOCK53

PADDATA47

ATFINT#15

KSHIPID147
KSHIPID047

HTKYSMI39

8

RM43

8

KCLOCK53
PADCLK47

KDATA53

MDATA53

KSMBALT#

KBC_P40

7
6
5

SMT8

10kx4 1/32W 5%

RM44

SMT8

5
6
7
8

10kx4 1/32W 5%

RM45

8
7
6
5

SMT8

100kx4 1/32W 5%

1
2
3
4

4
3
2
1

1
2
3
4

PWR_5VMAIN

GND1

9

SHEET

9

KBC

CAST

39 82

TITLE

Rickwood Main Board

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

1

CLK_ASIC334
CLK_ASIC484

CLK_PMU32K16,71

本クロックはノイズに弱いため

※

上下層に高速な信号が走らないように
配線すること

Mount

Reserve

※

JP FPC/FSC

R298

R299,R300

R299,R300

R298

2

21

C380

Reserve

220pF 50V

GND1

3

LPC_AD[0:3]16,20,37

LPC_FRAME#16,19,20,37

PMU_PARST#71
PMU_PE#71
PMU_PRM#71
PMU_SMI71

BAY1_LMP#41,55

HDDLED#41,56

SPKSYS17,18
SPKPCM29

PCI_RST#11,16,19,20,24,26,27,37 IDE_RST_HDD#

FDSELO#37,53

FDATCH#53

HPSENSE

PME_LAN#42
BLUE_RI41

PME_MINI#50

PME_1394#27,41

PME_711#29,41
PCM_RI#29,41

HTKYSMI38

PWR_3VSUS

12

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

34

SERB_RI#

4

PWR_PMU

5

PWR_5VMAIN PWR_5VMAIN

PWR_PMU

M21A

148
117

14

87
88
89
90
86

71
72
73
79

131
132
133

32
31

47
43
44
45
46

142
143
144

135
107

91

92
123
134

125
126
129
130

98

99
101
102
119
120
122

PCICLK
CLK48M
CLK32IN

LAD0
LAD1
LAD2
LAD3
LFRAME#

PARST#
PE#
PRM#
PMUSMII#

1

BAYLMP0#

2

BAYLMP1#

3

CDLMP#

4

HDLMP#

SPK1
SPK2
SPK3

HPIN
DKAMPEN#

FDSELI#
FDATCH1#
FDATCH2#
FDATCH3#
FDATCH4#

992MODE#
163MODE#
007MODE#

OZACTIN#
THRMACT#

WAKEA#
WAKEB#
WAKEC#
WAKED#

RI1#
RI2#
RI3#
RI4#

ESMIBE0
ESMIBE1
ESMIBE2
ESMIBE3
ESMIBE4
ESMIBE5
ESMIBE6

HOOP

CLK4M

GID0
GID1
GID2
GID3
GID4
GID5
GID6
GID7

CAPS#

NUM#

SCR#

SPKOUT

DKMUTE#

INTMUTE#

FDSELO#

FMODE#

RIOUT#

EXTSCI#

EXTSMI#

OZACTOUT

WAKEOUT#

VDD1(5V)
VDD1(5V)
VDD1(5V)
VDD1(5V)
VDD1(5V)

VDD2(3.3V)
VDD2(3.3V)
VDD2(3.3V)
VDD2(3.3V)

PD0
PD1
PD2
PD3

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

85

11
29
49
84
93
128
137
172

18
62
115
150

9
10
13

103

33
34

48
124

110

109
108

136

112

12
51
100
121
139

23
77
111
165

17
28
50
61
83
94
116
127
138
149
171

GND1

BAY2_ID1
BAY2_ID2

PMU_D0
PMU_D1
PMU_D2
PMU_D3

6

PMU_D[0:3]

7

※

21

D8
HRC0103A

PWR_PMUPWR_5VSUS

12

21

21

21

C381 0.1uF 16V

C382 0.1uF 16V

C383 0.1uF 16V

21

C384 0.1uF 16V

GND1

C385 0.1uF 16V

CLK_KBC4 38

BAY1_ID0 41,55
BAY1_ID1 41,55
BAY1_ID2 41,55
BAY1_ID3 55

PMU_D[0:3] 71

CAPS 38
NUM 38
SCRL 38

GSPKOUT 33,34

FMODE# 53

RIOUT# 16

EXTSCI# 16

EXTSMI# 16,19

SP_HP# 16,19
WAKEOUT# 16

8

9

43signals

R201 10k 1/16W 5%

SERB_RI#

32

Q9
2SK3019

SERB_RI37

1

2

1

GND1

3

GND1

HOOP-1

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

40 82

1

PLLB16,71

PMU_ACON33

MAINON#41,48,71

SUSSW#48

3VSUSOK27,29,45
POWERGOOD245
PCURDY#71
3VMAINOK45
SUSB#4,16,37,42,45,60,61,62,69,76

LCDEN24

GBLEN24
LCDCL#48

PCICLED029
PCICLED129
JBSYA#30,32
JBSYB#30,55

PCI_RST#11,16,19,20,24,26,27,37

ｸﾗｲｼｽﾌﾞｰﾄ用TP
CN19右ﾊｯﾁﾝｸﾞｼﾙｸｴﾘｱに実装

LAN_RST#42
LAN_ISORATE#4,16,37,40,45,60,61,62,69,76

BLUE_DETACH57

2

TP98 CRY1

PWR_5VMAIN

TP99 CRY2

RSMRST#16,45

BLUE_ON57
BLUE_RST#57

SUSTAT#16,37

PWR_PMU

3

PWR_CARD1

PWR_CARD0

GND1

4

M21B

76

PLB#

78

PLLB#

15

ACON

16

BT1SWR

19

BT2SWR

59

MAINSW#

64

RSTSW#

66

SUSSW#

65

SUSOK

63

PMUVCCOK

60

PMURDY#

53

MAINOK

104

SUSB#

95

LCDEN

96

BLEN

70

LCDCL#

39

JAVCC

42

JBVCC

81

PCMLMP0

82

PCMLMP1

40

JBSYA#

41

JBSYB#

80

PCIRST#

22

GPSBSEL

5

GPIO0/BT1CHG(D)

6

GPIO1/BT1PWR(D)

7

GPIO2/BT2CHG(D)

8

GPIO3/BT2PWR(D)

173

GPIO4

174

GPIO5(D)

175

GPIO6

176

GPIO7

152

RSMRST#

168

G3STDIO0

169

G3STDIO1

170

G3STDIO2

151

G3STDIO3

118

G3STDIO4

114

G3STDIO5

57

SUSTAT#

113

TEST#

HOOP

BT1SWO
BT2SWO

PMURST#

PWRGOOD

PWRON
PWROK

BAY1ON
BAY2ON

EBLENO

ACTOUT#

EXACT0#

EXACT1#

VGARST#

VGASTBY#

G3PIO0/BT1ALM(D)
G3PIO1/BT2ALM(D)

G3PIO2/SPSEL(D)

G3PIO3/BT1CID(D)

G3PIO4/BT1ON(D)

G3PIO5/BT2CID(D)

G3PIO6/BT2ON(D)

G3PIO7/VSNA(D)

G3PIO8(D)
G3PIO9(D)

G3PIO10/BAY1ATCH1#
G3PIO11/BAY1ATCH2#
G3PIO12/BAY2ATCH1#
G3PIO13/BAY2ATCH2#

G3PIO14

G3PIO15
G3PIO16(D)
G3PIO17(D)
G3PIO18(D)
G3PIO19(D)
G3PIO20(D)

SRBTN3#

G3STDIO6

BLCDCL#

SUSSW2#

SUSTAT

OZ163EN

VOLUME

BLO

5

20
21

67
52
68
69

105
106

97

140

58

37
38

75
74

24
25
26

IR_EXIST

27
30

SOUT_EXIST

54
55
56

153
154

155
156
157

BAY2_CD2#

158
159
160
161
162
163
164
166

146
147

35
36
167
141

145

GND1

6

IDE_RST_BAY3V

PMU_PCURST# 71

POWERON 45,62
ICHPWROK 16,17,25

BAY1_ON 41,70
BAY2_ON 55

EBLEN 57

BKLVOL 57

PCICACT# 17

MPCIACT# 41,50

VGARST# 29,41

FR_EXIST# 41,52
BLUE_EXIST# 41,57
SECURITY# 48

EAPD_EN#20
FWHWP# 20
FWHTBL# 20

PHS_ON 55,56

BAY1_CD1# 41,55
BAY1_CD2# 41,55
PR_CD1# 41,55

FANFAULT# 41,55
MUTE 34
SUBBATON 76
MPCIRST# 50
SMB_CNCT0 50
SMB_CNCT1 23
CID0E# 50

BSRBTN# 16

BLID 16

VOLUME_5V 34

7

3VSUSOK27,29,45
POWERGOOD245
PCURDY#71
3VMAINOK45

PWR_3VMAIN

8

12

12

12

12

C389 1000pF 25V

C387 1000pF 25V

C388 1000pF 25V

GND1

C386 1000pF 25V

Reserve

Reserve

Reserve

ESD対策用

Reserve

本コンデンサはHOOP(M29)のピンのすぐそばに配置すること

PWR_3VMAIN

SOUT_EXIST

IR_EXIST

PWR_3VMAIN

1

IDE_RST_BAY3V

2 1

R202 0 1005

2 1

R203 0 1005

Q64

DTC143TEA

2 3

IDE_RST_BAY# 55,56

9

HOOP-2

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

41 82

1

2

3

4

5

6

7

8

9

BLUE_EXIST#40,57
FR_EXIST#40,52
FANFAULT#15

BAY1_CD1#40,55
BAY1_CD2#40,55
HDDLED#39,56

BAY1_LMP#39,55

PR_CD1#40,55

FDATCH#39,55

BAY1_ID039,55
BAY1_ID139,55
BAY1_ID239,55
BAY1_ID339,55

ピンスワップ可

PME_711#29,39

PCM_RI#29,39
VGARST#29,40
PME_1394#27,39

12

21

SMT8

PWR_3VMAIN

4
3
2
1

PME_LAN#39
BLUE_RI39

4
3
2
1

GBLEN

MPCIACT#40,50

40,52

RM47

8
7
6
5

SMT8

10kx4 1/32W 5%

PWR_3VSTD

1
2
3
4

GND1

PWR_3VMAIN

PWR_PMU

R204 100k 1/16W 5%

PWR_3VMAIN

MAINON#40,48,71

SUSSW#48

LCDCL#48

1
2
3
4

BAY1_CD1#40,55

BAY1_CD2#40,55

PWR_3VSUS

5
6
7
8

PR_CD1#40,55

1 2

R499 10k 1/16W 5%

2 1

R500 100k 1/16W 5%

1 2

C713

12

1uF 6.3V

C714

12

1uF 6.3V

C715

12

1uF 6.3V

GND1

RM46

SMT8

5
6
7

BAY1_ON40,70

8

10kx4 1/32W 5%

RM48

5
6
7
8

SMT8

10kx4 1/32W 5%

R483 10K 1/16W 5%

R471 10K 1/16W 5%

RM50

8
7
6
5

SMT8

10kx4 1/32W 5%

RM49

4
3
2
1

10kx4 1/32W 5%

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

42 82

1

2

M49A

3

4

5

X7

FCX03MD (25.000MHz)

1 2

6

M49B

7

8

9

CLK_LAN334

LAN_RST#40

LAN_ISORATE#

PCI_AD[0:31]16,27,29,50

PCI_C/BE#016,27,29,50
PCI_C/BE#116,27,29,50
PCI_C/BE#216,27,29,50
PCI_C/BE#316,27,29,50

PCI_FRAME#
PCI_IRDY#
PCI_GNT#316

1

PCI_AD[0:31]

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

LAN_IDSEL

2

116

PCLK

115

PRST#

95

ISOLATE#

45

AD0

44

AD1

43

AD2

42

AD3

41

AD4

39

AD5

38

AD6

37

AD7

34

AD8

33

AD9

32

AD10

31

AD11

29

AD12

28

AD13

27

AD14

26

AD15

13

AD16

11

AD17

10

AD18

9

AD19

8

AD20

6

AD21

5

AD22

4

AD23

128

AD24

127

AD25

126

AD26

125

AD27

123

AD28

122

AD29

121

AD30

120

AD31

36

C/BE#0

24

C/BE#1

14

C/BE#2

2

C/BE#3

3

IDSEL

15

FRAME#

16

IRDY#

117

GNT#

RTL8139CL(LQFP)

LWAKE/CSTSCHG

PME#

INTA#

CLKRUN#

DEVSEL#

TRDY#

PERR#
SERR#

STOP#

REQ#

EEDO/MA0

EEDI/MA1

EESK/MA2

9356SEL/MA6

MA10
MA11
MA12
MA13
MA14
MA15
MA16

EECS

ROMCS#

PCI_AD[0:31]16,27,29,50

CID0E#16

3

PAR

MA3
MA4
MA5

MA7
MA8
MA9

OE#

WE#

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

4

5

3

5

1 2

12

C661

22pF 25V 5%

PWR_3VSTD

12

C662

GND1

C707

0.1uF 16V 20%

Reserve

PWR_5VSUS

12

GND1

R451
0 (1005)

RXIN+43

RXIN-43

0.1uF 16V 20%

LAN_IDSEL

21

1 2

GND1

1M 1/16W 5%

R450

2 1

1.69K 1/16W 1%

R452

GND1

21

C724 0.1uF 16V 20%

R493

100K 1/16W 5%

Reserve

79

X1

78

X2

87

RXIN+

86

RXIN-

82

RTT2

81

RTT3

84

RTEST

54

N.C

71

N.C

72

N.C

73

N.C

94

1 2

6

N.C

RTL8139CL(LQFP)

Rev.

DATE Design

2001.01.16 Komahara

7

92

TXD+

91

TXD-

99

LED0

98

LED1

97

LED2

PWR_3VSTD

1

VDD

12

VDD

25

VDD

35

VDD

46

VDD

58

VDD

59

VDD

77

VDD

90

VDD

96

VDD

106

VDD

109

VDD

119

VDD

7

GND

18

GND

30

GND

40

GND

55

GND

56

GND

62

GND

74

GND

80

GND

85

GND

93

GND

111

GND

112

GND

113

GND

124

GND

GND1

Appr.

CheckDesign

Yoshida Aoki

12

C663 0.1uF 16V 20%

GND1

Description

TXD+ 43

TXD- 43

21

C664 0.1uF 16V 20%12C665 0.1uF 16V 20%

Appr.

8

FL40

<FILTER>

221

BLM18PG300SN1

(BLM11P300S)

FL41

<FILTER>

112

BLM18PG300SN1

(BLM11P300S)

FL42

<FILTER>

221

BLM18PG300SN1

(BLM11P300S)

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

PWR_3VSTD

1

2

1

LAN

9

SHEET

CAST

43 82

83

76

114
75
19
17
23
21
22
20
118

47
48
49
51
52
53
57
60
61
63
64
65
66
67
68
69
70

50
110
88
89

108
107
105
104
103
102
101
100

PME_LAN# 39

PCI_INT#5 16,19
PCI_CLKRUN# 16,19,27,29,37,50
PCI_DEVSEL# 16,19,27,29,50
PCI_TRDY# 16,19,27,29,50
PCI_PAR 16,27,29,50
PCI_PERR# 16,19,27,29,50
PCI_SERR# 16,19,27,29,50
PCI_STOP# 16,19,27,29,50
PCI_REQ#3 16,19

M50

3

CS

4

SK

5

DI

1

NC1

8

NC2

RTL_MA8

10K 1/16W 5%

If use D3 cold,Shoud be pulled high.

R454
10 1/16W 5%

2 1

PCI_AD25

Reserve

Reserve

4

12

C660

22pF 25V 5%

GND1 GND1

Serial
EEPROM

BR93LC46FV-W

2

Vcc

6

DO

7

Vss

R453

PWR_3VSTD

C666 0.1uF 16V 20%12C667 0.1uF 16V 20%12C668 0.1uF 16V 20%21C669 0.1uF 16V 20%12C670 0.1uF 16V 20%12C671 0.1uF 16V 20%

GND1

PWR_3VSTD

21

NOTE
pin55‑pin58,pin109‑pin112間はﾊﾟｽｺﾝを直近に
搭載すること。

R501
10 1/16W 5%

2 1

M53

2

A

B

1

OE#

VCC

GND

CBT1G125

Reserve

1

PWR_3VSTD

2

3

4

5

6

7

8

9

15pF 25V 5%

21

Reserve

2 1

49.9 1/16W 5%

C672

R455

RXIN+42

RXIN-42

TXD+42

TXD-42

Reserve

2 1

49.9 1/16W 5%

C673

R456

15pF 25V 5%

12

このブロックは、M49付近に搭載のこと。

1 2

1 2

49.9 1/16W 5%

49.9 1/16W 5%

R458

R457

12

このブロックは、M51付近に搭載のこと。

0.1uF 16V 20%

C676

GND1

PWR_3VSTD

12

0.1uF 16V 20%

C674

GND1

GND1

21

21

R494

0 1005

M51

6

RD+

7

RD-

5

CT1

4

N.C1

3

CT2

1

TD+

2

TD-

TLA-6T207A

TDK製

0.1uF 16V 20%

C675

N.C2

RX+

9

8

RX-

10

CT3

11

12

CT4

14

TX+

13

TX-

LAN_PR_RX+ 53

LAN_PR_RX- 53

LAN_PR_TX+ 53

LAN_PR_TX- 53

Laurel

C1CPxxxxxx-X1

FUJITSU
LTD.

USB CN

SHEET

44 82

9

CAST

TITLE

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

1

※本ページのReset
ICは各電源の発生源の近傍に配置願います。

2

3

4

5

6

7

8

9

PWR_PMU

C719

1 2

0.1uF 16V 20%

GND1

PWR_PMU

12

C396

2200pF 25V

Reserve

GND1

PWR_3VSUS

12

C399

2200pF 25V

Reserve

PWR_3VSUS PWR_3VMAIN

GND1

1 2

12

C397

0.033uF 16V

C400

0.01uF 16V

M54

4

V+

1

2

2

5

3

OS#

HYST

VTEMP

GND

LM26CIM5X-ZHA (120degC)

M23

2

VDD

5

CD

OUT

3

GND

S-80927AL

M24

VDD

1

CD

OUT

GND

S-80927AL

PWR_3VSTD

5

3

R502

1

1K 1/16W 5%

12

C401

2200pF 25V

Reserve

GND1

21

21

C398

2200pF 25V

Reserve

GND1

POWERGOOD2 40

PWR_3VMAIN

3VSUSOK 27,29,40

12

GND1

R207

0 1608

C392

2200pF 25V

Reserve

POWERON40,62

12

21

TP19
PWR_3VIR

GND1

C393

0.01uF 16V

12

C404

4.7uF 6.3V B

PWR_3VMAIN

GND1

21

C402

4.7uF 10V F

M22

2

VDD

5

CD

3

GND

S-80927AL

R206

1 2

2.7 1/2W 5%

OUT

1

C403

1 2

0.1uF 16V 20%

12

C405

0.47uF 10V F

R205 1.5k 1/16W 5%

21

C395

2200pF 25V

Reserve

GND1

1SS400

M25

10

LEDA

6

NC

7

GND

1

VCC

2

AGND

QSDL-M137#00

D9

2 1

21

TXD

RXD

FIR_SEL

MD0

MD1

FG

9

8

3

4

5

FG1

12

GND1

RSMRST# 16,40

C394

2200pF 25V

Reserve

GND1

R459

1 2

IR_TX 37

IR_RXA# 37

IR_MODE 37

10k 1/16W 5%

SUSB#

GND1

M26

8

VCC

7

SENSE

2

RESIN#

3

C409

4

10uF 10V

CT

GND

TLC7725

1 2

0.1uF 16V

C407

0.1uF 16V

GND1

1 2

C406

12

RESET#

RESET

REF

5

6

1

21

GND1

C408

2200pF 25V

Reserve

R208

1 2

1K 1/16W 5%

40

3VMAINOK 40

VGATE 16

3VMAINOK#

遅延ターゲット
S-8094x:

Example(0.1uF):
Td(ms)=5.7xCd(nF)
=5.7x100=570(ms)=0.57(s)

RESET IC/SW

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

46 82

1

2

3

4

5

6

7

8

9

C412

1 2

12

S-OUT

L3

2 1

NLC322522T-1R5M

S-OUT

S-OUT

C410 82pF 25V

L4

2 1

NLC322522T-1R5M

S-OUT

82pF 25V

2 1

2 1

S-OUT

C411 82pF 25V

S-OUT

C413 82pF 25V

TP20
TVOC

TP21
TVOY

CN26

1
3
4
2

S-OUT JACK

※045/25

部品変更CN26

TV_S_Y26

21

R209

75 1/16W 1%

S-OUT

GND1

TV_S_C26

12

R210

S-OUT

75 1/16W 1%

GND1 GND1

本コネクタはVGAchipの近傍に配置すること。

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

47 82

1

2

THYME KeyBoard Connector

CN8

INT_KBD

ROW#0
ROW#1

ROW#2
ROW#3A
ROW#3B

ROW#4

ROW#5

ROW#6

ROW#7

CLM#0
CLM#1
CLM#2
CLM#3
CLM#4
CLM#5
CLM#6
CLM#7
CLM#8

CLM#9
CLM#10
CLM#11
CLM#12
CLM#13
CLM#14
CLM#15

ID-C

28
17
16
13
9
11
10
8
7

27
26
25
24
23
22
21
20
19
18
15
14
12
6
5
4

3
2

ID0

1

ID1

KeyboardStrap(N86C‑7664‑0203‑E)
ID1:ID0(KBCSide)

GND1

JP00
US01
UK10

ROW#0
ROW#1
ROW#2
ROW#3

ROW#4
ROW#5
ROW#6
ROW#7

CLM#0
CLM#1
CLM#2
CLM#3
CLM#4
CLM#5
CLM#6
CLM#7
CLM#8
CLM#9
CLM#10
CLM#11
CLM#12
CLM#13
CLM#14
CLM#15

3

4

5

6

7

8

9

※最優先に配線願います。

PWR_LCD

LVDSBxx,LVDSxxの設計条件
(ST/SWCNまで両信号の合計で)
‑各線長の誤差は2mm以下にする
‑LVDSC+,‑とLVDS0+,‑とLVDS1+,‑
とLVDS2+,‑の間はGNDでｶﾞｰﾄﾞする
‑各線のｲﾝﾋﾟｰﾀﾞﾝｽを100Ωにする
‑ビヤ打ちは最小限(３回以下)にする

C415

C416

C414

r 10pF 25V

R

GND1

2 1

r 10pF 25V

R

2 1

r 10pF 25V

R

2 1

r 10pF 25V

R

C417

2 1

C418

r 10pF 25V

R

2 1

C419

r 10pF 25V

R

2 1

R

C420

2 1

r 10pF 25V

C421

r 10pF 25V

R

LVDS_L0- 24

LVDS_L0+ 24

LVDS_L1- 24

LVDS_L1+ 24

LVDS_L2- 24

LVDS_L2+ 24

LVDS_LC- 24

LVDS_LC+ 24

2 1

ROW#[0:7] 38

CLM#[0:15] 38

KSHIPID1 38
KSHIPID0 38

CN25

LCD CN

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

GND1

C422

1 2

C423

2 1

100pF 25V

C424

1 2

1000pF 25V

0.1uF 16V

CN5

POINTING CN

1

TP22

TP23

TP

12

r 47pF 25V

GND1

r 47pF 25V

C426

R

Reserve

TP

PADDATA 38
PADCLK 38

3

4

5

6

PWR_5VMAIN

FL17 BLM11A121S

<FILTER>

1

1

2

2

3

3

4

4

5

5

6

6

1 2

12

C427

0.1uF 16V

12

C425

R

2

上記のコンデンサはLCD
CNの近傍に設置すること

Rev.

DATE Design

2001.01.16 Komahara

Appr.

CheckDesign

7

Yoshida Aoki

Pullup for IDE

Description

Appr.

8

TITLE

DRAW. No.

FUJITSU
LTD.

Laurel

C1CPxxxxxx-X1

SHEET

9

CAST

48 82

1

Mode SW

2

3

LOCATION

A B WWW Mail

SWA# SWB# SWC# SWD# SW_ENTER#

LED

Enter

4

Sus/Res

SUSSW#

5

6

PMU_APPLED

R470

100K 1/16W 5%

2 1

7

PWR_3VMAIN

R211

330 1/16W 5%

2 1

6

2

1

AUD_LEDOUT

Q10A
UM6K1N

AUD_LEDIN

PWR_3VMAIN

R213

100K 1/16W 5%

2 1

8

APP_LEDOUT

3

Q10B
UM6K1N

5

4

9

※055/31

SECURITY#40

ピンアサイン変更
TP追加TP86〜TP89

TP28

TP TP32

PMU_LEDIN

TP33

TP34

TP

TP

1

TP35

TP

Q12
DTC144EEA

1

R215

1 2

1K 1/16W 5%

R216

1 2

1K 1/16W 5%

Appr.

GND1

PWR_3VSTD

C428

TITLE

DRAW. No.

FUJITSU
LTD.

GND1

GND1

R214

330 1/16W 5%

1 2

PMU_LEDIN

PMU_LEDOUT

2 3

21

0.22uF 10V

12

C429

0.22uF 10V

HDD CN

Laurel

C1CPxxxxxx-X1

LCDCL# 40

MAINON# 40,41,71

SHEET

49 82

9

CAST

Rev.

DATE Design

2001.01.16 Komahara

GND1

PMU_LED71

SW2

1 3

2

LCD COVER CLOSE SW

GND1

TP42

TP

1:OFF
3:ON

GND1 GND1

C697

0.033uF 16V

7

SW1

1

3

MAIN SWITCH

D58

2 1

21

RB521S-30

Appr.

CheckDesign

Yoshida Aoki

2

Description

8

123

TP24

TP25

TP26

TP

TP

TP

TP27

CN7

112

334

556

778

9910

111112

131314

151516

171718

191920

212122

232324

252526

272728

292930

ST-ApliSW CN

2

TP

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

PMU_LEDOUT

GND1

3

TP29

TP31

TP

TP

TP

TP36TPTP37

TP
TP38

TP
TP40

TP
TP43

TP
TP45

TP
TP47

TP
TP49

このﾓｼﾞｭｰﾙ間でのﾋﾟﾝｽﾜｯﾌﾟ可

TP30

TP

TP

AUD_LEDOUTAUD_LEDIN

APP_LEDOUT

TP
TP39

TP
TP41

TP
TP44

TP
TP46

TP
TP48

TP
TP50

4

RM51

ARRAY

ARRAY

1
2
3
4

4
3
2
1

ARRAY

8
7
6
5

4
3
2
1

ARRAY

4
3
2
1

ARRAY

8
7
6
5

1Kx4 1/32W 5%

RM52

5
6
7
8

1Kx4 1/32W 5%

RM53

1
2
3
4

0x4 1/32W 5%

RM54

5
6
7
8

0x4 1/32W 5%

RM55

5
6
7
8

0x4 1/32W 5%

このﾓｼﾞｭｰﾙ間でのﾋﾟﾝｽﾜｯﾌﾟ可

45

678

SUSSW#

678

4 5

GND1

5

GND1

CM6

0.1uFx4 16V

CM7

0.1uFx4 16V

123

PMU_SLCDS5 71
PMU_SLCDS3 71
PMU_SLCDS1 71
PMU_SLCDC1 71

PMU_SLCDC0 71
PMU_SLCDC2 71
PMU_SLCDS0 71
PMU_SLCDS2 71

PMU_SLCDS4 71
PMU_SLCDS6 71
PMU_SLCDS7 71
PMU_SLCDS8 71

SWA# 71
SWC# 71
SW_ENTER# 71

SUSSW# 40
SWD# 71
SWB# 71
APPMODE# 71

SUSSW#

6

1

2

3

4

5

6

7

8

9

PWR_5VSUS

I/O CN

1

USB_OC#016

PS1

1 2

MINISMDC100(1A)

CN21

1394CN(4pin)

C/D

FL18 BLM11A121S

12

R218 330K 1/16W 5%

1 2

C437 0.1uF 16V

R220 330K 1/16W 5%

GND1

TP51

TP52

TP53

2

1 2

FILTER

FL20 BLM11A121S

1 2

FILTER

FL22

<FILTER>

2

112

BLM41P600S

1 2

12

2 1

C441 r 10pF 25V

C440 r 10pF 25V

R

GND1

PWR_5VSUS

CN9

1

VCC

2

-DATA

3

+DATA

1 2

C430 4.7uF 6.3V

1 2

C434 16pF 25V

GND1 GND1 GND1 GND1 GND1 GND1

1 2

DLW21SN181SQ2

C/D

1 2

DLW21SN181SQ2

C/D

12

12

R

C442 r 10pF 25V

C443 r 10pF 25V

R

R

3

4

GND

5

FG1

6

FG2

USB_CON_STD#0

本体横 本体後

2 1

C435 16pF 25V

L5

34

L6

34

4

MINISMDC100(1A)

USB_OC#116

C438

220pF 25V

1 2

C/D

USB_P0N16

USB_P0P16 USB_P1P16,53

TP54

1

TPB-

2

TPB+

3

TPA-

4

TPA+

PS2

2 1

GND1

USB_P1N16,53

PWR_5VUSB1

12

C439

1uF 10V

C/D

12

R217 330K 1/16W 5%

2 1

C436 0.1uF 16V

R219 330K 1/16W 5%

GND1

C/D

12

R221

56 1/16W 1%

5

FL19 BLM11A121S

2 1

FILTER

FL21 BLM11A121S

2 1

FILTER

FL23

<FILTER>

112

BLM41P600S

2 1

C/D

12

R222

56 1/16W 1%

21

R223

56 1/16W 1%

C/D

R225

1 2

5.1K 1/16W 5%

C/D

2

C4314.7uF 6.3V

21

1 2

GND1

12

2 1

C432 16pF 25V

TPBIAS 27

TPB- 27

TPB+ 27

TPA- 27

TPA+ 27

TPA+とTPA‑
は等長配線すること

R224

TPB+とTPB‑

56 1/16W 1%

は等長配線すること

C/D

C444

220pF 25V

C/D

6

CN10

1

VCC

2

-DATA

3

+DATA

4

GND

5

FG1

6

FG2

USB_CON_STD#1

1 2

16pF 25V

C433

1394CNと1394PHY
間の線長は
なるべく短くすること

Minimize

TPBIASx

1394CN

TPBx
TPAx

R

TSB43AA211

R

RC Network

上記の図のように、TPA+‑,
TPB+‑に直接つながる抵抗は、
なるべくTSB43AA21の近傍に置くこと

TITLE

Laurel

Rev.

DATE Design

2001.01.16 Komahara

DRAW. No.

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

50 82

1

2

3

4

5

6

7

8

9

下記コンデンサ(C329,C330,C350,C351,C742,C743,C744,C745)は
CN9のPWRMINIPCIを接続している各電源PINの
近くに１個づつ配置すること。

21

C447

C452

21

C448

0.1uF 16V

C453

0.1uF 16V

PCI_INT#316,19

CLK_MINI334

MPCI_REQ#225

PCI_AD3116,27,29,42
PCI_AD2916,27,29,42

PCI_AD2716,27,29,42
PCI_AD2516,27,29,42

PCI_C/BE#316,27,29,42
PCI_AD2316,27,29,42

PCI_AD2116,27,29,42
PCI_AD1916,27,29,42

PCI_AD1716,27,29,42
PCI_C/BE#216,27,29,42
PCI_IRDY#16,19,27,29,42

PCI_CLKRUN#16,19,27,29,37,42
PCI_SERR#16,19,27,29,42

PCI_PERR#16,19,27,29,42
PCI_C/BE#116,27,29,42
PCI_AD1416,27,29,42

PCI_AD1216,27,29,42
PCI_AD1016,27,29,42

PCI_AD816,27,29,42
PCI_AD716,27,29,42

PCI_AD516,27,29,42

PCI_AD316,27,29,42

PCI_AD116,27,29,42

AC97_SYNC17,33

AC97_BITCLK17

12

0.1uF 16V

12

0.1uF 16V

リアルテック対応

PWR_3VMAIN

21

R230

1k 1/16W 5%

REAL_3VMAIN

AC97_SDIN117

C445

GND1

12

0.1uF 16V

R231

0 1/16W

C446

C451

21

0.1uF 16V

21

0.1uF 16V

12

C454

12

PWR_3VSUS

0.1uF 16V

PWR_5VSUS

CN16

1

3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

101
103
105
107
109
111
113
115
117
119
121
123

2

1

2

4

3

4

6

5

6

8

7

8

10

9

10

12

11

12

14

13

14

16

15

16

18

17

18

20

19

20

VIO

22

21

22

24

23

24

26

25

26

28

27

28

30

29

30

32

31

32

34

33

34

36

35

36

38

37

38

40

39

40

42

41

42

44

43

44

46

45

46

48

47

48

50

49

50

52

51

52

54

53

54

56

55

56

58

57

58

60

59

60

62

61

62

64

63

64

66

65

66

68

67

68

70

69

70

72

71

72

74

73

74

76

75

76

78

77

78

80

79

80

82

81

82

84

83

84

86

85

86

88

87

88

90

89

90

92

91

92

94

93

94

96

95

96

98

97

98

100

99

100

102

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122
124

123

M66ENMINI

104
106
108
110
112
114
116
118
120
122
124

下記コンデンサ(C352,C353)はCN9‑18pin/97pinの
近くに均等に配置すること。

12

21

C450

C449

0.1uF 16V

GND1

PCI_INT#2 16,19

MPCIRST# 40

PCI_GNT#2 16

PCI_AD30 16,27,29,42

PCI_AD28 16,27,29,42
PCI_AD26 16,27,29,42
PCI_AD24 16,27,29,42

PCI_AD22 16,27,29,42
PCI_AD20 16,27,29,42
PCI_PAR 16,27,29,42
PCI_AD18 16,27,29,42
PCI_AD16 16,27,29,42

PCI_FRAME# 16,19,27,29,42
PCI_TRDY# 16,19,27,29,42
PCI_STOP# 16,19,27,29,42

PCI_DEVSEL# 16,19,27,29,42

PCI_AD15 16,27,29,42
PCI_AD13 16,27,29,42
PCI_AD11 16,27,29,42

PCI_AD9 16,27,29,42
PCI_C/BE#0 16,27,29,42

PCI_AD6 16,27,29,42
PCI_AD4 16,27,29,42
PCI_AD2 16,27,29,42
PCI_AD0 16,27,29,42
PHS_ON 57
PHS_LED# 57

AC97_SDOUT 17,18,33

AC_RST# 17,33

C456

**

0.1uF 16V

4.7uF 6.3V
C698

0.1uF 16V

PWR_5VMAIN

MODEM 33

1 2

21

12

MPCIIDSEL

D12

1SS400

R228

10k 1/16W 5%

PWR_3VSUS

PWR_3VSUS

21

CLK_32K_STD16

SMB_CLK_ICH4,17,23,25

SMB_DATA_ICH4,17,23,25

SMB_CNCT040

R229

10k 1/16W 5%

PME_MINI# 39

2001.01.31
NETCHANGE
CN9.110をAC97RESET#‑>ACRST#に変更

GND1

MPCIACT# 40,41

PCI_AD2916,27,29,42

PCI_REQ#216,19,25

MPCI_REQ#225

GND1

PWR_3VSUS

R226 100 1/16W 5%

2 1

M27

2

1A

5

2A

9

3A

12

4A

1

1OE#

4

2OE#

10

3OE#

13

4OE#

CBT3125PW,PI5C3125L,FST3125MTC

注）M16はminiPCIコネクタCN9の近くに配置すること。

印はAnalogLineのため、
極力GNDAUDでガード(上下層を含む)すること。

*

VCC

GND

1B

2B

3B

4B

MPCIIDSEL

3

6

8

11

14

7

PWR_5VSUS

21

C455

0.1uF 16V

GND1

CLK_32K_SUS 29,31

SMBCLK 15,38,52

SMBDATA 15,38,52

1 2

Reserve

C457 100pF 25V

GND1

C357はCN9‑107pinの近くに置くこと

1

2

3

miniPCI CN

GND1GND_AUD

21

C458

C459

1 2

1uF 10V

0.1uF 16V

GND1

C358,C359はCN9‑124pinの近くに置くこと

4

MiniPCI CN

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

51 82

1

2

3

4

5

6

7

8

9

CN19

PWR_PMU

PWR_3VMAIN1

PWR_3VMAIN2

USB_ON

PWR_5VMAIN

SUSTAT#

BUZZER

SMBCLK

SMBDATA

GND_USB1

USB+

USB-

GND_USB2

FR_EXIST#

STM_EXIST#

SPK_OFF

GND1

GND2

GND3

FP CN_1

A/B

TP55TPTP56

TP57

TP

TP

20

19

18

17

16

15

14

13

12

11

10

※

9

※

8

7

6

5

NC

4

3

2

1

TP

TP

TP58

TP TP59
TP60

PWR_3VMAIN PWR_5VMAIN

GND1

※
※

FR_USBON 16

SMBCLK 15,38,50

SMBDATA 15,38,50

USB_P4P 16

USB_P4N 16

FR_EXIST# 40,41

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

53 82

1

2

3

PWREXDCINDはPWREXDCINと同じ配線条件で引くこと。

PWR_EXDCIND

PWR_5VMAIN

4

FL24

<FILTER>

221

BLM41P600S

A/B

PWR_EXDCIN

1

※MAX3A

5

6

7

PWR_5VMAINPWR_5VMAIN PWR_5VUSB1

8

9

CN1A

PC1

DCIN1

1

GND1

2

SYSDET1

PRPATCH#2

3

GND3

4

N.C1

5

N.C3

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

6

7

8

9

FSIDE#

GND5

FRDDT#

GND7

FMODE#

FINDEX#

5VMAIN1

FTRK0#

GND9

FSTEP#

FMOTOR#

GND11

RIA

CTSA

RTSA

DSRA

GND13

GND15

PAFD#

PPERR#

FSIDE#37

FRDDT#37

FMODE#39

FINDEX#37

FTRK0#37

FSTEP#37

FMOTOR#37

RIA37

CTSA37

RTSA37

DSRA37

PAFD#37

PPERR#37

DCIN2

GND2

GND4

N.C2

N.C4

FDATCH#

GND6

FWD#

GND8

FDSELO#

FWP#

5VMAIN2

FWG#

GND10

FDIR#

FDCHG#

GND12

DTRA

SOUTA#

SINA#

DCDA

GND14

PSTB#

PRD0

PRD1

P-R_CN_TH

A/B

PC3

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

PWR_5VSUS

FDATCH# 39

FWD# 37

FDSELO# 37,39

FWP# 37

FWG# 37

FDIR# 37

FDCHG# 37

DTRA 37

SOUTA# 37

SINA# 37

DCDA 37

PSTB# 37

PRD0 37

PRD1 37

PINIT#37

PSLIN#37

PRD437

PRD637

PACK#37

PPE37

CRT_BLUE12,57

CRT_GREEN12,57

CRT_RED12,57

USB_P1N16,49

KDATA38

KCLOCK38

52

USB_P5N

USB_OC#549

LAN_PR_RX+43 LAN_PR_TX+ 43

TPB_PR+

49

TPB_PR-

49

PR_CD1#43

※MAX3A ※MAX3A

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

PC2

CN1B

PINIT#

PSLIN#

PRD4

PRD6

PACK#

PPE

VGAGND

VGAB

VGAG

VGAR

VGAGND

USBVCC0

USB0-

USBGND

KDATA

KCLOCK

5VMAIN

N.C

N.C

LANRXD-

LANRXD+

N.C

N.C

PRPATCH#1

GND1

DCIN1RTN

PRD2

PRD3

PRD5

PRD7

PBUSY

PSLCT

VGAGND

DDCCLK

DDCDATA

VGAVS

VGAHS

USBVCC0

USB0+

USBGND

MDATA

MCLK

5VMAIN

LANTXD-

LANTXD+

SYSDET#2

GND1

DCIN1RTN

P-R_CN_TH

A/B

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

N.C

94

N.C

95

96

97

N.C

98

N.C

99

100

PC4

PRD2 37

PRD3 37

PRD5 37

PRD7 37

PBUSY 37

PSLCT 37

CRT_Q_DDCCLK 25,57

CRT_Q_DDCDAT 25,57

CRT_Q_VSYNC 25,57

CRT_Q_HSYNC 25,57

USB_P1P 16,49

MDATA 38

MCLOCK 38

USB_P5P 52

49

TPA_PR+

49

TPA_PR-

LAN_PR_TX- 43LAN_PR_RX-43

C703

220pF 25V

2 1

C/D
Reserve

P-R CN

1

GND1

2 1

C704

1uF 10V

C/D
Reserve

12

C/D

R484

GND1 GND1 GND1 GND1

49

C/D

12

56 1/16W 1%

Reserve

R485

56 1/16W 1%

Reserve

21

C/D

R486

R488

2 1

C/D

2

21

C/D

R487

56 1/16W 1%

Reserve

C705

2 1

Reserve

5.1K 1/16W 5%

C/D

GND1

49
49
49
49

56 1/16W 1%

Reserve

220pF 25V

Reserve

TPBIAS_PR

TPA_PR+
TPA_PR­TPB_PR+
TPB_PR-

3

注）LAN信号線(LANTXD+,LANTXD‑,LANRXD+,LANRXD‑)は、
LANTXD+‑LANTXD‑,LANRXD+‑LANRXD‑をそれぞれ
  対で配線し、対の距離は、最低配線距離、TXD,RXD間はその
  ５倍の距離を離すこと。
  また、この４本を通している上下２層は配線領域から横方向に
  ３ｍｍを内層ｸﾘｱとする。
  上下３層目は、GND1にて、配線の上をGND1でガードすること。
  但し、ｶﾞｰﾄﾞも含め、本信号線のｽﾙﾎｰﾙおよび、配線から3mm
  以内は、絶縁距離として確保し、いかなる信号線も3mm以下の
  距離になってはならない。
  但し、例外条件として、上下３層目は本信号と完全に直行する
  場合のみ他の信号線の布線を許可する。（必要最低限に抑える
  こと）

注）PWREXDCIND(FL1‑P‑RCN間)は、ｺﾈｸﾀ引出し部
ｽﾙﾎｰﾙ各３個計６個で引き出し、3mm以上のﾊﾟﾀｰﾝ幅、
最短距離でFL1へ接続すること。
  PWREXDCINは3mm以上のﾊﾟﾀｰﾝ幅で布線することが要求
される。

4

5

Rev.

DATE Design

6

CN2

TX+

TX-

RX+

RX-

LAN-RJ

A/B

2001.01.16 Komahara

Appr.

7

1

2

3

4

Description

CheckDesign

Yoshida Aoki

8

Appr.

LAN_PR_TX+ 43

LAN_PR_TX- 43

LAN_PR_RX+ 43

LAN_PR_RX- 43

TITLE

DRAW. No.

FUJITSU
LTD.

Laurel

C1CPxxxxxx-X1

SHEET

9

CAST

54 82

1

2

3

4

5

6

7

8

9

全項AUDIOAREA

CN12A

Line-OPT_1

CN12B

7

VCC

6

Vin

8

GND

Line-OPT_1

CN14

HP JACK

1
3
4
2

本ページ中に記載されているフィルタ(FLxx)はそれぞれ接続
されているコネクタの近くに配置し、フィルターコネクタ間の配
線は非常に短く配線すること。
Thefiltersinthispage(referedwithFLxx)haveto
beplacedneareachconnectorconnectingtorespective
filters.Thetracesbetweenconnectorandfilterhave
tobeshortasmuchaspossible.

本項中※印のついたパターンは、AUDIOGNDでガードし、その上
下はAUDIOGNDのベタパターンで覆うこと。また、Mxの下の基板
面およびその下の層には、ディジタル系の信号線を配線しないこ
と。
Thetracesmarkedwith※havetobeguardedbothsideand
bothadjacentlayerwithAUDIOGND.UnderneathMxon
surfacelayerandinonemoreinternallayerdon'tallow
digitaltracestoberun.

1

C473

GND1

5

4

3

2

1

12

1800pF 25V

1800pF 25V

C467

2 1

C466

2 1

C468

1800pF 25V

上記のフィルタ、コンデンサ、抵抗は

1 2

GND_AUD

SPDIF

0.1uF 16V

LINEINJACKの近くに配置すること。

SPDIF

R232

0 1005

PWR_3VMAIN

12

SPDIFO 33

※

21

21

1 2

1000pF 25V

1000pF 25V

1000pF 25V

C476

GND_AUD

上記のフィルタ、コンデンサ、抵抗は
HPJACKの近くに配置すること。

C477

2

C478

FL26

<FILTER>

BLM11A102S
FL28

<FILTER>

1 2

BLM11A102S
FL30

<FILTER>

BLM11A102S

1 2

1 2

1 2

21

21

FL32

<FILTER>

BLM11A102S
FL33

<FILTER>

BLM11A102S
FL35

<FILTER>

BLM11A102S
FL37

<FILTER>

BLM11A102S

3

GND_AUD

21

GND_AUD

※

※

R234

12

0 1005

C474
r 0.1uF 16V

R

GND_AUD

※ ※

※025/11

4

LINEIN_R 33

LINEIN_L 33

PWR_AUD

R233
100K 1/16W 5%

1 2

HPSENSE 34

21

HPOUTR 34

※※※

HPOUTL 34

部品削除R91,R92

SPKOUTL+34

SPKOUTL-34

SPKOUTR+34

SPKOUTR-34

GND_AUD

C475

1uF 10V

CN15

MIC IN JACK

5

※096/13

TP追加

FL25

<FILTER>

1

※
※

※

※

INTMIC_OUT35

BLM11A121S
FL27

<FILTER>

1

BLM11A121S
FL29

<FILTER>

2

BLM11A121S
FL31

<FILTER>

1

BLM11A121S

221

221

112

221

GND1

TP61

TP

123

TP

678

45

TP62

TP64

TPTP63

TP

CM8

0.1uFx4 16V

1

2

3

4

CN13

SPL1

SPL2

SPR1

SPR2

SPK CN

12

1000pF 25V

C461

100pF 25V

12

C462

0.01uF 16V

GND1

C460

GND_AUD

GND_AUD

21

C469

1000pF 25V

上記のコンデンサは下記のように
ねじ止めスルーホール付近に並べて
配置すること。

C470

r 100pF 25V

R

C471

2 1

100pF 25V

GND1

12

12

C463

1000pF 25V

C472

2 1

2 1

1000pF 25V

GND1

PWR_MIC

21

R235

2 1

21

1000pF 25V

C479

1K 1/16W 5%

R236

1K 1/16W 5%

21

<FILTER>

FL38

GND_AUD

BLM11A102S

21

r 1000pF 25V

C480

R

6

1 2

r 1000pF 25V

C481

21

r 1000pF 25V

C482

R
R

GND_AUD

FL34 BLM11A102S

<FILTER>

2 1

FL36 BLM11A102S

<FILTER>

2 1

Reserve

Rev.

DATE Design

2001.01.16 Komahara

GND_AUD

Placement location of
audio connectors

※

Appr.

7

MICIN 35

Description

CheckDesign

Yoshida Aoki

CN13
HeadPhone

CN12
LINE IN/OPT

CN14
Mic

DOCK CN-1

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

Appr.

8

FUJITSU
LTD.

9

SHEET

CAST

55 82

12

5
4
3
6
2
1

PWR_CARDP1

1

PWR_CARD1

JWPB30

JDB230

JDB130

JDB030

JAB030

JAB130

JAB230

JAB330

JAB430

JAB530

JAB630

JAB730

JAB1230

JAB1530

JAB1630

JBSYB#30,40

JWEB#30

JAB1430

JAB1330

JAB830

JAB930

JAB1130

JOEB#30

JAB1030

JCE1B#29,30

JDB730

JDB630

JDB530

JDB430

JDB330

BAY1_ID239,41

BAY1_ID039,41

2

CN6A

80

GND1

79

PCMVCC1

78

PCMVCC2

77

JWPA

76

JDB2

75

JDB1

74

JDB0

73

JAB0

72

JAB1

71

JAB2

70

JAB3

69

JAB4

68

JAB5

67

GND3

66

JAB6

65

JAB7

64

JAB12

63

JAB15

62

JAB16

61

PCMVPP1

60

GND5

59

JBSYB#

58

JWEB#

57

JAB14

56

JAB13

55

JAB8

54

GND7

53

JAB9

52

JAB11

51

JOEB#

50

JAB10

49

JCE1B

48

JDB7

47

JDB6

46

JDB5

45

JDB4

44

JDB3

43

GND9

42

BAYID2

41

BAYID0

DOCK_INT_CN_R6

GND2

PCMVCC3

PCMVCC4

JCD2B#

JDB10

JDB9

JDB8

JBVD1B

JBVD2B

JREGB#

JINPACKB#

JWAITB#

JRTSB

GND4

JVS2B#

JAB25

JAB24

JAB23

JAB22

PCMVPP2

GND6

JAB21

JAB20

JAB19

JAB18

JAB17

GND8

JIOWRB#

JIORDB#

JVS1B#

JCE2B#

JDB15

JDB14

JDB13

JDB12

JDB11

JCD1B#

GND10

BAYID3

BAYID1

3

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

JCD2B# 30

JDB10 30

JDB9 30

JDB8 30

JBVD1B 30

JBVD2B 30

JREGB# 30

JINPACKB# 30

JWAITB# 30

JRSTB 30

JVS2B# 30

JAB25 30

JAB24 30

JAB23 30

JAB22 30

JAB21 30

JAB20 30

JAB19 30

JAB18 30

JAB17 30

JIOWRB# 30

JIORDB# 30

JVS1B# 30

JCE2B# 29,30

JDB15 30

JDB14 30

JDB13 30

JDB12 30

JDB11 30

JCD1B# 30

BAY1_ID3 39

BAY1_ID1 39,41

PMU_VSENSE273,75

PWR_BT2ROM

PMU_BT2TEMP068

PWR_CARDP1

IDE_SDIOR_BAY#56

4

USB_P2P16

PMU_BT2DAT068

BAY1_CD2#40,41

BAY1_LMP#39,41

IDE_SDCS#117

IDE_SDA017

IDE_SDA117

IRQ15_BAY16,56

IDE_SDIOW_BAY#56

IDE_SDD017,56

IDE_SDD117,56

IDE_SDD217,56

IDE_SDD317,56

IDE_SDD417,56

IDE_SDD517,56

IDE_SDD617,56

IDE_SDD717

IDE_RST_BAY#40,56

CDL33

CDGND33

BAY1_CD1#40,41

PWR_5VSUS

CN6B

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

5

USBP1+

USBVCC1

GND1

GND1

VSENSE

BATT2

BATT2

BATT2

BATT2

BATT2

BATTM2

CINT1

BT2DAT

BAYATCH

GND1

DASP#

5VBAY

5VBAY

BPDCS1#

BPDA0

BPDA1

IRQ14

SPDIOR#

SPDIOW#

GND1

BPDD0

BPDD1

BPDD2

BPDD3

BPDD4

BPDD5

BPDD6

BPDD7

RSTDRV#

GND1

CDL

CDRTN

BAYATCH

GND1

GND1

DOCK_INT_CN_R6

USBP1-

USBVCC1

GND1

GND1

SCONT2

BATT2

BATT2

BATT2

BATT2

BATT2

BT2IN

BT2CLK

GNDA

GND1

BPDCS3#

5VBAY

5VBAY

5VBAY

BPDA2

PDIAG

PDDACK#

PIORDY

GND1

BPDDREQ

BPDD15

BPDD14

BPDD13

BPDD12

BPDD11

BPDD10

BPDD9

BPDD8

GND1

CDRTN

GND1

GND1

GND1

CDR

6

F6

1 2

10A 60V

120

119

118

117

116

115

114

113

112

111

110

109

108

107

N.C

106

105

104

103

102

101

100

99

N.C

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

USB_P2N 16

PMU_SCONT2 75

PMU_BT2IN#0 68

PMU_BT2CLK0 68

BAY2_ON 40

IDE_SDCS#3 17

IDE_SDA2 17

IDE_SDDACK# 17

IDE_SDIORDY_BAY

IDE_SDDREQ 17,56

IDE_SDD15 17

IDE_SDD14 17

IDE_SDD13 17

IDE_SDD12 17

IDE_SDD11 17

IDE_SDD10 17

IDE_SDD9 17

IDE_SDD8 17

CDR 33

CDGND 33

TP65
PWR_BATT2

PWR_BATT2

A2

GNDA

PWR_BAYPWR_BAY

7

8

9

※025/12

接続変更CN6‑26pin

BayConnectorBoardBayUnit

Upper Side

Upper Side

81

160 80

1

CD-ROM
DRIVE

PC-Card Slot

1 2

49 50

1

34

A1B1

IDE/USB/BATTCARD/USB

Lower Side

A34B34

35

69

A1B1

Lower Side

A44B44

GND1GND1GND1GND1

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

56 82

1

IDE_PDIOR#17

IDE_PDIOW#17

IDE_PDIORDY17

※ICH2pinAB13直裏面に搭載

IDE_PDD[0:15]17

ピンスワップ可

※HDDCN側に搭載

IDE_SDIOR#17

IDE_SDIOW#17

IDE_SDIORDY17

※ICH2pinAB19直裏面に搭載

IDE_SDD[0:15]17,55

IDE_RST_BAY#40,55

HDD

1

12

1K 1/16W 5%

2K 1/16W 5%

1 2

2

R239 0 1/16W 5%

C483 0.1uF 16V

R240 22 1/16W 5%

R241 10 1/16W 5%

Reserve

1K 1/16W 5%

R238

1 2

2K 1/16W 5%

R243

1 2

※
※
※

Reserve

21

12

12

PWR_5VMAIN PWR_5VMAIN

R237

1 2

R242

GND1 GND1

※HDDCN側に搭載

RM56

IDE_PDD0
IDE_PDD2
IDE_PDD1
IDE_PDD3

IDE_PDD4
IDE_PDD5
IDE_PDD6

GND1

PWR_BAY PWR_BAY

12

1K 1/16W 5%

R245

1 2

2K 1/16W 5%

R250

2 1

GND1 GND1 GND1

1
2
3
4

1
2
3
4

IDE_RST_HDD#

R247 22 1/16W 5%

C485 0.1uF 16V

R248 10 1/16W 5%

R249 18 1/16W 5%

10kx4 1/32W 5%

RM58

10kx4 1/32W 5%

21

21

12

SMT8

SMT8

8
7
6
5

8
7
6
5

R246

2 1

1K 1/16W 5%

R251

2K 1/16W 5%

Reserve

1 2

※BAYCN側に搭載

RM59

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3

IDE_SDD4
IDE_SDD5
IDE_SDD6

4
3
2
1

4
3
2
1

2

SMT8

5
6
7

10kx4 1/32W 5%

RM60

10kx4 1/32W 5%

8

SMT8

5
6
7
8

R510 1K 1/16W 5%

12

3

※IDEPDIORHDD#,IDEPDIOWHDD#,IDEPDIORDYHDD#は
それぞれGND1のｶﾞｰﾄﾞを付けて付線すること。

IDE_PDIOR_HDD#

IDE_PDIOW_HDD#

IDE_PDIORDY_HDD#

12

C484

Reserved

r68pF 25V

GND1

PWR_5VMAIN

IRQ1516,55
IDE_PDDREQ17
IDE_SDDREQ17,55

4

PWR_3VMAIN

RM57

16

4
3
2
1

10kx4 1/32W 5%

※ICH2裏面に搭載

16,55

3 2

BAY1_ON17

※
※
※

C488

Reserve

3

21

r68pF 25V

PWR_BAY

Reserved

IDE_SDIOR_BAY# 55

IDE_SDIOW_BAY# 55

IDE_SDIORDY_BAY

4

5
6
7
8

Q61

2SK3019

1

5

PWR_BAY

IRQ14

GND1

IRQ15_BAY

5

6

6

IDE_PDD[0:15]17

IDE_PDDREQ17

IDE_PDDACK#17

IDE_PDCS#117

PWR_5VMAIN

FL39

<FILTER>

1 2

BLM21P300S

7

CN4

1

GND1

IDE_PDD7

IDE_PDD6

IDE_PDD5

IDE_PDD4

IDE_PDD3

IDE_PDD2

IDE_PDD1 IDE_PDD13

IDE_PDD0

IDE_PDIOR_HDD#

※

IRQ1416

IDE_PDA117

IDE_PDA017

HDDLED#39,41

2

BPDD7

3

BPDD6

4

BPDD5

5

BPDD4

6

BPDD3

7

BPDD2

8

BPDD1

9

BPDD0

10

GND1

11

BPDDREQ

12

GND1

13

GND1

14

BPDIOR#

15

GND1

16

PDDACK#

17

IRQ14

18

BPDA1

19

BPDA0

20

BPDCS1#

21

HDDLED#

22

5VMAIN

23

5VMAIN

24

5VMAIN

25

5VMAIN

Thyme HDD CN

8

RSTDRV#

GND1

BPDD8

BPDD9

BPDD10

BPDD11

BPDD12

BPDD13

BPDD14

BPDD15

GND1

GND1

BPDIOW#

GND1

GND1

BPDIORDY

GND1

IOCS16#

PDIAG#

BPDA2

BPDCS3#

GND1

GND1

GND1

GND1

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

GND1

IDE_PDD8

IDE_PDD9

IDE_PDD10

IDE_PDD11

IDE_PDD12

IDE_PDD14

IDE_PDD15

IDE_PDIOW_HDD#

IDE_PDIORDY_HDD#

1 2

R244 1K 1/16W 5%

9

IDE_RST_HDD#

※

※

IDE_PDA2 17

IDE_PDCS#3 17

※025/12

ピンアサイン変更CN4

1 2

1 2

4.7uF 6.3V

C486

Rev.

100pF 25V

C487

DATE Design

2001.01.16 Komahara

Appr.

7

GND1

Description

CheckDesign

Yoshida Aoki

TITLE

Laurel

DRAW. No.

C1CPxxxxxx-X1

Appr.

8

FUJITSU
LTD.

9

SHEET

CAST

57 82

※025/9
電源変更

1

PWR_5VMAIN

PWR_CHARGEIN

2

CRT_Q_DDCCLK25,53

CRT_Q_VSYNC25,53

CRT_Q_HSYNC25,53

CRT_Q_DDCDAT25,53

BKLVOL40

EBLEN40

USB_P3P16

USB_P3N16

BLUE_ON40

PHS_LED#50

3

CN3

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

CB CN

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

4

PWR_2

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

INTMIC_IN 35INTMIC_RTN35

5

BLUE_RI 16,17

BLUE_DETACH 40

BLUE_EXIST# 40,41

BLUE_RST# 40

PHS_ON 50

6

CRT_RED 12,53

CRT_GREEN 12,53

CRT_BLUE 12,53

LCDID0 20,24

LCDID1 20,24

PWR_3VSTD

※025/12

ピンアサイン変更
CN3(Bluetooth信号ピンアサイン検討要）

※055/31

ピンアサイン変更

※106/15

ピンアサイン変更

PWR_3VSUS

7

8

9

GND_AUD

GND1GND1

Backup

TITLE

Lurel

DRAW. No.

Rev.

DATE Design

1

2

3

4

5

6

2001.01.16 Komahara

Appr.

7

Description

CheckDesign

Yoshida Aoki

Appr.

8

C1CPxxxxxx-X1

FUJITSU
LTD.

9

SHEET

CAST

58 82

1

2

3

4

Power

Desgin requirement of power circuit.

PWR_VCH2.5

maximam current
500mA (320mATYP)

SourcePowr Plane

Enable Control

PWR_3VSUS 3VSUS (Power Sequence)

5

Type
LDO

6

Placement location
Close the VCH

7

Destination pages
P24,P25

8

DDC ; DC to DC Convertor

9

VTTPWRGD

RQUEST I/F
TYPE

OD

SourceSignal Name

Destination

Power ciucuit CPU

Remarks
Pull-up to 1.5VMAIN

VTTPWRGD# OD Power ciucuit PLL Pull-up to 3VMAIN P4

1

2

3

4

5

6

Destination pages
P5,P8

Rev.

DATE Design

7

Appr.

…

TITLE

Laurel

DRAW. No.

Description

CheckDesign

Appr.

8

C1CP064740-X1

FUJITSU
LTD.

9

SHEET

CAST

58

76

A

B

C

D

E

F

G

H

I

LAUREL Power

Power Tree

PR CN

DCIn CN Diode

Battery1 CN

Battery2 CN

SubBattery CN

4A

ChargeIn

4A

Charger's

4A

AmMeter

Charger DDC

MB3879

MainChg

Batt1

AmMeter

MM1380

Batt2

AmMeter

6A

MM1380

SubBatt

Switch

100mA 100mA

uPA1914

Power Contents

DC to DC Convertor 61

Regulator

PowerLine

PowerManagement

Power/ TopPage

A

CPUCore
CPUBus
3VSstd/5VSus
Charger
LDO_SYSTEM
LDO_Audio
LDO_PMU
DCIn
Battery
SubBattry
PWR_1,2
Switch
PMU
AmMeter
VolMeter
ACon/BtIn
Scont

B

2001/08/13
2001/11/01

DCIn

4A

1.6A

1.6A

Charge1

6A6A

Charge2

6A

6A

6A

Switch

Diode

Diode

Diode

PageContents

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77

C

4A

6A

6A

100mA

Pow1

6A

3.5A

CPUCoreVcc DDC

2.5A

3VStd DDC

POWERON

LTC3778

5A

10mA

3VStd

ICH3, LAN, pull up, CN Board

1.5A

DDC

0.1A

LDO

0.5A 0.5A

Switch

2.0A

Switch

LTC1773

LP2951

BD6520F

BD6520F

TPC5120

2.0A

Switch

5A

3.5A

5VSus DDC

SUSC#

D

E

2.0A

5VSus

PCIC, USB, HOOP, MiniPCI, BAY

1.5A

Switch BayCN

2.0A

Switch

10mA

LDO

0.5A 0.5A

Fuse

0.5A

LDO BlueTooth

BD6520F

TPC8103

BD6520F

LP2951

BA3948FP

F

2.7A

CPUBus

SUSB#

0.1A

1.8VStd

LCD

LCDEn

3VSus

SUSC#

2.0A

3VMain

SUSC#

Bay1_On

5VMain

SUSB#

PWR_2

Rev.

15A

CPUCore

3A

2.0A 1.5A

10mA

PMU

0.5A

DATE Design

CPU:Tualatin LV

CPU, GMCH

ICH3

LCD

GMCH, PLL, DIMM, VCH, PCIC, S-I/O, 1394,
HOOP, MiniPCI, Cn Board

0.5A 0.5A

LDO

BA3965F

0.5A

ICH3, VCH, S-Video, FWH, Audio, S-I/O, HOOP,
FingerPoint, Pullup

0.85A

LDO

PQ070XZ1HZP

1.0A

LDO

PQ070XZ1HZP

1.5A

Bay

PR, CN Board, HDD, HOOP, KBC,
Pointing, FingerPoint

1.0A

LDO

BA3948FP

0.1A

PMU,

NJU7241F40

…

Invertor

Appr.

G

Description

CheckDesign

CN Board

DDC ; DC to DC Convertor

2.5VSus

0.85A

1.5VMain

1.8VMain

Appr.

H

PLL, VCH

CPU, GMCH, ICH3

1.0A

GMCH, ICH3

1.0A

0.1A

Codec, AMP

AUD

0.1A

1.0A

MicLDO

MIC

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

59

76

1

PWR_1 VIN_3778

1 2

パターン接続指定（エディタ）

VIN_3778

R419

2

1

2001.11.01
R429削除

100K 1/16W 0.5%

R438

12.7K 1/16W 0.5%

1 2

27pF 25V

C649

1 2

6

1

2 3

12

PWR_CPUBUS

21

R421

10K 1/16W 5%

100K 1/16W 5%

R425

1 2

GND1

VIN_3778

12

R426

10 1/16W 5%

21

C647

1uF 25V

R436

21

C641

2.2uF 16V

R427

1 2

0 1/16W

1 2

SUSB#

r 0 1/16W R

C648100pF 25V

2 1

R428

R437

20K 1/16W 5%

21

パターン接続指定（エディタ）

F4

6.3A 60V

Reserve

100K 1/16W 5%

5

Q50A
UM6K1N

Q52
2SC4617

12

C650 0.1uF 16V

R441

10K 1/16W 5%

2

VIN_3778INTVCC

R430

12

C651

12

3

21

1 2

1 2

1 2

C723

0.1uF 25V
10uF 25V B

C623

10uF 25V B

C624

10uF 25V B

C625

1 2

2001.11.01
C623〜C628変更:CAH06‑R1E1005K⇒CAH39‑R1E1005K

3

Q50B
UM6K1N

4

footprint変更:⇒1510P103

2001.11.01
D51変更:HRC0103A⇒RB521S‑30

A

M46

1

C653

C642

0.01uF 25V

1uF 10V

GND1

10

11

6

5

4

8

2

7

RUN/SS

LTC3778

EXTVCC

VIN

FCB

ITH

VRNG

ION

VON

SGND

LTC3778

PWR_CPUCORE

21

R431

1K 1/16W 5%

330K 1/16W 5%

12

C652

1000pF 25V

21

GND1

PWR_5VSUS

12

0.01uF 25V

1 2

10uF 25V B

C626

C627

⇒CA47002‑0109

20

BOOST

19

TG

18

SW

14

BG

17

SENSE+

16

SENSE-

12

INTVcc

13

DRVCC

15

PGND

9

VFB

3

PGOOD

1 2

10uF 25V B

DRVCC

C643

INTVCC

12

C654

GND1

4

1 2

10uF 25V B

C628

GND1

e1

21

D51

RB521S-30

21

0.1uF 25V

R434 10 1/16W 5%

1 2

C645

4.7uF 6.3V

12

1000pF 25V

10uF 25V B

C722

e2

12

G

C646

G

4

Q45 uPA1707G

567

4

1uF 10V

GND1

567

5

8

567

8

G

SD

123

8

SD

123

Q47 uPA1706

4m 1W 1%

R422

SD

123

4

Q46 uPA1707G

567

8

567

8

G

4

1 2

SD

123

6m 1W 1%

R423

G

SD

2 1

123

4

Q48 uPA1706

1 2

Q49 uPA1706

D48RB151L-40F

D49RB151L-40F

2 1

6

L11
CEP125-0R8MH

D50r RB151L-40F

2 1

3

Reserved

7

12

12

+

220uF 2.5V(POS)

C630

12

+

C631

220uF 2.5V(POS)

GND1

21

12

+

C637 4.7uF 10V

220uF 2.5V(POS)

C629

12

+

B

8

12

+

220uF 2.5V(POS)

C632

12

+

220uF 2.5V(POS)

C633

12

+

220uF 2.5V(POS)

C634

TP97
CPUCORE

220uF 2.5V(POS)

C635

9

PWR_CPUCORE

12

C638 10uF 6.3V B

21

C639 10uF 6.3V B

【配線について】

電源ライン、平滑コンデンサ±端子で30Aのパターン幅、

A

☆

GND1

g1

ビア数で配線すること
電源ライン、平滑コンデンサ±端子で25Aのパターン幅、

B

☆

ビア数で配線すること
最短でなるべくVIAを使わずにパターンを引くこと

D

☆

電源制御ICに接続する各ゲート信号のパターン幅をそれ

e

☆

ぞれ0.5〜1.0mmで同一かつ均一で、最短で配線すること
g1,g2は一点アースにてGND1に配線すること

g

☆

【配置について】

互いに近傍に配置し、電源制御IC近傍に置くこと

A

☆

VIAのことを考慮して部品間隔は広いめにとること
同一面上に配置すること

B 互いに近傍に配置し、電源制御IC近傍に置くこと

☆

VIAのことを考慮して部品間隔は広いめにとること
電源制御ICと同一面上に配置すること

D

電源制御ICと同一面、接続端子近傍に置くこと

☆

(A,Bよりも優先すること)

DPRSLPVR 16

TABLE FOR RESISTER VALUE

R422

R423

R438

R428

R432

R439

R433

R443

R444

MOBILE LV ULVRef

6m 6m

4m

6m 6m

4m

12.7K

21K

100K

187K

9.1K

16.2K

22.6K

56.2K

9.76K

10K

100K

215K

12.1K 14.7K

CPU_DPSLP# 5,8,16

PWR_3VMAIN

23

2 1

10K 1/16W 5%

R505

VR_HI/LO# 16

21K

21K

33.2K

37.4K

9.31K

274K

17.4K

DRVCC

21

R433

R444

GND1

21

9.76K 1/16W 0.5%
C644 1000pF 25V

12.1K 1/16W 0.5%

12

R432

6

9.1K 1/16W 0.5%

1

12

R439

22.6K 1/16W 0.5%

Q55A

6

UM6K1N

1

GND1

Q53A
UM6K1N

2

2

Q53B

3

UM6K1N

4

GND1 GND1

R443

5

PWR_1.5VMAIN

1

1 2

Q55B

3

100K 1/16W 0.5%

UM6K1N

5

4

g2

Q62
DTC143TEA

R481

1 2

10K 1/16W 5%

D

Power/ DDC/ CPUCore

1

2

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

3

4

5

6

Appr.

7

Description

CheckDesign

Appr.

8

C1CP064740-X1

FUJITSU
LTD.

9

SHEET

CAST

60

76

A

PWR_3VSTD

SUSB#

2

R254

1 2

6

1

B

120K 1/16W 5%

5

Q16A
UM6K1N

PWR_3VSTD

3

Q16B
UM6K1N

4

1 2

C490 10uF 6.3V B

GND1

21

8200pF 16V

C495

PWR_CPUBUS

12

12

1 2

C489 10uF 6.3V B

12

C496

R414

10K 1/16W 5%

R415

100K 1/16W 5%

C

R252
10m 1W 1%

1 2

470pF 25V

C494

220pF 25V

GND1

1 2

12

R256
30K 1/16W 5%

12

SUSB#4,16,38,41,43,46,61,62,63,70,71

C620

1uF 10V

D

Q13 uPA1815

2
3
6

S D

7

4

G

7

10

6

4

5

GND1

9

8

3

2

1

SENSE-

VIN

SYNC/FCB

RUN/SS

ITH

M28

LTC1773

LTC1773

2001.11.01

TG

SW

BG

VFB

GND

R256変更:120K1/16W5%⇒30K1/16W5%

⇒CAA30‑Q1J3002J

C496変更:470pF25V⇒47pF25V

⇒CAF34‑A1E47R0J

C496接続変更,C494とR256入れ換え

PWR_3VSTD

21

R413

100K 1/16W 5%

6

Q39A
UM6K1N

2

1

Q41

1

2SC4617

2 3

E

L7

1
5
8

Q38
2SK3019

3

Q39B
UM6K1N

5

4

G

Q14 uPA1707G

1

CDRH104-1.8uH

567

SD

4

GND1

32

GND1

12

8

123

1 2

12

VTTPWRGD# 4

VTTPWRGD 5,8

F

TP66

12

+

C492

PWR_CPUBUS

1 2

220uF 2.5V(POS)

PWR_CPUBUS

12

+

220uF 2.5V(POS)

C491

Ｃ４９１はCPUの近くに実装
Ｃ４９２はＭ３ Ａｌｍａｄｏｒ近くに実装

GND1

22K 1/16W 0.5%

R253

R255

39K 1/16W 0.5%

G

1.25V 2.7A
/Peak 5.7A

C493

4.7uF 10V

H

I

Power/ DDC/ CPUBus

A

B

GND1

R416

1 2

r 100K 1/16W 5%

Reserve

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

61

76

A

PWR_5VSUS

PWR_PMU

R259

1 2

100K 1/16W 5%

POWERON41,46

SUSC#16,51,71,72

SUSB#

2001.11.01

1

TRIP1

TRIP2

Q19
DTC144EEA

R265

1 2

12K 1/16W 5%

1 2

C508 0.1uF 25V

R267 9.1K 1/16W 5%

C513 0.1uF 25V

12

R262

100K 1/16W 5%

2 3

GND1

12

12

GND1

R267変更:8.2K1/16W5%⇒9.1K1/16W5%

⇒CAA30‑Q1J9101J

12

12

0.1uF 16V

C515

Power/ DDC/ 3V,5V

A

B

2 1

0.01uF 25V

C516

B

PWR_1

C503

2 1

GND1

100K 1/16W 5%

R263

GND1

12

0.01uF 25V

C517

0.1uF 25V

12

GND1

24

21

9

10

4

5

6

11

25

23

12

3

13

7

C518 47pF 25V

TPS5120

VCC

REG5VIN

STBY1

STBY2

PWM

CT

5VSTBY

SCP

TRIP1

TRIP2

PGOOD

SS1

SS2

GND

TPS5120

C

M29

VREF5

LH1

OUT1-H

OUT1-L

OUT1GND

FB1

INV1

REF

LH2

OUT2-H

OUT2-L

OUT2GND

FB2

INV2

C

LL1

LL2

10uF 10V

C502

GND1

22

30

29

28

27

26

2

2200pF 25V

1

8

16

17

18

19

20

14

15

12

C505

GND1

2200pF 25V

21

12

C519

1 2

21

D13

12

R264

100 1/16W 5%

C507

0.1uF 16V

2 1

D

2001.11.01
C497変更:CAH06‑R1E1005K⇒CAH39‑R1E1005K

footprint変更:⇒1510P103

PWR_1

C716追加:CAH39‑R1E1005K

2 1

2 1

10uF 25V B

C716

GND1

RB521S-30

C504

1uF 10V

2001.11.01
C506変更:CAH06‑R1E1005K⇒CAH39‑R1E1005K

12

21

R271

100 1/16W 5%

D15

RB521S-30

12

C512
1uF 10V

footprint変更:⇒1510P103

C717追加:CAH39‑R1E1005K

PWR_1

【配置について】

互いに近傍に配置し、電源制御IC近傍に置くこと

A

☆

VIAのことを考慮して部品間隔は広いめにとること
同一面上に配置すること

B 互いに近傍に配置し、電源制御IC近傍に置くこと

☆

VIAのことを考慮して部品間隔は広いめにとること
電源制御ICと同一面上に配置すること

他回路 A部、制御ICのパターン・部品下の全層に対し、

他回路の部品は配置しないこと

D

10uF 25V B

C497

e2

1 2

E

TRIP1

e1

10uF 25V B

C717

GND1

e3

e4

E

1 2

8
7
6
5

Q17

10uF 25V B

C506

uPA1707G

SD

G

TRIP2

1
2
3

4

Q20

8
7
6
5

uPA1707G

F

L8

CEP125-4R0MH

12

3

GND1

567

8

Q18

G

SD

D14

2 1

uPA1707G

一点アース

L9
CEP125-4R0MH

1 2

GND1

Q21

8

uPA1707G

SD

123

RB151L-40

3

D16

123

4

g1

GND1

1
2

SD

3

4

G

567

G

4

一点アース

GND1

☆
☆

☆

☆ A部のパターン・部品下の全層に対し、他回路の周波数

Rev.

F

G

H

3.3V/ 5A

A1

2200pF 25V

C501

1 2

12

510 1/16W 5%

R257

GND1

R258

27K 1/16W 0.5%

1 2

R260

9.1K 1/16W 0.5%

1 2

GND1

12

+

C498

12

21

+

C499

150uF 6.3V(POS)

150uF 6.3V(POS)

B2

C500 4.7uF 10V

A2

12

12

+

+

680 1/16W 5%

2 1

R266

RB151L-40

2 1

12

4700pF 25V

C514

2 1

R268 75K 1/16W 0.5%

GND1

C509

C510

150uF 6.3V(POS)

2 1

150uF 6.3V(POS)

B1

g2

15K 1/16W 0.5%

R270

2 1

Appr.

GND1

Description

CheckDesign

Appr.

H

【配線について】

電源ライン、平滑コンデンサ±端子で6Aのパターン幅、

A

ビア数で配線すること
電源ライン、平滑コンデンサ±端子で6Aのパターン幅、

B

ビア数で配線すること
電源制御ICに接続する各ゲート信号のパターン幅をそれぞれ

e

0.5〜1.0mmで同一かつ均一で、最短で配線すること
g1,g2,g3は一点アースにてM1-20PIN(GNDP)に配線すること

g
他回路

の早い信号、インピーダンスの高い信号、重要な信号の
パターンを配線しないこと

DATE Design

G

5.0V / 5A

4.7uF 10V

C511

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

PWR_3VSTD

PWR_5VSUS

I

TP67
PWR_3VSTD

PWR_5VSUS

SHEET

62

I

TP68

CAST

76

PWR_3879REF

PWR_DCIN

A

R

C677 r 0.1uF 25V

21

12

R

C678 r 0.1uF 25V

2 1

R277
15K 1/16W 5%

PWR_3879REF

21

2 1

0.1uF 25V

C542

GND1

R463

R275
51K 1/16W 5%

R276
100K 1/16W 5%

R278
47K 1/16W 5%

PMU_MAINCHG72,73

1 2

0.1uF 16V

C543

R272
20m 1W 1%

1 2

12

0 1005

1 2

1 2

2 1

PWR_3879REF

PWR_PMU

PWR_PMU

PMU_VB172

PMU_VB272

2 1

0.1uF 16V

C544

Reserve

PMU_VBC

PMU_VBV

C545

0.033uF 16V

B

PWR_DCINPWR_CHARGEIN

12

0 1005

R464

C530
3300pF 25V

C531
6800pF 25V

1 2

GND1

C546

2 1

0.033uF 16V

TP69
PWR_DCIN

パターン接続指定（エディタ）

M30

Reserve

47

-INC1

48

+INC1

46

21

FB1

45

OUTC1

44

-INE1

42

21

FB2

Input Current/Voltage Amp

-INE2

DTC

VDD

VSS

DecorderControlPower and Condition

D0

D1

D2

D3

CTL

+INE1

+INE2

+INE3

+INE4

VB

VCC

TEST

CS1

CS2

CT

GND

MB3879

C533

0.1uF 16V

21

41

39

8

6

2

3

4

5

7

43

40

19

31

9

1

28

23

22

37

100pF 25V

C547

38

C

R2721pinPAD横にR463,R2722pin
PAD横にR464を搭載のこと。
C677､C678はM30 47,48piN付近搭載のこと。

21

C528

C532
3300pF 25V

C534
3300pF 25V

C535
3300pF 25V

C536
3300pF 25V

PWR_DCIN

21

0.1uF 25V

21

21

21

12

25

VCCO

27

GNDO

26

VH

24

OUT

15

+INC2

14

IN1

16

FB3

17

OUTC2

18

-INE3

20

FB6

Output1 Current/Voltage AmpOutput2 Current/Voltage Amp

21

-INE6

35

+INC3

36

IN2

34

FB4

33

OUTC3

32

-INE4

30

FB5

29

-INE5

10

OUT-EV

11

OUT-EC

Output Mode Power and Driver

13

OUT-EA1

12

OUT-EA2

0.1uF 25V

C529

2 1

R279
51K 1/16W 5%

2 1

R280
100K 1/16W 5%

2 1

R282
27K 1/16W 5%

1 2

R283
51K 1/16W 5%

1 2

R284
100K 1/16W 5%

1 2

R285
27K 1/16W 5%

D

PWR_DCIN

D1

E

Q22

uPA1717

1
2
3

21

4

2 1

10uF 25V B

C522

2 1

10uF 25V B

C718

Reserve

0.1uF 25V

C525

2001.11.01
C522変更:CAH06‑R1E1005K⇒CAH39‑R1E1005K

footprint変更:⇒1510P103

C718追加:CAH39‑R1E1005K

1 2

R290
0 1/16W

2 1

GND1

e

PMU_CHGMASK 72

R

C539

r 1000pF 25V

H

S D

G

F

BA

L10

02 01

D18

MBRS130LT3

CDRH104R-22uH

1 2

12

+

8
7
6
5

C520

G

H

8.4V-12.6V 1.823A

2 1

R274

10K 1/16W 5%

D17
RB053L-30

12

12

+

100uF 16V(AL)

100uF 16V(AL)

C521

g

10uF 16V B

C526

12

GND1GND1

f1

f2

8.4V-12.6V 1.823A

2 1

D22
RB053L-30

f3

f4

PWR_DCIN

2 1

R286

100K 1/16W 0.5%

C540

1 2

51K 1/16W 0.5%

R291

r 0.1uF 25V

R

1 2

GND1 GND1 GND1 GND1

PWR_3879REF

R287

2 1

100K 1/16W 0.5%

PMU_VBV PMU_VBC

21

C541

r 0.1uF 16V

39K 1/16W 0.5%

R292

R

1 2

PWR_3879REF

2 1

1 2

R

R288

r 100K 1/16W 0.5%

R

21

R293

r 100K 1/16W 0.5%

PMU_VB1 72

C537

0.1uF 16V

R273
39m 1W 1%

1 2

d2

R281
39m 1W 1%

2 1

d3

PWR_3879REF

PWR_CHARGE1

PWR_CHARGE2

R

2 1

R289

r 100K 1/16W 0.5%

R

1 2

R294

r 100K 1/16W 0.5%

21

I

PMU_VB2 72

C538

0.1uF 16V

D4

Power/ DDC/ Charger

A

B

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

63

76

A

B

C

D

E

F

G

H

I

PWR_3VSTD

PWR_3VMAIN

D25
1SS400

TP70
PWR_1.8VSTD

12

10uF 16V B

C679

TP71
PWR_1.8VMAIN

12

10uF 16V B

C680

PWR_3VSUS

1 2

C559

Reserve

0.1uF 16V

C552

GND1

GND1

12

+

PWR_1.8VSTD

PWR_1.8VMAIN

220uF 2.5V(POS)

C553

M31

8

IN

5

ERR#

3

1 2

SHUTDOWN

4

GND

LP2951ACDM-3.3

C551

0.1uF 16V

D23
1SS400

M32
PQ070XZ1HZP

1

VIN

2

VC

C548

1 2

0.1uF 16V

SENSE

GND

1

OUT

2

7

FB

6

TAP

21

3

VO

4

VADJ

5

1.8V 0.1A

R295
11K 1/16W 0.5%

2 1

R296
24K 1/16W 0.5%

1 2

1.8V 1.0A

R297

3.3K 1/16W 0.5%

2 1

R298

7.5K 1/16W 0.5%

2 1

12

21

M34
BA3965FP

0.1uF 16V

1

VIN

8

VC

2

N.C1

4

N.C2

GND1

GND2

3

VO

5

ST

6

7

21

C560

0.01uF 16V R

【配置について】

☆

ICHとGMCHの近傍に配置すること

☆ 各入力コンデンサと出力コンデンサはレギュレータの近傍に配置すること

【配線について】

-端子はレギュレータのグランドと一点アースとすること

☆

【配置について】

☆

ICHのすぐ近傍に配置すること

2.5V 0.5A

PWR_2.5VSUS

12

12

+

Reserve

0.1uF 16V

C557

GND1

47uF 6.3V(POS)

C558

TP73
PWR_2.5VSUS

☆ 各入力コンデンサと出力コンデンサはレギュレータの近傍に配置すること

【配線について】

-端子はレギュレータのグランドと一点アースとすること

☆

D24
1SS400

21

12

+

C555

PWR_1.5VMAINPWR_3VMAIN

220uF 2.5V(POS)

M33
PQ070XZ1HZP

1

VIN

2

VC

C556

1 2

0.1uF 16V

GND

3

VO

4

VADJ

5

1.5V 0.85A

12

R299

1.5K 1/16W 0.1%

12

R300

7.5K 1/16W 0.1%

12

Reserve

0.1uF 16V

C554

TP72
PWR_1.5VMAIN

Power/ LDO/ System

A

B

GND1

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

64

76

A

B

C

D

E

F

G

H

I

【配置について】

☆ Audio回路のすぐ近傍に配置すること

各入力コンデンサと出力コンデンサはレギュレータの近傍に配置すること

☆

【配線について】

コンデンサの-端子はレギュレータのグランドと一点アースとすること

☆

【GNDAUDとGND1の接点について】

GND1とGNDAUDはPWRAUDを生成するRegulatorのGND端子で、

☆

カットが可能なように、表面層にて一点接続とする。
(下図参照)

GND1 GND_AUD

Regulator

Output
Capasitor

PWR_5VMAIN

D52
1SS400

21

M47
BA3948FP

2

VIN

1

12

0.1uF 16V

C655

VC

4

VO

C

GND

3

21

5

R446
33K 1/16W 0.5%

12

R448
15K 1/16W 0.5%

4.0V 1.0A

PWR_AUD

12

+

C656

100uF 6.3V(POS)

TP92
PWR_AUD

GND_AUD

PWR_AUD PWR_MIC

R445

2 1

0 1005

D53

Reserve

1SS400

21

PWR_5VMAIN PWR_MIC

R447

2 1

330k 1/16W 5%

12

Reserve

0.1uF 16V

C657

Reserve

Reserve

M48

VIN2VOUT

5

STB

1

GND

NJU7241F40

Reserve

N.C.

3

4

2 1

Reserve

10uF 16V B

C658

GND_AUD

GND_AUD

TP93
PWR_MIC

R465

r 0 1/8W

R

To
Power
block

12

GND1

(重要)
R465はM42(2)の近傍に配置すること。
PT板のエディタ処理時
R465のFOOT幅でGDNAUD
とGND1を接続すること｡

To
Audio
block

→←

【配置について】

☆ Audio回路のすぐ近傍に配置すること

各入力コンデンサと出力コンデンサはレギュレータの近傍に配置すること

☆

【配線について】

コンデンサの-端子はレギュレータのグランドと一点アースとすること

☆

Power/ LDO/ Audio

A

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

B

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

65

76

A

B

C

D

E

F

G

H

I

8

5

21

C562

0.1uF 25V

3

4

【配置について】

PMU接続端子近傍に配置すること☆
各入力コンデンサと出力コンデンサはレギュレータの近傍に配置すること☆

【配線について】

-端子はレギュレータのグランドと一点アースとすること☆

M35

IN

ERR#

SHUTDOWN

GND

LP2951ACDM-3.3

OUT

SENSE

TAP

3.3V 10mA

TP74
PWR_PMU

PWR_PMUPWR_1

1

2

7

FB

6

21

10uF 16V B

C564

2001.11.01

R497 0 1608

2 1

R497追加:01608P142
CA53003‑0422

GNDAGND1

Power/ LDO/ PMU

A

B

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

66

76

A

B

TP76
PWR_EXDCIN

PWR_EXDCIN

C

2 1

D26
RB053L-30

2 1

D27
RB053L-30

D

PWR_CHARGEIN

12

+

C565
47uF 25V(AL)

GND1

TP77
PWR_CHARGEIN

E

F

G

H

I

Power/ Node/ DCIn

A

B

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

67

76

A

B

C

D

E

F

G

H

I

2001.11.01

3rd BATTERY

CN23

1

01

2

02

3

03

4

04

5

05

6

06

7

07

8

08

9

09

10

10

MAINBAT CN

GND1

F3変更:CA53004‑0430⇒CA53004‑0472
footprint変更:⇒1510P102

1 2

C568

4.7uF 25V

12

Reserve

C569

0.22uF 25V

F3
10A 72V

2 1

12

C570

0.1uF 25V

12

C571

0.1uF 25V

2001.11.01
R327変更:実装⇒リザーブ

TP79
GND1

R327
0 1/16W

Reserve

TP80
GNDA

21

GNDAGND1

パターン接続指定（エディタ）

【Aにある部品の配置・パターンについて】

☆

コンデンサはコネクタの接続端子の近傍に配置し、内層でなく表面層にて
コネクタの端子に直接パターンを引くこと。
(GNDA、もしくはすべてのGND1に対しても同様、かつバッテリコネクタの
10pinで一点アースすること)

【Bにある部品の配置について】

それぞれバッテリコネクタの接続先端子の近傍に配置すること

【Cにある部品の配置について】

PMUの接続端子近傍に配置すること

【Dにある部品の配置について】

D1,D2それぞれ互いに近傍に配置すること

【GND1〜GNDA間の一点アースについて】

バッテリコネクタとベイコネクタの中間に配置すること

A1

PMU_BT1TEMP0

PMU_BT1IN#0

PMU_BT1CLK0

PMU_BT1DAT0

Reserve

2 1

C572

0.1uF 25V

TP78
PWR_BATT1

PWR_BATT1

PMU_VSENSE1 74,76

PMU_SCONT1 76

PWR_BT1ROM

GNDA

PWR_PMU PWR_PMU

PMU_BT1CLK0

PMU_BT1DAT0

2

3

1

PWR_PMU

R319

PMU_BT1TEMP0

PMU_BT2TEMP056

10K 1/16W 0.5%

12

12

Reserve

Reserve

100K 1/16W 5%

100K 1/16W 5%

R306

1 2

R305

D281SS302

3

R320

2 1

10K 1/16W 0.5%

R309
100 1/16W 5%

2 1

2 1

PWR_PMU

R311
100 1/16W 5%

2

D291SS302

1

1 2

R313
100 1/16W 5%

D1 D2

GND1

R323
100 1/16W 5%

2 1

R325
100 1/16W 5%

2 1

C573

12

C566

12

220pF 50V

Q24
TP0610T

220pF 50V

1 2
3

4

GND1

21

220pF 50V

C574

PMU_BT1CLK 72

PMU_BT1DAT 72

3 2

1

1K 1/16W 5%

R317

Q26B

UM6K1N

5

PMU_BT1TEMP 72

PMU_BT2TEMP 72

PWR_PMU

2 1

R315
470K 1/16W 5%

PMU_BT2CLK056

PMU_BT2DAT056

12

12

Reserve

Reserve

100K 1/16W 5%

100K 1/16W 5%

R307

R308

R310
100 1/16W 5%

1 2

2 1

PWR_PMU

R312
100 1/16W 5%

2

3

1

PWR_BT2ROMPWR_BT1ROM

PMU_BT1IN#0

PMU_BT2IN#056 PMU_BT2IN# 72

1 2

R314
100 1/16W 5%

PWR_PMU

21

21

R322 100K 1/16W 5%

R321

D301SS302

3

21

C567

GND1

100K 1/16W 5%

R324
1K 1/16W 5%

2 1

R326
1K 1/16W 5%

2 1

2

1

GND1GND1

Q25
TP0610T

220pF 50V

1 2
6

1

GND1

0.1uF 16V

C575

D311SS302

3 2

1K 1/16W 5%

R318

Q26A

UM6K1N

2

12

C576

0.1uF 16V

GND1GNDA

1

12

PMU_BT2CLK 72

PMU_BT2DAT 72

PWR_PMU

2 1

R316
470K 1/16W 5%

PMU_BT2ID 72PMU_BT1ID 72

B

PMU_BT1IN# 72

C

Power/ Node/ Battery

A

B

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

68

76

A

B

CN24

1

+

2

-

SUB BAT CN

Sub-Batt

A B

C621

12

C

R

r 2200pF 25V

GND1

12

C622

r 0.1uF 16V

PWR_SUBBATT

R

TP91

PWR_SUBBAT

D

M45
S-80761SL

2

VDD

E

Sub-Batt

12

5

2

R417
470K 1/16W 5%

Sub-Batt

1

OUT

VSS

3

GND1 GND1

SUBBATON41

4

3

3

Q43B
UM6K1N

Sub-Batt

4
6

Q43A
UM6K1N

Sub-Batt

1

F

Q42

S D

G

uPA1914

Sub-Batt

G

D47

1
2
5
6

2 1

M1FP3

Sub-Batt

R418

6.8K 1/10W 5%

Sub-Batt

PWR_1

12

H

I

Power/ PMU/ Etc3

A

【Aの配置について】

互いに近くに配置すること

B

【Bの配置について】

互いに近くに配置すること

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

69

76

A

B

PWR_DCIN

PWR_CHARGE2

PWR_CHARGE1

PMU_VS24,16,38,41,43,46,61,62,63,71,77

C

5

2 1

D32
RB053L-30

2 1

D33
RB053L-30

2 1

D37
RB031-30FA

2 1

D38
RB031-30FA

2 1

D34
RB031-30FA

2 1

D35
RB031-30FA

Q56

8
7
6
5

G

TPC8103

PWR_PMU

R462

1 2

100K 1/16W 5%

3

Q57B
UM6K1N

4

D

TP81
PWR_1

PWR_1

E

F5

2A 24V

F

PWR_2

12

G

H

I

2001.11.01
D34,D35,D37,D38変更:RB031L‑20⇒RB031‑30FA

⇒CA47002‑0154

1
2

SD

3

4

R460

47K 1/16W 5%

1 2

D54
1SS400

12

R461

4.7K 1/16W 5%

6

Q57A
UM6K1N

2

1

PWR_DCIN

21

Power/ Node/ PWR_1

A

B

GND1 GND1

C

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

70

76

A

B

C

D

E

F

G

H

I

PWR_3VSTD PWR_3VSUS

M39

SUSC#16,51,63,72

C681

1uF 10V

1

VDDA

2

VDDB

3

SSCTL

4

12

C583

220pF 25V

CTRL

BD6520FP

12

OUTA

OUTB

OUTC

VSS

8

7

6

5

2001.11.01
接続変更:M39.3とM39.4入れ換え

5.0V 2.0A

PWR_5VSUS PWR_BAY

R329

1 2

470K 1/16W 5%

BAY1_ON41,42

Q28 uPA1815

2
3

1

6

5

S D

7

8

4

C585

1 2

0.1uF 16V

G

21

R330

47K 1/16W 5%

32

1

Q29

2SK3019

GND1

3.3V 2.0A

TP85
PWR_3VSUS

GND1 GND1

TP86
PWR_BAY

PWR_3VSTD PWR_3VMAIN

M36

1

VDDA

2

VDDB

21

3

4

C577

680pF 25V

SSCTL

CTRL

BD6520FP

SUSB#4,16,38,41,43,46,61,62,63,71,77

C682

1uF 10V

21

2001.11.01
接続変更:M36.3とM36.4入れ換え

1

2

3

LCDEN39,56

1uF 10V

C684

2 1

4

21

C685

100pF 25V

3.3V 2.0A

8

OUTA

7

OUTB

6

OUTC

5

VSS

M52

VDDA

VDDB

SSCTL

CTRL

BD6520F

OUTA

OUTB

OUTC

VSS

8

7

6

5

TP82
PWR_3VMAIN

GND1

TP94

PWR_LCDPWR_3VSTD

PWR_LCD

PWR_5VSUS PWR_5VMAIN

M37

SUSB#4,16,38,41,43,46,61,62,63,71,77

12

12

C683

1uF 10V

C579

560pF 25V

2001.11.01
接続変更:M37.3とM37.4入れ換え

1

2

3

4

VDDA

VDDB

SSCTL

CTRL

BD6522FP

OUTA

OUTB

OUTC

VSS

8

7

6

5

GND1

5.0V 2.0A

TP83
PWR_5VMAIN

Power/ Node/ Switch

A

B

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

71

76

A

B

C

D

E

F

G

H

I

X1

X2

R341
75K 1/16W 0.5%

R342
56K 1/16W 0.5%

01

03

02

B

FAR101

X

X5
4MHz

PWR_PMU

R334

10K 1/16W 5%

2 1

CLK_PMU32K40

※ 本クロックはノイズに弱いため

上下層に高速な信号が走らないように
配線すること

【Aについて】

☆

各部品は互いに近くに配置し、PMUの同一面/近傍
に配置すること
そのパターンはVIAを使用せず、最短で配線すること
部品、PMUへのパターンともに三次元グランドガード
すること

PWR_PMU

21

21

2001.11.01
R?追加:r01608P142CA53003‑0422RESERVEPAD
GNDA‑‑‑>GND1へ変更
X5.2,C590.1,C594.1,C595.2,C596.2,
M40.56,M40.77,M40.5,M40.1,R346.2,
C591.2,R345.2

Power/ PMU/ PMU

A

GND1

21

C589

0.1uF 16V

R498 r 0 1608

1 2

TP75
VREF1.2

13K 1/16W 0.1%

R

R331

3.3M 1/16W 5%

2 1

21

C586
10pF 25V

GND1

PWR_PMU

PWR_PMU

R304

GNDAGND1

21

R303

12

GNDAGNDA

A

R340
18K 1/16W 5%

1 2

22K 1/16W 0.1%

12

PWR_PMU

GND1

C

PWR_VREF1.2

0.1uF 16V

C561

12

C594

0.1uF 16V

PMU_PCURST#41

2 1

R337 47K 1/16W 5%

2 1

R338 47K 1/16W 5%

2 1

R339 47K 1/16W 5%

PMU_ACON73,75
PMU_BT1SWON#76
PMU_BT2SWON#76
PMU_LED49

PWR_PMU

PWR_PMU

21

C592

4.7uF 10V

GNDA

PWR_PMU

PWR_PMU

12

C595

0.1uF 16V

1 2

R335
1K 1/16W 5%

PWR_VREF1.2

PWR_PMU

21

C590

GND1

21

C593

4.7uF 10V

12

C596

0.1uF 16V

D

0.1uF 16V

2

X0

3

X1

100

X0A

99

X1A

4

RST

32

V0

33

V1

34

V2

35

V3

25

P50/ALR1

26

P51/ALR2

27

P52/ALR3(LCD-A0)

28

P53/ACO

29

P54/OFB1

30

P55/OFB2

31

P56/OFB3(MAILLED)

67

CVRH2

66

CVRH1

65

CVRL

55

CVcc

56

CVss

89

AVR

80

AVcc

73

AVss

24

BVcc

47

Vcc(2)

98

Vcc

5

Vss

1

MODA

M40

MB89577
MB89P578

P00(PD-0)
P01(PD-1)
P02(PD-2)
P03(PD-3)

P04(PMUSMI)

P05(PRM#)

P06(PARST#)

P07(PE#)

P10/AN4(BT1VOL)
P11/AN5(BT2VOL)
P12/AN6(DCCUR)
P13/AN7(BT1TMP)
P14/AN8(BT2TMP)

P15/AN9(SW-WWW)

P16/AN10(BT1CUR)
P17/AN11(BT2CUR)

P90/AN3(VOLAD)

P91/DA1(VB1)
P92/DA2(VB2)

P21(TMPALM)

P22(SW-APA)

P23(PCUREDY#)

P24(LLB#)

P25(CHG-MASK)

P26(MAINCHG)

P27(SW-APB)

P30/SCL1
P31/SDA1

P32/ALART

P33/SCL2
P34/SDA2

P35/UO(LCD-CS)

P40/SCL3
P41/SDA3

P42/SCL4(LCD-CLK)

P43/SDA4(LCD-DATA)

P70/DCIN

P71/DCIN2(SW-MAIL)

P72/VOL1(BAT1IN)

P73/VSI1(VS1IN)

P74/VOL2(BAT2IN)

P75/VSI2(VS2IN)

P76/VOL3(LCD-BL1)

P77/VSI3(LCD-BL2)

P80/INT0(SUSA#)
P81/INT1(SUSC#)

P82/INT2(MAINON#)

P83/INT3(BT2ROMPW)

P84/EC(DVTMODE)

P85/SW1(BT1IN#)
P86/SW2(BT2IN#)

P87/SW3(BAYPOW)

P60/SEG8

P61/SEG9
P62/SEG10
P63/SEG11

P64/SEG12(LCD-DATA)

P65/SEG13(BT1ROMPW)

PB7/COM3

TQFP-100pin

E

90
91
92
93
94
95
96
97

81
82
83
84
85
86
87
88

77
78
79

6

P20

7
8
9
10
11
12
13

14
15
16
17
18
19

20
21
22
23

57
58
59
60
61
62
63
64

68
69
70
71
72
74
75
76

36

COM0

37

COM1

38

COM2

40

SEG0

41

SEG1

42

SEG2

43

SEG3

44

SEG4

45

SEG5

46

SEG6

48

SEG7

49
50
51
52
53
54

39

MB89577PFT-G-708(PMU)

PMU_D0
PMU_D1
PMU_D2
PMU_D3

PMU_SMI 40
PMU_PRM# 40
PMU_PARST# 40
PMU_PE# 40

PMU_BT1VOL 74
PMU_BT2VOL 74

PMU_BT1TEMP 69
PMU_BT2TEMP 69
SWC# 49
PMU_BT1DCHG 73
PMU_BT2DCHG 73

PMU_VB1 64
PMU_VB2 64

PMU_BT1CLK 69
PMU_BT1DAT 69

PMU_BT2CLK 69
PMU_BT2DAT 69
PMU_ROMCLK 75
PMU_ROMDAT 75

PMU_DCCMPIN 75

PMU_BAT1IN 75
PMU_VS1ALMIN 74
PMU_BAT2IN 75
PMU_VS2ALMIN 74

APPMODE# 49

SUSA# 16
SUSC# 16,51,63,71
MAINON# 41,42,49
PMU_BT2ID 69

PMU_BT1IN# 69
PMU_BT2IN# 69

PMU_SLCDC0
PMU_SLCDC1
PMU_SLCDC2

PMU_SLCDS0
PMU_SLCDS1
PMU_SLCDS2
PMU_SLCDS3
PMU_SLCDS4
PMU_SLCDS5
PMU_SLCDS6
PMU_SLCDS7

PMU_SLCDS8

PMU_APPLED 74

PMU_BT1ID 69

F

PMU_D[0:3]

GND1

PMU_SLCDC[0:2]

PMU_SLCDS[0:8]

PMU_D[0:3] 40

12

C588

0.1uF 16V

Rev.

DATE Design

PWR_PMU

R332

1 2

270K 1/16W 0.5%

R336

2 1

240K 1/16W 0.5%

GNDA

PMU_SLCDC[0:2] 49

PMU_SLCDS[0:8] 49

G

RM61

Appr.

5

4

876

123

CheckDesign

876

5

RM62

10Kx4 1/32W 5%

123

4

PMU_SCL1

PWR_3VSTD

21

R343

12

R346

Description

PMU_POWDWN#

10Kx4 1/32W 5%

1

GND1

10K 1/16W 5%

C591

0.1uF 16V

100K 1/16W 5%

Appr.

H

PLLB49

SWC#49

APPMODE#49

THLTL# 55,65

32

Q59
2SK3019

SW_ENTER# 49

SWA# 49
PCURDY# 41
PLLB 16,41
PMU_CHGMASK 64
PMU_MAINCHG 64,73
SWB# 49

SMB_CLK_PMU
SMB_DATA_PMU
ICHSMBALT# 17

PMU_POWDWN# 79

SWD# 49

1 2

R344

12

1K 1/16W 5%

RM63

3
4
2
1

100Kx4 1/32W 5%

PMU_SCL1

12

R345

GND1

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

79

100K 1/16W 5%

SHEET

I

SCL1

SCL2

6
5
7
8

PWR_PMU

72

CAST

76

PWR_PMU

PWR_PMU

A

D41

2 1

1SS400

D42

2 1

1SS400

R348

2 1

1K 1/16W 5%

R360

2 1

1K 1/16W 5%

B

2 1

R347
10m 1W 1%

b1 b2

12

1K 1/16W 5%

R349

12

C597

0.1uF 25V

1 2

R359
10m 1W 1%

b4 b3

21

21

1K 1/16W 5%

R350

21

12

C

TP87

PWR_1

12

R468

PWR_CHARGE1

100K 1/16W 5%

R466

r 100K 1/16W 5%

R

1

ISEL

IN-2VCC

3

IN+

GND4COM

M41
BD3180FV

PWR_CHARGE1PWR_BATT1

C598

0.1uF 25V

2001.11.01
M41変更:MM1380AWBE⇒BD3180FV

⇒新規部品(CA46005‑0383)

TP88

PWR_CHARGE2PWR_BATT2

PWR_CHARGE2

2001.11.01
M42変更:MM1380AWBE⇒BD3180FV

⇒新規部品(CA46005‑0383)

12

GSEL

OUT

D

E

F

☆

【bの配線について】
VIAを使用せずに最短でケルビン接続すること

他のパターンと分岐しないこと

G

H

I

【Aにある部品の配置について】☆
PMUの接続端子近傍に配置すること

PMU_POWDWN# 78

R467

21

r 100K 1/16W 5%

R

8

7

6

5

PWR_1

12

C600

0.1uF 25V

PMU_AMCOMSHIFT

R353

21

51K 1/16W 5%21C601

GNDA

1

PWR_PMU

0.1uF 16V

2 1

32

GNDA

2 1

R351

16K 1/16W 0.5%

R354

Q30

2SK3019

24K 1/16W 0.5%

2 1

R355

750K 1/16W 0.5%

2 1

R352
10K 1/16W 5%

GNDA

PMU_ACON72,75

PMU_MAINCHG64,72

12

A1

C599

0.22uF 10V

PMU_BT1DCHG 72

1 2

R356
0 1/16W

1 2

R358
0 1/16W

Reserve

PMU_AMCOMSHIFT

1K 1/16W 5%

R361

21

C602

Power/ PMU/ AmMeter

A

B

R362

0.1uF 25V

1K 1/16W 5%

12

C603

0.1uF 25V

1

ISEL

IN-2VCC

3

IN+

GND4COM

M42
BD3180FV

C

GSEL

OUT

8

7

6

5

R469

2 1

100K 1/16W 5%

D

PWR_1

Appr.

GNDA

12

A2

CheckDesign

C604

0.22uF 10V

PMU_BT2DCHG 72

Description

TITLE

Laurel

DRAW. No.

C1CP064740-X1

Appr.

H

FUJITSU
LTD.

I

SHEET

CAST

73

76

1 2

R364

Rev.

10K 1/16W 5%

DATE Design

G

12

12

C605

0.1uF 25V

12

51K 1/16W 5%

R365

GNDA

0.1uF 16V

C606

E

F

PWR_1

12

A

PMU_VSENSE169,76

R374

100K 1/16W 5%

1 2

R368
1K 1/16W 5%

B

2001.11.15
R368追加

12

R370

270K 1/16W 0.1%

6

Q32A

2

UM6K1N

1

21

R377

240K 1/16W 0.1%

GNDA

R371
220K 1/16W 5%

21

C608

C

2 1

2

2

3

3

M43A
TLC27L4IPW

470pF 25V

D

E

F

G

H

I

2001.08.07

R369

PWR_PMU

R372
160K 1/16W 0.5%

2 1

-

1

1

+

21

R378

220K 1/16W 0.1%

12

C609

130K 1/16W 0.1%

1 2

R379

0.1uF 16V

2 1

R375
160K 1/16W 0.5%

PMU_VS1ALMIN 72

300K 1/16W 0.1%

1 2

12

R376

300K 1/16W 0.1%

GNDA

6

6

5

5

-

+

M43B
TLC27L4IPW

R373
10K 1/16W 5%

7

7

1 2

A1

0.22uF 10V

C607

GNDA

21

TP89削除

PMU_BT1VOL 72

PMU_VSENSE256,76

1 2

R380
1K 1/16W 5%

12

3

5

4

21

GNDA

【配置について】

アンプおよび周辺回路はPMU近傍に配置すること

☆

Aにある部品はPMUの接続端子近傍に配置すること

☆
☆

アンプの入力の接続する部品はアンプ入力端の近傍に配置しすること

Power/ PMU/ VolMeter

A

B

2001.11.15
R380追加

R382

270K 1/16W 0.1%

Q32B

UM6K1N

R389

240K 1/16W 0.1%

R383
220K 1/16W 5%

12

C611

1 2

9

10

470pF 25V

C

9

-

+

10

M43C
TLC27L4IPW

8

8

R390

R391

GNDA

12

220K 1/16W 0.1%

21

C612

130K 1/16W 0.1%

GNDA

PWR_PMU

2 1

D

PMU_VS2 72

0.1uF 16V

R384
160K 1/16W 0.5%

1 2

2 1

R387
160K 1/16W 0.5%

PMU_VS2ALMIN 72

R381
300K 1/16W 0.1%

2 1

12

R388

300K 1/16W 0.1%

GNDA

PWR_1

E

13

12

1

13

-

+

12

M43D
TLC27L4IPW

D55
1SS302

2001.08.07
TP90削除

R385
10K 1/16W 5%

G

2 1

A2

Appr.

Appr.

PMU_BT2VOL 72

TITLE

Laurel

DRAW. No.

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

74

76

12

0.22uF 10V

C610

GNDA

Description

CheckDesign

H

14

14

2

3

4

4

21

C613

M43E

TLC27L4IPW

0.1uF 25V

Rev.

DATE Design

11

11

GNDA

F

A

B

C

D

E

F

G

H

I

PWR_DCIN

PWR_BATT1

PWR_BATT2

R394
12K 1/16W 0.5%

12

2 1

GNDA

R400
82K 1/16W 0.5%

2001.11.01
R399削除

R403
82K 1/16W 0.5%

2001.11.01
R402削除

【配置について】

☆

PMU接続端子近傍に配置すること

12

R396

1.2K 1/16W 0.5%

12

GNDA

12

GNDA

C614

0.01uF 25V

2 1

R401

1 2

R404

12

C616

15K 1/16W 0.5%

21

C617

15K 1/16W 0.5%

R395
51K 1/16W 5%

1000pF 25V

1000pF 25V

21

PMU_DCCMPIN 72

PMU_ACON 72,73

PMU_BAT1IN 72

PMU_BAT2IN 72

PWR_BT2ROM

GND1

M44

8

A0

A1

A2

Vss

NM24C02LMT8

SCL

SDA

Vcc

7

N.C

6

5

1

2

3

4

【配置について】☆
PMU近傍に配置すること

PWR_BT2ROM

12

0.1uF 16V

C615

GND1

PWR_BT2ROM

12

R397

12

4.7K 1/16W 5%

4.7K 1/16W 5%

R398

PMU_ROMCLK 72

PMU_ROMDAT 72

Power/ PMU/ Etc1

A

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

B

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

75

76

A

B

A1

A2

C

R406

2.4K 1/16W 5%

PMU_VSENSE169,74

PMU_VSENSE256,74

1 2

R410

2.4K 1/16W 5%

2 1

GND1

GND1

21

12

D

4700pF 25V

C618

4700pF 25V

C619

PWR_1

PWR_1

PWR_1

PWR_1

1

2 1

GND1

1

2 1

GND1

Q34
TP0610T

R408

Q36
TP0610T

R412

D45
DAN222

01

32

02

470K 1/16W 5%

D46
DAN222

01

32

02

470K 1/16W 5%

E

R405

1 2

03

10K 1/16W 5%

PMU_BT1SWON#72

R409

1 2

03

10K 1/16W 5%

PMU_BT2SWON#72

1

21

1

21

F

32

R407

470K 1/16W 5%

GND1

32

R411

470K 1/16W 5%

GND1

Q35

Q37

2SK3019

2SK3019

PMU_SCONT1 69

PMU_SCONT2 56

G

H

I

Power/ PMU/ Etc2

A

【Aの配置について】

互いに近傍に配置すること

TITLE

Laurel

DRAW. No.

Rev.

DATE Design

B

C

D

E

F

Appr.

G

Description

CheckDesign

Appr.

H

C1CP064740-X1

FUJITSU
LTD.

I

SHEET

CAST

76

76