FUJITSU SIEMENS Pro V8010 Schematics
5
4
3
2
1
MAX1845 ( +1.5V & VCCP1.05V )
P31
EF6 SYSTEM BLOCK DIAGRAM
SC486IMLTRT ( +1.8SUS & 0.9V )
D D
P32
SC4215 ( +2.5V )
P32
MAX1999 ( 3VPCU & 5VPCU )
P33
BATTERY CHARGER
P34
DDR II
MAX1907 ( CPU_CORE )
P35
C C
DISCHARGE
P36
SODIMM0
SMDDR_VTERM
DDR II
SODIMM1
P10,11
1.8VSUS
Dual Channel
DDR2
Intel Dothan Processor
VCC_CORE
GMCH_VTT
VCCA
478 uFCPGA
FSB
533/400MHz
Alviso-GM
GMCH
GMCH_VTT
1.8VSUS
+1.5V
+2.5V
+3V
82915GM
1257 PCBGA
X'TAL
32.768K
DMI interface
P5,6,7,8,9
P3,4
CPU Thermal
Sensor
+5V
VIN
+5V
LCD/INV
+3V
CONN
+5V
+2.5V
CRT
S-VIDEO
P13
P12
P12
P3
X'TAL
14.318M
CK-GEN
CK410M
+3V
ICS954206
P2
SATA
PATA
USB 2.0
SATA
( reserved )
B B
HDD/CD-ROM
+5V
P18
P18
USB Port 0 ~ 3
5VSUS
P17
AC'97
+3V
3VSUS
+2.5V
+1.5V
1.5VSUS
VCCRTC
GMCH_VTT
EC/KBC
AMCODEC
CONEXANT
20468-31
P19
MIC IN
JACK
A A
P21
Audio
Amplifier
GMT1428
+5V
P21
Stereo Speaker
P21
MODEM DAA
CONEXANT
20463-31
RJ11
P27
P20
ISA BIOS
TOUCHPAD
Keyboard
X'TAL
32.768K
3VPCU
P22
+5V
P23
P23
Headphone Jack
P21
5
4
PC97551
3VPCU
+3V
VCCRTC
COM&PRT
PORT
ICH6-M
P22
609 BGA
LPC
CRT
PORT
USB PORT
5,6
P14,15,16
SIOPC87383
FIR
PORT
REPLICATOR
RJ45
JACK
3
PCI Bus interface
USB,PCI Express
P24
3VSUS
5VSUS
P30
P30
PS/2
CONN.
TYPE III
MINI-PCI
Socket
INTB/C
REQ1
GNT1
AD20
( reserved )
BLUETOOTH
H/P
JACK
P25
NEW
CARD
POWER
JACK
X'TAL
24.576M
P37
P37
2
TI PCI7411
288 PBGA
( PCMCIA+1394
+Cardreader )
+3V
3VSUS+3V
5VSUS
+1.5V
INTA/B/C
REQ0 AD16
GNT0
AD25
3 in 1 Cardreader
Socket
CARDBUS
Slot
type I X II
1394
Conn.
P29
Size Document Number Rev
Date: Sheet
P28
RELTEK
RTL8100CL(10/100M)
RTL8110SB(1G)
X'TAL
25M
LANVCC3
LANVCC18
LANVCC10
P29
P28
PROJECT : EF6
Quanta Computer Inc.
Block Diagram
INTD
REQ2
GNT2
P26
RJ45
P27
137Monday, January 03, 2005
1
of
1ACustom
5
+3V
D D
+3V
C C
L57
ACB2012L-120
120 ohms@100Mhz
L63
ACB2012L-120
120 ohms@100Mhz
CLKVDD
C358
0.047U
R277 2.2
R322 2.2
R326 1
CLK_VDDA
CLKVDD1
CLK_VDD48
CLK_VDDREF
C373
0.047U
C405
0.047U
C368
0.047U
C372
0.047U
C436
0.047U
C409
0.047U
C383
0.047U
C378
4.7U/10V
C452
4.7U/10V
C387
4.7U/10V
C404
0.047U
C375
0.047U
C369
0.01U
FSC FSB FSA CPU SRC PCI
1 0 1 100 100 33
0 0 1 133 100 33
0 1 1 166 100 33
0 1 0 200 100 33
0 0 0 266 100 33
1 0 0 333 100 33
1 1 0 400 100 33
1 1 1 RESERVED
B B
* Frequence select by CPU auto s e n s e .
+3V
VCCP
VCCP
4
Place these termination to close
ICS954226
C111
20P
C109
20P
CLK_EN#35
STP_PCI#15
STP_CPU#15,35
CLK48_USB15 SRC_MCH 6
CLK48_741128
CG_BSEL2
Iref=5mA,
Ioh=4*Iref
DOT965
DOT96#5
R58 22
R61 22
R319 4.7K
R74 475/F
DOT96 R_PCLK_MINI
DOT96#
C TEST modified EMI
+3V
C520
.1U/50V/X7R
C521
.1U/50V/X7R
21
RP31
1
3
Y2
14.318MHZ
33X2
CG_XIN
CG_XOUT
CLK_EN#
STP_PCI#
STP_CPU#
CGCLK_SMB
CGDAT_SMB
CG_BSEL0
CG_BSEL1
U18_FSC
CLK_VDDREF
CLKVDD
CLKVDD1
CLKVDD
CLK_VDD48
IREF
R_DOT96
2
R_DOT96#
4
C522
.1U/50V/X7R
PDAT_SMB15,37
PCLK_SMB15,37
50
49
10
55
54
46
47
12
16
53
48
42
1
7
21
28
34
11
39
14
15
ICS954226
C523
.1U/50V/X7R
3
CLK_VDDA
U12
XTAL_IN
XTAL_OUT
VTT_PWRGD#/PD
PCI_STOP#
CPU_STOP#
SCLK
SDATA
FSA/USB_48
FSB/TEST_MODE
FSC/TEST_SEL
VDD_REF
VDD_CPU
VDD_PCI_1
VDD_PCI_2
VDD_SRC0
VDD_SRC1
VDD_SRC2
VDD_48
IREF
DOT96
DOT96#
ICS954226
Q25
CH2507S
3
Q26
CH2507S
3
37
VDDA
CK-410M
GND_REF
GND_PCI_2
GND_PCI_1
GND_48
51
62945
2
13
+3V
2
+3V
2
38
VSSA
CPU0#
CPU1#
CPU2_ITP/SRC7
CPU2#_ITP/SRC7#
SRC6#
SRC5#
SRC4#
SRC3#
SRC2#
SRC1#
SRC0#
PCIF0/ITP_EN
GND_SRC
GND_CPU
250mA ( MAX. )
SMbus address D2
R330
10K
1
1
REF
CPU0
CPU1
SRC6
SRC5
SRC4
SRC3
SRC2
SRC1
SRC0
PCI5
PCI4
PCI3
PCI2
PCIF1
VCCP9,16,31,36
+3V10,12,13,15,16,18,21,22,23,25,26,30,33,36,37
52
44
43
41
40
36
35
33
32
31
30
26
27
24
25
22
23
19
20
17
18
R_PCLK_591
5
R_PCLK_7411
4
R_PCLK_SIO
3
56
R_PCLK_LAN
9
R_PCLK_ICH
8
R296
10K
CGDAT_SMB
CGCLK_SMB
14M_REF
RHCLK_MCH
RHCLK_MCH#
RHCLK_CPU
RHCLK_CPU#
NEWCARDCLKREQ#
RSRC_MCH
RSRC_MCH#
RSRC_SATA
RSRC_SATA#
RSRC_ICH
RSRC_ICH#
RSRC_NEW
RSRC_NEW#
RDREFSSCLK
RDREFSSCLK#
RP30
RP32
RP35
RP37
RP36
RP34
RP33
+3V
CGDAT_SMB 10
CGCLK_SMB 10
2
R54 12.1/F
R57 12.1/F
1
3
1
3
1
3
3
1
3
1
3
1
3
1
R46 33
R42 33
R38 33
R48 33
R56 33
R50 33
R43
10K
2
4
33X2
2
4
33X2
2
4
33X2
4
2
33X2
4
2
33X2
4
2
*33X2
4
2
33X2
14M_SIO 30
14M_ICH 15
HCLK_MCH 5
HCLK_MCH# 5
HCLK_CPU 3
HCLK_CPU# 3
NEWCARDCLKREQ# 37
SRC_MCH# 6
SRC_SATA 14
SRC_SATA# 14
SRC_ICH 15
SRC_ICH# 15
CLK_PCIE_NEWC 37
CLK_PCIE_NEWC# 37
DREFSSCLK 5
DREFSSCLK# 5
PCLK_591 22
PCLK_7411 28
PCLK_SIO 30
PCLK_MINI 25
PCLK_LAN 26
PCLK_ICH 14
R_PCLK_ICH
R_PCLK_LAN
HCLK_MCH
HCLK_MCH#
HCLK_CPU
HCLK_CPU#
SRC_MCH
SRC_MCH#
SRC_ICH
SRC_ICH#
CLK_PCIE_NEWC
CLK_PCIE_NEWC#
DREFSSCLK
DREFSSCLK#
DOT96
DOT96#
SRC_SATA
SRC_SATA#
R_PCLK_LAN
( 48 MHz )
CLK48_USB
CLK48_7411
( 33 MHz )
PCLK_SIO
PCLK_LAN
PCLK_MINI
PCLK_ICH
PCLK_7411
PCLK_591
( 14 MHz )
14M_SIO
14M_ICH
1
R327 10K
R311 10K
R60 49.9/F
R65 49.9/F
R69 49.9/F
R72 49.9/F
R82 49.9/F
R91 49.9/F
R92 49.9/F
R94 49.9/F
R79 *49.9/F
R83 *49.9/F
R73 49.9/F
R75 49.9/F
R66 49.9/F
R70 49.9/F
R96 49.9/F
R99 49.9/F
R316 *10K
C140 *10P
C144 *10P
C112 *10P
C137 *10P
C126 *10P
C127 *10P
C122 *10P
C125 *10P
C136 *10P
C139 *10P
02
+3V
R288
R302
10K
SELPSB1_CLK3
A A
SELPSB0_CLK3
R281 0
R301 0
5
R294
*10K
*1K
R289
*0
R310
*1K
CG_BSEL0
CG_BSEL1
CG_BSEL2
R318
*0
R282 1K
R293 1K
MCH_BSEL1 5
MCH_BSEL2 5
4
Size Document Number Rev
Custom
3
2
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
CLOCK GENERATOR
1
of
237Monday, January 03, 2005
1A
A
B
C
D
E
R297
200
C162
0.1U
03
CPUPWRGD 14
THERMDA
C161
2200P
THERMDC
HD#[0..63]
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
T84
T23
T80
T9
T104
T20
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
PM_PSI#
SELPSB0_CLK
SELPSB1_CLK
H_GTLREF
THCLK_SMB
THDAT_SMB
6648_ALERT#
SYS_SHDN#
HDSTBN0#
HDSTBP0#
HD#[0..63]
HDSTBN1#
HDSTBP1#
Layout note: 0.5" max length.
R23
2K/F
THCLK_SMB22
THDAT_SMB22
6648_ALERT#22
SYS_SHDN#33
A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
C23
C22
D25
H23
G25
L23
M26
H24
F25
G24
M23
L26
N24
M25
H26
N25
K25
K24
L24
C16
C14
AF7
AC1
E26
AD26
J23
J25
J26
E1
B2
C3
U10B
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#
PSI#
BSEL0
BSEL1
RSVD
RSVD
RSVD
RSVD
RSVD
GTLREF
Dothan_478P
2
DATA GRP
0
3
DATA GRP
1
MISC
RSVD/DPRSTP#
+3V
R98
10K
D32#
D33#
D34#
D35#
DATA GRP
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
DSTBN2#
DSTBP2#
DINV2#
D48#
D49#
D50#
D51#
DATA GRP
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DSTBN3#
DSTBP3#
DINV3#
COMP0
COMP1
COMP2
COMP3
DPSLP#
DPWR#
PWRGOOD
SLP#
TEST1
TEST2
R95
10K
R93
10K
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
W25
W24
T24
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26
AE24
AE25
AD20
P25
P26
AB2
AB1
G1
B7
C19
E4
A6
C5
F23
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
COMP0
COMP1
COMP2
COMP3
DPWR#
CPUPWRGD
H_TEST1
H_TEST2
R63
*1K
R100 200
R85
*10K
VCCP
HD#[0..63]5
HDSTBN0#5
HDSTBP0#5
HDSTBN1#5
HDSTBP1#5
DINV#15
SELPSB0_CLK2
SELPSB1_CLK2
R24 1K/F
DINV#05
AA3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1
AE5
P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
Y3
U3
R2
P3
T2
P1
T1
C2
D3
A3
C6
D1
D4
B4
U10A
A3#
A4#
ADDR GROUP
0
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
ADSTB#0
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
A17#
A18#
ADDR GROUP
1
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB#1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
Dothan_478P
TDI
TMS
TDO
CPURST#
TCK
TRST#
PREQ#
THRMTRIP#_1
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROLXTP/ITP
RESET#
RS0#
RS1#
RS2#
TRDY#
HIT#
HITM#
BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
SIGNALS
DBR#
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
THERMH CLK
ITP_CLK1
ITP_CLK0
BCLK1
BCLK0
R106 150
R104 39.2
R107 *54.9
R105 54.9
R109 27.4
R108 680
R103 56
R115 *56
N2
L1
J3
L4
H2
M2
N4
A4
B5
J2
B11
H1
K1
L2
M3
K3
K4
C8
B8
A9
C9
A10
B10
A13
C12
A12
C11
B13
A7
B17
B18
A18
C17
A15
A16
B14
B15
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
HBREQ0#
IERR#
CPUINIT#
HLOCK#
CPURST#
RS#0
RS#1
RS#2
HTRDY#
HIT#
HITM#
BPM#0HA#19
BPM#1HA#20
BPM#2HA#21
BPM#3HA#22
PRDY#
PREQ#HA#24
TCK
TDI
TDO
TMS
TRST#
DBR#
CPU_PROCHOT#
THERMDA
THERMDC
THRMTRIP#_1
HCLK_CPU#
HCLK_CPU
VCCP
VCCP
ADS# 5
BNR# 5
BPRI# 5
DEFER# 5
DRDY# 5
DBSY# 5
HBREQ0# 5
CPUINIT# 14
HLOCK# 5
CPURST# 5
RS#0 5
RS#1 5
RS#2 5
HTRDY# 5
HIT# 5
HITM# 5
T26
T27
T28
T70
T29
DBR# 15
R110
0
T24
T25
HCLK_CPU# 2
HCLK_CPU 2
VCCP
R101
56
VCCP
R114
56
THRMTRIP# 5,14
HA#[3..31]5
4 4
HADSTB0#5
HREQ#05
HREQ#15
HREQ#25
HREQ#35
HREQ#45
3 3
HADSTB1#5
2 2
HA#[3..31]
HA#[3..31]
A20M#14
FERR#14
IGNNE#14
STPCLK#14
INTR14
NMI14
SMI#14
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HADSTB0#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HA#17
HA#18
HA#23
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HADSTB1#
A20M#
FERR#
IGNNE#
STPCLK#
INTR
NMI
HDSTBN2#
HDSTBP2#
HDSTBN3#
HDSTBP3#
R55 27.4
R51 54.9
R345 27.4
R346 54.9
R102
*1K
U14
8
SCLK
7
SDA
6
ALERT#
4
OVERT#
HD#[0..63]
HDSTBN2# 5
HDSTBP2# 5
HD#[0..63]
H_DPRSTP# 14
H_DPSLP# 14
DPWR# 5
H_CPUSLP# 5,14
DINV#2 5
HDSTBN3# 5
HDSTBP3# 5
DINV#3 5
VCCP
CPUSLP#
1.connected between Dothan and
ICH6 for Dothen A Stepping.
2.connected between Dothan and
Alviso for Dothen B Stepping.
6648VCC
1
VCC
2
DXP
3
DXN
5
GND
1 1
A
+3V10,12,13,15,16,18,21,22,23,25,26,30,33,36,37
VCCP9,16,31,36
Size Document Number Rev
Custom
B
C
D
Date: Sheet
G781P8/MAX6648MUA
PROJECT : EF6
Quanta Computer Inc.
Dothan CPU (Host Bus)
337Monday, January 03, 2005
E
1A
of
A
CPU_CORE CPU_CORE
U10C
AA11
VCC0
AA13
VCC1
AA15
VCC2
AA17
VCC3
AA19
4 4
3 3
2 2
AA21
AA5
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC9
AD10
AD12
AD14
AD16
AD18
AD8
AE11
AE13
AE15
AE17
AE19
AE9
AF10
AF12
AF14
AF16
AF18
AF8
D18
D20
D22
E17
E19
E21
F18
F20
F22
G21
D6
D8
E5
E7
E9
F6
F8
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
Dothan_478P
VCCA1/RSVD
VCCA2/RSVD
VCCA3/RSVD
VCCSENSE
VSSSENSE
CPU_CORE
C397
C391
0.1U
C400
0.1U
C392
0.1U
0.1U
1 1
CPU_CORE
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCCA0
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCQ0
VCCQ1
VID0
VID1
VID2
VID3
VID4
VID5
C467
0.1U
G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6
F26
B1
N1
AC26
D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21
P23
W4
E2
F2
F3
G3
G4
H4
TP_VCCSENSE
AE7
TP_VSSSENSE
AF6
CPU_CORE
CPU_CORE
TP_VCCA1
TP_VCCA2
TP_VCCA3
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
R349
*54.9
C505
0.1U
CPU_VCCA
C503
0.1U
T75
T99
T10
CPU_VID0 35
CPU_VID1 35
CPU_VID2 35
CPU_VID3 35
CPU_VID4 35
CPU_VID5 35
R347
*54.9
C398
0.1U
C146
0.01U
VCCP
B
C390
0.1U
C149
10U
C466
0.1U
CPU_VCCA
+
CPU_CORE
C469
10U
C429
10U
C135
10U
C472
10U
C165
150U
+
C499
330U
CPU_CORE
C107
10U
CPU_CORE
C428
10U
CPU_CORE
C101
10U
CPU_CORE
C473
10U
C394
0.1U
C147
0.1U
C468
10U
C423
10U
C426
10U
C474
10U
R84 0
R81 *0
C461
C393
0.1U
0.1U
+
C500
*270U
C132
10U
C119
10U
C471
10U
C118
10U
+
C
C498
*270U
C131
10U
C115
10U
C424
10U
C117
10U
C445
0.1U
+1.5V
+1.8V
C444
0.1U
C105
10U
C114
10U
C130
10U
D
VCCPVCCP
C463
0.1U
C450
0.1U
CPU_CORE35,36
C395
0.1U
VCCP9,16,31,36
+1.5V15,16,31,36,37
+1.8V36
C458
0.1U
C396
0.1U
CPU_CORE
C106
10U
C129
10U
C427
10U
C470
10U
CPU_CORE
C113
C116
10U
10U
C425
10U
C102
10U
CPU_CORE
C104
10U
C133
10U
C103
10U
C134
10U
A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24
B12
B16
B19
B22
B25
C10
C13
C15
C18
C21
C24
D11
A2
A5
A8
B3
B6
B9
C1
C4
C7
D2
D5
D7
D9
U10D
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
Dothan_478P
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
E
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
04
C430
0.1U
C399
C504
C502
0.1U
0.1U
A
0.1U
C496
0.1U
C418
0.1U
C497
0.1U
C495
0.1U
0.1U
B
0.1U
Size Document Number Rev
Custom
C
D
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
Dothan CPU (Power)
E
of
437Monday, January 03, 2005
1A
C501
C494
5
E4
E1
F4
H7
E2
F1
E3
D3
K7
F2
J7
J8
H6
F3
K8
H5
H1
H2
K5
K6
J4
G3
H3
J1
L5
K4
J5
P7
L7
J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6
W6
U3
V5
W8
W7
U2
U1
Y5
Y2
V4
Y7
W1
W3
Y3
Y6
W2
C1
C2
D1
T1
L1
P1
U9A
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HADSTB0#
HADSTB1#
HCPURST#
HOST
HDEFER#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HEDRDY#
HPCREQ#
HCPUSLP#
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HADS#
HVREF
HBNR#
HBPRI#
BREQ0#
HCLKINN
HCLKINP
HDBSY#
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#
HDRDY#
HHIT#
HHITM#
HLOCK#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HRS0#
HRS1#
HRS2#
HTRDY#
ALVISO
HD#[0..63]3
D D
C C
B B
HD#[0..63]
HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13
F8
B9
E13
J11
A5
D5
E7
H10
AB1
AB2
C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4
G8
B5
4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
ADS#
HADSTB0#
HADSTB1#
HVREF
BNR#
BPRI#
HBREQ0#
CPURST#
HCLK_MCH#
HCLK_MCH
DBSY#
DEFER#
DINV#0
DINV#1
DINV#2
DINV#3
DPWR#
DRDY#
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
HIT#
HITM#
HLOCK#
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
RS#0
RS#1
RS#2
HCPUSLP#
HTRDY#
HA#[3..31]
HA#[3..31] 3
ADS# 3
HADSTB0# 3
HADSTB1# 3
BNR# 3
BPRI# 3
HBREQ0# 3
CPURST# 3
HCLK_MCH# 2
HCLK_MCH 2
DBSY# 3
DEFER# 3
DINV#0 3
DINV#1 3
DINV#2 3
DINV#3 3
DPWR# 3
DRDY# 3
HDSTBN0# 3
HDSTBN1# 3
HDSTBN2# 3
HDSTBN3# 3
HDSTBP0# 3
HDSTBP1# 3
HDSTBP2# 3
HDSTBP3# 3
HIT# 3
HITM# 3
HLOCK# 3
HREQ#0 3
HREQ#1 3
HREQ#2 3
HREQ#3 3
HREQ#4 3
RS#0 3
RS#1 3
RS#2 3
HTRDY# 3
VCCP
R335
100/F
R332
200/F
T79
T22
R44 0
SMDDR_VREF10,32
1.8VSUS8,9,10,36
VCCP9,16,31,36
C442
0.1U
SMDDR_VREF
should be populated
to support Dothan B
stepping.
3
L71 BK2125HS121
1 2
1 2
L72 BK2125HS121
H_CPUSLP# 3,14
T108
T105
T110
T107
T113
T111
C577
0.1U
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
CLK_SDRAM0
CLK_SDRAM1
CLK_SDRAM2
CLK_SDRAM3
CLK_SDRAM4
CLK_SDRAM5
CLK_SDRAM0#
CLK_SDRAM1#
CLK_SDRAM2#
CLK_SDRAM3#
CLK_SDRAM4#
CLK_SDRAM5#
CKE0
CKE1
CKE2
CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
M_OCDCOMP0
M_OCDCOMP1
M_ODT0
M_ODT1
M_ODT2
M_ODT3
M_RCOMPN
M_RCOMPP
SMXSLEW
SMYSLEW
It's point to point, 55ohm trace,
keep as short as possible.
DMI_TXN015
DMI_TXN115
DMI_TXN215
DMI_TXN315
DMI_TXP015
DMI_TXP115
DMI_TXP215
DMI_TXP315
DMI_RXN015
DMI_RXN115
DMI_RXN215
DMI_RXN315
DMI_RXP015
DMI_RXP115
DMI_RXP215
DMI_RXP315
CLK_SDRAM010
CLK_SDRAM110
CLK_SDRAM310
CLK_SDRAM410
CLK_SDRAM0#10
CLK_SDRAM1#10
CLK_SDRAM3#10
CLK_SDRAM4#10
CKE010,11
CKE110,11
CKE210,11
CKE310,11
SM_CS0#10,11
SM_CS1#10,11
SM_CS2#10,11
SM_CS3#10,11
M_ODT010,11
M_ODT110,11
M_ODT210,11
M_ODT310,11
C576
0.1U
C TEST modified EMI
AA31
AB35
AC31
AD35
AA35
AB31
AC35
AA33
AB37
AC33
AD37
AA37
AB33
AC37
AM33
AE11
AJ34
AF6
AC10
AN33
AK1
AE10
AJ33
AF5
AD10
AP21
AM21
AH21
AK21
AN16
AM14
AH15
AG16
AF22
AF16
AP14
AL15
AM11
AN10
AK10
AK11
AF37
AD1
AE27
AE28
AF9
AF10
Y31
Y33
AL1
2
U9C
DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3
DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3
DMITXN0
DMITXN1
DMITXN2
DMITXN3
DMITXP0
DMITXP1
DMITXP2
DMITXP3
SM_CK0
SM_CK1
SM_CK2
SM_CK3
SM_CK4
SM_CK5
SM_CK0#
SM_CK1#
SM_CK2#
SM_CK3#
SM_CK4#
SM_CK5#
SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3
SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#
SM_OCDCOMP0
SM_OCDCOMP1
SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3
SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT
1
VCCP
R339
1K
CFG0
G16
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG14
DMIDDR MUXING
CFG15
CFG16
CFG17
CFG18
CFG19
CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
CFG/RSVDPMLCKNC
RSVD26
RSVD27
BM_BUSY#
EXT_TS0#
EXT_TS1#
THRMTRIP#
PWROK
RSTIN#
DREF_CLKN
DREF_CLKP
DREF_SSCLKN
DREF_SSCLKP
ALVISO
Note :
a). DREF_CLKN , DREF_CLKP
Display Clock Frequency at 96MHz ( CRT,SDVO an d T VOU T )
b). DREF_SSCLKN , DREF_SSCLKP
Display Clock Frequency (with SSC) at 96,100MHz ( LVDS)
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
MCH_BSEL1
H13
MCH_BSEL2
G14
CFG3
F16
CFG4
F15
CFG5
G15
CFG6
E16
CFG7
D17
CFG8
J16
CFG9
D15
CFG10
E15
CFG11
D14
CFG12
E14
CFG13
H12
CFG14
C14
CFG15
H15
CFG16
J15
CFG17
H14
CFG18
G22
CFG19
G23
CFG20
D23
G25
G24
CFG[2:0] ==>External Pull-ups are required.
J17
CFG[17:3] ==>has internal pull u p.
A31
CFG[20:18] ==>has internal pull up.
A30
D26
D25
R331
10K
PM_BMBUSY#
J23
PM_EXTTS#0
J21
PM_EXTTS#1
H22
R47 0
F5
AD30
R350 100
AE29
DOT96#
A24
DOT96
A23
C37
D37
TP_NC1
AP37
TP_NC2
AN37
TP_NC3
AP36
TP_NC4
AP2
TP_NC5
AP1
TP_NC6
AN1
TP_NC7
B1
TP_NC8
A2
TP_NC9
B37
TP_NC10
A36
TP_NC11
A37
MCH_BSEL1 2
MCH_BSEL2 2
+2.5V
R329
10K
DOT96# 2
DOT96 2
DREFSSCLK# 2
DREFSSCLK 2
T5
T7
T4
T2
T6
T8
T18
T21
T14
T19
T17
T102
CFG3 6
T92
CFG5 6
CFG6 6
CFG7 6
T98
CFG9 6
T82
CFG11 6
CFG12 6
CFG13 6
T85
T77
CFG16 6
T94
CFG18 6
CFG19 6
T81
PM_BMBUSY# 15
THRMTRIP# 3,14
IMVP_PWG 15,35
PLTRST# 14,15,30,37
05
1.8VSUSVCCP VCCP VCCP
4
HXSCOMP
HXRCOMP
HYSCOMP
HYRCOMP
R351
R352
40.2/F
40.2/F
Route as short
as possible.
3
M_OCDCOMP0
M_OCDCOMP1
R353
80.6/F
M_RCOMPN
M_RCOMPP
R354
80.6/F
Size Document Number Rev
Custom
2
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
Alviso Host(1/5)
1
of
537Monday, January 03, 2005
1A
R67 54.9
R59
A A
221/F
HXSWING
R303
100/F
C138
0.1U
R343
221/F
HYSWING
R344
100/F
5
C108
0.1U
R64 24.9/F
VCCP
R340 54.9
R32 24.9/F
5
TV_COMP12
TV_Y/G12
TV_C/R12
D D
CRT_COM#
CRT_BLUE
CRT_GREEN
CRT_RED
C C
B B
R292 0
R304 150/F
R291 150/F
R290 150/F
CFG165
CFG195
resistor no stuff
CFG16
Low=FSB Dynamic ODT Disabled
High=FSB Dynamic ODT Enabled
CFG19
Low=CPU VTT 1.05V
High=CPU VTT 1.2V
+2.5V
R333
*2.2K
R275
*1K
R323
*2.2K
CDDCCLK12
CDDCDATA12
CRT_B_COM12
CRT_G_COM12
CRT_R_COM12
VSYNC_COM12
HSYNC_COM12
BLON13
LDDC_CLK13
LDDC_DATA13
DISP_ON13
CFG95CFG55
4
T95
T97
SRC_MCH#2
SRC_MCH2
TV_COMP
TV_Y/G
TV_C/R
R88 150/F
R86 150/F
R87 150/F
C TEST Modified
CDDCCLK
CDDCDATA
CRT_B_COM CRT_BLUE
+2.5V
CFG9
VSYNC_COM
HSYNC_COM
R306 100K
R315 100K
R314 2.2K
R309 2.2K
R307 1.5K/F
TXLCLKOUT-13
TXLCLKOUT+13
TXUCLKOUT-13
TXUCLKOUT+13
TXLOUT0-13
TXLOUT1-13
TXLOUT2-13
TXLOUT0+13
TXLOUT1+13
TXLOUT2+13
TXUOUT0-13
TXUOUT1-13
TXUOUT2-13
TXUOUT0+13
TXUOUT1+13
TXUOUT2+13
R300
*2.2K
R279 39
R280 39
R336 255/F
H24
SRC_MCH#
SRC_MCH
TV_COMP_A
TV_Y/G_A
TV_C/R_A
R334 4.7K/F
CRT_GREENCRT_G_COM
CRT_REDCRT_R_COM
CRT_COM#
VSYNC
HSYNC
REFSET
T78
T83
T86
T90
T88
TLCO-_1
TLCO+_1
TUCO-_1
TUCO+_1
TLO0-_1
TLO1-_1
TLO2-_1
TLO0+_1
TLO1+_1
TLO2+_1
TUO0-_1
TUO1-_1
TUO2-_1
TUO0+_1
TUO1+_1
TUO2+_1
CFG125
CFG135 CFG65
H25
AB29
AC29
A15
C16
A17
J18
B15
B16
B17
E24
E23
E21
D21
C20
B20
A19
B19
H21
G21
J20
E25
F25
C23
C22
F23
F22
F26
C33
C31
F28
F27
B30
B29
C25
C24
B34
B33
B32
A34
A33
B31
C29
D28
C27
C28
D27
C26
CFG12
CFG13
U9F
SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP
TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC
DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET
LBKLT_CTRL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL
LACLKN
LACLKP
LBCLKN
LBCLKP
LADATAN0
LADATAN1
LADATAN2
LADATAP0
LADATAP1
LADATAP2
LBDATAN0
LBDATAN1
LBDATAN2
LBDATAP0
LBDATAP1
LBDATAP2
R313
R328
*2.2K
*2.2K
3
EXP_COMP
EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9
EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
ALVISO
D36
D34
E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34
D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34
E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36
D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36
MISC
EXP_COMPI
EXP_ICOMPO
TV VGA LVDS
EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15
EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15
PCI-EXPRESS GRAPHICS
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15
2
R62 24.9/F
VCC3G_PCIE
+2.5V5,8,12,13,16,32,36
VCC3G_PCIE8
VCCP9,16,31,36
ALVISO POWER STRAP PIN define
CFG[2:0] : 001=FSB533
101=FSB400
other = Reserved
CFG[4:3] : Reserved
CFG5 : 0=DMI X 2
1=DMI X 4 ( Default )
CFG6 : 0=DDR2
1=DDR ( Default )
CFG7 : 0=Reserved
1=Dothan ( Default )
CFG8 : Reserved
CFG9 : 0=Reserve Lanes (15->0, 14->1 etc)
1=Normal Operation ( Default )
CFG[11:10] : Reserved
CFG[13:12] : 00=Reserved
01=XOR Mode Enabled
10=All Z Mode Enabled
11=Normal Operation ( Default )
CFG[15:14] : Reserved
CFG16 : 0=Dynamic ODT Disabled
1=Dynamic ODT Enabled ( Default )
CFG17 : Reserved
CFG18 : 0=1.05V ( Default )
1
06
1=1.5V
CFG6
R308
2.2K
CFG19 : 0 =1.05V ( Default )
1=1.2V ( Reserved )
CFG 20 : Reserved
Low=DMIx2
High=DMIx4
CFG7
CFG75
A A
5
R299
*2.2K
Low=Reserved
High=Dothan
CFG185
PCI-E Graphics Lane
Low = Reverse Lane
High = Normal Operation
+2.5V
R276
*1K
CFG18
Low=CPU core VCC 1.05V
High=CPU core VCC 1.5V
4
CFG115
00 : Reserved
01 : XOR Mode Enabled
10 : All Z Mode Enabled
11 : Normal Operation
CFG11
R298
*2.2K
Low=FSB533
CFG35
3
Low=DDR II
High=DDR
CFG3
Low=DDR533
R321
*2.2K
SDVOCRTL_DATA :0=No SDVO device present (Default)
1=SDVO device present
Size Document Number Rev
Custom
2
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
VGA DMI(2/5)
637Monday, January 03, 2005
1
1A
of
5
4
3
2
1
07
D D
R_B_MD[0..63]10
R_A_MD[0..63]10
C C
B B
R_A_MD[0..63]
R_A_MD0
R_A_MD1
R_A_MD2
R_A_MD3
R_A_MD4
R_A_MD5
R_A_MD6
R_A_MD7
R_A_MD8
R_A_MD9
R_A_MD10 R_B_DQS6
R_A_MD11
R_A_MD12
R_A_MD13
R_A_MD14
R_A_MD15
R_A_MD16
R_A_MD17
R_A_MD18
R_A_MD19
R_A_MD20
R_A_MD21
R_A_MD22
R_A_MD23
R_A_MD24
R_A_MD25
R_A_MD26
R_A_MD27
R_A_MD28
R_A_MD29
R_A_MD30
R_A_MD31
R_A_MD32
R_A_MD33
R_A_MD34
R_A_MD35
R_A_MD36
R_A_MD37
R_A_MD38
R_A_MD39
R_A_MD40
R_A_MD41
R_A_MD42
R_A_MD43
R_A_MD44
R_A_MD45
R_A_MD46
R_A_MD47
R_A_MD48
R_A_MD49
R_A_MD50
R_A_MD51
R_A_MD52 R_B_MD61
R_A_MD53
R_A_MD54
R_A_MD55
R_A_MD56
R_A_MD57
R_A_MD58
R_A_MD59
R_A_MD60
R_A_MD61
R_A_MD62
R_A_MD63
AG35
AH35
AL35
AL37
AH36
AJ35
AK37
AL34
AM36
AN35
AP32
AM31
AM34
AM35
AL32
AM32
AN31
AP31
AN28
AP28
AL30
AM30
AM28
AL28
AP27
AM27
AM23
AM22
AL23
AM24
AN22
AP22
AM9
AL9
AL6
AP7
AP11
AP10
AL7
AM7
AN5
AN6
AN3
AP3
AP6
AM6
AL4
AM3
AK2
AK3
AG2
AG1
AL3
AM2
AH3
AG3
AF3
AE3
AD6
AC4
AF2
AF1
AD4
AD5
U9B
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SADQ35
SADQ36
SADQ37
SADQ38
SADQ39
SADQ40
SADQ41
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
SA_BS0#
SA_BS1#
SA_BS2#
SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8
SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13
DDR SYSTEM MEMORY A
SA_CAS#
SA_RAS#
SA_RCVENIN#
SA_RCVENOUT#
SA_WE#
ALVISO
AK15
AK16
AL21
AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3
AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5
AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4
AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15
AN15
AP16
AF29
AF28
AP15
R_A_BS0#
R_A_BS1#
R_A_BS2#
R_A_DM0
R_A_DM1
R_A_DM2
R_A_DM3
R_A_DM4
R_A_DM5
R_A_DM6
R_A_DM7
R_A_DQS0
R_A_DQS1
R_A_DQS2
R_A_DQS3
R_A_DQS4
R_A_DQS5
R_A_DQS6
R_A_DQS7
R_A_DQS#0
R_A_DQS#1
R_A_DQS#2
R_A_DQS#3
R_A_DQS#4
R_A_DQS#5
R_A_DQS#6
R_A_DQS#7
R_A_MA0
R_A_MA1
R_A_MA2
R_A_MA3
R_A_MA4
R_A_MA5
R_A_MA6
R_A_MA7
R_A_MA8
R_A_MA9
R_A_MA10
R_A_MA11
R_A_MA12
R_A_MA13
R_A_SCASA#
R_A_SRASA#
R_A_BMWEA#
R_A_DM[0..7]
R_A_DQS[0..7]
R_A_DQS#[0..7]
R_A_MA[0..13]
T106
T109
R_A_BS0# 10,11
R_A_BS1# 10,11
R_A_BS2# 10,11
R_A_DM[0..7] 10
R_A_DQS[0..7] 10
R_A_DQS#[0..7] 10
R_A_MA[0..13] 10,11
R_A_SCASA# 10,11
R_A_SRASA# 10,11
R_A_BMWEA# 10,11
R_B_MD[0..63]
R_B_MD0
R_B_MD1
R_B_MD2
R_B_MD3
R_B_MD4
R_B_MD5
R_B_MD6
R_B_MD7
R_B_MD8
R_B_MD9
R_B_MD10
R_B_MD11
R_B_MD12
R_B_MD13
R_B_MD14
R_B_MD15
R_B_MD16
R_B_MD17
R_B_MD18
R_B_MD19
R_B_MD20
R_B_MD21
R_B_MD22
R_B_MD23
R_B_MD24
R_B_MD25
R_B_MD26
R_B_MD27
R_B_MD28
R_B_MD29
R_B_MD30
R_B_MD31
R_B_MD32
R_B_MD33
R_B_MD34
R_B_MD35
R_B_MD36
R_B_MD37
R_B_MD38
R_B_MD39
R_B_MD40
R_B_MD41
R_B_MD42
R_B_MD43
R_B_MD44
R_B_MD45
R_B_MD46
R_B_MD47
R_B_MD48
R_B_MD49
R_B_MD50
R_B_MD51
R_B_MD52
R_B_MD53
R_B_MD54
R_B_MD55
R_B_MD56
R_B_MD57
R_B_MD58
R_B_MD59
R_B_MD60
R_B_MD62
R_B_MD63
AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31
AJ31
AK30
AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23
AJ22
AK22
AH24
AH23
AG22
AJ21
AG10
AG9
AG8
AH8
AH11
AH10
AK9
AK6
AH5
AK8
AK4
AG5
AG4
AD8
AD9
AH4
AG6
AE8
AD7
AC5
AB8
AB6
AA8
AC8
AC7
AA4
AA5
U9G
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37
AJ9
SBDQ38
SBDQ39
AJ7
SBDQ40
SBDQ41
AJ4
SBDQ42
SBDQ43
SBDQ44
AJ8
SBDQ45
AJ5
SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
SB_BS0#
SB_BS1#
SB_BS2#
SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7
SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7
SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#
SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8
SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
DDR SYSTEM MEMORY B
SB_CAS#
SB_RAS#
SB_RCVENIN#
SB_RCVENOUT#
SB_WE#
ALVISO
AJ15
AG17
AG21
AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7
AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4
AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5
AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15
AH14
AK14
AF15
AF14
AH16
R_B_BS0#
R_B_BS1#
R_B_BS2#
R_B_DM0
R_B_DM1
R_B_DM2
R_B_DM3
R_B_DM4
R_B_DM5
R_B_DM6
R_B_DM7
R_B_DQS0
R_B_DQS1
R_B_DQS2
R_B_DQS3
R_B_DQS4
R_B_DQS5
R_B_DQS7
R_B_DQS#0
R_B_DQS#1
R_B_DQS#2
R_B_DQS#3
R_B_DQS#4
R_B_DQS#5
R_B_DQS#6
R_B_DQS#7
R_B_MA0
R_B_MA1
R_B_MA2
R_B_MA3
R_B_MA4
R_B_MA5
R_B_MA6
R_B_MA7
R_B_MA8
R_B_MA9
R_B_MA10
R_B_MA11
R_B_MA12
R_B_MA13
R_B_SCASA#
R_B_SRASA#
R_B_BMWEA#
R_B_DM[0..7]
R_B_DQS[0..7]
R_B_DQS#[0..7]
R_B_MA[0..13]
T114
T112
R_B_BS0# 10,11
R_B_BS1# 10,11
R_B_BS2# 10,11
R_B_DM[0..7] 10
R_B_DQS[0..7] 10
R_B_DQS#[0..7] 10
R_B_MA[0..13] 10,11
R_B_SCASA# 10,11
R_B_SRASA# 10,11
R_B_BMWEA# 10,11
A A
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
ALVISO DDR(3/5)
1
of
737Monday, January 03, 2005
1A
5
VCCP
C464
2.2U
D D
C475
4.7U/10V
+2.5V
VCCP
D14
2 1
CH751H-40H
R89 10
4
L10 BLM11A121S
C408
0.1U
VCCA_CRTDAC
C417
0.022U
VVSA_CRTDAC
C481
0.1U
VCCA_MPLL
L66 1uH
+
C485
470U
3
+1.5V
C479
0.1U
L64 1uH
+
C465
470U
+1.5V
2
+1.5V15,16,31,36,37
VCCP9,16,31,36
+3V10,12,13,15,16,18,21,22,23,25,26,30,33,36,37
1
08
C128
0.22U
C C
VCCP_GMCH_CAP4
G1
VTT51
VTT49
VTT50
C95
0.22U
VCCP_GMCH_CAP3
VTT48
VCCP_GMCH_CAP2
VTT47
VTT45
VTT46
C157
0.47U/10V
VTT42
VTT43
VTT44
VTT40
VTT41
VCCP_GMCH_CAP1
VTT38
VTT39
C158
0.47U
VTT37
VTT35
VTT36
VTT34
VTT32
VTT33
VTT30
VTT31
VTT28
VTT29
VCCP
VTT27
VTT25
VTT26
L60 BLM11A121S
+2.5V
N10
M10
K10
J10Y9W9U9R9P9N9M9L9J9N8M8N7M7N6M6A6N5M5N4M4N3M3N2M2B2V1N1M1
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
P10
VTT18
R10
VTT17
T10
VTT16
U10
VTT15
V10
VTT14
W10
VTT13
K11
VTT12
L11
VTT11
M11
VTT10
N11
P11
VTT9
R11
VTT8
T11
VTT7
C361
10U
U11
VTT6
V11
VTT5
VTT4
W11
VTT3
VCC_SYNC
C432
0.1U
K13
J13
K12
VTT0
VTT1
VTT2
H20
F19
E19
G19
VCC_SYNC
VVSSA_CRTDAC
VCCA_CRTDAC1
VCCA_DPLLB
C389
0.1U
VCCA_DPLLA
+1.5V
J25
K24
K23
K22
K21
W20
U20
T20
K20
V19
U19
K19
W18
V18
T18
K18
K17
AC1
AC2
C35
B23
AA1
AA2
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLB
VCCA_DPLLA
VCCH_MPLL0
VCCA_CRTDAC0
VCCH_MPLL1
POWER
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37
VCCSM38
VCCSM39
VCCSM40
VCCSM41
VCCSM42
VCCSM43
VCCSM44
VCCSM45
VCCSM46
VCCSM47
VCCSM48
VCCSM49
VCCSM50
VCCSM51
VCCSM52
VCCSM53
VCCSM54
VCCSM55
VCCSM56
VCCSM57
VCCSM58
VCCSM59
VCCSM60
VCCSM61
VCCSM62
VCCSM63
VCCSM64
VCCTX_LVDS0
VCCTX_LVDS1
VCCTX_LVDS2
VCCA_SM0
VCCA_SM1
VCCA_SM2
VCCA_SM3
VCC3G0
VCC3G1
VCC3G2
VCC3G3
VCC3G4
VCC3G5
VCC3G6
VCCA_3GPLL0
VCCA_3GPLL1
VCCA_3GPLL2
VCCA_3GBG
VSSA_3GBG
AL26
AK26
AJ26
AH26
AG26
AF26
AE26
AP25
AN25
AM25
AL25
AK25
AJ25
AH25
AG25
AF25
AE25
AE24
AE23
AE22
AE21
AE20
AE19
AE18
AE17
AE16
AE15
AE14
AP13
AN13
AM13
AL13
AK13
AJ13
AH13
AG13
AF13
AE13
AP12
AN12
AM12
AL12
AK12
AJ12
AH12
AG12
AF12
AE12
AD11
AC11
AB11
AB10
AB9
AP8
AM1
AE1
B28
A28
A27
AF20
AP19
AF19
AF18
AE37
W37
U37
R37
N37
L37
J37
Y29
Y28
Y27
F37
G37
C362
4.7U/10V
V1.8_DDR_CAP6
V1.8_DDR_CAP3
V1.8_DDR_CAP4
+2.5V
C83
0.1U
C79
0.1U
C85
0.1U
Note: All VCCSM pins
shorted internally.
+
C75
330uF
C80
10U
1.8VSUS
C77
10U
C81
0.1U
V1.8_DDR_CAP5
VCC3G_PCIE
B B
+2.5V
VCCA_3GPLL
C386
0.1U
VCC_DDRDLL
C382
0.1U
K25
VCC32
VCCSM9
AM26
0.1U
VCC31
VCCSM8
H26
VCC30
VCCSM7
AN26
+
K26
VCC29
VCCSM6
AP26
H27
VCC28
VCCSM5
AC27
V1.8_DDR_CAP2
L62 10uH
C421
470U
C156
0.1U
N27
M27
L27
K27
J27
VCC23
VCC24
VCC25
VCC26
VCC27
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
AM37
AH37
AP29
AD28
AD27
V1.8_DDR_CAP1
C82
0.1U
P27
R27
VCC22
A21
VCC21
VCCHV2
L11 10uH
+
C160
470U
G28
V27
U27
T27
VCC17
VCC18
VCC19
VCC20
VCCA_LVDS
VCCHV0
VCCHV1
A35
B22
B21
H28
J28
VCC16
A25
+1.5V
K28
VCC15
VCCD_LVDS2
B25
L28
VCC14
VCCD_LVDS1
B26
M28
VCC13
VCCD_LVDS0
N28
VCC12
H17
P28
VCC11
VCCDQ_TVDAC
D19
R28
VCC10
VCCD_TVDAC
VCC9
+1.5V
V28
U28
T28
VCC6
VCC7
VCC8
VCCA_TVBG
VSSA_TVBG
H18
G18
VCCA_TVBG
K29
J29
VCC5
VCCA_TVDACC1
F18
E18
C438
0.022U
M29
VCC4
VCCA_TVDACC0
C18
C388
0.022U
VCC3
VCCA_TVDACB1
N29
D18
R29
VCC2
VCCA_TVDACB0
E17
C407
0.022U
VCC1
VCCA_TVDACA1
T29
VCC0
VCCA_TVDACA0
F17
C366
0.1U
U9H
ALVISO
C401
0.1U
L58 BLM11A121SC487
C420
0.1U
C431
0.022U
C478
0.1U
C462
0.1U
D33
CH751H-40H
C416
0.1U
VCCA_TVDAC
C454
C451
0.1U
10U
+1.5V +3V
21
R90
10
R278
0
C446
10U
VCCP
C476
10U
Note: All VCCSM pins
shorted internally.
+1.5V
3
C379
0.1U
+2.5V
C141
10U
+2.5V +1.5V
C380
C381
0.01U
0.1U
BLM11A121S
+
C121
220U
L5
L8
BLM11A121S
VCCA_3GPLL
C480
0.1U
A A
R348 0.5/F
C477
10U
5
L65
BLM11A121S
+1.5V +1.5V
VCC_DDRDLL
VCC3G_PCIE
4
C76
C96
10U
C484
0.1U
VCC3G_PCIE
C100
10U
+
100U
C482
0.1U
VCCD_TVDAC
C402
0.022U
VCCDQ_TVDAC
C437
0.022U
C88
10U
2
L59 BLM11A121S
C367
0.1U
L61 BLM11A121S
C365
0.1U
Size Document Number Rev
Custom
Date: Sheet
+1.5V
+1.5V
PROJECT : EF6
Quanta Computer Inc.
Alviso Power(4/5)
1
1A
of
837Monday, January 03, 2005
5
4
3
2
1
09
D D
AF23
H23
AL22
AH22
J22
E22
D22
A22
AN21
AF21
F21
C21
AK20
V20
G20
F20
E20
D20
A20
AN19
AG19
W19
T19
J19
H19
C19
AL18
U18
B18
A18
AN17
AJ17
AF17
G17
C17
AL16
K16
H16
D16
A16
K15
C15
AN14
AL14
AJ14
AG14
K14
J14
F14
B14
A14
J12
D12
B12
AN11
AL11
AJ11
AG11
AF11
AA11
Y11
H11
F11
AA10
Y10
L10
D10
AN9
AH9
AE9
AC9
AL5W5E5
AN4
B36
C C
AL24J2G2D2Y1
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSSALVDS
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
H29
G29
F29
E29
D29
A29
AC28
AB28
AA28
W28
E28
AN27
AL27
AJ27
AG27
AF27
AB27
AA27
W27
G27
E27
AJ24
AG24
J24
F24
D24
B24
AJ3
AC3
AB3
AA3C3A3
AN2
AL2
AH2
AE2
AD2V2T2P2L2
B27
J26
G26
E26
A26
AN24
AF4Y4U4P4L4H4C4
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
C30
AM29
AJ29
AG29
AD29
AA29
W29
V29
U29
P29
L29
AA6T6P6L6J6B6AP5
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
V31
U31
T31
R31
P31
N31
M31
L31
K31
J31
H31
G31
F31
E31
D31
AP30
AE30
AC30
AB30
AA30
Y30
AK7
AG7
AA7V7G7
AJ6
AE6
AC6
AA9V9T9K9H9A9AL8Y8P8L8E8C8AN7
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
U9E
ALVISO
VSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
AG37
Y37
V37
T37
P37
M37
K37
H37
E37
AN36
AL36
AJ36
AF36
AE36
AD36
AC36
AB36
AA36
C36
AE35
Y35
W35
V35
U35
T35
R35
P35
N35
M35
L35
K35
J35
H35
G35
F35
E35
D35
B35
AN34
AH34
AD34
AC34
AB34
AA34
C34
AL33
AF33
AD33
W33
V33
U33
T33
R33
P33
N33
M33
L33
K33
J33
H33
G33
F33
E33
D33
AN32
AJ32
AD32
AC32
AB32
AA32
Y32
C32
A32
AL31
AG31
AD31
W31
VCCP
U9D
W13
V13
U13
T13
R13
P13
N13
M13
L13
W12
V12
U12
T12
R12
P12
N12
M12
VSS_NCTF0
L12
VTT_NCTF17
VTT_NCTF16
VTT_NCTF15
VTT_NCTF14
VTT_NCTF13
VTT_NCTF12
VTT_NCTF11
VTT_NCTF10
VTT_NCTF9
VTT_NCTF8
VTT_NCTF7
VTT_NCTF6
VTT_NCTF5
VTT_NCTF4
VTT_NCTF3
VTT_NCTF2
VTT_NCTF1
VTT_NCTF0
AB26
AA26
Y26
AB25
AA25
Y25
AB24
AA24
Y24
AB23
AA23
Y23
AB22
AA22
Y22
AB21
AA21
Y21
R21
AB20
AA20
AB19
AA19
AB18
AA18
AB17
AA17
Y17
R17
AB16
AA16
Y16
W16
V16
U16
T16
R16
P16
N16
M16
L16
AB15
AA15
Y15
W15
V15
U15
T15
R15
P15
N15
M15
L15
AB14
AA14
Y14
W14
V14
U14
T14
R14
P14
N14
M14
L14
AA13
Y13
AA12
Y12
B B
VSS_NCTF13
VSS_NCTF14
VSS_NCTF15
VSS_NCTF16
VSS_NCTF17
VSS_NCTF18
VSS_NCTF19
VSS_NCTF20
VSS_NCTF21
VSS_NCTF22
VSS_NCTF23
VSS_NCTF24
VSS_NCTF25
VSS_NCTF26
VSS_NCTF27
VSS_NCTF28
VSS_NCTF29
VSS_NCTF30
VSS_NCTF31
VSS_NCTF32
VSS_NCTF33
VSS_NCTF34
VSS_NCTF35
VSS_NCTF36
VSS_NCTF37
VSS_NCTF38
VSS_NCTF39
VSS_NCTF40
VSS_NCTF41
VSS_NCTF42
VSS_NCTF43
VSS_NCTF44
VSS_NCTF45
VSS_NCTF46
VSS_NCTF47
VSS_NCTF48
VSS_NCTF49
VSS_NCTF50
VSS_NCTF51
VSS_NCTF52
VSS_NCTF53
VSS_NCTF54
VSS_NCTF55
VSS_NCTF56
VSS_NCTF57
VSS_NCTF58
VSS_NCTF59
VSS_NCTF60
VSS_NCTF61
VSS_NCTF62
VSS_NCTF63
VSS_NCTF64
VSS_NCTF65
VSS_NCTF66
VSS_NCTF67
VSS_NCTF68
VSS_NCTF7
VSS_NCTF8
VSS_NCTF9
VSS_NCTF10
VSS_NCTF11
VSS_NCTF12
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
ALVISO
NCTF
VCCSM_NCTF0
VCCSM_NCTF1
VCCSM_NCTF2
VCCSM_NCTF3
VCCSM_NCTF4
VCCSM_NCTF5
VCCSM_NCTF6
VCCSM_NCTF7
VCCSM_NCTF8
VCCSM_NCTF9
VCCSM_NCTF10
VCCSM_NCTF11
VCCSM_NCTF12
VCCSM_NCTF13
VCCSM_NCTF14
VCCSM_NCTF15
VCCSM_NCTF16
VCCSM_NCTF17
VCCSM_NCTF18
VCCSM_NCTF19
VCCSM_NCTF20
VCCSM_NCTF21
VCCSM_NCTF22
VCCSM_NCTF23
VCCSM_NCTF24
VCCSM_NCTF25
VCCSM_NCTF26
VCCSM_NCTF27
VCCSM_NCTF28
VCCSM_NCTF29
VCCSM_NCTF30
VCCSM_NCTF31
VCC_NCTF0
VCC_NCTF1
VCC_NCTF2
VCC_NCTF3
VCC_NCTF4
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF8
VCC_NCTF9
VCC_NCTF10
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VCC_NCTF15
VCC_NCTF16
VCC_NCTF17
VCC_NCTF18
VCC_NCTF19
VCC_NCTF20
VCC_NCTF21
VCC_NCTF22
VCC_NCTF23
VCC_NCTF24
VCC_NCTF25
VCC_NCTF26
VCC_NCTF27
VCC_NCTF28
VCC_NCTF29
VCC_NCTF30
VCC_NCTF31
VCC_NCTF32
VCC_NCTF33
VCC_NCTF34
VCC_NCTF35
VCC_NCTF36
VCC_NCTF37
VCC_NCTF38
VCC_NCTF39
VCC_NCTF40
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
VCC_NCTF44
VCC_NCTF45
VCC_NCTF46
VCC_NCTF47
VCC_NCTF48
VCC_NCTF49
VCC_NCTF50
VCC_NCTF51
VCC_NCTF52
VCC_NCTF53
VCC_NCTF54
VCC_NCTF55
VCC_NCTF56
VCC_NCTF57
VCC_NCTF58
VCC_NCTF59
VCC_NCTF60
VCC_NCTF61
VCC_NCTF62
VCC_NCTF63
VCC_NCTF64
VCC_NCTF65
VCC_NCTF66
VCC_NCTF67
VCC_NCTF68
VCC_NCTF69
VCC_NCTF70
VCC_NCTF71
VCC_NCTF72
VCC_NCTF73
VCC_NCTF74
VCC_NCTF75
VCC_NCTF76
VCC_NCTF77
VCC_NCTF78
AD26
AC26
AD25
AC25
AD24
AC24
AD23
AC23
AD22
AC22
AD21
AC21
AD20
AC20
AD19
AC19
AD18
AC18
AD17
AC17
AD16
AC16
AD15
AC15
AD14
AC14
AD13
AC13
AB13
AD12
AC12
AB12
W26
V26
U26
T26
R26
P26
N26
M26
L26
W25
V25
U25
T25
R25
P25
N25
M25
L25
W24
V24
U24
T24
R24
P24
N24
M24
L24
W23
V23
U23
T23
R23
P23
N23
M23
L23
W22
V22
U22
T22
R22
P22
N22
M22
L22
W21
V21
U21
T21
P21
N21
M21
L21
Y20
R20
P20
N20
M20
L20
Y19
R19
P19
N19
M19
L19
Y18
R18
P18
N18
M18
L18
W17
V17
U17
T17
P17
N17
M17
L17
A A
5
4
3
2
1.8VSUSVCCP
Size Document Number Rev
Custom
Date: Sheet
PROJECT : EF6
Quanta Computer Inc.
VSS/NCTF(5/5)
1
of
937Monday, January 03, 2005
1A
1
SMDDR_VREF
1.8VSUS
R_A_MD0
R_A_MD1
R_A_DQS#0
R_A_DQS0
A A
B B
CKE05,11 CKE25,11 CKE3 5,11
R_A_BS2#7,11
R_A_BS0#7,11
R_A_BMWEA#7,11
R_A_SCASA#7,11
SM_CS1#5,11
M_ODT15,11
C C
D D
R_A_MD6
R_A_MD3
R_A_MD8
R_A_MD13
R_A_DQS#1
R_A_DQS1
R_A_MD14 R_B_MD10
R_A_MD15
R_A_MD20
R_A_MD17
R_A_DQS#2
R_A_DQS2
R_A_MD18
R_A_MD22
R_A_MD25
R_A_MD24
R_A_DM3
R_A_MD26
R_A_MD30
CKE0
R_A_BS2#
R_A_MA12
R_A_MA9
R_A_MA8
R_A_MA5
R_A_MA3
R_A_MA1
R_A_MA10
R_A_BS0#
R_A_BMWEA#
R_A_SCASA#
SM_CS1#
M_ODT1
R_A_MD32
R_A_MD33
R_A_DQS#4
R_A_DQS4
R_A_MD34
R_A_MD35
R_A_MD40
R_A_MD41
R_A_DM5
R_A_MD43 R_A_MD46
R_A_MD42
R_A_MD48
R_A_MD49
R_A_DQS#6
R_A_DQS6
R_A_MD51
R_A_MD60
R_A_MD57
R_A_DM7
R_A_MD58
R_A_MD59
CGCLK_SMB
+3V
1
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
2
CN30
1
VREF
3
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
83
85
87
89
91
93
95
97
99
PC4800 DDR2
VDD7
NC1
A16_BA2
VDD9
A12
A9
A8
VDD5
A5
A3
A1
VDD10
A10/AP
BA0
WE#
VDD2
CAS#
S1#
VDD3
ODT1
VSS11
DQ32
DQ33
VSS26
DQS#4
DQS4
VSS2
DQ34
DQ35
VSS27
DQ40
DQ41
VSS29
DM5
VSS51
DQ42
DQ43
VSS40
DQ48
DQ49
VSS52
NCTEST
VSS30
DQS#6
DQS6
VSS31
DQ50
DQ51
VSS33
DQ56
DQ57
VSS3
DM7
VSS34
DQ58
DQ59
VSS14
SDA
SCL
VDD(SPD)
PC4800_DDR2_R_4H
CLOCK 0,1 CLOCK 3,4
2
1.8VSUS 1.8VSUS 1.8VSUS
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
SDRAM SO-DIMM
(200P)
VDD8
84
A15
86
A14
88
VDD11
90
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
R_A_MD4
R_A_MD5
R_A_DM0
R_A_MD2
R_A_MD7
R_A_MD12
R_A_MD9
R_A_DM1
CLK_SDRAM0
CLK_SDRAM0#
R_A_MD11
R_A_MD10
R_A_MD16
R_A_MD21
R_A_DM2
R_A_MD23
R_A_MD19
R_A_MD29
R_A_MD28
R_A_DQS#3
R_A_DQS3
R_A_MD27
R_A_MD31
CKE1
R_A_MA11
R_A_MA7
R_A_MA6
R_A_MA4
R_A_MA2
R_A_MA0
R_A_BS1#
R_A_SRASA#
SM_CS0#
M_ODT0
R_A_MA13
R_A_MD36
R_A_MD37
R_A_DM4
R_A_MD38
R_A_MD39
R_A_MD45
R_A_MD44
R_A_DQS#5
R_A_DQS5
R_A_MD47
R_A_MD52
R_A_MD53
CLK_SDRAM1
CLK_SDRAM1#
R_A_DM6
R_A_MD50
R_A_MD54R_A_MD55
R_A_MD61
R_A_MD56
R_A_DQS#7
R_A_DQS7
R_A_MD63
R_A_MD62
R10 10K
R9 10K
SMbus address A0 SMbus address A4
3
CLK_SDRAM0 5
CLK_SDRAM0# 5
SMDDR_VREF
C571
0.1U
C TEST
modified EMI
CKE1 5,11
R_A_BS1# 7,11
R_A_SRASA# 7,11
SM_CS0# 5,11
M_ODT0 5,11
CLK_SDRAM1 5
CLK_SDRAM1# 5
3
R_A_DM[0..7] 7
R_A_DQS[0..7] 7
R_A_DQS#[0..7] 7
R_A_MA[0..13] 7,11
C573
C572
0.1U
0.1U
R_B_BS2#7,11
R_B_BS0#7,11
R_B_BMWEA#7,11
R_B_SCASA#7,11
SM_CS3#5,11
M_ODT35,11
CGDAT_SMB2
CGCLK_SMB2
4
SMDDR_VREF
CN29
1
VREF
3
R_B_MD7
R_B_MD1
R_B_DQS#0
R_B_DQS0
R_B_MD0
R_B_MD2
R_B_MD12
R_B_MD9
R_B_DQS#1
R_B_DQS1
R_B_MD8
R_B_MD14
R_B_MD16
R_B_MD17
R_B_DQS#2
R_B_DQS2
R_B_MD19
R_B_MD22
R_B_MD24
R_B_MD25
R_B_DM3
R_B_MD26
R_B_MD27
CKE2
R_B_BS2#
R_B_MA12
R_B_MA9
R_B_MA8
R_B_MA5
R_B_MA3
R_B_MA1
R_B_MA10
R_B_BS0#
R_B_BMWEA#
R_B_SCASA#
SM_CS3#
M_ODT3
R_B_MD37
R_B_MD33
R_B_DQS#4
R_B_DQS4
R_B_MD35
R_B_MD34
R_B_MD41
R_B_MD40
R_B_DM5
R_B_MD42 R_B_MD47
R_B_MD43
R_B_MD48
R_B_MD49
R_B_DQS#6
R_B_DQS6
R_B_MD50
R_B_MD61
R_B_MD56
R_B_DM7
R_B_MD58
R_B_MD59
CGDAT_SMBCGDAT_SMB
CGCLK_SMB
+3V
VSS47
5
DQ0
7
DQ1
9
VSS37
11
DQS#0
13
DQS0
15
VSS48
17
DQ2
19
DQ3
21
VSS38
23
DQ8
25
DQ9
27
VSS49
29
DQS#1
31
DQS1
33
VSS39
35
DQ10
37
DQ11
39
VSS50
41
VSS18
43
DQ16
45
DQ17
47
VSS1
49
DQS#2
51
DQS2
53
VSS19
55
DQ18
57
DQ19
59
VSS22
61
DQ24
63
DQ25
65
VSS23
67
DM3
69
NC4
71
VSS9
73
DQ26
75
DQ27
77
VSS4
79
CKE0
81
VDD7
83
NC1
85
A16_BA2
87
VDD9
89
A12
91
A9
93
A8
95
VDD5
97
A5
99
A3
101
A1
103
VDD10
105
A10/AP
107
BA0
109
WE#
111
VDD2
113
CAS#
115
S1#
117
VDD3
119
ODT1
121
VSS11
123
DQ32
125
DQ33
127
VSS26
129
DQS#4
131
DQS4
133
VSS2
135
DQ34
137
DQ35
139
VSS27
141
DQ40
143
DQ41
145
VSS29
147
DM5
149
VSS51
151
DQ42
153
DQ43
155
VSS40
157
DQ48
159
DQ49
161
VSS52
163
NCTEST
165
VSS30
167
DQS#6
169
DQS6
171
VSS31
173
DQ50
175
DQ51
177
VSS33
179
DQ56
181
DQ57
183
VSS3
185
DM7
187
VSS34
189
DQ58
191
DQ59
193
VSS14
195
SDA
197
SCL
199
VDD(SPD)
PC4800_DDR2_R_4H
CKE 2,3CKE 0,1
4
5
2
VSS46
4
DQ4
6
DQ5
8
VSS15
10
DM0
12
VSS5
14
DQ6
16
DQ7
18
VSS16
20
DQ12
22
DQ13
24
VSS17
26
DM1
28
VSS53
30
CK0
32
CK0#
34
VSS41
36
DQ14
38
DQ15
40
VSS54
42
VSS20
44
DQ20
46
DQ21
48
VSS6
50
NC3
52
DM2
54
VSS21
56
DQ22
58
DQ23
60
VSS24
62
DQ28
64
DQ29
66
VSS25
68
DQS#3
70
DQS3
72
VSS10
74
DQ30
76
DQ31
78
VSS8
80
CKE1
82
PC4800 DDR2
SDRAM SO-DIMM
(200P)
VDD8
84
A15
86
A14
88
VDD11
90
A11
92
A7
94
A6
96
VDD4
98
A4
100
A2
102
A0
104
VDD12
106
BA1
108
RAS#
110
S0#
112
VDD1
114
ODT0
116
A13
118
VDD6
120
NC2
122
VSS12
124
DQ36
126
DQ37
128
VSS28
130
DM4
132
VSS42
134
DQ38
136
DQ39
138
VSS55
140
DQ44
142
DQ45
144
VSS43
146
DQS#5
148
DQS5
150
VSS56
152
DQ46
154
DQ47
156
VSS44
158
DQ52
160
DQ53
162
VSS57
164
CK1
166
CK1#
168
VSS45
170
DM6
172
VSS32
174
DQ54
176
DQ55
178
VSS35
180
DQ60
182
DQ61
184
VSS7
186
DQS#7
188
DQS7
190
VSS36
192
DQ62
194
DQ63
196
VSS13
198
SA0
200
SA1
5
R_B_MD4
R_B_MD5
R_B_DM0
R_B_MD6
R_B_MD3
R_B_MD11
R_B_MD13
R_B_DM1
CLK_SDRAM3
CLK_SDRAM3#
R_B_MD15
R_B_MD20
R_B_MD21
R_B_DM2
R_B_MD23
R_B_MD18
R_B_MD28
R_B_MD29
R_B_DQS#3
R_B_DQS3
R_B_MD31
R_B_MD30
CKE3
R_B_MA11
R_B_MA7
R_B_MA6
R_B_MA4
R_B_MA2
R_B_MA0
R_B_BS1#
R_B_SRASA#
SM_CS2#
M_ODT2
R_B_MA13
R_B_MD36
R_B_MD32
R_B_DM4
R_B_MD38
R_B_MD39
R_B_MD44
R_B_MD45
R_B_DQS#5
R_B_DQS5
R_B_MD46
R_B_MD52
R_B_MD53
CLK_SDRAM4
CLK_SDRAM4#
R_B_DM6
R_B_MD55
R_B_MD54R_B_MD51
R_B_MD60
R_B_MD57
R_B_DQS#7
R_B_DQS7
R_B_MD63
R_B_MD62
R13 10K
R12 10K
+3V
6
CLK_SDRAM3 5
CLK_SDRAM3# 5
R_B_BS1# 7,11
R_B_SRASA# 7,11
SM_CS2# 5,11
M_ODT2 5,11
CLK_SDRAM4 5
CLK_SDRAM4# 5
6
R_B_DM[0..7] 7R_A_MD[0..63] 7
R_B_MD[0..63] 7
R_B_DQS[0..7] 7
R_B_DQS#[0..7] 7
R_B_MA[0..13] 7,11
7
8
10
1.8VSUS
Place these Caps near So-Dimm1.
C67
C19
C17
C16
2.2U
2.2U
2.2U
2.2U
1.8VSUS
Place these Caps near So-Dimm1.
C51
C55
C46
C54
0.1U
0.1U
0.1U
0.1U
SMDDR_VREF
C49
0.1U
C25
2.2U
+3V
C40
2.2U
Place these Caps near So-Dimm1.
No Vias Between the Trace of PIN to
CAP.
1.8VSUS
Place these Caps near So-Dimm2.
C63
2.2U
C42
0.1U
C50
2.2U
C53
0.1U
C65
2.2U
C68
2.2U
C44
0.1U
+3V
C27
2.2U
C38
2.2U
1.8VSUS
Place these Caps near So-Dimm2.
C52
0.1U
SMDDR_VREF
C20
0.1U
Place these Caps near So-Dimm2.
No Vias Between the Trace of PIN to
CAP.
CLK_SDRAM4CLK_SDRAM3
C61
10P
C31
10P
CLK_SDRAM0# CLK_SDRAM1#
Size Document Number Rev
Custom
System DRAM Expansion (200P-DDR_SODIMM X 2)(1/2)
Date: Sheet
7
PROJECT : EF6
Quanta Computer Inc.
C62
10P
CLK_SDRAM4#CLK_SDRAM3#
CLK_SDRAM1CLK_SDRAM0
C30
10P
10 37Monday, January 03, 2005
8
C18
2.2U
C26
0.1U
C66
2.2U
C39
0.1U
C64
2.2U
C47
2.2U
of
1A
1
2
3
4
5
6
7
8
11
A A
DDRII DUAL CHANNEL A,B.
DDRII A CHANNEL DDRII B CHANNEL
R_A_MA[0..13] 7,10 R_B_MA[0..13] 7,10
SMDDR_VTERM
C35
C70
0.1U
B B
0.1U
C34
0.1U
R_A_BMWEA#7,10
R_A_SCASA#7,10
C57
0.1U
C43
0.1U
M_ODT0
SM_CS0#
R_A_MA5
R_A_MA8
R_A_MA3
R_A_MA1
R_A_MA11
CKE1
R_A_MA10
R_A_BS0#
R_A_MA6
R_A_MA7
R_A_MA0
R_A_MA4
R_A_MA2
R_A_BS1#
R_A_MA9
R_A_MA12
R_A_BMWEA#
R_A_SCASA#
C41
0.1U
M_ODT05,10
SM_CS0#5,10
CKE15,10
R_A_BS0#7,10
R_A_BS1#7,10
C74
C73
0.1U
C37
0.1U
0.1U
1
RP9 56X2
3
1
RP6 56X2
3
1
RP5 56X2
3
1
RP14 56X2
3
1
RP4 56X2
3
1
RP13 56X2
3
1
RP12 56X2
3
1
RP11 56X2
3
1
RP7 56X2
3
1
RP3 56X2
3
C69
0.1U
C71
C72
C48
0.1U
0.1U
0.1U
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM 32,36
SMDDR_VTERM
C32
0.1U
C28
0.1U
C59
0.1U
C45
0.1U
C29
0.1U
C33
0.1U
C21
0.1U
C22
0.1U
C23
0.1U
C24
0.1U
C56
0.1U
C36
0.1U
C58
0.1U
Layout note: Place one cap close to every 2 pullup resistors terminated to SMDDR_VTERM
R_B_MA0
R_B_BS1#7,10
CKE25,10
R_B_BS2#7,10
R_B_SRASA#7,10
SM_CS2#5,10
R_B_BMWEA#7,10
M_ODT35,10
R_B_BS0#7,10
R_B_BS1#
R_B_MA1
R_B_MA3
R_B_MA5
R_B_MA8
R_B_MA4
R_B_MA2
R_B_MA9
R_B_MA12
R_B_MA6
R_B_MA7
CKE2
R_B_BS2#
R_B_SRASA#
SM_CS2#
R_B_BMWEA#
M_ODT3
R_B_MA10
R_B_BS0#
RP24 56X2
RP18 56X2
RP19 56X2
RP25 56X2
RP20 56X2
RP26 56X2
RP21 56X2
RP23 56X2
RP15 56X2
RP17 56X2
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
2
1
4
3
SMDDR_VTERM
SMDDR_VTERM
SMDDR_VTERM
C C
R_A_SRASA#7,10
M_ODT25,10
R_B_SCASA#7,10
SM_CS3#5,10
M_ODT15,10
C TEST modified EMI
SMDDR_VTERM
C526
C525
C524
0.1U
0.1U
D D
SMDDR_VTERM
C534
0.1U
1
C535
0.1U
0.1U
C536
0.1U
C527
0.1U
C537
0.1U
C528
0.1U
C538
0.1U
C529
C530
0.1U
0.1U
C540
C539
0.1U
0.1U
2
C531
0.1U
C541
0.1U
C532
0.1U
C542
0.1U
C533
0.1U
C543
0.1U
3
SM_CS1#5,10
CKE35,10
CKE05,10
R_A_BS2#7,10
R_A_MA13
R_A_SRASA#
M_ODT2
R_B_MA13
R_B_SCASA#
SM_CS3#
M_ODT1
SM_CS1#
R_B_MA11
CKE3
CKE0
R_A_BS2#
4
1
RP10 56X2
3
1
RP22 56X2
3
1
RP16 56X2
3
1
RP2 56X2
3
1
RP27 56X2
3
1
RP8 56X2
3
2
4
2
4
2
4
2
4
2
4
2
4
SMDDR_VTERM
5
Size Document Number Rev
Custom
6
Date: Sheet
7
PROJECT : EF6
Quanta Computer Inc.
DDR RES.ARRAY(2/2)
of
11 37Monday, January 03, 2005
8
1A
5
ESD PORTECTION
D D
CRT SWITCH
C C
SEL
FUNCTION(COM)
LOW
IN_B0
HIGH
IN_B1
+3V
R150
B B
PR_INSERT#_D
A A
10K
3
2
CH2507S
1
PR_HSYNC24
PR_VSYNC24
INTVGA_E
Q11
VGA_RED
PR_RED-1
VGA_GEN
PR_GEN-1
VGA_BLU
PR_BLU-1
5
+5V
+5V
+5V
TV_Y/G
C238
0.1U
CC0402
C240
0.1U
CC0402
C239
0.1U
CC0402
INTVGA_E
HSYNC_COM
INTVGA_E
VSYNC_COM
CRT_VS_1
CRT_HS_1
CRT_R_1
CRT_G_1
+5V
+5V
+5V
+5V
5
1
3
5
1
3
5
1
3
1
2
3
1
2
3
U32
2
VCC
1
IO1
3
IO2
*DALC208SC6
U30
2
VCC
1
IO1
3
IO2
*DALC208SC6
U5
2
VCC
1
IO1
3
IO2
*DALC208SC6
U27
VCC
IN_B1
IN_B0
NC7SB3157P6X
U28
VCC
IN_B1
IN_B0
NC7SB3157P6X
U29
VCC
IN_B1
IN_B0
NC7SB3157P6X
U24
1OE#
1A
2Y
SN74LVC2G125
U25
1OE#
1A
2Y
SN74LVC2G125
6
IO4
DDCCLK_1
4
IO3
5
GND
CRT_B_1
6
IO4
DDCDAT_1
4
IO3
5
GND
TV_COMP
6
IO4
TV_C/R
4
IO3
5
GND
R154 10K
PR_INSERT#_D
6
2OE#
2OE#
SEL
COM
GND
SEL
COM
GND
SEL
COM
GND
VCC
1Y
2AGND
VCC
1Y
2AGND
CRT_R_COM
4
2
6
CRT_G_COM
4
2
6
CRT_B_COM
4
2
+3V
+3V
C229
0.1U
8
7
6
54
8
7
6
54
CC0402
CRTHS_VGA
HSYNC_COM
+3V
+3V
C230
0.1U
CC0402
CRTVS_VGA
VSYNC_COM
4
+3V
2 1
D18 CH500H-40
CRT_R_COM 6
CRT_G_COM 6
CRT_B_COM 6
HSYNC_COM 6
VSYNC_COM 6
4
PR_INSERT#
CRT PORT
VGA_RED
VGA_GEN
VGA_BLU
R158
150/F
PR_INSERT# 26
3
L31 0
L33 0
L35 0
R160
150/F
R161
150/F
C250
*10P
+2.5V
CDDCCLK6
+2.5V
CDDCDATA6
C256
C253
*10P
*10P
R162 2.2K
CDDCCLK
CRTVS_VGA
CRTHS_VGA
R207 2.2K
CDDCDATA
TV-OUT
To port - replicator C.R.T
PR_RED-1
PR_GEN-1
PR_BLU-1
R148
150/F
3
2 1
+5V
D25 CH500H-40
C TEST Modified
C246
5.6P
+2.5V
2
CH2507S
Q13
R205 39
R206 39
+2.5V
2
CH2507S
Q18
TV_Y/G6
TV_C/R6
TV_COMP6
R139
150/F
3
3
TV_Y/G
TV_C/R
TV_COMP
C226
*10P
R142
150/F
1
1
CRTVDD1
RED_PI
GEN_PI
BLU_PI
R4
150/F
R2
150/F
R3
150/F
C220
*10P
C251
5.6P
DDCCLK2
CRT_VS2
CRT_HS2
DDCDAT2
F2
CRTVDD2
12
POLY_SWITCH_1.1A
L30 BK1608HS470
L32 BK1608HS470
L34 BK1608HS470
C254
5.6P
R163
2.2K
R208
2.2K
CRTVDD_5V
L36 BK1608HM121
L45 BK1608HM121
L47 BK1608HM121
L48 BK1608HM121
CRTVDD_5V
C TEST Modified
L4
BLM18BD151SN1
C10
5.6P
L2
BLM18BD151SN1
C9
5.6P
L3
1 2
BLM18BD151SN1
C8
5.6P
C TEST Modified
L20 0
L18 0
L16 0
C210
*10P
HI0805Q310R-00
CRT_R_1
CRT_G_1
CRT_B_1
C255
5.6P
V4
5.6P
TV_CHROMA_1
V2
5.6P
PR_RED-2
PR_GEN-2
PR_BLU-2
C221
5.6P
2
L46
C252
5.6P
DDCCLK2 24
DDCDAT2 24
TV_COMP_1
C212
5.6P
2
CRTVDD_5V
C297
*0.1U
C249
5.6P
3
L19 BK1608HS470
L17 BK1608HS470
L15 BK1608HS470
C207
5.6P
T50
7
7
V3
5.6P/VPORT-22
C257
*33P
TV_LUMA_1
CN2
S-VIDEO
5
5
10
C296
*33P
2
2
1
CRT_SENSE# 15
12 37Monday, January 03, 2005
12
of
1A
CN18
1617
CRT_CONN
6
111
7
12
2
8
13
3
9
14
4
15
5
DDCCLK_1
CRT_VS_1
CRT_HS_1
DDCDAT_1
C298
C299
*33P
*33P
46
46
89
89
13
C219
C209
5.6P
5.6P
Size Document Number Rev
C
Date: Sheet
CRT_SENSE#
C300
180P
PR_RED 24
PR_GRN 24
PR_BLU 24
C225
5.6P
PROJECT : EF6
Quanta Computer Inc.
SVIDEO/CRT/PANLE/HDTV
1
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