FUJITSU SIEMENS P7230 Schematics

PORTLAND 10/10G

MP BUILD

2006 0731

DRAWER
DESIGN
CHECK
RESPONSIBLE

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FILE NAME :

CHANGE NO.DATE

REV

P/N

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3 SIZE

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POWER

VER :

DATEDATE

INVENTEC

TITLE

Portland 10/10G

DOC. NUMBER

CODE

A3

1310A2076901 A02

CS

SHEET

REV

OF

681

TABLE OF CONTENTS

PAGE

1.COVER PAGE

2.INDEX

3.BLOCK DIAGRAM

4.POWER SEQUENCE BLOCK
5-12.SYSTEM POWER

13.CLOCK GENERATOR

14.CPU Yonah1

15.CPU Yonah2

16.CPU Yonah3

17.CPU Yonah4

18.FAN & THERMAL CONTROLLER

19.N/B Calistoga 1

20.N/B Calistoga 2

21.N/B Calistoga 3

22.N/B Calistoga 4

23.N/B Calistoga 5

24.N/B Calistoga 6

25.DDR2 DIMM0

26.DDR2 DIMM1

27.DDR DAMPING

28.CRT CONN

29.SVIDEO CONN

30.LCD CONN

31.S/B ICH7 1

PAGE

32.S/B ICH7 2

33.S/B ICH7 3

34.S/B ICH7 4

35.S/B ICH7 5

36.CARDBUS CONTROLLER

37.PCMCIA

38.5 IN 1 CARD SLOT

39.1394 CONTROLLER

40.LAN CONTROLLER

41. TRANSFORMER

42. RJ45

43.MINI CARD CONN

44. SATA HDD CONN

45.ODD CONN

46.USB CONN

47.BLUE TOOTH CONN

48.TPM 1.2

49.SUPER I/O

50.K/B & D/B CONN

51.CIR

52.AZALIA CODEC

53.AUDIO AMP & MIC & HP

54.MDC 1.5 CONN

55.SWITCH & LED (MB)

PAGE

56.SWITCH & LED (DB)

57.PICK BUTTON BOARD

58.USB BOARD

59.DRILL HOLE
60-61.VGA POWER

62.ATI_M54P 1

63.ATI_M54P 2

64.ATI_M54P 3

65.ATI_M54P 4

66.VIDEO RAM 1

67.VIDEO RAM 2

68.VIDEO RAM DAMPING

CHANGE by

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

DOC. NUMBER

CODE

SIZE

A3

1310A2076901 A02

CS

SHEET

REV

OF

682

Yonah

(uFCPGA)

ICS9LPR316

Clock generator

BATTERY

HDD

ODD

USB0

Bluetooth

S-video

LCM
CRT

USB1

FINGER PRINT

USB2

MDC / Modem

Module 56K

USB3

CONN C (DB)

SATA

Primary_IDE

USB4

CONN D (DB)

USB5

CONN A (MB)

CONN B (MB)

3.3V, AZALIA

AZALIA

FSB, 533/667 MHz

Calistoga

945GM/PM

1466 uFCBGA

DMI x4

ICH7-M

652 BGA

3.3V, LPC_Interface,33MHz

1.8V, DDR2 Interface, 533/667 MHz

1.8V, DDR2 Interface, 533/667 MHz

PCI_EXPRESS

Realtek

10/100 RTL8101E

1G RTL8111B

RJ45

MINI CARD

Wireless LAN

ANT

DDR2_SODIMM0

3.3V, PCI_Interface,33MHz

CARD BUS

ENE_CB714BF

ANT

Cardbus

SLOT A

DDR2_SODIMM1

Card reader

CONN

1394

VIA_VT6311S

1394

CONN

System Charger &

DC/DC System power

(IMVP-6

VR)

RJ11

MIC

JACK

HP

JACK

SPEAKER

SMSC

KBC1122

BIOS

FLASH ROM

CIR

CHANGE by

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

CODE

SIZE

A3

DOC. NUMBER

1310A2076901 A02

CS

SHEET

REV

OF

683

+VADPTR

+VBAT

SKIP#

EN_5V
EN_3V

5V

3V

+V5A

+V3LA

+V3A

+V3

+V3S

+VAUDIO_5S

+V5S

+VGA_3S

SCL
SDA

+VPACK

+V1.5S

EN

EN

+V1.2S

+2.5S

EN

+VGA_2.5S

+V0.9S

+V1.8

EN

+V1.8S

+VCCP

EN

+VGAVCC

EN

CHANGE by

+VCC_CORE

Drawer_Name 21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

SIZE

CODE

DOC. NUMBER

A3

1310A2076901 A02

CS

REV

OFSHEET

684

CN504

ACES_91202_0047L_TSB_4P

4
3
2
1

4
3
2
1

FUSE501

12

10A_125V

C55

1

10pF_50v

2

+VADPTR

5-

1
2

C75

0.1uF_25v

+VBAT

60-,10-,9-,8-,7-,6-,5-

+VADPTR

5-

+VBAT_A

5-

DTA143EKA

1 R67

RLZ18C

2

B

2

D8

D507

1

3

2

PDS1040_10A_40V

R5122

12

4.7K_5%

R5123

12

4.7K_5%

1

E

Q11

C

3

Q9

B

2

DTC124EK

1

R93

365K_1%

2

3

C
E

1

+VBAT

60-,10-,9-,8-,7-,6-,5-

2

D5005

3

BAT54S_30V_0.2A

1

1

C54

36.5K_1%
OPEN12

2

49-

ACPRES

51-,49-,46-,43-,41-,34-,33-,32-,14-,12-,11-,7-

1

C5108

2

R90

12

10_5%

1

R92

47K_5%

2

C74

1uF_10v

1

R91

100K_5%

2

+V3A

CHG_EN

68uF_25v

0.1uF_25v

1
2

1

2

49-

C524

C43

2.2uF_25v

+V5LA

1
2

51-,18-,7-,6-

1

R61

8.06K_1%

2
1

R62

39.2K_1%

2

49-

1

R63

22.6K_1%

2

R295

1

10K_5%

EC_CLK

EC_DATA

BATT_IN

2

R514

12

0.01_1%_1W

C523

0.1uF_25v

6-

49­49-

12

THRM1

+VBAT_A

5-

C518

1
2

0.1uF_25v

U504

12

VCC

3

ACN

4

ACP

6

BYPASS#

5

ACDET

11

VREF5

10

AGND

15

TS

1

CHGEN#

14

SCL

13

SDA

25

ALARM#

17

IOUT

TI_BQ24721_QFN_32P

ACDRV#

BATDRV#

PVCC

HIDRV

BTST

REGN

LODRV

PGND
SYNP
SYNN

ISYNSET

SYS

PH

SRP
SRN
BAT

EAO

EAI

FBO

TML

2

23

24

32

30

29

10_5%

R824

12

31

28

13

27

CHENMKO_BAT54_3P

26
22
21
20
19
18

7

8
9

16
33

1

R64

100K_5%

2

Q501

AM4825P_AP

1

S

2
3

G

C1095

0.1uF_25v

12

D5

1

R66

200K_5%

2

D

12

8
7
6
54

C22

1uF_25v

1

2

1
2

R65

18K_5%

C44

100pF_50v

C515

1
2

0.1uF_25v

Q502

D1

1
2

G1

8

G2

3

C46

1
2

56pF_50v

C21

1
2

10uF_25v_K_X5R

SP8K10SFD5_ROHM

5

S1_D2

6

1

R5126

7

4.7_5%

4

S2

2

C5052

1

2200pF_50v

2

1

R53

10K_5%

2

C45

1

1500pF_50v

2

C514

1
2

10uF_25v_K_X5R

PLC0755P_10uH_3.9A

L506

12

C30

1
2

10uF_25v_K_X5R

1
2

6 cell
9 cell

12 cell

R52

12

0.01_1%_1W

C519

12

0.1uF_25v

1
2

C521

0.1uF_25v

C522

0.1uF_25v

NEAR IC

Current Voltage

2.8A

2.8A

2.8A

+VPACK

6-

C31

1
2

10uF_25v_K_X5R

C520

1
2

12.6V

12.6V

12.6V

Q8

8

D

7
6
5

AM4825P_AP

0.1uF_25v

1

S

2
3
4

G

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

DC &BATTERY CHANGER

CODE

CS

SHEET

DOC. NUMBERSIZE

568

A3

REV

A021310A2076901

OF

+VPACK

FUSE2

LITTLEFUSE_R451012_12A_65V

5-

12

THRM1

BATT_DATA

BATT_CLK

+VBAT

5­49­49-

60-,10-,9-,8-,7-,5-

1
R348

1M_5%

2

1
R349

56.2K_1%

2

1
R350

180K_1%

2

1K_5%

R60

12

1

D3

EZJZ0V120JA

2

C5050

0.1uF_25v

1
2

1

D4

EZJZ0V120JA

2

U23

3

LTH

2

GND

1

HTH

GMT_G680LT1_SOT23_5P

RESET#

VCC

4
5

C5051

1000pF_50v

1
2

CN502
7
6
5
4
3
2
1

TYCO_1747603_1_7P

7-

+V5AUXON

7
6
5
4
3
2
1

+V5LA

51-,18-,7-,5-

C419

1
2

0.1uF_10v

CHANGE by

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

BATTERY CONN

SIZE

CODE

DOC. NUMBER

A3

1310A2076901 A02

CS

SHEET

REV

OF

686

+V5AUXON

THRM_SHUTDWN#

EC_PW_ON

SLP_S3#_3R

6-

63-,49-,18-

49-

49-,37-,32-,12-,11-,10-

100K_5%

R341

12

10K_5%

1

3

D37

BAT54C

R342

12

10K_5%

R695

2

+VBAT

60-,10-,9-,8-,6-,5-,7-

2

1

R696

0_5%

12

TPS51020

R378

10K_1%

2

C439

0.01uF_16v

1

2

C440 0.1uF_16v

12

C437

0.01uF_16v

2

1

R368

12

1M_5%

R357

12

10.2K_1%

1

R402

29.4K_1%

2

1

C448

1

2

0.033uF_16v

2

2

1

C424

3900pF_50v

R356

12

51.1K_1%

1
2

R377

2

2.7K_5%

R362

1.8K_5%

1

R361

220_5%

2

C423

6800pF_25v

1

C785

4700pF_50v

2

1

R403

330_5%

2

1

1

U28

1

INV1

2

COMP1

3

SSTRT1

4

SKIP#

5

VO1_VDDQ

6

DDR#

7

GND

8

REF_X

9

ENBL1

10

ENBL2

11

VO2

12

PGOOD

13

SSTRT2

14

COMP2

15

INV2

TI_TPS51020DBT_TSSOP_30P

VBST1

OUT1_U

OUT1_D

OUTGND1

TRIP1

TRIP2

VREG5

REG5_IN

OUTGND2

OUT2_D

OUT2_U

VBST2

30
29
28

LL1

27
26
25
24

VIN

23
22
21
20
19
18

LL2

17
16

R376

1

4.7_5%

1
2

C446

4.7uF_25v

2

R373

1

R360

12

2.2_5%

2

2

R367

1

15.8K_1%

C422

12

0.1uF_25v

10K_1%

C443

R401

12

2.2_5%

0.1uF_25v

12

8765

D

G

S

41

23

8765

D

G

S

123

4

C427

1
2

10uF_25v_K_X5R

1
2
8

3

SP8K10SFD5_ROHM

+V5LA

51-,18-,6-,5-,7-

C779

1

1uF_6.3v

2

+V5A

61-,60-,55-,46-,34-,12-,11-,9-,8-,7-

Q30

SI4800DY

Q29

FDS6680AS

1

C338

2

Q33

D1

5

S1_D2

G1

6
7

G2

4

S2

+VBAT

60-,10-,9-,8-,6-,5-,7-

C436

1
2

10uF_25v_K_X5R

L23

12

PLFC1055P_6R8A_6.8uH

68uF_25v

PLC_0755_4R7_5.1A

1

C407

2

330uF_6.3v

L25

12

C413

1
2

1uF_10v

1

C438

2

330uF_6.3v

POWERPAD_2_0610

1
2

1uF_10v

PAD4

POWERPAD_2_0610

PAD5

2

1

C447

+V5A

61-,60-,55-,46-,34-,12-,11-,9-,8-,7-

+V3LA

55-,51-,49-,31-,18-,7-

Q31

G

G

SSM3K17FU

+V5LA

D

S

51-,18-,6-,5-,7-

1

R352

10K_5%

2

D

S

+V3LA

55-,51-,49-,31-,18-,7-

CHENMKO_BAT54_3P

D514

13

R693

12

100K_5%

CLOSE TO PAD4

C774

1

0.1uF_10v

2

4

S

SI3433BDV

4

S

3

SI3433BDV

Q514

G

Q32

G

D

D

1
2
5
63

1
2
5
6

SSM3K17FU

+V3A

51-,49-,46-,43-,41-,34-,33-,32-,14-,12-,11-,5-

1

R692

200_5%

2

Q513

D

D

G

G

S

S

CHANGE by

INVENTEC

TITLE

Portland 10/10G

SYSTEM POWER(3V/5V)

SIZE REV

CODEOFDOC. NUMBER

A3

CS

SHEET

21-Jun-2006Drawer_Name

768

A021310A2076901

+V5A

R529

12

10_5%

R534

12

SLP_S5#_5R

12-

10K_5%

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,10-,8-

C559

1
2

0.22uF_6.3v

1
2

C553

1uF_6.3v

BAT54_30V_0.2A

R538

12

2.2_5%

13

14

15

17

16

U505

1

VOUT

2

VCCA

3

FB ILIM

4

PGD

TML-PAD

NC

5

NC

BST

TON

EN_PSV

VSSA

6

12

DH

11

LX

10

9

VDDP

DL

PGND

8

7

SEMTECH_SC411MLTRT_MLPQ_16P

+V5A

1

R650

10K_5%

2

C734

0.1uF_10v

61-,60-,55-,46-,34-,12-,11-,9-,7-,8-

C732

1
2

0.1uF_10v

1

R5086

100K_5%

2

+V3S

1
2

+V5A

1

3

D508

C563

0.1uF_25v

R532

12

C552

909K_1%

1
2

1000pF_50v

R5128

12

2.2_5%

R539

12

33.2K_1%

1
2

+V3S

1
2

+V5A

C564

1uF_6.3v

U514

1

POK9TML

2

VEN

36

VIN

4

VPP

GMT_G966_25ADJF1Uf_SOP_8P

C733

4.7uF_6.3v

12

+VBAT

60-,10-,9-,7-,6-,5-

Q19

D1

1
2
8

G1

G2

3

SP8K10SFD5_ROHM

C162

1
2

10uF_25v_K_X5R

8

GND

7

ADJ

VO

5

NC

+V1.8

5

S1_D2

6
7

4

S2

L513

2

1

MPLC0730_4R7

C551

1
2

82pF_50v

1

R527

26.1K_1%

1

C571

2

2

330uF_2v_15mR_Panasonic

1

R528

10K_1%

2

+V2.5S

61-,23-

1
2

C5048

820pF_25v

PAD502

POWERPAD_2_0610

C5049

1
2

0.47uF_6.3v

61-,26-,25-,24-,19-,11-

PAD504

1

R618

POWERPAD_2_0610

OPEN

C717

1

2

2

10uF_6.3v

1

R619

0_5%

2

CHANGE by

INVENTEC

TITLE

Portland 10/10G

SYSTEM POWER (+V2.5S / +VCCP)

SIZE

28-Jul-2006Drawer_Name

A3

CODE

CS

SHEET

DOC. NUMBER

OF

868

REV

A021310A2076901

PWR_GOOD_3

SLP_S3#_5R

11-

1

61-,60-,12-

R36

0_5%

+V5A

R366

R355

1

47K_5%

12

100K_5%

R365

12

10_5%

2

C421

1
2

0.1uF_10v

1
2

C432

1uF_6.3v

17

16

U24

TON

1

VOUT

TML-PAD

2

VCCA

3

FB ILIM

4

PGD

NC

VSSA

6

5

15

EN_PSV

14

NC

PGND

7

BAT54_30V_0.2A 1

12

2.2_5%

13

BST

DH

LX

VDDP

DL

8

SEMTECH_SC411MLTRT_MLPQ_16P

R679

12

11

10

9

+V5A

D39

C426

1
2

1000pF_50v

R354

12

33.2K_1%

1

C418

1uF_6.3v

2

3

C417

0.1uF_25v

909K_1%

+V5A

12

+VBAT

R359

12

60-,10-,8-,7-,6-,5-,9-

Q28

1

D1

2

S1_D2

8

G1

G2

3

S2

SP8K10SFD5_ROHM

C416

1

10uF_25v_K_X5R

2

61-,43-,34-,32-,24-,23-,20-,16-,11-

5

L24

12

1

R5149

4.7_5%

2

1

82pF_50v

2

C5098

2200pF_50v

MPLC0730_4R7

1

C431

2

1

R364

21K_1%

2

1

R372

10K_1%

2

1

10uF_6.3v

2

C398

C403

220uF_2v_15mR_Panasonic

6
7

4

+V1.5S

PAD3

POWERPAD_2_0610

1
2

+V5A

R59

12

100K_5%

10_5%

R48

1

2

2

C27

1
2

OPEN

1
2

C49

1uF_6.3v

17

16

U3

TON

1

VOUT

TML-PAD

2

VCCA

310

FB

4

PGD

NC

VSSA

5

6

15

EN_PSV

14

NC

PGND

7

8

BAT54_30V_0.2AD71

12

2.2_5%

13

BST

DH

LX

ILIM

VDDP

DL

SEMTECH_SC411MLTRT_MLPQ_16P

VCCP_GND

10-

VCCP_GND

MCH_GOOD

R37

12

11

9

VCCP_GND

33.2K_1%

VCCP_GND

+V5A

R35

1

C42

909K_1%

1
2

1000pF_50v

R50

12

1

C51

1uF_6.3v

2

3

2

C28

12

0.1uF_25v

+V5A

+VBAT

60-,10-,8-,7-,6-,5-,9-

Q7

D1

1
2

G1

8

G2

3

SP8K10SFD5_ROHM

C29

1

10uF_25v_K_X5R

2

5

S1_D2

6
7

4

S2

1
2

L505

12

1

R5127

4.7_5%

2

C5053

2200pF_50v

PLC_0755_4R7_5.1A

1

1
2

C41

2

82pF_50v

1

2

VCCP_GND

CHANGE by

R49

22K_1%

R58

20K_1%

1

C53

10uF_6.3v

2

Drawer_Name

34-,31-,24-,23-,21-,20-,16-,15-,14-,13-

PAD501

POWERPAD_2_0610

1

C531

2

220uF_2v_15mR_Panasonic

18-Jul-2006

+VCCP

INVENTEC

TITLE

Portland 10/10G

SYSTEM POWER(+V1.5S / +V1.8)

CODE

SIZE REVDOC. NUMBER

A3

1310A2076901 A02

CS

OFSHEET

689

D5012

VARISTOR_OPEN

12

15-,10-

31-,15-,10-

CPU_SINGNAL_GROUND

PM_DPRSLPVR

12

28K_1%

C35

1
2

18pF_50v

330pF_50v

C24

1000pF_50v

9-,10-

D5013 VARISTOR_OPEN

12

18-,13-,10-

D5014

12

13-,10-

H_VID6
H_VID5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0

9-,10-

+V3S

1

R27

3K_5%

2

18-,13-,10-

13-,10-

C37

0.012uF_16v

12

32-,19-,10-

R32

12

220pF_25v

C25

1

1.65K_1%

2

16-

16-

VARISTOR_OPEN

1uF_10v12

16-

TP501

16­16-

TP504

16­16­16-

TP506

16-

1

CPU_SINGNAL_GROUND

R24

3K_5%

2

12

C38

680pF_50v

R38

12

499_1%

C34

CPU_SINGNAL_GROUND

1

R31

2

VCCSENSE
VSSSENSE

+V5S

55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,18-,12-,10-

R11

2

1

10_5%

C10

TP502

TP500

TP503

TP505

1uF_10v12

R39

12

0_5%

CPU_SINGNAL_GROUND

C11

4700pF_50v

C18

1
2

36

41

40

39

37

TML

VID4

VID0

VID138VID2

EN
PWRGD
PGDELAY
CLKEN

U2

FBRYN

ADI_ADP3207_LFCSP_40P

FB
COMP
SS
STSET
DPRSLP

ILIMIT

11

R34

1

2

+VBAT

C19

12

VRPM

1

2

RRPM

13

1
2

14

1

2

VID3

RAMPADJ

RT

15

1

R25

274K_1%

2

R28

237K_1%

1
2
3
4
5
6
7
8
9

10

C26

1000pF_50v

1
2

82.5K_1%

R33

100K_1%

CPU_SINGNAL_GROUND

60-,9-,8-,7-,6-,5-,10-

1000pF_50v

35

VID534VID6

16

1
2

LLSET

MCH_GOOD

VR_PWRGD_CK410

IMVP_CKEN#

PSI#

H_DPRSTP#

MCH_GOOD

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,8-,10-

VR_PWRGD_CK410

IMVP_CKEN#

1
2

CPU_SINGNAL_GROUND

32

31

33

PSI

VCC

DPRSTP

TTSENSE

VRTT

PWM1
PWM2
PWM3

CSCOMP

CSREF

CSSUM

GND

19

17

18

20

CPU_SINGNAL_GROUND

C13

47pF_50v

C16

1000pF_50v

DCM

OD

SW1
SW2
SW3

H_DPRSTP#

PM_DPRSLPVR

30
29
28
27
26
25
24
23
22
21

C12

1
2

1800pF_50v

PSI#

MCH_GOOD

R20

12

OPEN

R21

1

73.2K_1%

1
2

R17

12

165K_1%

R503

12

357K_1%

R502

12

357K_1%

2

15-,10-

31-,15-,10-

32-,19-,10-

9-,10-

D5009

VARISTOR_OPEN

2

1

VARISTOR_OPEND5010

12

D5011

VARISTOR_OPEN

12

+V5S

55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,18-,12-,10-

3

12

DRVH

DRVL

GND

2.2_5%

BST

SW

D501

R9

10
9
8
7
6

0.22uF_25v

1

2

C5

1
2

4.7uF_6.3v

U1

1

IN

2

SD

3

DRVLSD

4

CROWBAR

5

VCC

ADI_ADP3419_RM_MSOP_10P

+V5S

55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,18-,12-,10-

C510

1
2

4.7uF_6.3v

R14

2.2_5%

U502

1

IN

2

SD

3

DRVLSD

4

CROWBAR

5

VCC

ADI_ADP3419_RM_MSOP_10P

DRVH

DRVL

10

BST

9
8

SW

7

GND

6

SLP_S3#_3R

VR_PWRGD_CK410

BAT54A

C3

1
2

1

C14

1
2

2

0.22uF_25v

49-,37-,32-,12-,11-,7-

18-,13-,10-

+VBAT

60-,9-,8-,7-,6-,5-,10-

1
2

10uF_25v_K_X5R

1
2

D31

CHENMKO_BAT54_3P

12

560K_1%

10uF_25v_K_X5R

C508

C509

1
2

0.1uF_25v

C8

C9

1
2

0.1uF_25v

13

R298

1
2

C502

1

1

2

2

0.1uF_25v

R5124

12

2.2_5%

765

G

4

Q3

FDS6676AS

C505

1

1

2

2

0.1uF_25v

R5125

12

2.2_5%

G

41S23

Q5

FDS6676AS

+V3S

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,13-,12-,11-,8-,10-

5

U17-A

6

1

C370

2

FAIR_NC7WZ17_SC70_6P

0.22uF_10v

765

8

C6

D

Q1

G

RQA130N03

S

4

123

8

65

87

D

D

1

G

S

123

C7

8765

D

41S23

Q4

FDS6676AS

8765

D

G

S

23

41

8

765

D

G

S

3

12

4

Q6

FDS6676AS

2

Q2

RQA130N03

1

D30

49-,32-,19-

1

R5106

4.7_5%

D5016

2

SSM34_3A40V

C5034

1
2

2200pF_50v

1

R5107

D5017

4.7_5%

2

SSM34_3A40V2

C5035

1
2

2200pF_50v

CHENMKO_BAT54_3P

13

R598

12

511K_1%

C369

1
2

0.22uF_10v

SB_3S_VRMPWRGD

L503

12

MPC1040LR45_TOKIN

330uF_2v_6mR

L504

12

MPC1040LR45_TOKIN

0.1uF_16v

5

U17-B

3

4

FAIR_NC7WZ17_SC70_6P

2

1

1

C511

2

2

1

C572

2

330uF_2v_6mR

330uF_2v_6mR

12

C713

C512

330uF_2v_6mR

1

C573

2

330uF_2v_6mR_OPEN

32-

1

2

PM_PWROK

C574

+VCC_CORE

16-

CPU_SINGNAL_GROUND

CHANGE by

Drawer_Name 21-Jun-2006

TITLE

Portland 10/10G

CPU POWER(VCC_CORE)

SIZE

A3

DOC. NUMBER

CODE

1310A2076901 A02

CS

SHEET

REV

OF

6810

SLP_S5#_3R
SLP_S3#_3R

M_VREF

49-,46-,32-,12-

49-,37-,32-,12-,10-,7-

26-,25-,19-

+V1.5S

61-,43-,34-,32-,24-,23-,20-,16-,9-

R89

12

1K_5%

+V5A

1
2

0.1uF_10v

2

1uF_10v

C219

C218

1

+V3A

51-,49-,46-,43-,41-,34-,33-,32-,14-,12-,7-,5-

1

R88

1K_5%

2

12

100K_5%

Q10

3

C

2

B

E

1

2SC2411K

D10CHENMKO_BAT54_3P

13
R87

1
2

U11

11

VDDQSNS

GND

10 2

VIN

VLDOIN

9

S5
GND
S3
VTTREF

PGND

VTTSNS

VTT

8
7
6

TI_TPS51100_DGQ_10P

+V3S

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,13-,12-,10-,8-

5

U5

24

TC7SH14F

3

C52

0.1uF_10v

+V0.9S

27-

+V1.8

61-,26-,25-,24-,19-,8-61-,60-,55-,46-,34-,12-,9-,8-,7-

1

3
4
5

C189

22uF_6.3v

1

R51

100K_5%

2

1
2

9-

C199

22uF_6.3v

PWR_GOOD_3

1
2

CHANGE by

Drawer_Name 21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

+V0.9S / POWER GOOD

CODE

DOC. NUMBER REVSIZE

A3

1310A2076901 A02

CS

SHEET OF

6811

SLP_S3#_5R

R336

200_5%

CHENMKO_BAT54_3P

61-,60-,9-

51-,49-,46-,43-,41-,34-,33-,32-,14-,11-,7-,5-

+V5S

55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,18-,10-,12-

R343

1

2

200_5%

CHENMKO_BAT54_3P

8-

D35

SLP_S5#_5R

1

3

U22-A

74ACT14MTC

1

2

CHENMKO_BAT54_3P

1

3

D36

61-,60-,55-,46-,34-,11-,9-,8-,7-,12-

U22-B

74ACT14MTC

+V5A

61-,60-,55-,46-,34-,11-,9-,8-,7-,12-

14

12

7

61-,60-,55-,46-,34-,11-,9-,8-,7-,12-

+V5A

14

7

+V5A

D38

3

1

34

C406

12

0.1uF_10v

Q511

1

786

D1

S1

2G14

FDS6875

1

R351

220K_5%

2

49-,37-,32-,11-,10-,7-

SLP_S5_3R

74ACT14MTC

3

5

D2

S2

G2

SLP_S3#_3R

U22-C

6

+V3+V3A

55-,54-,43-

1

C747

2

C735

1
2

OPEN

61-,60-,55-,46-,34-,11-,9-,8-,7-,12-

9

14

5

7

47uF_4v

+V5A

220K_5%

14

U22-D

7

49-,46-,32-,11-

R639

12

8

74ACT14MTC

12

+V3S

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,13-,11-,10-,8-

1

C736

2

BAT54A

D513

1

2

R640

220K_5%

SLP_S5#_3R

47uF_4v

R641

200_5%

C756

1
2

0.01uF_16v

3

2

1

R665

200_5%

2

1

Q512

D

D

G

G

SSM3K17FU

S

S

+V5A

61-,60-,55-,46-,34-,11-,9-,8-,7-,12- 55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,18-,10-,12-

4

3

SI3433BDV

4

SI3433BDV

C730

680pF_50v

R719

12

OPEN

R720

2

1

220K_5%

Q509

D

S

G

Q27

D

S

G

12

D515

3

BAT54_OPEN

+V5S

1
2
5
6

1
2
5
63

C807

4

3

1

SI3433BDV

C801

1
2

0.01uF_16v

S

12

Q516

OPEN

G

61-

SLP_S3_5R

+VAUDIO_5S

1

D

2
5
6

53-,52-

CHANGE by

INVENTEC

TITLE

Portland 10/10G

POWER(SLEEP)

CODE

SIZE REV

21-Jun-2006Drawer_Name

A3

CS

SHEET

DOC. NUMBER

OF

12 68

A021310A2076901

CPU_BSEL1

MCH_BSEL1

CPU_BSEL2

CLK_R3S_ICH14

VR_PWRGD_CK410

C5099

1
2

15-

19­19-,15-

1000pF_50v

+VCCP

2

R656

OPEN

1

2

R657

1K_5%

1

R655

1K_5%

2

1

R611

10K_5%

12

R612

24.9_1%

R613

10K_5%

10-

18-,10-

34-,31-,24-,23-,21-,20-,16-,15-,14-,9-

32-

IMVP_CKEN#

SSM3K17FU_OPEN

Layout note: All decoupling 0.047uF disperse closed to pin

C721

C716

1

1

2

2

10uF_6.3v

10uF_6.3v

1
2

C726

0.047uF_10v

+V3S

CPU_BSEL0

R635

10K_5%

2

1

Q510
G

G

+V3S

D

S

BSEL0

D

S

FSA

1

2

2

R661

OPEN

BSEL1

FSB

1

2

1 0 0
1 1 0

CLK_R3S_ICH48

CLK_R3S_CARD48

1

12

R615 10K_5%

12

R616 OPEN

LAYOUT NOTES : THE IREF(PIN_46) SIGNAL VIA R715 CONNECT TO GND DIRECTLY.

BSEL2

FSB CLOCK

FREQUENCY

FSC

533
667

2

0.047uF_10v

0.047uF_10v

C728

C722

1

1

2

Please place close to CLKGEN within 500mils

C715

33pF_50v

R643

19-,15-

R638
R642

32-

R660

36-

CLK_R3S_CBPCI
CLK_R3S_KBPCI

CLK_R3S_MINICARDPCI

CLK_R3S_1394PCI

CLK_R3S_TPMPCI

CLK_R3S_KBC14

ICH_3S_SMDATA

ICH_3S_SMCLK

CLK_R3S_ICHPCI

1

R606

4.7K_1%

2

HOST CLOCK

FREQUENCY

133
166

C712

1
2

0.047uF_10v

30PPM

X501

1

1

14.31818MHZ

2

2

1

10K_5%

12

10K_5%

12

12.1_1%

12

12.1_1%

36­49­43­39­48-

49-

32-,26-,25-

32-,26-,25-

33-

CLKREQA#

CLKREQB#
CLKREQC#
CLKREQD#

+V3S_CLKVDD

C714

0.047uF_10v

1

C723

33pF_50v

2

12
12
12
12
12
12

12

12
12
12

C727

1
2

0.047uF_10v

CLK_3S_ICH48

OPEN

24.9_1%

12.1_1%

12.1_1%

24.9_1%R648

24.9_1%

10K_5%
OPEN

1
2

2

R647
R646
R5085

R649

R624

R614 24.9_1%

R623
R645
R644 24.9_1%

CLK_REQB#

1

R5081

10K_5%

2

SRCCLK8

X

NFM40P12C223

L522

CLK_BSEL1
CLK_BSEL2

CLK_3S_CBPCI

CLK_3S_MINIPCI

CLK_3S_1394PCI

CLK_3S_TPMPCI

CLK_3S_KBC14

CLK_3S_ICHPCI

43-

X

+V3S

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,12-,11-,10-,8-,13-

1

1

4

BLM11A121S

L525

3

2

2

C737

1
2

0.047uF_10v

U513

24

VDDSRC

41

VDDSRC

5

12

0_5%R617

SRCCLK6

X

VDDPCI

10

VDD48

16

VDD

33

VDDSRC

50

VDDCPU

57

X1

56

X2

11

FSLA_USB_48MHZ

15

FSLB_TEST_MODE

59

REF1_FSLC_TEST_SEL

6

PCICLK6

2

PCICLK4

3

PCICLK5

1

PCI_REFSEL_PCICLK3

62

SEL_REQ_PCICLK2

60

REF0_PCICLK1

54

SDATA

53

SCLK

7

SELSRC_LCDCLK#_PCICLK_F1

9

Vtt_PwrGd#_PD

46

VREF

64

CLKREQA#

63

CLKREQB#

4

GND

12

GND

40

GNDSRC

58

GND

17

GND

25

GNDSRC

32

GNDSRC

47

GNDCPU

ICS_ICS9LPR316_TSSOP_64P

SRCCLK5

X

PCI_SRC_STOP#

CPU_STOP#

CPUCLKC0

CPUCLKT2_ITP_CLKREQC#

CPUCLKC2_ITP_CLKREQD#

SRCCLKC5

SRCCLKC8

SRCCLKC7

SRCCLKC6

SRCCLKC4

SRCCLKC3

SRCCLKC2

SRCCLKC1

LCDCLK_SST_SRCCLKT0

LCDCLK_SSC_SRCCLKC0

DOTT_96MHZ
DOTC_96MHz

SRCCLK4

X

1
2

10uF_6.3v

VDDREF

CPUCLKT0

CPUCLKT1

CPICLKC1

SRCCLKT5

SRCCLKT8

SRCCLKT7

SRCCLKT6

SRCCLKT4

GNDSRC
GNDSRC

SRCCLKT3

SRCCLKT2

SRCCLKT1

SRCCLK3

X

C738

55

8
61

52

CLK_CPUBCLK
CLK_CPUBCLK#

51

CLK_MCHBCLK

49

CLK_MCHBCLK#

48

45
44

35

CLK_PEG_REF

CLK_PEG_REF#

34

CLK_PEG_MCH

43

CLK_PEG_MCH#

42

39
38

CLK_PCIE_ICH

37

CLK_PCIE_ICH#

36

CLK_SATA1

30
31

CLK_SATA1#

R628

28

R627

29

CLK_PCIE_MINI1

26
27

CLK_PCIE_MINI1#
CLK_PCIE_LAN

22

CLK_PCIE_LAN#

23

20
21

SSCLK1_DREF

18

SSCLK1_DREF#

19

CLK_DREF

13

CLK_DREF#

14

12
12

SRCCLK2

X

0_5%
0_5%

SRCCLK1

X

32-

PCISTOP#_3

32-

12

12.1_1%R610

12

R609

R608

R607 12.1_1%

12.1_1%

12

12.1_1%

12

+V3S

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,18-,12-,11-,10-,8-,13-

1

R5082

10K_5%

2

12

R601 24.9_1%

12

24.9_1%R600

12

R605

R604 24.9_1%

R603 24.9_1%

R625 24.9_1%

R629

R632 24.9_1%

R633 24.9_1%

R637 24.9_1%

Close to CLKGEN

SRCCLK0SRCCLK7

X

24.9_1%

12

12
12

24.9_1%R602

12

24.9_1%R626

12

12

24.9_1%R630

12

24.9_1%

12
12

24.9_1%R631

12

24.9_1%R634

12

12
12

24.9_1%R636

CPUSTOP#_3

14-

CLK_R_CPUBCLK

14-

CLK_R_CPUBCLK#

21-

CLK_R_MCHBCLK

21-

CLK_R_MCHBCLK#

19-

MCH_CLK_REQ#

63-

CLK_R_PEG_REF

63-

CLK_R_PEG_REF#

19-

CLK_R_PEG_MCH

19-

CLK_R_PEG_MCH#

32-

CLK_R_PCIE_ICH

32-

CLK_R_PCIE_ICH#

31-

CLK_R_SATA1

31-

CLK_R_SATA1#

43-

CLK_R_PCIE_MINI1

43-

CLK_R_PCIE_MINI1#

40-

CLK_R_PCIE_LAN

40-

CLK_R_PCIE_LAN#

19-

SSCLK1_R_DREF

19-

SSCLK1_R_DREF#

19-

CLK_R_DREF

19-

CLK_R_DREF#

R654

R653
R659

R658

12

12
12

12

OPEN

OPEN
OPEN

OPEN

CHANGE by

INVENTEC

TITLE

Portland 10/10G

CLOCK_GENERATOR

CODE

CS

SHEET

DOC. NUMBER

13 68

SIZE

21-Jun-2006Drawer_Name

A3

REV

A021310A2076901

OF

H_A#(31:3)

H_STPCLK#

21-

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)
H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)

H_REQ#(4:0)

H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)

31-

H_A20M#

31-

H_FERR#

31- 31-,19-,18-

H_IGNNE#

31­31-

H_INTR

31-

H_NMI

31-

H_SMI#

21-

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

H_ADSTB#0

H_ADSTB#1

21-

21-

CN505-1

J4

A3#

L4

A4#

M3

A5#

K5

A6#

M1

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L1

A13#

P4

A14#

P1

A15#

R1

A16#

L2

K3
H2
K2

J3
L5

Y2
U5
R3

W6

U4
Y5
U2
R4

T5

T3
W3
W5

Y4

W2

Y1
V4

A6
A5
C4

D5
C6
B4
A3

AA1
AA4
AB2
AA3

M4
N5

T2

V3
B2
C3

B25

ADDR GROUP 0ADDR GROUP 1

ADSTB0#

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#

A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#
ADSTB1#

A20M#
FERR#
IGNNE#

STPCLK#
LINT0
LINT1
SMI#

RSVD01
RSVD02
RSVD03
RSVD04
RSVD05
RSVD06
RSVD07
RSVD08
RSVD09
RSVD10

RSVD11

FOX_PZ47823_2743_01_478P

CONTROL

XDP/ITP SIGNALS

PROCHOT#

THERMDA
THERMDC

THERM

THERMTRIP#

H CLK

RESERVED

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

TRST#

DBR#

BCLK0
BCLK1

RSVD12

RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18
RSVD19
RSVD20

INIT#

HIT#

TCK

TDO
TMS

H1
E2
G5

H5
F21
E1

F1

D20
B3

H4

B1
F3
F4
G3
G2

G6
E4

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6

TDI

AB3
AB5
AB6
C20

D21
A24
A25

C7

A22
A21

T22

D2
F6
D3
C1
AF1
D22
C23
C24

12

R139

56_5%

34-,31-,24-,23-,21-,20-,16-,15-,13-,9-,14-

10mils/10mils

CPU

+VCCP

18-

H_THERMDA

18-

H_THERMDC

PM_THRMTRIP#

13-

CLK_R_CPUBCLK

13-

CLK_R_CPUBCLK#

21­21­21-

21­21­21-

21-

31-

21-

21-

21-

21­21-

ICH7GMCH

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BREQ#0

H_INIT#

H_LOCK#

H_CPURST#

H_TRDY#
H_HIT#

H_HITM#

H_RS#(0)
H_RS#(1)
H_RS#(2)

1

2

+VCCP

R56

56_5%

21-

H_RS#(0:2)

+V3A

51-,49-,46-,43-,41-,34-,33-,32-,12-,11-,7-,5-

1

1

R137

R41

240_5%

56_5%

2

2

1

R42

56_5%

2

+VCCP

34-,31-,24-,23-,21-,20-,16-,15-,13-,9-,14-

1

R138

56_5%

2

CLOSED TO CPU

+VCCP

34-,31-,24-,23-,21-,20-,16-,15-,13-,9-,14-

1

1

R40

R55

56_5%

56_5%

2

2

32-

H_BPM5_PREQ#
H_TCK
TDI_FLEX

H_TMS
H_TRST#
ITP_DBRESET#

PM_THRMTRIP# should be without T at CPU

CHANGE by

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

Yonah-1

SIZE

CODE

CS

SHEET

DOC. NUMBER

14 68

A3

REV

A021310A2076901

OF

H_D#(63:0)

H_DSTBN#0
H_DSTBP#0

H_DINV#0

H_D#(63:0)

+VCCP

34-,31-,24-,23-,21-,20-,16-,14-,13-,9-,15-

1

R507

1K_1%

2

H_GTLREF

1

R506

2K_1%

CLOSED TO CPU WITHIN 0.5"

2

21-,15-

21­21­21-

21-,15-

H_DSTBN#1
H_DSTBP#1

H_DINV#1

CN505-2

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)

H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)

21­21­21-

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

19-,13­13­19-,13-

1

R533

OPEN

2

1

R530

51_5%

2

E22

D0#

F24

D1#

E26

D2#

H22

D3#

F23

D4#

G25

D5#

E25

D6#

E23

D7#

K24

D8#

G24

D9#

J24

D10#

J23

D11#

H26

D12#

DATA GRP 0DATA GRP 1

F26

D13#

K22

D14#

H25

D15#

H23

DSTBN0#

G22

DSTBP0#

J26

DINV0#

N22

D16#

K25

D17#

P26

D18#

R23

D19#

L25

D20#

L22

D21#

L23

D22#

M23

D23#

P25

D24#

P22

D25#

P23

D26#

T24

D27#

R24

D28#

L26

D29#

T25

D30#

N24

D31#

M24

DSTBN1#

N25

DSTBP1#

M26

DINV1#

AD26

GTLREF

C26

TEST1

D25

B22
B23
C21

MISC

TEST2

BSEL0
BSEL1
BSEL2

FOX_PZ47823_2743_01_478P

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#

DATA GRP 2DATA GRP 3

D45#
D46#

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#

COMP0
COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
W24
Y25
V23

AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
AD23
AE24
AC20

R26
U26
U1
V1

E5
B5
D24
D6
D7
AE6

CPU_COMP0
CPU_COMP1
CPU_COMP2
CPU_COMP3

R517 54.9_1%

R70 54.9_1%

31-,10-

H_DPRSTP#

COM0, COM2, trace impedance

NOTE:

should be 27.4 ohm
COM1, COM3, trace impedance

should be 55 ohm

H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)

H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

12

27.4_1%R518

12
12

27.4_1%R71

12

CLOSED TO CPU

31­21-

31-,21-

10-

21­21­21-

H_DPSLP#
H_DPWR#

H_CPUSLP#
PSI#

H_DSTBN#3
H_DSTBP#3
H_DINV#3

21-,15-

H_D#(63:0)

21-

H_DSTBN#2

21-

H_DSTBP#2

21-

H_DINV#2

21-,15-

H_D#(63:0)

+VCCP

34-,31-,24-,23-,21-,20-,16-,14-,13-,9-,15-

2

R541

OPEN

1

CLOSED TO CPU

31-

H_PWRGD

CHANGE by

INVENTEC

TITLE

Portland 10/10G

Yonah-2

CS

SHEET

DOC. NUMBER

OF

15 68

REV

A021310A2076901

SIZE CODE

21-Jun-2006Drawer_Name

A3

PLACE THESE INSIDE SOCKET

CAVITY ON L8 (NORTH SIDE

SECONDARY)

PLACE THESE INSIDE SOCKET

CAVITY ON L8 (SOUTH SIDE

SECONDARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (NORTH SIDE
PRIMARY)

PLACE THESE INSIDE SOCKET
CAVITY ON L1 (SOUTH SIDE
PRIMARY)

1
2

1
2

1
2

1
2

1
2

1
2

C545

22uF_6.3v

C548

22uF_6.3v

C110

22uF_6.3v

C60

22uF_6.3v

C115

OPEN

C550

OPEN

1
2

1
2

1
2

1
2

1
2

C528

22uF_6.3v

C547

22uF_6.3v

C111

22uF_6.3v

C113

22uF_6.3v

C90

OPEN

1
2

1
2

1
2

1
2

C525

22uF_6.3v

C529

22uF_6.3v

C112

22uF_6.3v

C59

22uF_6.3v

1
2

1
2

1
2

1
2

1
2

1
2

1
2

+VCC_CORE +VCC_CORE

10-,16-

CN505-3

A7

VCC001

A9

VCC002

C526

22uF_6.3v

C527

1
2

22uF_6.3v

C546

22uF_6.3v

C549

1
2

22uF_6.3v

C56

22uF_6.3v

C57

1
2

22uF_6.3v

C114

22uF_6.3v

C58

1 0.1uF_10v
2

22uF_6.3v

C530

NOTE:

NO_STUFF

OPEN

22UF X 12

C101

OPEN

C61

OPEN

A10

VCC003

A12

VCC004

A13

VCC005

A15

VCC006

A17

VCC007

A18

VCC008

A20

VCC009

B7

VCC010

B9

VCC011

B10

VCC012

B12

VCC013

B14

VCC014

B15

VCC015

B17

VCC016

B18

VCC017

B20

VCC018

C9

VCC019

C10

VCC020

C12

VCC021

C13

VCC022

C15

VCC023

C17

VCC024

C18

VCC025

D9

VCC026

D10

VCC027

D12

VCC028

D14

VCC029

D15

VCC030

D17

VCC031

D18

VCC032

E7

VCC033

E9

VCC034

E10

VCC035

E12

VCC036

E13

VCC037

E15

VCC038

E17

VCC039

E18

VCC040

E20

VCC041

F7

VCC042

F9

VCC043

F10

VCC044

F12

VCC045

F14

VCC046

F15

VCC047

F17

VCC048

F18

VCC049

F20

VCC050

AA7

VCC051

AA9

VCC052

AA10

VCC053

AA12

VCC054

AA13

VCC055

AA15

VCC056

AA17

VCC057

AA18

VCC058

AA20

VCC059

AB9

VCC060

AC10

VCC061

AB10

VCC062

AB12

VCC063

AB14

VCC064

AB15

VCC065

AB17

VCC066

AB18

VCC067

FOX_PZ47823_2743_01_478P

VCC068
VCC069
VCC070
VCC071
VCC072
VCC073
VCC074
VCC075
VCC076
VCC077
VCC078
VCC079
VCC080
VCC081
VCC082
VCC083
VCC084
VCC085
VCC086
VCC087
VCC088
VCC089
VCC090
VCC091
VCC092
VCC093
VCC094
VCC095
VCC096
VCC097
VCC098
VCC099

VCC0100

VCCP01
VCCP02
VCCP03
VCCP04
VCCP05
VCCP06
VCCP07
VCCP08
VCCP09
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16

VCCA

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

V6
G21
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26

AD6

VID0

AF5

VID1

AE5

VID2

AF4

VID3

AE3

VID4

AF2

VID5

AE2

VID6

AF7

AE7

+VCCP

10-,16-

+VCCP

34-,31-,24-,23-,21-,20-,15-,14-,13-,9-

C541

1
2

34-,31-,24-,23-,21-,20-,15-,14-,13-,9-

1

C89

2

330uF_2.5v

0.1uF_10v

+V1.5S

61-,43-,34-,32-,24-,23-,20-,11-,9-,16-

10-

H_VID0

10-

H_VID1

10­10­10­10­10-

R30

10_1%

+VCC_CORE

H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

1

2

10-,16-

1

R10

10_1%

2

10-

VCCSENSE

10-

VSSSENSE

LAYOUT NOTE:

ROUTE VCCSENSE AND VSSSENSE TRACE AT

27.4 OHM WITH 50 MIL SPACING.
PLACE PU AND PD WITHIN 1 INCH OF CPU

C540

1
2

0.1uF_10v

PLACE THESE INSIDE SOCKET
CAVITY ON L8 SIDE (NORTH SIDE

SECONDARY)

C536

1
2

0.1uF_10v

C535

C538

1

1

2

2

0.1uF_10v

+V1.5S

61-,43-,34-,32-,24-,23-,20-,11-,9-,16-

C569

1
2

10uF_6.3v

1
2

LAYOUT NOTE:
PLACE C119 NEAR PIN B26

1
2

C558

0.01uF_16v

C537

0.1uF_10v

CHANGE by

Drawer_Name 21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

Yonah-3

SIZE

A3

DOC. NUMBER

1310A2076901 A02

CS

SHEET

REVCODE

OF

6816

CN505-4

A4

VSS001

A8

VSS002

A11

VSS003

A14

VSS004

A16

VSS005

A19

VSS006

A23

VSS007

A26

VSS008

B6

VSS009

B8

VSS010

B11

VSS011

B13

VSS012

B16

VSS013

B19

VSS014

B21

VSS015

B24

VSS016

C5

VSS017

C8

VSS018

C11

VSS019

C14

VSS020

C16

VSS021

C19

VSS022

C2

VSS023

C22

VSS024

C25

VSS025

D1

VSS026

D4

VSS027

D8

VSS028

D11

VSS029

D13

VSS030

D16

VSS031

D19

VSS032

D23

VSS033

D26

VSS034

E3

VSS035

E6

VSS036

E8

VSS037

E11

VSS038

E14

VSS039

E16

VSS040

E19

VSS041

E21

VSS042

E24

VSS043

F5

VSS044

F8

VSS045

F11

VSS046

F13

VSS047

F16

VSS048

F19

VSS049

F2

VSS050

F22

VSS051

F25

VSS052

G4

VSS053

G1

VSS054

G23

VSS055

G26

VSS056

H3

VSS057

H6

VSS058

H21

VSS059

H24

VSS060

J2

VSS061

J5

VSS062

J22

VSS063

J25

VSS064

K1

VSS065

K4

VSS066

K23

VSS067

K26

VSS068

L3

VSS069

L6

VSS070

L21

VSS071

L24

VSS072

M2

VSS073

M5

VSS074

M22

VSS075

M25

VSS076

N1

VSS077

N4

VSS078

N23

VSS079

N26

VSS080

P3

VSS081

FOX_PZ47823_2743_01_478P

VSS082
VSS083
VSS084
VSS085
VSS086
VSS087
VSS088
VSS089
VSS090
VSS091
VSS092
VSS093
VSS094
VSS095
VSS096
VSS097
VSS098

VSS099
VSS0100
VSS0101
VSS0102
VSS0103
VSS0104
VSS0105
VSS0106
VSS0107
VSS0108
VSS0109
VSS0110
VSS0111
VSS0112
VSS0113
VSS0114
VSS0115
VSS0116
VSS0117
VSS0118
VSS0119
VSS0120
VSS0121
VSS0122
VSS0123
VSS0124
VSS0125
VSS0126
VSS0127
VSS0128
VSS0129
VSS0130
VSS0131
VSS0132
VSS0133
VSS0134
VSS0135
VSS0136
VSS0137
VSS0138
VSS0139
VSS0140
VSS0141
VSS0142
VSS0143
VSS0144
VSS0145
VSS0146
VSS0147
VSS0148
VSS0149
VSS0150
VSS0151
VSS0152
VSS0153
VSS0154
VSS0155
VSS0156
VSS0157
VSS0158
VSS0159
VSS0160
VSS0161
VSS0162

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
AF3
AF6
AF8
AF11
AF13
AF16
AF19
AF21
AF24

CHANGE by

INVENTEC

TITLE

Portland 10/10G

Yonah-4

CS

SHEET

DOC. NUMBER

OF

17 68

REVCODE

A021310A2076901

SIZE

21-Jun-2006Drawer_Name

A3

FAN1_DAC0_3

+V5LA

51-,7-,6-,5-

49-

R136

12

150_5%

C155

0.1uF_10v

C719

2.2uF_10v

1
2

1
2

+V5S

55-,50-,49-,45-,44-,38-,37-,34-,32-,30-,28-,12-,10-

1
2

GMT_G995P1U_SOP8_8P

C725

2.2uF_10v

5

43

HYST

GMT_G708T1U_SOT23_5P

U512

2

3

4

CN510

1

VCC

2

GND

3

REFENCE

MLX_53398_0371_3P

FAN CN

SETVCC

GND

OT

81

FON

GND

7

VIN

GND

6

VO

GND

5

VSET

GND

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,19-,13-,12-,11-,10-,8-

+V3S

G1

U9

1

2

G

G2

G

R135

12

27.4K_1%

63-,49-,7-,18-

1

R622

10K_5%

2

C720

1
2

0.01uF_50v

THRM_SHUTDWN#

49-

FAN_TACH1

PM_THRMTRIP#

VR_PWRGD_CK410

R153

12

31-,19-,14-

330_5%

13-,10-

Q18

2

2SC2411K

+V3LA

55-,51-,49-,31-,7-

U536

1

VDD

2

BBUS

1

R127

2M_5%

2

49-

GND

3

BBUS

SMSC_EMC1212_SOT23_5P

SSM3K17FU

3

C

B

E

1

C158

1
2

OPEN

DN

DP

Q17

G

G

5

4

63-,49-,7-,18-

D

D

S

S

14-

14-

H_THERMDC

H_THERMDA

THRM_SHUTDWN#

Thermal Sensor For CPU

CHANGE by

Drawer_Name

21-Jun-2006

INVENTEC

TITLE

Portland 10/10G

THERMAL&FAN CONTROLLER

CODE

CS

SHEET

DOC. NUMBER

1310A2076901

OF

SIZE

A3

REV

A02

6818

AW41

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

AY41

AW1

AY1

A39

A40

A4

NC10B2NC11

NC12

NC13

NC17A3NC18

NC14

NC15

NC16

BA41

BA40

BA39

01

BA3

BA2

BA1

B41

NC9

NC8

C41

D1

C1

NC3

NC4

NC5

NC0

NC1

NC2

NC6

NC7

MCH_ICH_SYNC#

MCH_CLK_REQ#

PLT_RST#

13-

33-

100_5%

R694

K28

H32

H28

H27

ICH_SYNC#

CLK_REQ#

RSTIN#

SDVO_CTRLCLK

SDVO_CTRLDATA

PM_DPRSLPVR

PM_EXTTS#0

26-,25-

32-,10-

R168

R122

1

12

2

0_5%

0_5%

SB_3S_VRMPWRGD

PM_THRMTRIP#

2

2

BM_BUSY#

MCH_CFG(20)

31-,18-,14-

55-,49-,33-

49-,32-,10-

32-

12

AH33

AH34

G28

H26

F25

J26

G6

CFG_19

CFG_20

PM_BMBUSY#

PM_EXTTS#_0

PM_EXTTS#_1

PM_THRMTRIP#

PWROK

10K_5%

R169

1

10K_5%

R123

1

MCH_CFG(19)

MCH_CFG(18)

MCH_CFG(17)

MCH_CFG(16)

G18

K27

H15

J25

CFG_15

CFG_16

CFG_17

CFG_18

+V3S

MCH_CFG(15)

MCH_CFG(14)

MCH_CFG(13)

MCH_CFG(12)

MCH_CFG(11)

G15

C15

H16

K15

CFG_14

CFG_11

CFG_12

CFG_13

MCH_CFG(20:3)

19-

MCH_CFG(9)

MCH_CFG(8)

MCH_CFG(10)

G16

D16

D15

E16

CFG_8

CFG_9

CFG_10

MCH_CFG(7)

MCH_CFG(6)

MCH_CFG(5)

MCH_CFG(4)

D19

E18

E15

F15

CFG_6

CFG_7

CFG_4

CFG_5

MCH_BSEL1

13-

MCH_CFG(3)

MCH_BSEL2

K18

F18

J18

CFG_2

CFG_3

CFG_0

CFG_1

2

R72

1K_5%

MCH_BSEL0

2

1K_5%

K16

1

R74

D27

RSVD_13

1

RSVD_12

CPU_BSEL0

CPU_BSEL2

15-,13-

15-,13-

A41

A35

A34

D28

RSVD_8

RSVD_9

RSVD_10

RSVD_11

J19

RSVD_7

H7

RSVD_6

AF11

AG11

RSVD_4F7RSVD_5

RSVD_2F3RSVD_3

R32

T32

RSVD_1

U506-2

CHANGE by

Drawer_Name

(FSB Dynamic

MCH_CFG(16)

ODT)

Lane

LOW=Dynamic ODT

HIGH=Dynamic ODT

Disable

Enabled

NC

DMI

DMI_TXP_1

DMI_TXP_2

DMI_TXP_3

AF37

AG41

DMI_RXP(3)

DMI_RXP(2)

PCIE Graphics

MCH_CFG(9)

HIGH=Normal operation

LOW=Reverse Lane

DMI_TXN_3

DMI_TXP_0

AC37

AE41

DMI_RXP(1)

DMI_RXP(0)

32-

DMI_RXP(3:0)

HIGH=DMIx4

DMI_TXN_0

DMI_TXN_1

DMI_TXN_2

AE37

AF41

AG37

AH41

DMI_RXN(1)

DMI_RXN(3)

DMI_RXN(2)

MCH_CFG(5)

LOW=DMIx2

MISC

DMI_RXP_2

DMI_RXP_3

AF35

AG39

DMI_RXN(0)

DMI_TXP(3)

DMI_TXP(2)

32-

DMI_RXN(3:0)

DMI_RXP_1

DMI_RXP_0

AC35

AE39

DMI_TXP(1)

DMI_TXP(0)

32-

DMI_TXP(3:0)

2

OPEN

2

OPEN

DMI_RXN_1

DMI_RXN_2

DMI_RXN_3

AG35

AH39

DMI_TXN(3)

DMI_TXN(2)

MCH_CFG(5)

MCH_CFG(6)

19-

1

R79

1

R110

PM

CLK

D_REFSSCLKIN

DMI_RXN_0

D41

AE35

AF39

13-

SSCLK1_R_DREF

DMI_TXN(1)

DMI_TXN(0)

32-

DMI_TXN(3:0)

MCH_CFG(10)

MCH_CFG(11)

MCH_CFG(7)

MCH_CFG(9)

19-

19-

19-

19-

19-

D_REFSSCLKIN#

D_REFCLKIN#

D_REFCLKIN

G_CLKIN#

G_CLKIN

A26

A27

C40

AG33

AF33

13-

13-

13-

13-

13-

CLK_R_DREF#

CLK_R_DREF

CLK_R_PEG_MCH#

CLK_R_PEG_MCH

SSCLK1_R_DREF#

2

0.47uF_6.3v
C73

2

80.6_1%

MCH_CFG(13)

MCH_CFG(12)

MCH_CFG(16)

19-

19-

19-

SM_OCDCOMP_1

SM_ODT_2

SM_ODT_3

AY20

AU21

27-,26-

27-,26-

M_ODT3

M_ODT2

80.6_1%

R133

SM_ODT_0

SM_ODT_1

BA13

BA12

27-,25-

27-,25-

M_ODT1

M_ODT0

1

SM_OCDCOMP_0

SM_CS#_3

AF10

AL20

M_CS3#

+V1.8

SM_VREF_0

SM_VREF_1

AK1

AK41

26-,25-,11-

1

SM_RCOMP#

SM_RCOMP

AT9

AV9

MCH_SMRCOMPN

2

M_VREF

M_OCDCOMP0

M_OCDCOMP1

OPEN

1

2

1

R228

R132

mode)

(PCIE Backward

Interpoerability

operational

simultaneously via the PEG port

HIGH=SDVO and PCIE x1 are operating

1

2

OPEN

R125

MCH_CFG(20)

LOW=Only SDVO or PCIE x1 is

MCH_CFG(18)

(VCC Select)

HIGH=1.5V

LOW=1.05V

RSVDCFG

DDR MUXING

SM_CKE_3

SM_CKE_0

SM_CKE_1

SM_CKE_2

AW13

BA29

AY29

27-,26-

27-,25-

27-,26-

M_CKE3

M_CKE2

MCH_CFG(20)

SM_CK#_3

AU20

AT20

27-,25-

27-,25-

M_CKE1

M_CKE0

M_CLK_DDR4#

MCH_CFG(18)

MCH_CFG(19)

SM_CS#_1

SM_CS#_2

AY21

AW21

27-,26-

27-,26-

M_CS2#

M_CS1#

SM_CS#_0

AW12

27-,25-

M_CS0#

SM_CK#_0

SM_CK#_1

SM_CK#_2

SM_CK_3

AW40

AW35

AT1

AY7

AY40

26-

25-

25-

26-

26-

M_CLK_DDR3#

M_CLK_DDR1#

M_CLK_DDR0#

M_CLK_DDR4

SM_CK_0

SM_CK_1

SM_CK_2

AY35

AR1

AW7

26-

25-

25-

M_CLK_DDR3

M_CLK_DDR1

M_CLK_DDR0

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,20-,18-,13-,12-,11-,10-,8-,19-

21-Jun-2006

SIZE

A3

CODE

CS

SHEET

1310A2076901 A02

DOC. NUMBER

OF

6819

REV

Calistoga-1

TITLE

INVENTEC

Portland 10/10G

SELECT

MCH_CFG(10)

HOST PLL VCO

LOW=RESERVED

HIGH=MOBILITY

MCH_CFG(11)

HIGH=Reserved

LOW=Calistoga

MCH_CFG(6)

(DDR)

LOW=Moby Dick

HIGH=Calistoga

MCH_CFG(7)

(CPU Strap)

HIGH=Mobile CPU

LOW=RSVD

2

OPEN

2

OPEN

2

OPEN

2

2.2K_5%

2

OPEN

2

OPEN

2

OPEN

R109

R75

R77

R76

R73

R80

R78

19-

19-

1

1

1

1

1

1

1

REVERSAL)

(DMI LANE

MCH_CFG(19)

HIGH=LANES REVERSED

LOW=Normal

19-

+V3S

1

2

R158

OPEN

1

2

OPEN

R185

1

2

R167

OPEN

LVDS_R_TXCL-

LVDS_R_TXCL+

LVDS_R_TXCU-

LVDS_R_TXCU+

LVDS_R_TXDL0-

LVDS_R_TXDL0+

LVDS_R_TXDL1-

LVDS_R_TXDL1+

LVDS_R_TXDL2­LVDS_R_TXDL2+

LVDS_R_TXDU0-

LVDS_R_TXDU0+

LVDS_R_TXDU1-

LVDS_R_TXDU1+

LVDS_R_TXDU2-

LVDS_R_TXDU2+

+VCCP

RS505

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

63-,30­63-,30-

34-,31-,24-,23-,21-,16-,15-,14-,13-,9-,20-

1

R155

OPEN

2

1

R154

0_5%

CLOSE TO CALISTOGA

2

4

1
23

0_5%

RS501

1

4

23

0_5%

RS508

1

4

23

0_5%

RS506

1

4

23

0_5%

RS507

1

4

2

3

0_5%

RS503

1

4

23

0_5%

RS504

4

1
23

0_5%

RS502

1

4

23

0_5%

R57

12

120_0.5%

R535

12

120_0.5%

R145

12

120_0.5%

R143

12

120_0.5%

R142

12

120_0.5%

LCM_BKLTEN

20-

NB_LVDS_TXCL-

20-

NB_LVDS_TXCL+

20-

NB_LVDS_TXCU-

20-

NB_LVDS_TXCU+

20-

NB_LVDS_TXDL0-

20-

NB_LVDS_TXDL0+

20-

NB_LVDS_TXDL1-

20-

NB_LVDS_TXDL1+

20-

NB_LVDS_TXDL2-

20-

NB_LVDS_TXDL2+

20-

NB_LVDS_TXDU0-

20-

NB_LVDS_TXDU0+

20-

NB_LVDS_TXDU1-

20-

NB_LVDS_TXDU1+

20-

NB_LVDS_TXDU2-

20-

NB_LVDS_TXDU2+

NB_SVID_LUMA

NB_SVID_CHROMA

NB_B

NB_G

NB_R

62-,30-

R227

100K_1%

SVID_R_LUMA

SVID_R_CHROMA

12

255_1%

63-,62-,61-,55-,52-,50-,49-,48-,47-,46-,45-,43-,40-,39-,38-,37-,36-,34-,33-,32-,31-,30-,28-,26-,25-,23-,19-,18-,13-,12-,11-,10-,8-

R226

12

0_5%

1

LCM_R_DDCPCLK

LCM_R_DDCPDATA

2

+VCCP

R131

2

1

0_5%

R157

62-,30­62-,30-

LCM_3S_VDDEN

1

R547

1.5K_1%

2

61-,43-,34-,32-,24-,23-,16-,11-,9-

R43

0_5%

12

NB_SVID_LUMA

62-,29-

NB_SVID_CHROMA

12

62-,29-

R537

R181

12

0_5%

4.99K_1%

R47

12

0_5%

34-,31-,24-,23-,21-,16-,15-,14-,13-,9-,20-

1

1

OPEN

OPEN

R152

R130

2

2

CRT_R_DDCCLK

CRT_R_DDCDATA

CRT_R_HSYNC
CRT_R_VSYNC

62-,28­62-,28­62-,28-

62-,28-

R151
R105

R117

100K_5%

+V1.5S

R119
R120
R148

R544

12
12

63-,30-

R45

1

2

OPEN

B
G
R

0_5%
0_5%

R116

12

1

NB_LVDS_TXCL-

2

NB_LVDS_TXCL+
NB_LVDS_TXCU-

NB_LVDS_TXCU+
NB_LVDS_TXDL0-

NB_LVDS_TXDL1­NB_LVDS_TXDL2-

NB_LVDS_TXDL0+
NB_LVDS_TXDL1+
NB_LVDS_TXDL2+

NB_LVDS_TXDU0­NB_LVDS_TXDU1­NB_LVDS_TXDU2-

R536

R124

R46

R44

1

1

1

1

NB_LVDS_TXDU0+
NB_LVDS_TXDU1+
NB_LVDS_TXDU2+

2

2

2

2

OPEN

OPEN

OPEN

OPEN

62-,28-

R146

62-,28-

R128

62-,28-

R141

12

0_5%

12

0_5%

12

39_5%

12

39_5%

NB_LCM_DDCPCLK
NB_LCM_DDCPDATA

0_5%

12

0_5%

12

0_5%

12

0_5%

NB_CRT_DDCCLK

NB_CRT_DDCDATA
NB_CRT_HSYNC

NB_CRT_VSYNC

+V3S

1

1

R225

R186

10K_5%

10K_5%

2

2

R543

U506-3

D32

L_BKLTCTL

J30

L_BKLTEN

H30

L_CLKCTLA

H29

L_CLKCTLB

G26

L_DDC_CLK

G25

L_DDC_DATA

B38

L_IBG

C35

L_VBG

F32

L_VDDEN

C33

L_VREFH

C32

L_VREFL

20-

A33

LA_CLK#

A32

20-

LA_CLK

20-

E27

LB_CLK#

E26

20-

LB_CLK

C37

20-

LA_DATA#_0

B35

20-

LA_DATA#_1

A37

20-

LA_DATA#_2

B37

20-

LA_DATA_0

B34

20-

LA_DATA_1

A36

20-

LA_DATA_2

20-

G30

LB_DATA#_0

D30

20-

LB_DATA#_1

20-

F29

LB_DATA#_2

F30

20-

LB_DATA_0

D29

20-

LB_DATA_1

F28

20-

LB_DATA_2

A16

TV_DACA_OUT

C18

TV_DACB_OUT

A19

TV_DACC_OUT

J20

TV_IREF

B16

TV_IRTNA

B18

TV_IRTNB

B19

TV_IRTNC

K30

TV_DCONSEL0

J29

TV_DCONSEL1

NB_B

E23

CRT_BLUE

D23

NB_G

1

2

CRT_BLUE#

C22

CRT_GREEN

B22

CRT_GREEN#

NB_R

A21

CRT_RED

B21

CRT_RED#

C26

CRT_DDC_CLK

C25

CRT_DDC_DATA

G23

CRT_HSYNC

J22

CRT_IREF

H23

CRT_VSYNC

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

1

OPEN

OPEN

R147

2

D40

EXP_A_COMPI

D38

EXP_A_COMPO

EXP_A_RXN_0
EXP_A_RXN_1
EXP_A_RXN_2
EXP_A_RXN_3
EXP_A_RXN_4
EXP_A_RXN_5
EXP_A_RXN_6
EXP_A_RXN_7
EXP_A_RXN_8
EXP_A_RXN_9

EXP_A_RXN_10

LVDS

EXP_A_RXN_11
EXP_A_RXN_12
EXP_A_RXN_13
EXP_A_RXN_14
EXP_A_RXN_15

EXP_A_RXP_0
EXP_A_RXP_1
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
EXP_A_RXP_6
EXP_A_RXP_7
EXP_A_RXP_8

EXP_A_RXP_9
EXP_A_RXP_10
EXP_A_RXP_11
EXP_A_RXP_12
EXP_A_RXP_13
EXP_A_RXP_14
EXP_A_RXP_15

EXP_A_TXN_0

EXP_A_TXN_1

EXP_A_TXN_2

EXP_A_TXN_3

EXP_A_TXN_4

EXP_A_TXN_5

EXP_A_TXN_6

EXP_A_TXN_7

EXP_A_TXN_8

PCI-EXPRESS GRAPHICS

EXP_A_TXN_9
EXP_A_TXN_10

TV

EXP_A_TXN_11
EXP_A_TXN_12
EXP_A_TXN_13
EXP_A_TXN_14
EXP_A_TXN_15

EXP_A_TXP_0

EXP_A_TXP_1

EXP_A_TXP_2

EXP_A_TXP_3

EXP_A_TXP_4

EXP_A_TXP_5

VGA

EXP_A_TXP_6

EXP_A_TXP_7

EXP_A_TXP_8

EXP_A_TXP_9
EXP_A_TXP_10
EXP_A_TXP_11
EXP_A_TXP_12
EXP_A_TXP_13
EXP_A_TXP_14
EXP_A_TXP_15

F34
G38
H34
J38
L34
M38
N34
P38
R34
T38
V34
W38
Y34
AA38
AB34
AC38

D34
F38
G34
H38
J34
L38
M34
N38
P34
R38
T34
V38
W34
Y38
AA34
AB38

F36
G40
H36
J40
L36
M40
N36
P40
R36
T40
V36
W40
Y36
AA40
AB36
AC40

D36
F40
G36
H40
J36
L40
M36
N40
P36
R40
T36
V40
W36
Y40
AA36
AB40

63­63­63­63­63­63­63­63­63­63­63­63­63­63­63­63-

63­63­63­63­63­63­63­63­63­63­63­63­63­63­63­63-

20­20­20­20­20­20­20­20­20­20­20­20-

20­20­20-

20­20­20­20­20­20­20­20­20­20­20­20­20­20­20­20-

+V1.5S_PCIE

23-

R229

12

24.9_1%

PEG_C_RXN0
PEG_C_RXN1
PEG_C_RXN2
PEG_C_RXN3
PEG_C_RXN4
PEG_C_RXN5
PEG_C_RXN6
PEG_C_RXN7
PEG_C_RXN8
PEG_C_RXN9
PEG_C_RXN10
PEG_C_RXN11
PEG_C_RXN12
PEG_C_RXN13
PEG_C_RXN14
PEG_C_RXN15

PEG_C_RXP0
PEG_C_RXP1
PEG_C_RXP2
PEG_C_RXP3
PEG_C_RXP4
PEG_C_RXP5
PEG_C_RXP6
PEG_C_RXP7
PEG_C_RXP8
PEG_C_RXP9
PEG_C_RXP10
PEG_C_RXP11
PEG_C_RXP12
PEG_C_RXP13
PEG_C_RXP14
PEG_C_RXP15

PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15

PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15

PEG_TXP0
PEG_TXN0
PEG_TXP1
PEG_TXN1
PEG_TXP2
PEG_TXN2
PEG_TXP3
PEG_TXN3
PEG_TXP4
PEG_TXN4
PEG_TXP5
PEG_TXN5
PEG_TXP6
PEG_TXN6
PEG_TXP7
PEG_TXN7
PEG_TXP8
PEG_TXN8
PEG_TXP9

PEG_TXN9
PEG_TXP10
PEG_TXN10
PEG_TXP11
PEG_TXN11
PEG_TXP12
PEG_TXN12
PEG_TXP13
PEG_TXN13
PEG_TXP14
PEG_TXN14
PEG_TXP15
PEG_TXN15

C603
C604
C581
C582
C605
C606
C583
C584
C607
C608
C585
C586
C609
C610
C587
C588
C611
C612
C589
C590
C613
C614
C591
C592
C615
C616
C593
C594
C617
C618
C595
C596

12
1
12
12
12
1
12
1
12
12
12
12
12
12
12
12
12
1
12
12
1
12
12
12
12
12
12
12
12
12
12
12

2

2

2

2

2

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

0.1uF_10v

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-

20-20-

20-

20-

20-

20-

20-

20-

20-

20-

Place to near NB

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

63-

PEG_C_TXP0
PEG_C_TXN0
PEG_C_TXP1
PEG_C_TXN1
PEG_C_TXP2
PEG_C_TXN2
PEG_C_TXP3
PEG_C_TXN3
PEG_C_TXP4
PEG_C_TXN4
PEG_C_TXP5
PEG_C_TXN5
PEG_C_TXP6
PEG_C_TXN6
PEG_C_TXP7
PEG_C_TXN7
PEG_C_TXP8
PEG_C_TXN8
PEG_C_TXP9
PEG_C_TXN9
PEG_C_TXP10
PEG_C_TXN10
PEG_C_TXP11
PEG_C_TXN11
PEG_C_TXP12
PEG_C_TXN12
PEG_C_TXP13
PEG_C_TXN13
PEG_C_TXP14
PEG_C_TXN14
PEG_C_TXP15
PEG_C_TXN15

INVENTEC

TITLE

Portland 10/10G

Calistoga-2

SIZE CODE DOC. NUMBER REV

CHANGE by SHEET OF

Drawer_Name 21-Jun-2006

A3

1310A2076901 A02

CS

6820

12

MCH_HXSCOMP

MCH_HXRCOMP

MCH_HYSCOMP

MCH_HYRCOMP

MCH_HXSWING

MCH_HYSWING

NOTE:
MCH_HXRCOMP, MCH_HYRCOMP
MCH_HXSWING, MCH_HYSWING
should be 10 mil wide with 20 mil spacing

21-

12

21-

R82 24.9_1%

12

21-

12

21-

R86 24.9_1%

+VCCP

34-,31-,24-,23-,20-,16-,15-,14-,13-,9-,21-

1

R95

221_1%

2

21-

1

R96

100_1%

2

+VCCP

34-,31-,24-,23-,20-,16-,15-,14-,13-,9-,21-

1

R84

221_1%

2

21-

1

R85

100_1%

2

1
2

1
2

54.9_1%R81

54.9_1%R83

C91

0.1uF_10v

C67

0.1uF_10v

H_D#(63:0)

+VCCP

34-,31-,24-,23-,20-,16-,15-,14-,13-,9-,21-

+VCCP

34-,31-,24-,23-,20-,16-,15-,14-,13-,9-,21-

MCH_HXRCOMP
MCH_HXSCOMP

MCH_HXSWING

MCH_HYRCOMP
MCH_HYSCOMP

MCH_HYSWING

15-

21­21­21-

21­21­21-

H_D#(63:0)

H_D#(0)
H_D#(1)
H_D#(2)
H_D#(3)
H_D#(4)
H_D#(5)
H_D#(6)
H_D#(7)
H_D#(8)
H_D#(9)
H_D#(10)
H_D#(11)
H_D#(12)
H_D#(13)
H_D#(14)
H_D#(15)
H_D#(16)
H_D#(17)
H_D#(18)
H_D#(19)
H_D#(20)
H_D#(21)
H_D#(22)
H_D#(23)
H_D#(24)
H_D#(25)
H_D#(26)
H_D#(27)
H_D#(28)
H_D#(29)
H_D#(30)
H_D#(31)
H_D#(32)
H_D#(33)
H_D#(34)
H_D#(35)
H_D#(36)
H_D#(37)
H_D#(38)
H_D#(39)
H_D#(40)
H_D#(41)
H_D#(42)
H_D#(43)
H_D#(44)
H_D#(45)
H_D#(46)
H_D#(47)
H_D#(48)
H_D#(49)
H_D#(50)
H_D#(51)
H_D#(52)
H_D#(53)
H_D#(54)
H_D#(55)
H_D#(56)
H_D#(57)
H_D#(58)
H_D#(59)
H_D#(60)
H_D#(61)
H_D#(62)
H_D#(63)

Layout notes:
Trace need be 10 mils

CLK_R_MCHBCLK

CLK_R_MCHBCLK#

U506-1

F1

H_D#_0

J1

H_D#_1

H1

H_D#_2

J6

H_D#_3

H3

H_D#_4

K2

H_D#_5

G1

H_D#_6

G2

H_D#_7

K9

H_D#_8

K1

H_D#_9

K7

H_D#_10

J8

H_D#_11

H4

H_D#_12

J3

H_D#_13

K11

H_D#_14

G4

H_D#_15

T10

H_D#_16

W11

H_D#_17

T3

H_D#_18

U7

H_D#_19

U9

H_D#_20

U11

H_D#_21

T11

H_D#_22

W9

H_D#_23

T1

H_D#_24

T8

H_D#_25

T4

H_D#_26

W7

H_D#_27

U5

H_D#_28

T9

H_D#_29

W6

H_D#_30

T5

H_D#_31

AB7

H_D#_32

AA9

H_D#_33

W4

H_D#_34

W3

H_D#_35

Y3

H_D#_36

Y7

H_D#_37

W5

H_D#_38

Y10

H_D#_39

AB8

H_D#_40

W2

H_D#_41

AA4

H_D#_42

AA7

H_D#_43

AA2

H_D#_44

AA6

H_D#_45

AA10

H_D#_46

Y8

H_D#_47

AA1

H_D#_48

AB4

H_D#_49

AC9

H_D#_50

AB11

H_D#_51

AC11

H_D#_52

AB3

H_D#_53

AC2

H_D#_54

AD1

H_D#_55

AD9

H_D#_56

AC1

H_D#_57

AD7

H_D#_58

AC6

H_D#_59

AB5

H_D#_60

AD10

H_D#_61

AD4

H_D#_62

AC8

H_D#_63

E1

H_XRCOMP

E2

H_XSCOMP

E4

H_XSWING

Y1

H_YRCOMP

U1

H_YSCOMP

W1

H_YSWING

13­13-

AG2

H_CLKIN

AG1

H_CLKIN#

ITL_CALISTOGA_MICRO_FCBGA_TSB_1466P

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8

H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29

HOST

H_A#_30
H_A#_31

H_ADS#
H_ADSTB#_0
H_ADSTB#_1

H_VREF

H_BNR#

H_BPRI#

H_BREQ#0

H_CPURST#

H_DBSY#

H_DEFER#

H_DPWR#

H_DRDY#

H_VREF

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

H_HIT#

H_HITM#

H_LOCK#

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

H_RS#_0
H_RS#_1
H_RS#_2

H_SLPCPU#

H_TRDY#

H9
C9
E11
G11
F11
G12
F9
H11
J12
G14
D9
J14
H13
J15
F14
D12
A11
C11
A12
A13
E13
G13
F12
B12
B14
C12
A14
C14
D14

E8
B9
C13
J13
C6
F6
C7
B7
A7
C3
J9
H8
K13

J7
W8
U3
AB10

K4
T7
Y5
AC4

K3
T6
AA5
AC5

D3
D4
B3

D8
G8
B8
F8
A8

B4
E6
D6

E3
E7

H_VREF

H_VREF

H_A#(3)
H_A#(4)
H_A#(5)
H_A#(6)

H_A#(7)
H_A#(8)
H_A#(9)
H_A#(10)
H_A#(11)
H_A#(12)
H_A#(13)
H_A#(14)
H_A#(15)
H_A#(16)
H_A#(17)
H_A#(18)
H_A#(19)
H_A#(20)
H_A#(21)
H_A#(22)
H_A#(23)
H_A#(24)
H_A#(25)
H_A#(26)
H_A#(27)
H_A#(28)
H_A#(29)
H_A#(30)
H_A#(31)

14­14­14-

14­14­14­14­14­14­15­14-

15­15­15­15-

15­15­15­15-

15­15­15­15-

14­14-

31-,15-

H_BPRI#
H_CPURST#
H_DEFER#

H_DPWR#

14-

H_REQ#(0)
H_REQ#(1)
H_REQ#(2)
H_REQ#(3)
H_REQ#(4)

14-

14-

H_ADS#
H_ADSTB#0
H_ADSTB#1

H_BNR#
H_BREQ#0
H_DBSY#

H_DRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#

H_LOCK#

H_RS#(0)
H_RS#(1)
H_RS#(2)

H_CPUSLP#
H_TRDY#

H_A#(31:3)

+VCCP

34-,31-,24-,23-,20-,16-,15-,14-,13-,9-,21-

1

2

1

1

C164

2

0.1uF_10v

2

14-

14-

R170

100_1%

R159

200_1%

H_REQ#(4:0)

H_RS#(2:0)

LAYOUT NOTE:

Place R675 and R676 close to MCH within 100 mil

INVENTEC

TITLE

Portland 10/10G

Calistoga-3

CODE DOC. NUMBER REV

SIZE

CHANGE by SHEET OF

Drawer_Name

21-Jun-2006

A3

1310A2076901 A02

CS

6821