FUJITSU SIEMENS M9400 Schematics

D D

Inventec Corporation R&D Division

C C

Board name : Mother Board Schematic Project : M11D (Santa Rosa)

Version : 0.1

B B

A A

Initial Date : March 22 , 2007

Inventec Corporation

Title

Size

Date: Sheet of

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan TEL:+886-2-2881-0721

TEL:+886-2-2881-0721

M11D (Merom+Crestline+ICH8M)

Document Number

Friday, June 01, 2007

Title

Rev

AX1

Schematic Page Description

Santa Rosa Schematic Ver : 0.1

D D

1. Title

2. Schematic Page DESCR

3. Block Diagram

4. Annotations

5. Schematic Modify

6. Timing Diagram

7. DDRII Layout Guideline

8. Merom Processor(1/2)

9. Merom Processor(2/2)

10. CPU Core Power

11. CPU Thermal

12. Crestline Host(1/6)

13. Crestline DMI/Graph(2/6)

C C

14. Crestline DDRII(3/6)

15. Crestline Power(4/6)

16. Crestline Power(5/6)

17. Crestline Ground(6/6)

18. Clock Generator

19. DDRII SDRAM SO-DIMM0

20. DDRII SDRAM SO-DIMM1

25. LCD / CRT

26. DVI / TV-OUT

27. SATA / ODD / Docking

28. MiniCard / NewCard

29. LAN (88E8055B0)

30. USB / CardReader

31. KBC ITE8512F

32. Audio Codec ALC262/AMP

33. Audio MIC / Super I/O

34. Board CON

35. Adaptor in/Charge

36. Dual Battery

37. 5VLA/5VA/3VA

38. 3VS/5VS/1.25VS/1.05VS

39. 1.5VS/1.8V

40. GPU_Core

41. Audio Board

42. USB Board

43. Glidepad Board

21. ICH8M CPU/IDE/SATA(1/4)

22. ICH8M PCI/PCIE/DMI/USB(2/4)

23. ICH8M GPIO(3/4)

24. ICH8M Power/GND(4/4)

PCI & IRQ & DMA Description :

B B

IDSEL CHIP CHIPPCIINT REQ

BUSMASTER

CHIP

USB & PCI-Express Description :

USB DEVICE DEVICEPCI-E Port 0 Port 1 Port 2

A A

Port 3 Port 4

System System System System Mini Card(3G)

USB DEVICE Port 5 Port 6 Port 7 Port 8 Port 9

Docking Express Card Card Reader Web Cam Bluetooth

PCI-E

Port 1

Express Card

Port 2

LAN

Port 3

Mini Card(WLAN)

Port 4

Mini Card(3G) None

Port 5

Port 6

DEVICE None

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Schematic Page DESCR

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Rev

AX1

System Block Diagram :

CPU

FAN

D D

LCD

P.25

CRT

P.25

P.11

S-OUT

P.26

Docking

P.27

LVDS

TVO

RGB_CRT RGB

RGB_DOCK

Thermal

G784

CRT_SW

P.26

HDD

Thermal

SATA 150

P.27

C C

ODD

PATA 100

P.27

USB0USB1USB2USB3

System3

System2System3

USB Board

P.42P.30P.30P.30

USB 2.0/1.1

USB5USB6

B B

Docking

UMTS

P.28P.27

USB4

WLAN

P.28

USB 2.0/1.1

USB10

Bluetooth

P.34

4 IN 1

Slot

Web Cam

Cardreader

GL827

USB7USB8USB9

New CardCardreader

P.28P.30P.25

P.30 P.30

uFCPGA 478pin

Merom

P.8-9P.11

FSB 1.05V 667/800MHz

MCH

965GM/GML FCBGA 1299pin

35mmx35mm

Crestline GM

P.12-17

DMI x4

31mmx31mm

ICH

mBGA 676pin

ICH8M

EHCI#1

Support S0~S3 state

EHCI#2

Support S0~S2 state

P.21-24

DDR2 1.8V 533/667MHz

PCI-Express x1 2.5GHz

HDA 24MHz

MDC1.5

P.34

RJ11

LPC 3.3V 33MHz

PMU&KBC

ITE8512F

P.31

SPI

SODIMM0

SODIMM1

P.19 P.20

GbE

88E8055

Port#2

P.29

IntMic Stereo

P.34

Analog In

P.41

PS/2

Docking

P.27

P.31

Flash ROM

P.31

Glide Pad

RJ45

P.29

New Card

Port#1

Audio

Out

Codec

ALC262

Out

Super I/O

IT8305E

P.32

Serial port

Parallel port

PLL

ICS9LPRS365AGLF

P.18

MiniCard #1

Out

Out IN

UMTS/Robson

Port#4

Docking

P.27

80Port

P.28P.33

P.27

P.28

Docking

P.28

AMP

Analog Out

166MHz+/100MHz+/48MHz 33MHz 14MHz 27MHz/96MHz+/-

SIM Slot

P.28

MiniCard #2

WLAN/Robson

Port#3

P.28

SPK

P.P32

P.34

P.42

x2 x8 x1 x7 x1 x1

A A

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Friday, June 01, 2007

Block Diagram

Rev

AX1

4. Net name Description :

Voltage Rails

DCIN +5VLA 5.0V always on power rail by LATCH or ACIN

D D

+3VA 3.3V always on power rail by ECPWON +5VS

+1.8VS 1.8V switched power rail by SLP_S3#_3R VCC_CORE

+1.05VS +1.25VS 1.25V switched power rail by SLP_S3#_3R +1.5VS

Primary DC system power supply

5.0V always on power rail by ECPWON+5VA

5.0V switched power rail by SLP_S3#_3R

3.3V switched power rail by SLP_S3#_3R+3VS

Core Voltage for CPU

1.05V power rail for AGTL+ termination/Core for GMCH by SLP_S3#_3R

1.5V power rail for CPU PLL/DMI;PCIE;DDRII DLLs for GMCH/Core;PCIE

Power Rail

VCC_CORE

+1.05VS

+1.5VS

for ICH8m by SLP_S3#_3R

+1.8V

0.9VDDT_DDRII

Part Naming Conventions

Capacitor

C C

D F L Q R RP U Y

Connector

Diode

Fuse

Inductor

= =

Transistor Resistor

Resistor Pack

Arbitrary Logic Device

Crystal and Osc

1.8V power rail for DDRII by SLP_S5#_3R

0.9V DDRII Termination Voltage by SLP_S3#_3R

+1.8V

0.9VDDT_DDRII:

+2.5VS

+3VS

Net Name Suffix

# =

Active Low signal

5. Board Stack up Description

PCB Layers

B B

Layer 1 Layer 2 Layer 3

Component Side, Microstrip signal Layer Ground Plane Stripline Layer Power PlaneLayer 4

Layer 5

Power Plane Layer 6 Stripline Layer Layer 7 Layer 8

Host Clock

PCI-E Clock

DDR2 CLK

A A

DDR2 Strobe

DMI Bus

PCIE Bus

SDVO

SATA

USB

LVDS

Lan

Differential Impedance for Microstrip(5-mils) Differential Impedance for Stripline(4-mils)

95 ohm +/- 20% 100 ohm +/- 20%

70 ohm +/- 20% 70 ohm +/- 20%

85 ohm +/- 20%

95 ohm +/- 20%

95 ohm +/- 20% 100 ohm +/- 20%

95 ohm +/- 20%

90 ohm +/- 20%

95 ohm +/- 20% 100 ohm +/- 20%

Ground Plane

Solder Side,Microstrip signal Layer

90 ohm +/- 20%

100 ohm +/- 20%95 ohm +/- 20%

100 ohm +/- 20%

95 ohm +/- 20%

100 ohm +/- 20%

1.8VS

+3VA

+5VS

+5VA

+5VLA

Destination

Merom

HFM:

LFM: Merom: AGTL+ termination 965GM: Core 965GM: AGTL+ termination ICH8m: Merom PLL 965GM: PCIE 965GM: LVDS 965GM: TVDAC 965GM: Various PLLS analog supply 965GM: DDR DLLS,DDRII,FSB HSIO ICH8m: ICH8m: ICH8m: ICH8m: Mini Card: Express Card: 965GM: DDRII System Memory SO-DIMM: DDRII Terminator:

965GM: PCIE analog 965GM: LVDS analog 965GM: LVDS I/O 965GM: CRT DAC

965GM: HV CMOS 965GM: TVDAC analog ICH8m: ICH8m: ICH8m: ICH8m: ICH8m: Mini Card: UMTS Express Card: CLK Generator: ICS9LPRS365AGLF Mini Card: WirelessLan Bluetooth: Super I/O: IT8305E Azalia Codec: ALC262 Azalia MDC: HDD: SATA

DVI: Sil1364

Thermal Sensor: Lan: Marvell 88E8055B0 Azalia MDC: EC: ITE8512F ICH8m: RTC Flash ROM: BIOS LCD: Cardreader: GL827 Azalia Codec: ALC262 FAN: HDD: SATA ODD: PATA Audio AMP: G1432 Woofer AMP: None Inverter:

USB: x 3 ports

Control Power

Voltage

1.3319V~1.4375V~1.4591V

0.9221V~0.9625V~0.9739V

0.997V~1.05V~1.102V

1.0V~1.05V~1.1V

0.9475V~1.05V~1.1025V

1.425V~1.5V~1.575V

1.7V~1.8V~1.9V

0.855V~0.9V~0.945V

2.32V~2.5V~2.625V

2.375V~2.5V~2.625V

2.32V~2.5V~2.625V

3.135V~3.3V~3.465V

3.0V~3.3V~3.6V

4.75V~5.0V~5.25V

5VA 1.5A

S0 Current

36A

2.5A

4.6A

1.4A

120mA

1.5A 60mA 24mA 320mA

1.885A

3.1A

1.0A

2mA 10mA 60mA 70mA

40mA 120mA

400mA

1.0A

Max: 1.0A ; R/W: 460mA ; STDBY: 70mA Max: 1.8A ; R/W: 900mA ; STDBY: 45mA

Inventec Corporation

<OrgAddr4> Title

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan TEL:+886-2-2881-0721

TEL:+886-2-2881-0721

ANNOTATIONS

Rev

AX1

Schematic modify Item and History :

V0.1 First release

V0.1 to AX1

D D

1.For FAN PWM Control Change C259 From 0.01uF to NU

Change C538 From 1uF to NU Change R118 From 47Kohm to 1Kohm Change R119 From 4.7Kohm to 0 ohm Change R415 From 10 ohm to NU

2.For Power sequence issue (VRMPWRGD From CORECLK_EN Change to VCORE_GD) Change R131 From NU to 0 ohm

Change R133 From 100K ohm to NU Change U13 From TC7SZ04FU to NU

3.For Power sequence issue (Delay VCORE_GD to PM_ICH_PWROK ) ADD C1202 to 0.1uF

ADD R1116 to 100K ohm ADD D34 BAT54C-7

4.For VESA Specification Requirement (MB Side)

C C

B B

Change C5,C6,C8 From 22pF to 18pF Change L3,L4,L5 From 17ohm 600mA to 10ohm 500mA Change C9,C10,C11 From 10pF to NU Change R4,R5,R6 From 200ohm to 220ohm

5.For VESA Specification Requirement (Docking Side) Change R266,R267,R268 From 200ohm to 220ohm

6.For Serial RING Wake (Change from to EC) Change RING# single connect to U9 IT8512E Pin119

Change U4 MAX3243 Pin26 From 3VS to 3VA

7.For Audio Change Speaker single change connect to pin35,36

Change Heardphone single change connect to pin39,41 Change R586 From 5.1Kohm to 39.2Kohm DEL R584,R580,R588,R589,C679,U46

8.For EMI Requirement ADD C1206~C1251 0.1uF in 3VA,5VA,DCIN,VADPTR_DOCK

ADD C1204,C1205 1000pF in SW Board connecter ADD L1105~L1108 in Speaker connecter Change Q29,Q30,Q32,Q33 From FDS6676AS to FDMS8670S ADD C1252~C1254 0.1uF in USB_VCC1

9.For SATA Eye issue Change C587,C591 From 3300pF to 3900pF

10.For Docking DVI

TX2 Change to CN28 Pin 13,14 TX1 Change to CN28 Pin 16,17 TX0 Change to CN28 Pin 19,20 TXC Change to CN28 Pin 22,23

A A

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Schematic Modify

Friday, June 01, 2007

Rev

AX1

SYSTEM POWER ON/OFF SEQUENCE

Power on/off sequence AC insert(First)

Power on sequence Power off sequence

SW OFF:

D D

RTCVCC

5VLA

5VAUXON

3VA,5VA

5VA must be powered up before 3VA, or after 3VA within 0.7V

10ms

1.5VA,2.5VA

SW ON:

PWR_SWIN#

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

5VS,3VS

1.5VS,2.5VS

C C

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST#

RTCVCC

3VLA,5VLA

PWR_SWIN#

LATCH_ON

3VA,5VA

1.5VA,2.5VA



MRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

1.5VS,2.5VS

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST#

Power on/off sequence AC insert(S4)

Power on sequence Power off sequence

RTCVCC

B B

3VLA,5VLA

5VAUXON

3VA,5VA

PWR_SWIN#

1.5VA,2.5VA

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V

5VS,3VS

1.5VS,2.5VS

0.9VS_DIMM

A A

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

PLT_RST# PLT_RST#

RTCVCC

3VLA,5VLA

PWR_SWIN#

LATCH_ON

3VA,5VA

1.5VA,2.5VA

RSMRST#

PWR_BTN#

SUSB#

SUSC#

1.8V_DIMM

5VS,3VS

1.5VS,2.5VS

0.9VS_DIMM

VR_ON

+VCCP

VCCP_PWRGD

VCORE_GD

CPU_PWRGOOD

ALL_SYSPWRGD

Battery only Power on/off sequence

Power on sequence Power off sequence

5VS,3VS

Suspend resume sequence(S3)

Power on sequence Power off sequence

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan TEL:+886-2-2881-0721

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Custom

Date: Sheet of

Date: Sheet of 43

Friday, June 01, 2007

Timing Diagram

Rev

AX1

DDRII Layout Guideline :

Crestline DDRII Layout Guidelines

DDRII Signal Groups

Group Signal Name

D D

Data

M_A_DQ[63..0]/M_B_DQ[63..0] M_A_DM[7..0]/M_B_DM[7..0] M_A_DQS[7..0]/M_A_DQS#[7..0] M_B_DQS[7..0]/M_B_DQS#[7..0]

M_A_A[13..0]/M_B_A[13..0]Address M_A_BS[2..0]/M_B_BS[2..0] M_A_RAS#/M_B_RAS# M_A_CAS#/M_B_CAS# M_A_WE#/M_B_WE#

M_CS#[3..0]Control M_CKE[3..0] M_ODT[3..0]

Clock M_CLK_DDR[3..0]

M_CLK_DDR#[3..0]

SA_RCVEN#/SB_RCVEN#FeedBack

CLK group : M_CLK_DDR[3..0],M_CLK_DDR#[3..0]

GMCH

P1P1L0L0L1L1L2L2S1

C C

Topology

Reference Plane

Single Ended Trace Impedance

Differential Mode Impedance

Minimum Serpentine Spacing Inner Layer : 12 mils

Package Length Range - P1 350 mils ~ 625 mils

Min. Serpentine Spacing 25 mils

Trace Length Limit - L0 (MS)

Trace Length Limit - L1 (SL)

(Breakout length segment)

B B

Stub Length S1-Stub from via to SO-DIMM Max = 200 mils (Breakin)

MB Length Limits - L0 + L1 + L2 + S1 Min = 500 mils

Maximim Via Count 2 (Per side)

SCK to SCK# Length Matching Match total length to within 5 mils

Clock to Clock Length Match (Total Length) Breakout Exceptions (Reduce geometries for GMCH break-out region)

Breakin Exceptions (Reduce geometries for SO-DIMM break-in region)

Feedback group : SA_RCVENIN#],SA_RCVENOUT#,SB_RCVENIN#],SB_RCVENOUT#

These signals are routed internally on the GMCH package and don't require any routing on the MB. As a result, can be left as NC.

A A

4/4/12 7/4/16 8/5/15

Escape

Breakout Breakin

SLMS SL MS

Length Matching and Length Formulas

Signal Group Minimum Length Maximum Length

Control-to-Clock

Command-to-Clock

Strobe-to-Clock

Data-to-Strobe

Clock - 1.0"

Clock - 0.5"

Strobe - 220mils

SO-DIMM

Differential Pair Point-to-Point

Ground

42 +/- 15%

70 +/- 20%

Outer Layer : 15 mils

Nominal Trace Width : 5mils, 4mils

Length Limit: Max = 50 mils (Escape)

Min. Trace Spacing : 5mils, 4mils

Length Limit: Max = 700 mils

Nominal Trace Width : 4mils

Min. Trace Spacng (pair) : 4mils

Min. Trace Spacng (Other) : 12 mils

Max = 4000 mils

Max = 4500 milsTotal Length - P1 + L0 + L1 + L2 + S1

Total Length for Channel A : X0 Total Length for Channel B : X1

Match Channel A clocks to X0 +/- 20mils Match Channel A clocks to X1 +/- 20mils

Inner Layer : 4/12 mils to other DDR2 Outer Layer : 5/15 mils to other DDR2

Max. breakout length is 500 mils

CK to CK# spacing rule waived at connector spacing of 15 mils to other DDR2

Max. breakin length is 200 mils

Clock - 0.0"

Clock + 1.0"

Strobe - 180mils

Control group : SM_CKE[3..0],SM_CS#[3..0],SM_ODT[3..0]

GMCH

4/4/12

Escape

Breakout SL

MS SL/MS

SL/MS

Vtt

8/5/15

7/4/16

SO-DIMM

Topology

Reference Plane

Characteristic Trace Impedance

Nominal Trace Width

Minimum CTRL Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2

Package Length P1

Trace Length Limit - L0

Trace Length Limit - L1

Stub Length S1-Stub from via to SO-DIMM

MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad

Parallel Termination Resistor 56 +/- 5%

Maximim Via Count

CTRL to SCK/SCK# Length Matching (Total Length including package) Breakout Exceptions (Reduce geometries for GMCH break-out region)

Command group : SA_MA[13..0],SB_MA[13..0],SA_BS[2..0],SB_BS[2..0],SA_RAS#, SB_RAS#,SA_CAS#,SB_CAS#,SA_WE#,SB_WE#

GMCH

Escape

4/4

Breakout

Point-to-Point with parallel termination

Ground

55 +/- 15%

Inner Layer : 4 mils Outer Layer : 5 mils

Inner Layer : 8 mils Outer Layer : 10 mils

Inner Layer : 12 mils Outer Layer : 15 mils

25 mils

750 mils +/- 200 mils

Max = 50 mils (Escape)

Max = 500 mils (Breakout)

Max = 200 mils (Breakin)

Min = 500 mils Max = 4500 mils

Max = 5000 mils

Max = 1500 milsTrace Length L3

(CLK-1.0") </= CTRL </= (CLK-0.0")

Inner Layer : 4 mils spacing allowed Outer Layer : 5 mils spacing allowed Max. breakout length is 500 mils

4/6,5/10

SL/MS

SL/MSMS SL

Vtt

SO-DIMM

Topology

Reference Plane

Characteristic Trace Impedance

Nominal Trace Width

Minimum CMD Bus Trace Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2

Package Length P1

Trace Length Limit - L0

Trace Length Limit - L1

Stub Length S1-Stub from via to SO-DIMM

MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Trace Length L3

Parallel Termination Resistor

Maximim Via Count

CTRL to SCK/SCK# Length Matching (Total Length including package) Breakout Exceptions (Reduce geometries for GMCH break-out region)

Point-to-Point with parallel termination

Ground

55 +/- 15%

Inner Layer : 4 mils Outer Layer : 5 mils

Inner Layer : 6 mils Outer Layer : 10 mils

Inner Layer : 12 mils Outer Layer : 15 mils

25 mils

750 mils +/- 350 mils

Max = 50 mils (Escape)

Max = 500 mils (Breakout)

Max = 200 mils (Breakin)

Min = 500 mils Max = 4500 mils

Max = 5000 mils

Max = 1500 mils

56 +/- 5%

(CLK-1.0") </= CMD </= (CLK+1.0")

Inner Layer : 4 mils spacing allowed Outer Layer : 5 mils spacing allowed Max. breakout length is 500 mils

Data group : SA_DQ[63..0],SB_DQ[63..0],SA_DM[7..0],SB_DM[7..0]

4/6

GMCH

P1 L0

4/4

Escape

Breakout

MS SLSL MS

SO-DIMM

Topology

Reference Plane

Characteristic Trace Impedance

Nominal Trace Width

Minimum DQ Bus Trace Spacing

Minimum Serpentine Spacing Same as DQ-to-DQ routing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2

Package Length P1

Trace Length Limit - L0

Trace Length Limit - L1

Stub Length S1-Stub from via to SO-DIMM

MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Trace Length L3

Maximim Via Count

DQ/DM to DQS Length Matching (Total Length including package)

Breakout Exceptions (Reduce geometries for GMCH break-out region)

Point-to-Point

Ground

55 +/- 15%

Inner Layer : 4 mils Outer Layer : 5 mils

Inner Layer : 6 mils Outer Layer : 8 mils

Inner Layer : 12 mils Outer Layer : 15 mils

25 mils

750 mils +/- 350 mils

Max = 50 mils (Escape)

Max = 500 mils (Breakout)

Max = 200 mils (Breakin)

Min = 500 mils Max = 4500 mils

Max = 5000 mils

Max = 1500 mils

Match DQ/DM to [SDQS - 200mils] +/- 20mils, per byte lane Inner Layer : 4 mils spacing allowed

Outer Layer : 5 mils spacing allowed Max. breakout length is 500 mils

Data Strobe group : SA_DQS[7..0],SA_DQS[7..0]#,SB_DQS[7..0],SB_DQS[7..0]#

SO-DIMM

5/5/10

4/4/12

GMCH

Topology

Reference Plane

Single Ended Trace Impedance

Differential Mode Impedance

Nominal Trace Width

Nominal DQS to DQS# Spacing (edge to edge)

Minimum Serpentine Spacing

Minimum Spacing to Other DDR2

Minimum Isolation Spacing to non-DDR2

Package Length Range - P1

Trace Length Limit - L0

Trace Length Limit - L1

Stub Length S1-Stub from via to SO-DIMM

MB Length Limits - L0 + L1 + L2 + S1 From GMCH ball to SO-DIMM pad Total Length - P1 + L0 + L1 + L2 + S1 From GMCH die to SO-DIMM pad Maximim Via Count

DQS to DQS# Length Matching

Clock to Clock Length Match (Total Length include package) Breakout Exceptions (Reduce geometries for GMCH break-out region)

Breakin Exceptions (Reduce geometries for SO-DIMM break-in region)

Escape

4/4/8

Breakout SL SL MS

Differential Pair Point-to-Point

Ground

55 +/- 15%

85 +/- 20%

Inner Layer : 4 mils Outer Layer : 5 mils

Inner Layer : 12 milsMinimum DQS to DQ Spacing Outer Layer : 15 mils

Inner Layer : 8 mils Outer Layer : 10 mils

Inner Layer : 12 mils Outer Layer : 15 mils

25 mils

750 mils +/- 350 mils

Max = 50 mils (Escape)

Max = 500 mils (Breakout)

Max = 200 mils (Breakin)

Min = 500 mils Max = 4500 mils

Max = 5000 mils

2 (Per side)

Match total length to within 5 mils

(CLK-0.5") </= DQS </= (CLK+1.0")

Inner Layer : 8 mils to other DDR2 Outer Layer : 10 mils to other DDR2 Max. breakout length is 500 mils

DQS to DQS# spacing rule waived at connector spacing of 10 mils to other DDR2

Max. breakin length is 200 mils

Breakin

Inventec Corporation

<OrgAddr4> Title

Title

Size

Date: Sheet of

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan TEL:+886-2-2881-0721

TEL:+886-2-2881-0721

M11D (Merom+Crestline+ICH8M)

Document Number

DDRII Layout Guideline

Friday, June 01, 2007

Rev

AX1

CN8A

H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14

H_A#[35..3]

H_A#15 H_A#16

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

4 4

3 3

H_A#[35..3]<12>

H_ADSTB#0<12>

H_REQ#[4..0]<12>

H_ADSTB#1<12>

H_A20M#<21>

H_FERR#<21>

H_IGNNE#<21>

H_STPCLK#<21>

H_INTR<21>

H_NMI<21>

H_SMI#<21>

H_A#[35..3]

H_REQ#[4..0]

H_A#[35..3]<12>

No stub on H_STPCLK test point

CN8A

A[3]#

A[4]#

A[5]#

A[6]#

A[7]#

A[8]#

A[9]#

A[10]#

A[11]#

A[12]#

A[13]#

A[14]#

A[15]#

A[16]#

ADSTB[0]#

REQ[0]#

REQ[1]#

REQ[2]#

REQ[3]#

REQ[4]#

A[17]#

A[18]#

A[19]#

A[20]#

A[21]#

A[22]#

A[23]#

A[24]#

A[25]#

A[26]#

A[27]#

A[28]#

A[29]#

A[30]#

A[31]#

A[32]#

AA4

A[33]#

AB2

A[34]#

AA3

A[35]#

ADSTB[1]#

A20M#

FERR#

IGNNE#

STPCLK#

LINT0

LINT1

SMI#

RSVD[01]

RSVD[02]

RSVD[03]

RSVD[04]

RSVD[05]

RSVD[06]

RSVD[07]

D22

RSVD[08]

RSVD[09]

RSVD[10]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

Rout to TP via and place gnd via w/in 100mils

A#[32-39], APM#[0-1]:Leave escape routing on for future functionality

ICH

ADS#

ADDR GROUP 0 ADDR GROUP 1

BNR#

BPRI#

DEFER#

DRDY# DBSY#

BR0#

IERR#

INIT#

LOCK#

CONTROL

RESET#

RS[0]# RS[1]# RS[2]#

TRDY#

HITM#

BPM[0]# BPM[1]# BPM[2]# BPM[3]#

PRDY# PREQ#

TRST#

DBR#

XDP/ITP SIGNALS

THERMAL

PROCHOT#

THERMDA THERMDC

THERMTRIP#

H CLK

BCLK[0] BCLK[1]

RESERVED

H1 E2 G5

H5 F21 E1

H_IERR#

D20 B3

H4 C1

F3 F4 G3 G2

HIT#

E4 AD4

AD3 AD1 AC4 AC2 AC1 AC5

TCK

AA6

TDI

AB3

TDO

AB5

TMS

AB6 C20

D21 A24 B25

A22 A21

R319 56-5%-1/16W-0402R319 56-5%-1/16W-0402

R249 SHORT-0402-5MILR249 SHORT-0402-5MIL

XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET#

H_ADS# <12> H_BNR# <12>

H_BPRI# <12> H_DEFER# <12>

H_DRDY# <12> H_DBSY# <12>

H_BREQ#0 <12>

H_INIT# <21>

H_LOCK# <12>

H_CPURST# <12> H_RS#0 <12> H_RS#1 <12> H_RS#2 <12> H_TRDY# <12>

H_HIT# <12> H_HITM# <12>

1.05VS<9,12,15,16,18,21,24,38>

R318

R318 75-1%-1/16W-0402

75-1%-1/16W-0402

1.05VS <9,12,15,16,18,21,24,38>

R244

54.9-1%-1/16W-0402_NU

H_PROCHOT# <10> H_THERMDA <11> H_THERMDC <11>

PM_THRMTRIP# <13,21>

CLK_CPU_BCLK <18> CLK_CPU_BCLK# <18>

1.05VS <9,12,15,16,18,21,24,38>

Topology : FERR#

VCCP

VCCP L1

Rtt

VCCP

CPU IMVP6

Rtt

ICH7mCPU

L2+L1 L3 Strip-line

0" - 3.0" Micro-strip0.5" - 12"

0.5" - 12"L1

0" - 3.0"

Rtt

0.5" - 6.5"

Topology : PWRGOOD

CPU

ICH7m

Transmission Line

0.5" - 12"

Micro-strip

0.5" - 12" Strip-line

Topology : INTR , NMI , A20M# , DPSLP# , IGNNE# , INIT# , SMI# , STPCLK#

Transmission Line

L1CPU ICH7m

Topology : THERMTRIP#

GMCHL2CPU ICH8m

0.5" - 12" Micro-strip

Strip-line

0.5" - 12"

VCCP

RttL1 L4

Rtt

L1 L2

1" - 12"

1" - 12" 1" - 6"

Rtt Transmission Line

56 +/-5%

Strip-line

0" - 3.0"

Rtt Transmission LineL2L1

Micro-strip70 +/-5%0.5" - 6.5"

70 +/-5%0.5" - 6.5"

L3 L4

0" - 3.0"

Topology : CPUSLP#

GMCH

Topology : RESET#

GMCH

L1+L3

1" - 6" 0" - 3.0"

1" - 12"

0" - 3.0"

Rss

24 +/-5%

L1CPU

0.5" - 12"

1" - 6"

Transmission Line

Micro-strip

Strip-line

Transmission LineCPU

Micro-strip

Strip-line

Rtt

56 +/-5%

Transmission LineL4

Micro-strip

Strip-line0" - 3.0"

Should be connect to ICH8 and Calistoga without T-ing(no stub)

XDP P/U & P/D

XDP_DBRESET#

XDP_TMS XDP_TDI XDP_BPM#5

XDP_TRST# XDP_TCK

R316 1K-5%-1/16W-0402R316 1K-5%-1/16W-0402

R247 39.2-1%-1/16W-0402R247 39.2-1%-1/16W-0402 R245 150-1%-1/16W-0402R245 150-1%-1/16W-0402 R246 54.9-1%-1/16W-0402R246 54.9-1%-1/16W-0402

R248 649-1%-1/16W-0402R248 649-1%-1/16W-0402 R240 27-5%-1/10W-0603R240 27-5%-1/10W-0603

7/4 MODIFY

3VS <10,11,13,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

1.05VS <9,12,15,16,18,21,24,38>

FSB Common Clock Signal Layout Guide :

H_ADS# , H_BNR# , H_BPRI# , H_BR0# , H_DBSY# , H_DEFER# , H_DPWR# , H_DRDY# , H_HIT# , H_HITM# , H_LOCK# ,H_ RS#[2..0] , H_TRDY# , H_CPURST#.

Transmission Line Type Total Trace Length Normal Impedance Spacing (mils)

Strip-line(Int. Layer)

Micro-strip(Ext. Layer)

1.0 ~ 6.5 inch

55+/-15%

W=4 & S=8 mils

W=5 & S=10 mils

H_D#[63..0]<12>

2 2

H_DSTBN#0<12>

H_DSTBP#0<12>

H_DINV#0<12>

H_D#[63..0]<12>

1.05VS<9,12,15,16,18,21,24,38>

R314

1K-1%-1/16W-0402

R315

2K-1%-1/16W-0402

1 1

2K-1%-1/16W-0402

H_DSTBN#1<12>

H_DSTBP#1<12>

H_DINV#1<12>

Zo=55ohm, 0.5" max for GTLREF, Space any other switch signals away from GTLREF with a minimum of 25mils.

Don't allow the GTLREF routing to create splits or discontinuities in the reference planes of the FSB signals

H_D#[63..0]

1K-5%-1/16W-0402_NU

1K-5%-1/16W-0402_NU R299

R299 R317

R317

1K-5%-1/16W-0402_NU

1K-5%-1/16W-0402_NU C431

C431

0.1uF 10V 10% 0402 X5R_NU

CLK_BSEL0<18>

H_TEST2

CN8B

H_D#0

E22

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15

H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31

GTLREF COMP0 H_TEST1

H_TEST4

D[0]#

F24

D[1]#

E26

D[2]#

AD26

AF26

G22

F23

G25

E25

E23

K24

G24

J24

J23

H22

F26

K22

H23

J26

H26

H25

N22

K25

P26

R23

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

T25

N25

L26

M26

N24

C23

D25

C24

AF1

A26

B22

B23

C21

DATA GRP 0 DATA GRP 1

D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]#

D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]#

GTLREF

MISC

TEST1 TEST2 TEST3 TEST4 TEST5 TEST6

BSEL[0] BSEL[1] BSEL[2]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]#

DATA GRP 2DATA GRP 3

D[45]# D[46]#

D[47]# DSTBN[2]# DSTBP[2]#

DINV[2]#

D[48]#

D[49]#

D[50]#

D[51]#

D[52]#

D[53]#

D[54]#

D[55]#

D[56]#

D[57]#

D[58]#

D[59]#

D[60]#

D[61]#

D[62]#

D[63]# DSTBN[3]# DSTBP[3]#

DINV[3]# COMP[0]

COMP[1] COMP[2] COMP[3]

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22

AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20

R26 U26 AA1 Y1

E5 B5 D24 D6 D7 AE6

PSI#

H_D#[63..0] H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47

H_D#[63..0] H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

R312 27.4-1%-1/16W-0402R312 27.4-1%-1/16W-0402

COMP1

R313 54.9-1%-1/16W-0402R313 54.9-1%-1/16W-0402

COMP2

R243 27.4-1%-1/16W-0402R243 27.4-1%-1/16W-0402

COMP3

R242 54.9-1%-1/16W-0402R242 54.9-1%-1/16W-0402

H_DPRSTP# <10,13,21> H_DPSLP# <21> H_DPWR# <12> H_PWRGD <21> H_CPUSLP# <12> PSI# <10>

H_PWRGD rise time : Max : 15ns

H_D#[63..0] <12>

H_DSTBN#2 <12> H_DSTBP#2 <12> H_DINV#2 <12>

H_D#[63..0] <12>

H_DSTBN#3 <12> H_DSTBP#3 <12> H_DINV#3 <12>

Comp0,2 connect with Zo=27.4ohm, make trace length shorter than 0.5" and width is 18mils.

Comp1,3 connect with Zo=55ohm, make trace length shorter than 0.5" and width is 5mils

FSB Source Synchronous Data Length Variation and Strobe Matching Requirements :

Signals Name

H_D#[15..0] , H_DINV#0

H_D#[31..16] , H_DINV#1

H_D#[47..32] , H_DINV#2

H_D#[63..48] , H_DINV#3

FSB Source Synchronous Data Signal Routing Topology#1 :

Signal Name

H_DINV#[3..0]

H_DATA#[63..0]

H_DSTBN#[3..0]

H_DSTBP#[3..0]

FSB Source Synchronous Address Length Variation and Strobe Matching Requirements :

H_A#[16..3] , H_REQ#[4..0]

H_A#[35..17]

*** No length matching requirements exist between H_ADSTB#0 and H_ADSTB#1

FSB Source Synchronous Address Signal Routing :

Signal Name

H_A#[35..3]

H_REQ#[4..0]

H_ADSTB#[1..0]

Signals Matching

+/- 100 mils

Transmission Line Type

Strip-line

Signals MatchingSignals Name

+/- 200 mils

Transmission Line Type

Strip-line

Strobes associated with the group Strobe-to-Strobe Complement Matching

H_DSTBP#0, H_DSTBN#0

H_DSTBP#1, H_DSTBN#1

H_DSTBP#2, H_DSTBN#2

H_DSTBP#3, H_DSTBN#3

Total Trace Length

0.5 ~ 5.5 inch

Strobes associated with the group

H_ADSTB#0

H_ADSTB#1

Total Trace Length Normal Impedance

0.5 ~ 6.5 inch

Normal Impedance

55+/-15%

55+/-15%Strip-line

+/- 25 mils+/- 100 mils

+/- 25 mils

Width & Spacing (mils)

Data-to-Data,Strobe-to-strobe Strobe-to-Data

W=4 & S=8 mils

W=4 & S=4 mils

Strobe to Assoc. Address Signal Matching

+/- 200 mils

Width & Spacing (mils)

W=4 & S=8 mils

W=4 & S=12 mils

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Merom Processor(1/2)

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

N/A

W=4 & S=12 mils

Rev

AX1

Place these inside socket cavity on L8 (North side secondary)

4 4

3 3

VCORE_CPU<10>

Place these inside socket cavity on L1 (North side Primary)

C381

C357

C366

C363

C373

10uF 6.3V 10% 0805 X5R

C66 10uF 6.3V 10% 0805 X5RC66 10uF 6.3V 10% 0805 X5R

C92 10uF 6.3V 10% 0805 X5RC92 10uF 6.3V 10% 0805 X5R

C35 10uF 6.3V 10% 0805 X5RC35 10uF 6.3V 10% 0805 X5R

C87 10uF 6.3V 10% 0805 X5RC87 10uF 6.3V 10% 0805 X5R

C78 10uF 6.3V 10% 0805 X5RC78 10uF 6.3V 10% 0805 X5R

North side secondary

C94 T330uF 2V 9m 7343 PANASONIC_NU+C94 T330uF 2V 9m 7343 PANASONIC_NU

C80 T330uF 2V 9m 7343 PANASONIC_NU+C80 T330uF 2V 9m 7343 PANASONIC_NU

C27 T330uF 2V 9m 7343 PANASONIC+C27 T330uF 2V 9m 7343 PANASONIC

2 2

Place these inside socket cavity on L8 (South side secondary)

C382 10uF 6.3V 10% 0805 X5RC382 10uF 6.3V 10% 0805 X5R C93 10uF 6.3V 10% 0805 X5RC93 10uF 6.3V 10% 0805 X5R

C369 10uF 6.3V 10% 0805 X5RC369 10uF 6.3V 10% 0805 X5R

C374 10uF 6.3V 10% 0805 X5RC374 10uF 6.3V 10% 0805 X5R

C364 10uF 6.3V 10% 0805 X5RC364 10uF 6.3V 10% 0805 X5R

C358 10uF 6.3V 10% 0805 X5RC358 10uF 6.3V 10% 0805 X5R

Place these inside socket cavity on L1 (South side Primary)

C36 10uF 6.3V 10% 0805 X5RC36 10uF 6.3V 10% 0805 X5R

C79 10uF 6.3V 10% 0805 X5RC79 10uF 6.3V 10% 0805 X5R

C67 10uF 6.3V 10% 0805 X5RC67 10uF 6.3V 10% 0805 X5R

South side secondary

C37 T330uF 2V 9m 7343 PANASONIC+C37 T330uF 2V 9m 7343 PANASONICC88 10uF 6.3V 10% 0805 X5RC88 10uF 6.3V 10% 0805 X5R

C81 T330uF 2V 9m 7343 PANASONIC+C81 T330uF 2V 9m 7343 PANASONIC+C99 T330uF 2V 9m 7343 PANASONIC+C99 T330uF 2V 9m 7343 PANASONIC

CN8C

VCC[001]

VCC[068]

VCC[002]

VCC[069]

VCC[003]

VCC[070]

VCC[004]

VCC[071]

VCC[005]

VCC[072]

VCC[006]

VCC[073]

VCC[007]

VCC[074]

VCC[008]

VCC[075]

VCC[009]

VCC[076]

VCC[010]

VCC[077]

VCC[011]

VCC[078]

VCC[012]

VCC[079]

VCC[013]

VCC[080]

VCC[014]

VCC[081]

VCC[015]

VCC[082]

VCC[016]

VCC[083]

VCC[017]

VCC[084]

VCC[018]

VCC[085]

VCC[019]

VCC[086]

VCC[020]

VCC[087]

VCC[021]

VCC[088]

VCC[022]

VCC[089]

VCC[023]

VCC[090]

VCC[024]

VCC[091]

VCC[025]

VCC[092]

VCC[026]

VCC[093]

VCC[027]

VCC[094]

VCC[028]

VCC[095]

VCC[029]

VCC[096]

VCC[030]

VCC[097]

VCC[031]

VCC[098]

VCC[032]

VCC[099]

VCC[033]

VCC[100] VCC[034] VCC[035]

VCCP[01] VCC[036]

VCCP[02] VCC[037]

VCCP[03] VCC[038]

VCCP[04] VCC[039]

VCCP[05] VCC[040]

VCCP[06] VCC[041]

VCCP[07] VCC[042]

VCCP[08] VCC[043]

VCCP[09] VCC[044]

VCCP[10] VCC[045]

VCCP[11] VCC[046]

VCCP[12] VCC[047]

VCCP[13] VCC[048]

VCCP[14] VCC[049]

VCCP[15] VCC[050]

VCCP[16] VCC[051] VCC[052]

VCCA[01] VCC[053]

VCCA[02] VCC[054] VCC[055]

VID[0]

VCC[056]

VID[1]

VCC[057]

VID[2]

VCC[058]

VID[3]

VCC[059]

VID[4]

VCC[060]

VID[5]

VCC[061]

VID[6] VCC[062] VCC[063] VCC[064]

VCCSENSE VCC[065] VCC[066] VCC[067]

VSSSENSE

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AC10 AB10 AB12 AB14 AB15 AB17 AB18

A9 A10 A12 A13 A15 A17 A18 A20

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10 C12 C13 C15 C17 C18

D9 D10 D12 D14 D15 D17 D18

E9 E10 E12 E13 E15 E17 E18 E20

F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9

AB9

AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21

B26 C26

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AF7

AE7

H_VID0 <10> H_VID1 <10> H_VID2 <10> H_VID3 <10> H_VID4 <10> H_VID5 <10> H_VID6 <10>

Route VCCSENSE and VSSSENSE traces at 27.4 ohms with 50mil spacing. Place PU and PD within 1 inch of CPU

C350 0.1uF 10V 10% 0402 X7RC350 0.1uF 10V 10% 0402 X7R

C398 0.1uF 10V 10% 0402 X7RC398 0.1uF 10V 10% 0402 X7R

C368 0.1uF 10V 10% 0402 X7RC368 0.1uF 10V 10% 0402 X7R

C399 0.1uF 10V 10% 0402 X7RC399 0.1uF 10V 10% 0402 X7R

Close to CPU pin B26

C433

0.01uF 16V 10% 0402 X7R

VCORE_CPU<10>

R260

R260 100-1%-1/16W-0402

100-1%-1/16W-0402

R259

R259 100-1%-1/16W-0402

100-1%-1/16W-0402

C349 0.1uF 10V 10% 0402 X7RC349 0.1uF 10V 10% 0402 X7R

C367 0.1uF 10V 10% 0402 X7RC367 0.1uF 10V 10% 0402 X7R

20mil

160mil

1.05VS <8,12,15,16,18,21,24,38>

C442

T220uF 2V 15m 7343 PANASONIC

Place these inside socket cavity on L8 (North side secondary)

1.5VS<16,21,22,24,28,38,39>

C436

C436 10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

VCCSENSE <10> VSSSENSE <10>

18mil 7mil space

CN8D

VSS[001]

VSS[002]

A11

VSS[003]

A14

VSS[004]

A16

VSS[005]

A19

VSS[006]

A23

VSS[007]

AF2

VSS[008]

VSS[009]

VSS[010]

B11

VSS[011]

B13

VSS[012]

B16

VSS[013]

B19

VSS[014]

B21

VSS[015]

B24

VSS[016]

VSS[017]

VSS[018]

C11

VSS[019]

C14

VSS[020]

C16

VSS[021]

C19

VSS[022]

VSS[023]

C22

VSS[024]

C25

VSS[025]

VSS[026]

VSS[027]

VSS[028]

D11

VSS[029]

D13

VSS[030]

D16

VSS[031]

D19

VSS[032]

D23

VSS[033]

D26

VSS[034]

VSS[035]

VSS[036]

VSS[037]

E11

VSS[038]

E14

VSS[039]

E16

VSS[040]

E19

VSS[041]

E21

VSS[042]

E24

VSS[043]

VSS[044]

VSS[045]

F11

VSS[046]

F13

VSS[047]

F16

VSS[048]

F19

VSS[049]

VSS[050]

F22

VSS[051]

F25

VSS[052]

VSS[053]

VSS[054]

G23

VSS[055]

G26

VSS[056]

VSS[057]

VSS[058]

H21

VSS[059]

H24

VSS[060]

VSS[061]

VSS[062]

J22

VSS[063]

J25

VSS[064]

VSS[065]

VSS[066]

K23

VSS[067]

K26

VSS[068]

VSS[069]

VSS[070]

L21

VSS[071]

L24

VSS[072]

VSS[073]

VSS[074]

M22

VSS[075]

M25

VSS[076]

VSS[077]

VSS[078]

N23

VSS[079]

N26

VSS[080]

VSS[081]

SCKT CPU 478P PZ4782K-274M-41 FOXCONN

6026B0056801

VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163]

P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25

1 1

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Merom Processor(2/2)

Date: Sheet of

Merom Processor(2/2)

Friday, June 01, 2007

Rev

AX1

D D

2.2K-5%-1/16W-0402

C C

H_VID0<9> H_VID1<9> H_VID2<9> H_VID3<9> H_VID4<9> H_VID5<9> H_VID6<9>

B B

R605 10K-5%-1/16W-0402_NUR605 10K-5%-1/16W-0402_NU

8770GND

R608 10K-5%-1/16W-0402_NUR608 10K-5%-1/16W-0402_NU

R607 10K-5%-1/16W-0402_NUR607 10K-5%-1/16W-0402_NU

R606 10K-5%-1/16W-0402_NUR606 10K-5%-1/16W-0402_NU

8770GND

VCORE_GD<13,23>

CORECLK_EN#<23>

R609 10K-5%-1/16W-0402_NUR609 10K-5%-1/16W-0402_NU

R610 10K-5%-1/16W-0402_NUR610 10K-5%-1/16W-0402_NU

R611 10K-5%-1/16W-0402_NUR611 10K-5%-1/16W-0402_NU

PSI#<8> VR_ON<31> H_DPRSTP#<8,13,21>

PM_DPRSLPVR<13,23>

8770GND

8770VCC

R391

R612 SHORT-0402-5MILR612 SHORT-0402-5MIL R388 SHORT-0402-5MILR388 SHORT-0402-5MIL

R613 SHORT-0402-5MILR613 SHORT-0402-5MIL

C513 470pF 50V 10% 0402 X7RC513 470pF 50V 10% 0402 X7R

R396 71.5K 1% 1/10W 0603R396 71.5K 1% 1/10W 0603

C511

0.22uF 10V 10% 0603 X7R

R393

R393 10K-5%-1/16W-0402

10K-5%-1/16W-0402

H_PROCHOT#<8>

TP1TP1

5VA <24,27,30,34,37,38,39,40>

R376

10-5%-1/10W-0603

8770VCC

C502

2.2uF 10V 10% 0805 X5R

3VS <8,11,13,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

8770GND

U31

R392

2.2K-5%-1/16W-0402

8770GND

U31

2 1

31 32 33 34 35 36 37

3 38 40 39

8770REF

11 18

MAX8770GTL+ TQFN 40P MAXIM

6019B0130201

8770GND

PWRGD CLKEN

D0 D1 D2 D3 D4 D5 D6

PSI SHDN DPRSTP DPRSLPVR

CCV

TIME

REF GND

THRM

VRHOT POUT

VCC

R102

SHORT-0402-40MIL

TON

VDD

BST1

LX1 DH1 DL1

PGND1

CCI

GNDS

CSN1 CSP1

CSP2 CSN2

DH2 DL2 LX2

BST2

PGND2

C494

C494 10uF 6.3V 10% 0805 X5R

10uF 6.3V 10% 0805 X5R

8 30 28 29 26 27

16 17

14 15

21 24 22 20 23

R394

R394 200K 1% 1/16W 0402

200K 1% 1/16W 0402

R369 2.2-5%-1/10W-0603R369 2.2-5%-1/10W-0603

R384 3.9K 1% 1/10W 0603R384 3.9K 1% 1/10W 0603

10K-5%-0603-NTC_NU

5.11K-1%-1/10W-0603_NU

5.11K-1%-1/10W-0603_NU R387

R387

20K-1%-1/16W-0402

R395

C514

470pF 50V 10% 0402 X7R

8770CSN1 8770CSP1

8770CSP2 8770CSN2

R370 2.2-5%-1/10W-0603R370 2.2-5%-1/10W-0603

0.22uF 25V 10% 0603 X5R

0.22uF 25V 10% 0603 X5R C496

C496

R385

8770GND

0.22uF 25V 10% 0603 X5R

100-1%-1/16W-0402

100-1%-1/16W-0402 R386

R386

C508

C508 1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

R383

100-1%-1/16W-0402

C505

C505 1000pF 50V 10% 0402 X7R

1000pF 50V 10% 0402 X7R

C497

Q32

Q33

789

Q34

789

D S

VCCSENSE <9>

VSSSENSE <9>

789

D S

789

D S

DCIN<27,35,36,37,39,40>

10UF 25V 10% 1206 X5R

L51

0.36uH 20% 25.5A 11.5X10X4

R304

2.67K 1% 1/10W 0603

R308

2.1K 1% 1/10W 0603

C427

0.22uF 10V 10% 0603 X7R

FDMS8690 30V 19.8A 8P_NU

Q30

FDMS8670S 30V 20A 8P

8770CSP2 8770CSN2

DCIN

C477

10K-5%-0603-NTC

10K-5%-0603-NTC R320

R320

10UF 25V 10% 1206 X5R

C475

L52

0.36uH 20% 25.5A 11.5X10X4

R305

2.67K 1% 1/10W 0603

R309

2.1K 1% 1/10W 0603

C428

0.22uF 10V 10% 0603 X7R

C478

C478 10UF 25V 10% 1206 X5R

10UF 25V 10% 1206 X5R

DCIN<27,35,36,37,39,40>

10UF 25V 10% 1206 X5R

C476

10K-5%-0603-NTC

10K-5%-0603-NTC R321

R321

C480 T5.6uF 25V 100m 3528 SANYO_NU

C479 T5.6uF 25V 100m 3528 SANYO_NU

VCORE_CPU<9>

FDMS8690 30V 19.8A 8P_NU

789

D S

789

D S

FDMS8690 30V 19.8A 8P_NU

Q35

Q29

Q29 FDMS8670S 30V 20A 8P

FDMS8670S 30V 20A 8P

8770CSP1 8770CSN1

789

Q36

789

D S

FDMS8690 30V 19.8A 8P

FDMS8670S 30V 20A 8P

FDMS8690 30V 19.8A 8P

Q37

FDMS8670S 30V 20A 8P

A A

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Custom

Date: Sheet of 4310

Friday, June 01, 2007

CPU Core Power

Rev

AX1

D D

THERMAL SENSOR

3VS<8,10,13,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

C435

0.1uF 10V 10% 0402 X7R

10mil

THRM#<31>

C C

H_THERMDA<8> H_THERMDC<8>

C435

H_THERMDC

R322

R322 10K-5%-1/16W-0402

10K-5%-1/16W-0402

C437 2200pF 50V 5% 0603 X7RC437 2200pF 50V 5% 0603 X7R

U27

VDD

DXP

DXN

ALERT#

THERM#4GND

G784P81U MSOP 8P

6019B0221201

SCLK

SDATA

THRMSCK

THRMSDAH_THERMDA

7 6 5

THRMSCK <31> THRMSDA <31>

10mil

B B

B Change

5VS<24,25,26,27,30,31,32,33,34,38>

A A

Fan control

FDN338P 20V 1.6A SOT3

C259

0.01uF 16V 10% 0402 X7R_NU

C259

0.01uF 16V 10% 0402 X7R_NU 1K-5%-1/16W-0402

1K-5%-1/16W-0402

C243

10UF 25V 10% 1206 X5R

FANCTL1<31>

Q40

S D

R118

0-5%-1/16W-0402

R119

NPN PDTC144EU 50V 100mA SOT223

E C

30mil

5VS_FAN

R415

10-5%-1/16W-0402_NU

R415

10-5%-1/16W-0402_NU

CN17

FAN_TACH1<31>

C537

3300pF 50V 10% 0402 X7R_NU

C537

3300pF 50V 10% 0402 X7R_NU

C538

1uF 6.3V 10% 0402 X5R_NU

C538

1uF 6.3V 10% 0402 X5R_NU

CN 3P 3702-F03C-02R ENTERY

6012B0191701

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Friday, June 01, 2007

CPU Thermal

Rev

AX1

H H

1.05VS<8,9,15,16,18,21,24,38>

R54

54.9-1%-1/16W-0402

G G

F F

54.9-1%-1/16W-0402

H_SCOMP#

1.05VS<8,9,15,16,18,21,24,38> 1.05VS<8,9,15,16,18,21,24,38>

R46

54.9-1%-1/16W-0402

H_SCOMP

H_RCOMP

R32

24.9-1%-1/16W-0402

10mil

R24

R24 221-1%-1/16W-0402

221-1%-1/16W-0402

R25

R25 100-1%-1/16W-0402

100-1%-1/16W-0402

10mil

H_SWING

H_D#[63..0]<8>

C58

0.1uF 10V 10% 0402 X7R

H_D#[63..0]

Trace should be 10-mil wide with 20-mil spacing

E E

D D

H_SWING H_RCOMP

H_SCOMP H_SCOMP#

H_CPURST#<8>

1.05VS<8,9,15,16,18,21,24,38>

C C

R18

R18 1K-1%-1/16W-0402

1K-1%-1/16W-0402

H_CPUSLP#<8>

H_AVREF

U7A

H_D#0

H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63

H_D#_0

H_D#_1

H_D#_2

H_D#_3

H_D#_4

H_D#_5

H_D#_6

H_D#_7

H_D#_8

H_D#_9

M10

H_D#_10

N12

H_D#_11

H_D#_12

H_D#_13

P13

H_D#_14

H_D#_15

H_D#_16

W10

H_D#_17

H_D#_18

H_D#_19

H_D#_20

H_D#_21

H_D#_22

H_D#_23

H_D#_24

H_D#_25

H_D#_26

H_D#_27

H_D#_28

H_D#_29

H_D#_30

H_D#_31

AD12

H_D#_32

AE3

H_D#_33

AD9

H_D#_34

AC9

H_D#_35

AC7

H_D#_36

AC14

H_D#_37

AD11

H_D#_38

AC11

H_D#_39

AB2

H_D#_40

AD7

H_D#_41

AB1

H_D#_42

H_D#_43

AC6

H_D#_44

AE2

H_D#_45

AC5

H_D#_46

AG3

H_D#_47

AJ9

H_D#_48

AH8

H_D#_49

AJ14

H_D#_50

AE9

H_D#_51

AE11

H_D#_52

AH12

H_D#_53

AJ5

H_D#_54

AH5

H_D#_55

AJ6

H_D#_56

AE7

H_D#_57

AJ7

H_D#_58

AJ2

H_D#_59

AE5

H_D#_60

AJ3

H_D#_61

AH2

H_D#_62

AH13

H_D#_63

H_SWING

H_RCOMP

H_SCOMP

H_SCOMP#

H_CPURST#

H_CPUSLP#

H_AVREF

H_DVREF

Crestline FBGA 1299P INTEL 6019B0412201

H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8

H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35

H_ADS# H_ADSTB#_0 H_ADSTB#_1

H_BNR#

H_BPRI#

H_BREQ#

H_DEFER#

HOST

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HIT#

H_HITM# H_LOCK# H_TRDY#

H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3

H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3

H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3

H_REQ#_0 H_REQ#_1

H_REQ#_2 H_REQ#_3

H_REQ#_4

H_RS#_0

H_RS#_1

H_RS#_2

B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19

G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7

K5 L2 AD13 AE13

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

M14 E13 A11 H13 B12

E12 D7 D8

H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35

H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4

H_A#3

J13

H_A#[35..3]

H_REQ#[4..0]

H_A#[35..3] <8>

H_ADS# <8> H_ADSTB#0 <8> H_ADSTB#1 <8> H_BNR# <8> H_BPRI# <8> H_BREQ#0 <8> H_DEFER# <8> H_DBSY# <8> CLK_MCH_BCLK <18> CLK_MCH_BCLK# <18> H_DPWR# <8> H_DRDY# <8> H_HIT# <8> H_HITM# <8> H_LOCK# <8> H_TRDY# <8>

H_DINV#0 <8> H_DINV#1 <8> H_DINV#2 <8> H_DINV#3 <8>

H_DSTBN#0 <8> H_DSTBN#1 <8> H_DSTBN#2 <8> H_DSTBN#3 <8>

H_DSTBP#0 <8> H_DSTBP#1 <8> H_DSTBP#2 <8> H_DSTBP#3 <8> H_REQ#[4..0] <8>

H_RS#0 <8> H_RS#1 <8> H_RS#2 <8>

10mil

R28

R19

R19 2K-1%-1/16W-0402

2K-1%-1/16W-0402

C38

0.1uF 10V 10% 0402 X7R

R28 0-5%-1/16W-0402

0-5%-1/16W-0402

H_DVREF

B B

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

A A

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Crestline Host(1/6)

Friday, June 01, 2007

Rev

AX1

U7B

P36

RSVD1

P37

H H

C372

Add for Intel ref design v1.3

C372

0.1uF 10V 10% 0402 X7R

G G

F F

MCH_BSEL0<18> MCH_BSEL1<18> MCH_BSEL2<18>

E E

PM_BMBUSY#<23>

D D

H_DPRSTP#<8,10,21> PM_EXTTS#0<19> PM_EXTTS#1<20>

PLT_RST#<22,31> PM_THRMTRIP#<8,21> PM_DPRSLPVR<10,23>

VCORE_GD<10,23>

PM_ICH_PWROK<23,25>

NC_MCH_CFG3 NC_MCH_CFG4 MCH_CFG5 NC_MCH_CFG6 NC_MCH_CFG7 NC_MCH_CFG8 MCH_CFG9 NC_MCH_CFG10 NC_MCH_CFG11 MCH_CFG12 MCH_CFG13 NC_MCH_CFG14 NC_MCH_CFG15 MCH_CFG16 NC_MCH_CFG17 MCH_CFG18 MCH_CFG19 MCH_CFG20

PM_EXTTS#0 PM_EXTTS#1

R327 100-1%-1/16W-0402R327 100-1%-1/16W-0402

R390 0-5%-1/16W-0402R390 0-5%-1/16W-0402 R614 0-5%-1/16W-0402_NUR614 0-5%-1/16W-0402_NU

Please Layout in Top Side

C C

B Change

3VS <8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

R277

R277 10K-5%-1/16W-0402

10K-5%-1/16W-0402 R276

R276 10K-5%-1/16W-0402

10K-5%-1/16W-0402

PM_EXTTS#0

PM_EXTTS#1

RSVD2

R35

RSVD3

N35

RSVD4

AR12

RSVD5

AR13

RSVD6

AM12

RSVD7

AN13

RSVD8

J12

RSVD9

AR37

RSVD10

AM36

RSVD11

AL36

RSVD12

AM37

RSVD13

D20

RSVD14

H10

RSVD20

B51

RSVD21

BJ20

RSVD22

BK22

RSVD23

BF19

RSVD24

BH20

RSVD25

BK18

RSVD26

BJ18

RSVD27

BF23

RSVD28

BG23

RSVD29

BC23

RSVD30

BD24

RSVD31

BH39

RSVD34

AW20

RSVD35

BK20

RSVD36

B44

RSVD39

C44

RSVD40

A35

RSVD41

B37

RSVD42

B36

RSVD43

B34

RSVD44

C34

RSVD45

P27

CFG_0

N27

CFG_1

N24

CFG_2

C21

CFG_3

C23

CFG_4

F23

CFG_5

N23

CFG_6

G23

CFG_7

J20

CFG_8

C20

CFG_9

R24

CFG_10

L23

CFG_11

J23

CFG_12

E23

CFG_13

E20

CFG_14

K23

CFG_15

M20

CFG_16

M24

CFG_17

L32

CFG_18

N33

CFG_19

L35

CFG_20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#_0

J36

PM_EXT_TS#_1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC_1

BK51

NC_2

BK50

NC_3

BL50

NC_4

BL49

NC_5

BL3

NC_6

BL2

NC_7

BK1

NC_8

BJ1

NC_9

NC_10

NC_11

C51

NC_12

B50

NC_13

A50

NC_14

A49

NC_15

BK2

NC_16

Crestline FBGA 1299P INTEL

DDR MUXINGCLK

CFGRSVD

DMI

GRAPHICS VID

MISC

SM_RCOMP_VOH SM_RCOMP_VOL

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

SDVO_CTRL_CLK

SDVO_CTRL_DATA

CRESTLINE (965GM) Strapping:

B B

A A

MCH_CFG18

R292 1K-5%-1/16W-0402_NUR292 1K-5%-1/16W-0402_NU

MCH_CFG19

R270 4.02K-1%-1/16W-0402R270 4.02K-1%-1/16W-0402

MCH_CFG20

R291 4.02K-1%-1/16W-0402_NUR291 4.02K-1%-1/16W-0402_NU

MCH_CFG5

R283 4.02K-1%-1/16W-0402_NUR283 4.02K-1%-1/16W-0402_NU

MCH_CFG9

R280 2.2K-5%-1/16W-0402_NUR280 2.2K-5%-1/16W-0402_NU

MCH_CFG16

R293 4.02K-1%-1/16W-0402_NUR293 4.02K-1%-1/16W-0402_NU

MCH_CFG12

R288 4.02K-1%-1/16W-0402_NUR288 4.02K-1%-1/16W-0402_NU

MCH_CFG13

R279 4.02K-1%-1/16W-0402_NUR279 4.02K-1%-1/16W-0402_NU

3VS<8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

MCH_CFG5

MCH_CFG9 (PCIE Graphic Lane)

MCH_CFG16 (FSB Dynamic ODT)

MCH_CFG18 (VCC Select)

MCH_CFG19 (DMI Lane Reversal)

MCH_CFG20

AV29

SM_CK_0

BB23

SM_CK_1

BA25

SM_CK_3

AV23

SM_CK_4

AW30

SM_CK#_0

BA23

SM_CK#_1

AW25

SM_CK#_3

AW23

SM_CK#_4

BE29

SM_CKE_0

AY32

SM_CKE_1

BD39

SM_CKE_3

BG37

SM_CKE_4

BG20

SM_CS#_0

BK16

SM_CS#_1

BG16

SM_CS#_2

BE13

SM_CS#_3

BH18

SM_ODT_0

BJ15

SM_ODT_1

BJ14

SM_ODT_2

BE16

SM_ODT_3

SM_RCOMP

SM_RCOMP#

SM_VREF_0 SM_VREF_1

PEG_CLK

PEG_CLK#

DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3

DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3

DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3

DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3

BL15 BK14

BK31 BL31

AR49 AW4

B42 C42 H48 H47

K44 K45

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

M_RCOMP M_RCOMP#

M_RCOMP_VOH M_RCOMP_VOL

M_VREF

DMI_TXN3 DMI_TXN2 DMI_TXN1 DMI_TXN0

DMI_TXP3 DMI_TXP2 DMI_TXP1 DMI_TXP0

DMI_RXN3 DMI_RXN2 DMI_RXN1 DMI_RXN0

DMI_RXP3 DMI_RXP2 DMI_RXP1 DMI_RXP0

Change 0,1,2,3 to 3,2,1,0.

E35

GFX_VID_0

A39

GFX_VID_1

C38

GFX_VID_2

B39

GFX_VID_3

E36

GFX_VR_EN

AM49

CL_CLK

AK50

CL_DATA

AT43

CL_PWROK

AN49

CL_RST# CL_VREF

CLK_REQ#

ICH_SYNC#

TEST_1 TEST_2

6019B0412201

MCH_CLVREF

AM50

H35 K36 G39 G40

MCH_TEST1

A37

MCH_TEST2

R32

Low

DMIx2

Reverse Lane

Dynamic ODT Disable

1.05V

Normal Lanes Reversed

Only SDVO or PCIE x1 is operation

M_CLK_DDR0 <19> M_CLK_DDR1 <19> M_CLK_DDR2 <20> M_CLK_DDR3 <20>

M_CLK_DDR#0 <19> M_CLK_DDR#1 <19> M_CLK_DDR#2 <20> M_CLK_DDR#3 <20>

M_CKE0 <19> M_CKE1 <19> M_CKE2 <20> M_CKE3 <20>

M_CS#0 <19> M_CS#1 <19> M_CS#2 <20> M_CS#3 <20>

M_ODT0 <19> M_ODT1 <19> M_ODT2 <20> M_ODT3 <20>

DREFCLK <18> DREFCLK# <18> DREFSSCLK <18> DREFSSCLK# <18>

CLK_PCIE_3GPLL <18> CLK_PCIE_3GPLL# <18>

DFGT_VID_0 <40> DFGT_VID_1 <40> DFGT_VID_2 <40> DFGT_VID_3 <40>

ALL_SYSPWRGD <23,31> CL_RST#0 <23>

20mil

M_VREF <19,20,39>

DMI_TXN[3..0]

DMI_TXP[3..0]

DMI_RXN[3..0]

DMI_RXP[3..0]

CL_CLK0 <23> CL_DATA0 <23>

SDVO_CTRL_CLK <26>

SDVO_CTRL_DATA <26> CLK_MCH_OE# <18> MCH_ICH_SYNC# <23>

High

DMIx4

Normal Operation

Dynamic ODT Enable

1.5V

Only SDVO or PCIE x1 with PEG port

Route M_OCDCMOP 0&1 as short as possible

DMI_TXN[3..0] <22>

DMI_TXP[3..0] <22>

DMI_RXN[3..0] <22>

DMI_RXP[3..0] <22>

C449

0.1uF 10V 10% 0402 X7R

TP4TP4

M_VREF

C441

0.1uF 10V 10% 0402 X7R

CRT_DDC_CLK<25> CRT_DDC_DATA<25> CRT_HSYNC<25>

CRT_VSYNC<25>

1.8V<15,16,19,20,26,39,40>

R91

R90

10mil

MCH_CLVREF

C139

0.1uF 10V 10% 0402 X7R

MCH_TEST1 MCH_TEST2

R22

0-5%-1/16W-0402

LCM_DDCPCLK<25> LCM_DDCPDATA<25>

LUMA<26> CHROMA<26>

CRT_BLUE<26> CRT_GREEN<26> CRT_RED<26>

M_RCOMP

20-1%-1/16W-0402

M_RCOMP#

20-1%-1/16W-0402

1.25VM_AXD <16>

R66

R66 1K-1%-1/16W-0402

1K-1%-1/16W-0402

R65

R65 392-1%-1/16W-0402

392-1%-1/16W-0402

R298

R298 20K-1%-1/16W-0402

20K-1%-1/16W-0402

R286 0-5%-1/16W-0402_NUR286 0-5%-1/16W-0402_NU

INV_PWM<25,31> BL_ENA<25>

LVDS_VDDEN<25>

LVDS_TXCLK_LN<25> LVDS_TXCLK_LP<25>

LVDS_TXOUT_L0N<25> LVDS_TXOUT_L1N<25> LVDS_TXOUT_L2N<25>

LVDS_TXOUT_L0P<25> LVDS_TXOUT_L1P<25> LVDS_TXOUT_L2P<25>

R281 75-1%-1/16W-0402R281 75-1%-1/16W-0402 R284 110 1% 1/16 0402R284 110 1% 1/16 0402 R289 110 1% 1/16 0402R289 110 1% 1/16 0402 R287 120-5%-1/16W-0402R287 120-5%-1/16W-0402 R290 120-5%-1/16W-0402R290 120-5%-1/16W-0402 R282 120-5%-1/16W-0402R282 120-5%-1/16W-0402

R272 30.1-0.5%-1/16W-0402R272 30.1-0.5%-1/16W-0402 R271 30.1-0.5%-1/16W-0402R271 30.1-0.5%-1/16W-0402

R285 SHORT-0402-5MILR285 SHORT-0402-5MIL

R294 2.37K-1%-1/16W-0402R294 2.37K-1%-1/16W-0402

TP5TP5

CRT_BLUE CRT_GREEN CRT_RED

10mil

NC_LVDS_TXOUT_U0N NC_LVDS_TXOUT_U1N NC_LVDS_TXOUT_U2N

NC_LVDS_TXOUT_U0P NC_LVDS_TXOUT_U1P NC_LVDS_TXOUT_U2P

3VS <8,10,11,16,18,19,20,21,22,23,24,25,26,27,28,29,31,32,33,34,38,39,40>

R274 10K-5%-1/16W-0402R274 10K-5%-1/16W-0402

R275 10K-5%-1/16W-0402R275 10K-5%-1/16W-0402

U7C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

L_VBG

LVDS_TXCLK_LN

LVDS_TXCLK_LP NC_LVDS_TXCLK_UN NC_LVDS_TXCLK_UP

LVDS_TXOUT_L0N

LVDS_TXOUT_L1N

LVDS_TXOUT_L2N

LVDS_TXOUT_L0P

LVDS_TXOUT_L1P

LVDS_TXOUT_L2P

TP6TP6 TP7TP7

REFSET

R273

1.3K-1%-1/16W-0402

1K-1%-1/16W-0402

3.01K 1% 1/16 0402

1K-1%-1/16W-0402

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#_0

E51

LVDSA_DATA#_1

F49

LVDSA_DATA#_2

C48

LVDSA_DATA#_3

G50

LVDSA_DATA_0

E50

LVDSA_DATA_1

F48

LVDSA_DATA_2

D47

LVDSA_DATA_3

G44

LVDSB_DATA#_0

B47

LVDSB_DATA#_1

B45

LVDSB_DATA#_2

E44

LVDSB_DATA_0

A47

LVDSB_DATA_1

A45

LVDSB_DATA_2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL_0

P33

TV_DCONSEL_1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

F33

CRT_HSYNC

C32

CRT_TVO_IREF

E33

CRT_VSYNC

Crestline FBGA 1299P INTEL

As close as possible to GMCH and Minimum spacing of 20 mils away from any toggle signals When the display is completely white , the RGB voltage is between 665mV to 770mV by VESA

Spec

If meet , CRT_IREF resistor value is optimal

Place 150ohm termination resistor close to GMCH

1.8V <15,16,19,20,26,39,40>

R93

0.01uF 16V 10% 0402 X7R

M_RCOMP_VOH

C168

C165

R92

R94

C165

2.2uF 10V 10% 0805 X5R

M_RCOMP_VOL

C169

C166

2.2uF 10V 10% 0805 X5R

0.01uF 16V 10% 0402 X7R

VCC_PEG<16>

R300

24.9-1%-1/16W-0402

PEG_COMP

N43

PEG_COMPI

M43

PEG_COMPO

J51

PEG_RX#_0

L51

PEG_RX#_1

N47

PEG_RX#_2

T45

PEG_RX#_3

T50

PEG_RX#_4

U40

PEG_RX#_5

Y44

PEG_RX#_6

Y40

PEG_RX#_7

AB51

PEG_RX#_8

LVDS

TV VGA

PCI-EXPRESS GRAPHICS

PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15

PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8

PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9

PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15

PEG_TX_0

PEG_TX_1

PEG_TX_2

PEG_TX_3

PEG_TX_4

PEG_TX_5

PEG_TX_6

PEG_TX_7

PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15

6019B0412201

W49 AD44 AD40 AG46 AH49 AG45 AG41

J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42

C404 0.1uF 10V 10% 0402 X7RC404 0.1uF 10V 10% 0402 X7R

N45 U39

C397 0.1uF 10V 10% 0402 X7RC397 0.1uF 10V 10% 0402 X7R

U47 N51

C384 0.1uF 10V 10% 0402 X7RC384 0.1uF 10V 10% 0402 X7R

R50 T42

C378 0.1uF 10V 10% 0402 X7RC378 0.1uF 10V 10% 0402 X7R

Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44

C407 0.1uF 10V 10% 0402 X7RC407 0.1uF 10V 10% 0402 X7R

M45 T38

C402 0.1uF 10V 10% 0402 X7RC402 0.1uF 10V 10% 0402 X7R

T46 N50

C386 0.1uF 10V 10% 0402 X7RC386 0.1uF 10V 10% 0402 X7R

R51 U43

C380 0.1uF 10V 10% 0402 X7RC380 0.1uF 10V 10% 0402 X7R

W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43

Inventec Corporation

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

Date: Sheet of

Friday, June 01, 2007

SDVOB_INT- <26>

SDVOB_INT+ <26>

SDVOB_RED- <26>

SDVOB_GREEN- <26>

SDVOB_BLUE- <26>

SDVOB_CLK- <26>

SDVOB_RED+ <26> SDVOB_GREEN+ <26> SDVOB_BLUE+ <26>

SDVOB_CLK+ <26>

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan TEL:+886-2-2881-0721

TEL:+886-2-2881-0721

Crestline DMI/Graph2/6)

Rev

AX1

H H

G G

M_A_DQ[63..0]<19>

F F

E E

D D

C C

M_A_DQ[63..0]

M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63

U7D

AR43

SA_DQ_0

AW44

SA_DQ_1

BA45

SA_DQ_2

AY46

SA_DQ_3

AR41

SA_DQ_4

AR45

SA_DQ_5

AT42

SA_DQ_6

AW47

SA_DQ_7

BB45

SA_DQ_8

BF48

SA_DQ_9

BG47

SA_DQ_10

BJ45

SA_DQ_11

BB47

SA_DQ_12

BG50

SA_DQ_13

BH49

SA_DQ_14

BE45

SA_DQ_15

AW43

SA_DQ_16

BE44

SA_DQ_17

BG42

SA_DQ_18

BE40

SA_DQ_19

BF44

SA_DQ_20

BH45

SA_DQ_21

BG40

SA_DQ_22

BF40

SA_DQ_23

AR40

SA_DQ_24

AW40

SA_DQ_25

AT39

SA_DQ_26

AW36

SA_DQ_27

AW41

SA_DQ_28

AY41

SA_DQ_29

AV38

SA_DQ_30

AT38

SA_DQ_31

AV13

SA_DQ_32

AT13

SA_DQ_33

AW11

SA_DQ_34

AV11

SA_DQ_35

AU15

SA_DQ_36

AT11

SA_DQ_37

BA13

SA_DQ_38

BA11

SA_DQ_39

BE10

SA_DQ_40

BD10

SA_DQ_41

BD8

SA_DQ_42

AY9

SA_DQ_43

BG10

SA_DQ_44

AW9

SA_DQ_45

BD7

SA_DQ_46

BB9

SA_DQ_47

BB5

SA_DQ_48

AY7

SA_DQ_49

AT5

SA_DQ_50

AT7

SA_DQ_51

AY6

SA_DQ_52

BB7

SA_DQ_53

AR5

SA_DQ_54

AR8

SA_DQ_55

AR9

SA_DQ_56

AN3

SA_DQ_57

AM8

SA_DQ_58

AN10

SA_DQ_59

AT9

SA_DQ_60

AN9

SA_DQ_61

AM9

SA_DQ_62

AN11

SA_DQ_63

Crestline FBGA 1299P INTEL 6019B0412201

DDR SYSTEM MEMORY A

SA_BS_0 SA_BS_1 SA_BS_2

SA_CAS#

SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7

SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6

SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7

SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8

SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14

SA_RAS#

SA_RCVEN#

SA_WE#

BB19 BK19 BF29

BL17 AT45

BD44 BD42 AW38 AW13 BG8 AY5 AN6

AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2

BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 BJ29

BE18 AY20

BA19

M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7

M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7

M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13

M_A_BS0 <19> M_A_BS1 <19> M_A_BS2 <19>

M_A_DM[7..0]

M_A_DQS[7..0]

M_A_DQS#[7..0]

M_A_A[14..0]

TP9TP9

M_A_CAS# <19> M_A_DM[7..0] <19>

M_A_DQS[7..0] <19>

M_A_DQS#[7..0] <19>

M_A_A[14..0] <19>

M_A_RAS# <19>

M_A_WE# <19>

M_B_DQ[63..0]<20>

M_B_DQ[63..0]

M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63

U7E

AP49

SB_DQ_0

AR51

SB_DQ_1

AW50

SB_DQ_2

AW51

SB_DQ_3

AN51

SB_DQ_4

AN50

SB_DQ_5

AV50

SB_DQ_6

AV49

SB_DQ_7

BA50

SB_DQ_8

BB50

SB_DQ_9

BA49

SB_DQ_10

BE50

SB_DQ_11

BA51

SB_DQ_12

AY49

SB_DQ_13

BF50

SB_DQ_14

BF49

SB_DQ_15

BJ50

SB_DQ_16

BJ44

SB_DQ_17

BJ43

SB_DQ_18

BL43

SB_DQ_19

BK47

SB_DQ_20

BK49

SB_DQ_21

BK43

SB_DQ_22

BK42

SB_DQ_23

BJ41

SB_DQ_24

BL41

SB_DQ_25

BJ37

SB_DQ_26

BJ36

SB_DQ_27

BK41

SB_DQ_28

BJ40

SB_DQ_29

BL35

SB_DQ_30

BK37

SB_DQ_31

BK13

SB_DQ_32

BE11

SB_DQ_33

BK11

SB_DQ_34

BC11

SB_DQ_35

BC13

SB_DQ_36

BE12

SB_DQ_37

BC12

SB_DQ_38

BG12

SB_DQ_39

BJ10

SB_DQ_40

BL9

SB_DQ_41

BK5

SB_DQ_42

BL5

SB_DQ_43

BK9

SB_DQ_44

BK10

SB_DQ_45

BJ8

SB_DQ_46

BJ6

SB_DQ_47

BF4

SB_DQ_48

BH5

SB_DQ_49

BG1

SB_DQ_50

BC2

SB_DQ_51

BK3

SB_DQ_52

BE4

SB_DQ_53

BD3

SB_DQ_54

BJ2

SB_DQ_55

BA3

SB_DQ_56

BB3

SB_DQ_57

AR1

SB_DQ_58

AT3

SB_DQ_59

AY2

SB_DQ_60

AY3

SB_DQ_61

AU2

SB_DQ_62

AT2

SB_DQ_63

Crestline FBGA 1299P INTEL 6019B0412201

DDR SYSTEM MEMORY B

SB_BS_0 SB_BS_1 SB_BS_2

SB_CAS# SB_DM_0

SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7

SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6

SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7

SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8

SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14

SB_RAS#

SB_RCVEN#

SB_WE#

AY17 BG18 BG36

BE17 AR50

BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3

BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 BE24

AV16 AY18

BC17

M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7

M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7

M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14M_A_A14

M_B_BS0 <20> M_B_BS1 <20> M_B_BS2 <20>

M_B_DM[7..0]

M_B_DQS[7..0]

M_B_DQS#[7..0]

M_B_A[14..0]

TP10TP10

M_B_CAS# <20> M_B_DM[7..0] <20>

M_B_DQS[7..0] <20>

M_B_DQS#[7..0] <20>

M_B_A[14..0] <20>

M_B_RAS# <20>

M_B_WE# <20>

B B

Inventec Corporation

Inventec Buliding,66 Hou-Kang Stree

Inventec Buliding,66 Hou-Kang Stree Shin-Lin District, Taipei 111, Taiwan

Shin-Lin District, Taipei 111, Taiwan

A A

Shin-Lin District, Taipei 111, Taiwan

TEL:+886-2-2881-0721

Title

M11D (Merom+Crestline+ICH8M)

Document Number

Size

Date: Sheet of

Friday, June 01, 2007

Crestline DDRII(3/6)

Rev

AX1

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