FUJITSU SIEMENS AMILO M1451G Schematic

5

4

3

2

1

Revision History

A

Model : M50EA0

D D

11/2004

ORIGINAL RELEASE

Mobile Dothan with INTEL 915PM / ICH6-M Chipset

PG01 INDEX
PG02 SYSTEM BLOCK DIAGRAM
PG03 POWER DIAGRAM & SEQUENCE
PG04 GPIO & POWER CONSUMPTION

C C

PG05 CPU Banias/Dothan-1/2
PG06 CPU Banias/Dothan-2/2
PG07 CLOCK GEN ICS954127
PG08 NB_Alviso Host-1/5
PG09 NB DDRCLK_VGA_PCIEXPR-2/5
PG10 NB DDR_MEM SYSTEM-3/5
PG11 NB POWER-4/5
PG12 NB VSS_NCTF-5/5

PG21 LANRTL8100CL
PG22 1394 TSB43AB22A
PG23 MINIPCI (Wirless) / CRT & AUDIO CONN
PG24 EC IT8510E / BIOS / Keyboard & TP CONN
PG25 CPU_CORE
PG26 1.05V / 1.5V / 1.8V / 2.5V / 0.9V
PG27 +3.3V / +5V / +12V
PG28 BATT IN / Charger
PG29 VCC SW / +1.05VS / +1.5VS
PG30 VGA MXM CON
PG31 Appendix A. Ver. History

PG13 DDR2 CHANNELA,B SODIMM0,1
PG14 DDR2 Terminate / Smart Power
PG15 SB ICH-6M-1/3
PG16 SB ICH-6M-2/3

B B

PG17 SB ICH-6M-3/3
PG18 DC IN / NEW CARD / FAN / MIC / BLUETOOH
PG19 LCD / INVERTER / USB / TV / IO
PG20 SATA HDD / CD-ROM

A A

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

UNIWILL COMPUTER CORP.

Custom

Custom

Custom

3145

3145

3145

M50EA0

M50EA0

M50EA0

INDEX

INDEX

INDEX

1

B

B

B

of

of

of

131Monday, June 06, 2005

131Monday, June 06, 2005

131Monday, June 06, 2005

5

4

3

2

1

M50EA0
BLOCK DIAGRAM

D D

HOST BUS

400/533MHZ

SODIMM1

+1.8VS

+0.9V terminal

Daugher BD-2

C C

AUDIO CODEC

ALC880

SODIMM0

+1.8VS

+0.9V terminal

DDR2 RAM BUS

AZALIA

PCI BUS

MDC

CPU

Dothan

Socket 478

North Bridge

INTEL
915PM

DMI

South Bridge

INTEL

ICH6-M

THERMAL

ADM1032

PCIE

ATI M22

RTC

EC

CRT
LCD

S-Video TV

AMPLIFIER

TPA6011A4

MIC

RJ11

LINE OUT * 1

INTERNAL
SPK

MIC * 1
SPDIF OUT * 1
LINE IN * 1

LAN

RTL8100CL

MINI PCI

( Wireless )

B B

CRYSTAL

14.318MHz

IEEE-1394A

RJ45

TSB43AB22A

SATA

CRYSTAL

25M HZ

SATA HDD

PATA

DVD
ROM

+5V

PRIMARY

MASTER

LPC BUS

USB*8

USB*4

PCIE

CARD READER

Daugher BD-2

NEW CARD

Daugher BD-1

GL817E

USB

Clock Gen

ICS

ICS954127

CRYSTAL

24.576M Hz

CRYSTAL

32.768K Hz

K/B CONTROLLER

ITE

8510

X-BUS

A A

FLASH ROM

INT K/B

T/P

FAN

CHARGER

BATTERY

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

UNIWILL COMPUTER CORP.

M50EA0

M50EA0

M50EA0

SYSTEM BLOCK DIAGRAM

SYSTEM BLOCK DIAGRAM

SYSTEM BLOCK DIAGRAM

3145

3145

3145

1

B

B

B

of

231Monday, June 06, 2005

of

231Monday, June 06, 2005

of

231Monday, June 06, 2005

5

4

3

2

1

POWER BLOCK DIAGRAM

ISL6224

D D

VIN

RSS090N03

+1.8VS/4.5A

RT9173B

+0.9VS

VID0

VID1

VID2

VID3

VID4

SC451

VIN

RSS090N03
SI4362

CPU_CORE

+1.8V

AO4422

VID5

VIN

RSS090N03

+5VA/ ≈9A

AO4422

+5VS

POWER Sequence

C C

SI4835

SC1404

+12VA

SI2301

VIN

RSS090N03

+3.3VA

+12VS

AO4422

SI4835

B B

VIN

ISL6225

RSS090N03

VIN

RSS090N03

A A

5

+1.5VS/4.5A

AO4422

+1.05VS/4.5A

AO4422

4

+5V

+3.3VS

RT9173B

+3.3V/ ≈0.9A

+1.5V

+2.5VS

+1.05V/1.8A

+3VA,+5VA,+12VA

PWRSW

.

+3.3VS_ON

+5VS,+12VS

+3.3VS

.

+1.5VS_ON

+1.5VS

.

+1.05VS_ON

.

+1.8V_DDR_ON

+1.8VS

+1.05VS

.

RSMRST#

.

PWRBTN#

.

+5V_ON

+5V

+3.3V

+2.5V

.

+1.8V_ON

+1.8V

+1.05V

+1.5V

.

Vcore_ON

Vcore

.

PWROK/VR_PWRGD

H_PWRGD

PCIRST#/PLTRST#

CPURST#

EC Control Pin

.

3

1ms

1ms

1ms

50ms

2

10ms

40ms

5.8ms

1s

7ms

110ms

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

3145

3145

3145

Date: Sheet

Date: Sheet

Date: Sheet

M50EA0

M50EA0

M50EA0

POWER DIAGRAM

POWER DIAGRAM

POWER DIAGRAM

1

B

B

331Monday, June 06, 2005

331Monday, June 06, 2005

331Monday, June 06, 2005

B

of

of

of

5

4

3

2

1

ICH6-M

GPIO

GPI6

BM_BUSY#
GP7
GP8
GPI11
GPI12

D D

GPI13
GPO18

EC_EXTSMI#

SMB_ALERT#

PM_STPPCI_ICH#
GPO19
GPO20
GPO21

PM_STPCPU_ICH#

TPM_EN
GPO23
GPIO24
GPIO25
GPIO26

SATA0_GP
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
GPIO33

C C

GPIO34

PNLSW1

PNLSW2

PNLSW0

PM_CLKRUN#

GPCF0
GPCF1
GPCF2
GPCF3
GPCF4
GPCF5
GPCF6
GPCF7
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPH7

ITE8510E

GPIO

TURBO#/PHOTO
SILENT#/TV
BAT_SEL
BAT_THROT_EN
TP_CLK
TP_DATA
MAIL#/DVD
BROWSER#/MP3
SCROLL#
CAPS#
NUM#
CHGLED_ON#
A/W_LED1#
SUSLED_ON#
A/W_LED2#
+1.8V_DDR_ON
+1.8V_ON
+1.05VS_ON
+3.3VS_ON
+5V_ON
SET_V
+1.5VS_ON
VCORE_ON

GPC0
GPC1
GPC2
GPC3
GPC4
GPC5
GPC6
GPC7
ANOTE

CATHODE

ITE8510E

GPIO

PWROK

BAT2_SMBCLK
BAT2_SMBDAT

A/W_LED3#
CHG_ON
SILENT_LED#

CPU CORE(V)

2.0G

2.2G

2.26G

2.4G

2.5G

2.53G

2.6G

2.66G

2.8G

3.06G

VCC

+3.3V
+3.3VA
+2.5V
+1.5V
+VCCP

+VCC_GMCH_CORE

1.525

1.525

1.525

1.525

1.525

1.525

1.525

1.525

1.525

1.525

ICC(mA)

108.19

501.3
1390

33.4
10
266

CPU

ICC(mA)

MCHE

35.7

37.5

38.1

39.3
40

40.4

41.05

43.35

44.86

55.9

0.357

1.254

2.502

0.084

0.018

0.452

W

W

54.3

57.1

58.0

59.8

61.0

61.5

62.6

66.1

68.4

85.2

TEMP( )

70

TEMP( )

69
70
70
71
72
72
72
74
75
81

ITE8510E

VCC

+3.3V

ICC(mA)

300

CLOCK GENERATOR

VCC

+3.3V

ICC(mA)

180

ADM1032

VCC

+3.3V

ICC

170uA

W
1

W

0.594

W

0.56mW

TEMP( )

70

TEMP( )

70

TEMP( )

150

GPG4
GPG5
GPG6
GPG7
GPB0
GPB1
GPB2
GPB3
GPB4
GPB5
GPB6
GPB7
GPE0

B B

GPE1
GPE2
GPE3
GPE4
GPE5
GPE6
GPE7
GPD0
GPD1
GPD2
GPD3

LCDSW
MUTE#
EXTTS#0
CELERON_VO_DET
TURBO_LED#
PM_RSMRST#
BAT_SMBCLK
BAT_SMBDAT
H_A20GATE
H_RCIN#
RFLED_ON#

CPU_BSEL0
TP_BTU
TP_BTD
PWRSW
LID#
RF_OFF
PM_SLP_S3#
ADAP_IN
AW#/CD
PCI_RST#/PLT_RST#
EC_EXTSMI#

SB INT_PIRQ List

INT_PIRQA
INT_PIRQB
INT_PIRQC
INT_PIRQD
INT_PIRQE
INT_PIRQF
INT_PIRQG
INT_PIRQH

CARD BUS
Mini PCI

1394

LAN

CARD BUS(op)

Mini PCI

NC
NC

VCC

+3.3V
+3.3VA
+1.5V
+1.5VA

+3.3VA_RTC

ICH6-M

ICC(mA)

96
275
487
27

0.003

W

0.315

0.909

0.876

0.049

0.00001

TEMP( )

70

GPD4
GPD5
GPD6
GPD7
GPA0

A A

GPA1
GPA2
GPA3
GPA4
GPA5
GPA6
GPA7

5

CLKREQ#
EC_PREST#
BTL_BEEP
EC_VID1
EC_VID2
EC_VID3
EC_VID4
SMP1_EN#
SMP2_EN#
PWRBTN#

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

3145

3145

3145

Date: Sheet

Date: Sheet

4

3

2

Date: Sheet

M50EA0

M50EA0

M50EA0

GPIO & POWER CONSU

GPIO & POWER CONSU

GPIO & POWER CONSU

1

431Monday, June 06, 2005

431Monday, June 06, 2005

431Monday, June 06, 2005

B

B

B

of

of

of

5

4

3

2

1

Z0509

H_RS#[2:0]

R310

R310

56_OP

56_OP

C34

C34

0.1u

0.1u

C615

C615

0.1u

0.1u

+1.05V

+1.05V

CPU_CORE

B

+3.3V

B

R30856R308

56

Place testpoint on
H_IERR# with a GND

0.1" away

H_RS#[2:0] 8

R5656R56

+1.05V

56

R315

R315

75_1

75_1

R313

R313
100K

100K

Z0510

Q74

Q74
2N3904

2N3904

E C

R610

R610
100K

100K

Z0512

Q80

Q80
2N3904

2N3904

E C

C336

C336
1u_6.3V

1u_6.3V

C614

C614
1u_6.3V

1u_6.3V

B

B

PM_THRMTRIP# 9,15

Q75

Q75

2N3904

2N3904

E C

Q79

Q79
2N3904

2N3904

E C

AUX_OFF# 27

3

H_D#[63:0]8

H_DSTBN#08
H_DSTBP#08

H_DINV#08
H_D#[63:0]8

CPU_BSEL07,24

+1.05V

R78

R78

100_1

100_1

R79

R79

200_1

200_1

PSB400
PSB533(dafault)

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30

TP14TP14
TP15TP15

TP16TP16
TP17TP17
TP18TP18

H_D#31

CPU_BSEL0
MCH_BSEL1

TP_CPU_NC1

TP_NC_2
TP_NC_3
TP_NC_4
TP_NC_5

H_DSTBN#18
H_DSTBP#18

H_GTLREF

H_DINV#18

Layout note: 0.5" max length.

R55

R55

470

CPU_BSEL0

470

R43

R43

1K_1

1K_1

BSEL00BSEL1

1

U37B

U37B

A19

D0#

A25

D1#

A22

D2#

B21

D3#

A24

D4#

B26

D5#

A21

D6#

B20

D7#

C20

D8#

B24

D9#

D24

D10#

E24

D11#

C26

D12#

B23

D13#

E23

D14#

C25

D15#

C23

DSTBN0#

C22

DSTBP0#

D25

DINV0#

H23

D16#

G25

D17#

L23

D18#

M26

D19#

H24

D20#

F25

D21#

G24

D22#

J23

D23#

M23

D24#

J25

D25#

L26

D26#

N24

D27#

M25

D28#

H26

D29#

N25

D30#

K25

D31#

K24

DSTBN1#

L24

DSTBP1#

J26

DINV1#

E1

PSI#

C16

BSEL0

C14

BSEL1

B2

NC1

C3

RSVD2

AF7

RSVD3

AC1

RSVD4

E26

RSVD5

AD26

GTLREF0

CPU_BSEL0 7,24

MCH_BSEL0 9

ICS954206 BSEL Settings:

01=PSB400(BSEL0=1 BSEL1=0)
00=PSB533(BSEL1=0 BSEL0=0)

0
0

2

DATA GRP0

DATA GRP0

DATA GRP1

DATA GRP1

MISC

MISC

D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#

DATA GRP2

DATA GRP2

D45#
D46#
D47#

DSTBN2#

DSTBP2#

DINV2#

D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#

DATA GRP3

DATA GRP3

D60#
D61#
D62#
D63#

DSTBN3#

DSTBP3#

DINV3#
COMP0

COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

TEST1
TEST2

H_D#32

Y26

H_D#33

AA24

H_D#34

T25

H_D#35

U23

H_D#36

V23

H_D#37

R24

H_D#38

R26

H_D#39

R23

H_D#40

AA23

H_D#41

U26

H_D#42

V24

H_D#43

U25

H_D#44

V26

H_D#45

Y23

H_D#46

AA26

H_D#47

Y25
W25
W24
T24

H_D#48

AB25

H_D#49

AC23

H_D#50

AB24

H_D#51

AC20

H_D#52

AC22

H_D#53

AC25

H_D#54

AD23

H_D#55

AE22

H_D#56

AF23

H_D#57

AD24

H_D#58

AF20

H_D#59

AE21

H_D#60

AD21

H_D#61

AF25

H_D#62

AF22

H_D#63

AF26
AE24
AE25
AD20

COMP0

P25
P26
AB2
AB1

G1
B7
C19
E4
A6

C5
F23

R71 27.4_1R71 27.4_1

COMP1

R70 54.9_1R70 54.9_1

COMP2

R76 27.4_1R76 27.4_1

COMP3

R77 54.9_1R77 54.9_1

H_DPRSTP# 15
H_DPSLP# 15
H_DPWR# 8

TEST1

TP80TP80

TEST2

TP81TP81

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

H_D#[63:0] 8

H_DSTBN#2 8
H_DSTBP#2 8
H_DINV#2 8
H_D#[63:0] 8

Layout note:

Comp1 ,3 connect with Zo = 55
Ohm,make

Comp0 ,2 connect with Zo = 27.4
Ohm,make

trace length shorter than 0.5"
trace length shorter than 0.5"

H_DSTBN#3 8
H_DSTBP#3 8
H_DINV#3 8

H_CPUSLP# 8,15

MCH_BSEL1

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

CPU Banias/Dothan-1/2

CPU Banias/Dothan-1/2

3145

3145

3145

CPU Banias/Dothan-1/2

+1.05V

+1.05V+1.05V

R306

R306

1K_1

1K_1

M50EA0

M50EA0

M50EA0

1

R307

R307
200_1

200_1

H_PWRGD 15

MCH_BSEL1 9

of

531Monday, June 06, 2005

of

531Monday, June 06, 2005

of

531Monday, June 06, 2005

B

B

B

U37A

H_A#[31:3]8

D D

H_ADSTB#08

H_REQ#[4:0]8

H_A#[31:3]8

C C

B B

H_ADSTB#18

H_A20M#15

H_FERR#15

H_IGNNE#15

H_STPCLK#15

H_INTR15
H_NMI15
H_SMI#15

H_STPCLK#
TMS
TDI
TRST#
TCK

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

R305 150_1R305 150_1
R309 39.2_1R309 39.2_1
R57 150_1R57 150_1
R311 680R311 680
R312 27.4_1R312 27.4_1

CPU Thermal Sensor

R299

R299

+3.3V

200_1_0603

200_1_0603

C30

C30
2200p

2200p

H_THERMDA
CPU_THERM#
H_THERMDC

A A

Z0511

C331

C331

2.2U_X5R_0603

2.2U_X5R_0603

U33

U33

2

D+

4

THERM#

3

D-

5

1

VDD

GND

ADM1032

ADM1032

5

ADATA

SCLK

ALERT

P4

A3#

U4

A4#

V3

A5#

R3

A6#

V2

A7#

W1

A8#

T4

A9#

W2

A10#

Y4

A11#

Y1

A12#

U1

A13#

AA3

A14#

Y3

A15#

AA2

A16#

U3

ADSTB#0

R2

REQ0#

P3

REQ1#

T2

REQ2#

P1

REQ3#

T1

REQ4#

AF4

A17#

AC4

A18#

AC7

A19#

AC3

A20#

AD3

A21#

AE4

A22#

AD2

A23#

AB4

A24#

AC6

A25#

AD5

A26#

AE2

A27#

AD6

A28#

AF3

A29#

AE1

A30#

AF1

A31#

AE5

ADSTB#1

C2

A20M#

D3

FERR#

A3

IGNNE#

C6

STPCLK#

D1

LINT0

D4

LINT1

B4

SMI#

+1.05V

Modify 27

7
8
6

U37A

ADDR GROUP 0 ADDR GROUP 1

ADDR GROUP 0 ADDR GROUP 1

ADS#
BNR#

BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

CONTROLITP SIGNALS

CONTROLITP SIGNALS

INIT#

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM#0
BPM#1
BPM#2
BPM#3
PRDY#
PREQ#

TDO

TRST#

DBR#

PROCHOT#

THERMDA
THERMDC

THERM

THERM

THERMTRIP#

ITP_CLK1
ITP_CLK0

BCLK1
BCLK0

H CLK

H CLK

DK_MXM_THERM#30

CPU_THERM#

SMBDAT_EC 7,24
SMBCLK_EC 7,24

TCK

TMS

TDI

N2
L1
J3

L4
H2
M2

N4

H_IERR#

A4
B5

J2

H_CPURST#

B11

H_RS#0

H1

H_RS#1

K1

H_RS#2

L2
M3

K3
K4

Z0501

C8

Z0502

B8

Z0503

A9

Z0504

C9

Z0505

A10

Z0506

B10

TCK

A13

TDI

C12

TDO

A12

TMS

C11

TRST#

B13

DBR#

A7

H_PROCHOT#

B17

H_THERMDA

B18

H_THERMDC

A18

PM_THRMTRIP#

C17

Z0507

A15

Z0508

A16
B14
B15

PM_THRMTRIP#

R635 0R635 0

H_ADS# 8
H_BNR# 8
H_BPRI# 8

H_DEFER# 8
H_DRDY# 8
H_DBSY# 8

H_BREQ#0 8

H_INIT# 15
H_LOCK# 8
H_CPURST# 8

H_TRDY# 8
H_HIT# 8

H_HITM# 8

TP1TP1
TP2TP2
TP3TP3
TP4TP4
TP5TP5

TP6TP6
TP7TP7
TP8TP8
TP9TP9
TP10TP10
TP11TP11

TP12TP12
TP13TP13

CLK_CPU_BCLK# 7
CLK_CPU_BCLK 7

R314 1KR314 1K

+3.3V

4

R611

R611
100K

100K

5

+1.5V

B36

B36

QT1608RL060

+1.05V

H_VID0 14
H_VID1 14
H_VID2 14
H_VID3 14
H_VID4 14
H_VID5 14

TP19TP19
TP20TP20

QT1608RL060

Z0601

C339

C339

0.1u

0.1u

B37

B37

QT1608RL060_OP

QT1608RL060_OP

Close to Pin

C43

C43

4.7U_10V_0805

4.7U_10V_0805

VCCA=120mA

CPU_CORE

D D

C C

B B

AA11
AA13
AA15
AA17
AA19
AA21

AA5
AA7

AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB22

AB6

AB8
AC11
AC13
AC15
AC17
AC19

AC9
AD10
AD12
AD14
AD16
AD18

AD8
AE11
AE13
AE15
AE17
AE19

AE9
AF10
AF12
AF14
AF16
AF18

AF8

D18

D20

D22

E17

E19

E21

G21

U37C

U37C

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44

D6

VCC45

D8

VCC46
VCC47
VCC48
VCC49

E5

VCC50

E7

VCC51

E9

VCC52

F18

VCC53

F20

VCC54

F22

VCC55

F6

VCC56
VCC57
VCC58

VCCSENSE
VSSSENSE

F8

POWER

POWER

VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71

VCCA0
VCCA1
VCCA2
VCCA3

VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8

VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24

VCCQ0

VCCQ1

VID0
VID1
VID2
VID3
VID4
VID5

CPU_CORE

G5
H22
H6
J21
J5
K22
U5
V22
V6
W21
W5
Y22
Y6

Z0602

R316 0R316 0

F26

Z0603

R52 0R52 0

B1
N1

Reserved for FSB400 MHz

AC26
D10

D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L21
L5
M22
M6
N21
N5
P22
P6
R21
R5
T22
T6
U21

P23
W4

E2
F2
F3
G3
G4
H4

Z0604

AE7

Z0605

AF6

Layout note :

VCCSENSE and VSSSENSE line

should be of equal length

+1.8V

C340

C340

0.1u

0.1u

4

FSB400 MHz=1.8V

FSB533 MHz=1.5V

C338

C338

C39

C39

0.1u

0.1u

0.1u

0.1u

+1.05V

C55

C55

0.1u

0.1u

C45

C45

0.1u

0.1u

C37

C37

0.1u

0.1u

C60

C60

0.1u

0.1u

CPU_CORE

C49

C49

0.1u

0.1u

C104

C104
1000P

1000P

C61

C61

0.1u

0.1u

C79

C79

4.7U_10V_0805

4.7U_10V_0805

C84

C84

4.7U_10V_0805

4.7U_10V_0805

C98

C98
1u_6.3V

1u_6.3V

C111

C111
1u_6.3V

1u_6.3V

C102

C102
1000P

1000P

C78

C78

0.1u

0.1u

C99

C99
1u_6.3V

1u_6.3V

C75

C75
1u_6.3V

1u_6.3V

C89

C89

0.1u

0.1u

3

C348

C348

4.7U_10V_0805

4.7U_10V_0805

C80

C80

4.7U_10V_0805

4.7U_10V_0805

C107

C107
1u_6.3V

1u_6.3V

C51

C51
1u_6.3V

1u_6.3V

C108

C108
1000P

1000P

C77

C77

0.1u

0.1u

C113

C113
1000P

1000P

C95

C95

0.1u

0.1u

C94

C94

4.7U_10V_0805

4.7U_10V_0805

C90

C90

4.7U_10V_0805

4.7U_10V_0805

C109

C109
1u_6.3V

1u_6.3V

C50

C50
1u_6.3V

1u_6.3V

C112

C112
1000P

1000P

C59

C59

0.1u

0.1u

C101

C101
1u_6.3V

1u_6.3V

C92

C92

0.1u

0.1u

C74

C74

4.7U_10V_0805

4.7U_10V_0805

C93

C93

4.7U_10V_0805

4.7U_10V_0805

C54

C54
1000P

1000P

C53

C53
1u_6.3V

1u_6.3V

C76

C76

0.1u

0.1u

C52

C52
1000P

1000P

C86

C86

0.1u

0.1u

C105

C105
1u_6.3V

1u_6.3V

C73

C73

4.7U_10V_0805

4.7U_10V_0805

C83

C83

4.7U_10V_0805

4.7U_10V_0805

C110

C110
1u_6.3V

1u_6.3V

C103

C103
1000P

1000P

C82

C82

0.1u

0.1u

C97

C97
1000P

1000P

C87

C87

0.1u

0.1u

2

C346

C346

4.7U_10V_0805

4.7U_10V_0805

C91

C91

4.7U_10V_0805

4.7U_10V_0805

C100

C100
1u_6.3V

1u_6.3V

C96

C96
1000P

1000P

C85

C85

4.7U_10V_0805

4.7U_10V_0805

C106

C106
1u_6.3V

1u_6.3V

C81

C81

4.7U_10V_0805

4.7U_10V_0805

C63

C63

4.7U_10V_0805

4.7U_10V_0805

C64

C64

4.7U_10V_0805

4.7U_10V_0805

AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26

AC10
AC12
AC14
AC16
AC18
AC21
AC24

AD11
AD13
AD15
AD17
AD19
AD22
AD25

AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26

AF11
AF13
AF15
AF17
AF19
AF21
AF24

A11
A14
A17
A20
A23
A26
AA1
AA4
AA6
AA8

AB3
AB5
AB7
AB9

AC2
AC5
AC8

AD1
AD4
AD7
AD9

AE3
AE6
AE8

AF2
AF5
AF9

B12
B16
B19
B22
B25

C10
C13
C15
C18
C21
C24

D11

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143

VSS

VSS

VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191

VSS97
VSS98
VSS99

1

D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1
M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23
T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24

U37D

U37D

A2

VSS0

A5

VSS1

A8

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

B3

VSS75

B6

VSS76

B9

VSS77
VSS78
VSS79
VSS80
VSS81
VSS82

C1

VSS83

C4

VSS84

C7

VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91

D2

VSS92

D5

VSS93

D7

VSS94

D9

VSS95
VSS96

A A

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

3145

3145

3145

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

M50EA0

M50EA0

M50EA0

CPU Banias/Dothan-2/2

CPU Banias/Dothan-2/2

CPU Banias/Dothan-2/2

1

B

B

B

of

631Monday, June 06, 2005

of

631Monday, June 06, 2005

of

631Monday, June 06, 2005

5

4

3

2

1

+3.3VS_CLKVDD

D D

Modify 13

Y4

Y4

14.318MHz_SMT

14.318MHz_SMT

C239

C239
33p

33p

C C

SB_SMB_CLK13,16,17
SB_SMB_DATA13,16,17

SMBCLK_EC5,24

B B

SMBDAT_EC5,24

C235

C235
33p

33p

+3.3V

CPU_BSEL05,24
PCICLK_PCM
PCICLK_LAN21

PCICLK_MINIPCI23

PCICLK_139422

CLK_PCI16

CLK_PCI_LPC24

R166 0_OPR166 0_OP
R167 0_OPR167 0_OP

R151 0R151 0
R152 0R152 0

R201

R201
10K

10K

CLK_USB4816

Modify 31

XTAL_IN
XTAL_OUT

R429 4.7KR429 4.7K
R180 56_OPR180 56_OP
R183 56R183 56
R172 56R172 56
R177 56R177 56

R164 56R164 56
R159 56R159 56
R192 10KR192 10K

R452

R452

2.2_0603

2.2_0603

VDD_A_CR

C258

C258
1u_6.3V

1u_6.3V

R203 33R203 33

Z0702

FSB

Z0703
Z0704
IREF

R210

R210

475_1

475_1

FSA

FSC

PCI3
PCI2
PCI1
PCI0
PCIF1

C263

C263

0.1u

0.1u

19
28
34

42
37
38

50
49
12
16

8
5
4
3

56

9
53
46
47
39
13

29
45

2

6
51

U22

U22

ICS 954127

ICS 954127

C256

C256

0.1u

0.1u

VDDSRC
VDD_PCIEX
VDD_PCIEX1

VDD_CPU
VDDA
GNDA

XTAL_IN
XTAL_OUT
FSA/USB_48
GND
FSC/PCICLK_F0
PCI3
PCI2
PCI1
PCICLK0~
FSB/PCICLK_F1
RTFS_0
SCLK
SDATA
IREF
VSS_48

VSS_PCIE
VSS_CPU
VSS_PCI
RESET#
VSS_REF

C247

C247

0.1u

0.1u

C268

C268

0.1u

0.1u

1

VDD_PCI17VDD_PCI0

VTT_PWRGD#/PD

C273

C273

4.7U_10V_0805

4.7U_10V_0805

Z0701

VDD_48

VDD_REF

RTFS_2
RTFS_1

CPUCLKT1

CPUCLKC1

CPUCLKT0

CPUCLKC0

PCIEXT6
PCIEXC6

PCIEXT5
PCIEXC5

PCIEXT4
PCIEXC4

PCIEXT3
PCIEXC3

PCIEXT2
PCIEXC2

PCIEXT1
PCIEXC1

PCIEXT0
PCIEXC0

SRC0

SRC0#

DOT96

DOT96#

REFOUT

Modify 31

11
48
55

54
41

40
44

43

36
35

33
32

31
30

26
27

24
25

22
23

20
21

17
18

14
15

10

REF

52

R196

R196

2.2_0603

2.2_0603

Z0705
VDD_REF_CR
Z0706

Z0707
CPU1

CPU#1
CPU0

CPU#0

PCIE4
PCIE#4

PCIE3
PCIE#3

PCIE2
PCIE#2

PCIE1
PCIE#1

PCIE0
PCIE#0

SRC0
SRC#0

DOT96
DOT96#

VTT_PWRGD#

B34

B34

QT1608RL600

QT1608RL600

C242

C242

0.1u

0.1u

R171 0_OPR171 0_OP
R175 0_OPR175 0_OP

R207 33R207 33
R211 33R211 33

R200 33R200 33
R202 33R202 33

R470 33R470 33
R469 33R469 33

R461 33R461 33
R464 33R464 33

R471 33R471 33
R472 33R472 33

R614 33R614 33
R615 33R615 33

R453 33_OPR453 33_OP
R457 33_OPR457 33_OP

R444 33R444 33
R448 33R448 33

R433 33_OPR433 33_OP
R439 33_OPR439 33_OP

R179 22R179 22
R176 33R176 33

R4351R435
1

PM_STPPCI# 16
PM_STPCPU# 16,25

CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8

CLK_CPU_BCLK 5
CLK_CPU_BCLK# 5

GCLK 9
GCLK# 9

CLK_PCIE_NEW_CARD 18
CLK_PCIE_NEW_CARD# 18

CLK_PCIE_ICH 16
CLK_PCIE_ICH# 16

CLK_PCIE_MXM 30
CLK_PCIE_MXM# 30

DOT96_SST 9
DOT96_SSC 9

CLK_SATA 15
CLK_SATA# 15

DREFCLK 9
DREFCLK# 9

CLK_ICH14 16
CODEC_14MHZ

C236

C236

0.1u

0.1u

+3.3V

C218

C218

1u_6.3V

1u_6.3V

C243 0.1uC243 0.1u

B33

B33

QT1608RL600

QT1608RL600

+3.3V

GCLK#
GCLK
CLK_PCIE_MXM

CLK_PCIE_MXM#
CLK_PCIE_NEW_CARD
CLK_PCIE_NEW_CARD#

DOT96_SSC

DOT96_SST

CLK_CPU_BCLK

CLK_CPU_BCLK#

CLK_MCH_BCLK

CLK_MCH_BCLK#

DREFCLK#

DREFCLK

CLK_PCIE_ICH#

CLK_PCIE_ICH

CLK_SATA#

CLK_SATA

Place termination close to source IC

CODEC_14MHZ
CLK_USB48
PCICLK_LAN
PCICLK_MINIPCI
PCICLK_1394
CLK_PCI_LPC
CLK_PCI
CLK_ICH14

R633 49.9_1R633 49.9_1
R634 49.9_1R634 49.9_1
R612 49.9_1R612 49.9_1
R613 49.9_1R613 49.9_1
R460 49.9_1R460 49.9_1
R465 49.9_1R465 49.9_1
R456 49.9_1_OPR456 49.9_1_OP
R454 49.9_1_OPR454 49.9_1_OP
R438 49.9_1R438 49.9_1
R443 49.9_1R443 49.9_1
R447 49.9_1R447 49.9_1
R450 49.9_1R450 49.9_1
R440 49.9_1_OPR440 49.9_1_OP
R434 49.9_1_OPR434 49.9_1_OP
R478 49.9_1R478 49.9_1
R477 49.9_1R477 49.9_1
R449 49.9_1R449 49.9_1
R445 49.9_1R445 49.9_1

C219 10p_OPC219 10p_OP
C248 10p_OPC248 10p_OP
C227 10p_OPC227 10p_OP
C220 10p_OPC220 10p_OP
C223 10p_OPC223 10p_OP
C216 10p_OPC216 10p_OP
C217 10p_OPC217 10p_OP
C226 10p_OPC226 10p_OP

R165

R165
10K

10K

VTT_PWRGD#25

A A

FSB

FSA

BSEL1

BSEL2

0

1

1

0

5

4

FSC
BSEL0

1

0

Host
Clock
frequency

100

133

3

2

Reserved FOR EMI

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

3145

3145

3145

Date: Sheet

Date: Sheet

Date: Sheet

M50EA0

M50EA0

M50EA0

CLOCK GEN ICS954127

CLOCK GEN ICS954127

CLOCK GEN ICS954127

1

of

731Monday, June 06, 2005

of

731Monday, June 06, 2005

of

731Monday, June 06, 2005

B

B

B

5

D D

+1.05V

+1.05V

C C

+1.05V

B B

+1.05V

R297

R297

24.9_1

24.9_1

R295

R295

54.9_1

54.9_1

R300

R300

221_1

221_1

R298

R298

100_1

100_1

R304

R304

54.9_1

54.9_1

R49

R49

221_1

221_1

R48

100_1

100_1

H_XRCOMP

H_XSCOMP

H_XSWING

C328

C328

0.1u

0.1u

H_YSCOMP

H_YSWING

C40

C40

0.1u

0.1u

4

H_D#[63:0]5

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_XRCOMP
H_XSCOMP
H_XSWING
H_YRCOMP
H_YSCOMP
H_YSWING

W6

W8
W7

W1
W3

W2

E4
E1
F4
H7
E2
F1
E3
D3
K7
F2

J7

J8
H6
F3
K8
H5
H1
H2
K5
K6

J4
G3
H3

J1
L5
K4

J5
P7
L7

J3
P5
L3
U7
V6
R6
R5
P3
T8
R7
R8
U8
R4
T4
T5
R1
T3
V8
U6

U3
V5

U2
U1
Y5
Y2
V4
Y7

Y3
Y6

C1
C2
D1
T1
L1
P1

3

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

HXRCOMP
HXSCOMP
HXSWING
HYRCOMP
HYSCOMP
HYSWING

915PM

915PM

U34A

U34A

HOST

HOST

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#

HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HADS#
HADSTB#0
HADSTB#1

HVREF

HBNR#

HBPRI#

HBREQ0#

HCPURST#

HCLKINN

HCLKINP

HDBSY#

HDEFER#

HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDPWR#

HDRDY#
HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3

HEDRDY#

HHIT#

HHITM#

HLOCK#

HPCREQ#

HREQ#0

HREQ#1

HREQ#2

HREQ#3

HREQ#4

HRS0#
HRS1#
HRS2#

HCPUSLP#

HTRDY#

G9
C9
E9
B7
A10
F9
D8
B10
E10
G10
D9
E11
F10
G11
G13
C10
C11
D11
C12
B13
A12
F12
G12
E12
C13
B11
D13
A13
F13

F8
B9
E13
J11
A5
D5
E7
H10

AB1
AB2

C6
E6
H8
K3
T7
U5
G6
F7
G4
K1
R3
V3
G5
K2
R2
W4
F6
D4
D6
B3
A11
A7
D7
B8
C7
A8
A4
C5
B4

H_CPUSLP#_GMCH

G8
B5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_VREF

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
Z0801

Z0802
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2

2

H_A#[31:3] 5

H_ADS# 5
H_ADSTB#0 5
H_ADSTB#1 5

H_BNR# 5
H_BPRI# 5
H_BREQ#0 5
H_CPURST# 5

CLK_MCH_BCLK# 7
CLK_MCH_BCLK 7
H_DBSY# 5
H_DEFER# 5
H_DINV#[3:0] 5

H_DPWR# 5
H_DRDY# 5
H_DSTBN#[3:0] 5

H_DSTBP#[3:0] 5

TP21TP21

TP22TP22

R32 0_OPR32 0_OPR48

H_HIT# 5
H_HITM# 5
H_LOCK# 5

H_CPUSLP# 5,15
H_TRDY# 5

+1.05V

C27

C27

0.1u

0.1u

H_REQ#[4:0] 5

H_RS#[2:0] 5

1

R42

R42

100_1

100_1

R41

R41

200_1

200_1

H_YRCOMP

R53

R53

24.9_1

24.9_1

A A

Reference from demo circuit

5

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

4

3

2

Date: Sheet

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

M50EA0

M50EA0

M50EA0

NB_Alviso Host-1/5

NB_Alviso Host-1/5

3145

3145

3145

NB_Alviso Host-1/5

1

B

B

B

of

831Monday, June 06, 2005

of

831Monday, June 06, 2005

of

831Monday, June 06, 2005

5

4

3

2

1

U34G

U34B

DMI_TXN[3:0]16

DMI_TXP[3:0]16

D D

C C

B B

DMI_RXN[3:0]16

DMI_RXP[3:0]16

R65

R65

R64

R64

40.2_1

40.2_1

40.2_1

40.2_1

as short as possible

+1.8VS

R328

R328
150_1

150_1

M_VREF_MCH

0.05A

C351

C351

R327

R327

0.1u

0.1u

150_1

150_1

MA_CK013
MA_CK113

MB_CK313
MB_CK413

MA_CK#013
MA_CK#113

MB_CK#313
MB_CK#413

MA_CKE013,14
MA_CKE113,14
MB_CKE213,14
MB_CKE313,14

MA_CS#013,14
MA_CS#113,14
MB_CS#213,14
MB_CS#313,14

M_OCDCOMP0
M_OCDCOMP1

C355

C355

0.1u

0.1u

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

MA_ODT013,14
MA_ODT113,14
MB_ODT213,14
MB_ODT313,14

M_RCOMPN
M_RCOMPP

SMXSLEW
SMYSLEW

AA31
AB35
AC31
AD35

AA35
AB31
AC35

AA33
AB37
AC33
AD37

AA37
AB33
AC37

AM33

AJ34

AN33

AJ33

AP21
AM21
AH21
AK21

AN16
AM14
AH15
AG16

AF22
AF16

AP14

AL15
AM11
AN10

AK10
AK11
AF37

AD1
AE27
AE28

AF9
AF10

Y31

Y33

AL1

AF6

AK1

AF5

U34B

DMIRXN0
DMIRXN1
DMIRXN2
DMIRXN3

DMIRXP0
DMIRXP1
DMIRXP2
DMIRXP3

DMITXN0
DMITXN1
DMITXN2
DMITXN3

DMITXP0
DMITXP1
DMITXP2
DMITXP3

SM_CK0
SM_CK1

SM_CK3
SM_CK4

SM_CK0#
SM_CK1#

SM_CK3#
SM_CK4#

SM_CKE0
SM_CKE1
SM_CKE2
SM_CKE3

SM_CS0#
SM_CS1#
SM_CS2#
SM_CS3#

SM_OCDCOMP0
SM_OCDCOMP1

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

SMRCOMPN
SMRCOMPP
SMVREF0
SMVREF1
SMXSLEWIN
SMXSLEWOUT
SMYSLEWIN
SMYSLEWOUT

915PM

915PM

G16

CFG0

H13

CFG1

G14

CFG2

F16

CFG3

F15

CFG4

G15

CFG5

E16

CFG6

D17

CFG7

J16

CFG8

D15

CFG9

E15

CFG10

D14

CFG11

E14

CFG12

DMI

DMI

CFG/RSVD

CFG/RSVD

PM

PM

DDR MUXING

DDR MUXING

DREF_SSCLKN
DREF_SSCLKP

CLK

CLK

NC

NC

CFG13
CFG14
CFG15
CFG16
CFG17
CFG18
CFG19

CFG20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31

BM_BUSY#

EXT_TS0#
EXT_TS1#

THRMTRIP#

PWROK

RSTIN#

DREF_CLKN
DREF_CLKP

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8

NC9
NC10
NC11

H12
C14
H15
J15
H14
G22
G23
D23
G25
G24
J17
A31
A30
D26
D25
AE11
AE10
AC10
AD10

J23
J21
H22
F5
AD30
AE29

A24
A23
C37
D37

AP37
AN37
AP36
AP2
AP1
AN1
B1
A2
B37
A36
A37

CFG0

Z0901
Z0902

Z0903
Z0904

Z0905
Z0906
Z0907
Z0908
Z0910

Z0911

Z0912
Z0913
Z0914
Z0915
Z0916
Z0917
Z0918
Z0919
Z0920
Z0921
Z0922
Z0923

PM_EXTTS#0
PM_EXTTS#1

Z0924
Z0925

R63 100R63 100

Z0926
Z0927
Z0928
Z0929
Z0930
Z0931
Z0932
Z0933
Z0934
Z0935
Z0909

A C

BAT54D7 BAT54D7

AC

BAT54_OPD28 BAT54_OPD28

TP50TP50
TP51TP51
TP52TP52
TP53TP53
TP54TP54
TP55TP55
TP56TP56
TP57TP57
TP58TP58
TP59TP59
TP60TP60

MCH_BSEL1 5

MCH_BSEL0 5

TP23TP23
TP24TP24

CFG5 12

CFG6 12

CFG7 12

TP25TP25

CFG9 12

TP26TP26
TP27TP27
TP28TP28
TP29TP29
TP30TP30
TP31TP31

CFG16 12

TP32TP32

CFG18 12

CFG19 12

TP33TP33
TP34TP34
TP35TP35
TP36TP36
TP37TP37
TP38TP38
TP39TP39
TP40TP40
TP41TP41
TP42TP42
TP43TP43
TP44TP44

BM_BUSY# 16
EXTTS#0 18,24

PM_THRMTRIP# 5,15
DELAY_VR_PWRGOOD 16
PLT_RST# 16,17,20,24,30
DREFCLK# 7
DREFCLK 7

R260R26

R27

R27

0

0_OP

0_OP

Reserved for spread clock

+1.5V

GCLK#7
GCLK7

+1.05V

DOT96_SSC 7
DOT96_SST 7

R201KR20

1K

H24

H25
AB29
AC29

A15

C16

A17

B15

B16

B17

E24

E23

E21

D21

C20

B20

A19

B19

H21

G21

E25

F25

C23

C22

F23

F22

F26

C33

C31

F28

F27

B30

B29

C25

C24

B34

B33

B32

A34

A33

B31

C29

D28

C27

C28

D27

C26

J18

J20

U34G

SDVOCTRL_DATA
SDVOCTRL_CLK
GCLKN
GCLKP

TVDAC_A
TVDAC_B
TVDAC_C
TV_REFSET
TV_IRTNA
TV_IRTNB
TV_IRTNC

DDCCLK
DDCDATA
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
VSYNC
HSYNC
REFSET

LBKLT_CRTL
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA
LVDD_EN
LIBG
LVBG
LVREFH
LVREFL

LACLKN
LACLKP
LBCLKN
LBCLKP

LADATAN0
LADATAN1
LADATAN2

LADATAP0
LADATAP1
LADATAP2

LBDATAN0
LBDATAN1
LBDATAN2

LBDATAP0
LBDATAP1
LBDATAP2

915PM

915PM

EXP_RXN0
EXP_RXN1
EXP_RXN2
EXP_RXN3
EXP_RXN4
EXP_RXN5
EXP_RXN6
EXP_RXN7
EXP_RXN8
EXP_RXN9

EXP_RXP0
EXP_RXP1
EXP_RXP2
EXP_RXP3
EXP_RXP4
EXP_RXP5
EXP_RXP6
EXP_RXP7
EXP_RXP8
EXP_RXP9

EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8

EXP_TXN9
EXP_TXN10
EXP_TXN11
EXP_TXN12
EXP_TXN13
EXP_TXN14
EXP_TXN15

EXP_TXP0

EXP_TXP1

EXP_TXP2

EXP_TXP3

EXP_TXP4

EXP_TXP5

EXP_TXP6

EXP_TXP7

EXP_TXP8

EXP_TXP9
EXP_TXP10
EXP_TXP11
EXP_TXP12
EXP_TXP13
EXP_TXP14
EXP_TXP15

D36
D34

E30
F34
G30
H34
J30
K34
L30
M34
N30
P34
R30
T34
U30
V34
W30
Y34

D30
E34
F30
G34
H30
J34
K30
L34
M30
N34
P30
R34
T30
U34
V30
W34

E32
F36
G32
H36
J32
K36
L32
M36
N32
P36
R32
T36
U32
V36
W32
Y36

D32
E36
F32
G36
H32
J36
K32
L36
M32
N36
P32
R36
T32
U36
V32
W36

EXP_COMPI

EXP_ICOMPO

MISCTVVGALVDS

MISCTVVGALVDS

EXP_RXN10
EXP_RXN11
EXP_RXN12
EXP_RXN13
EXP_RXN14
EXP_RXN15

EXP_RXP10
EXP_RXP11
EXP_RXP12
EXP_RXP13
EXP_RXP14
EXP_RXP15

PCI-EXPRESS GRAPHICS

PCI-EXPRESS GRAPHICS

PEG_RXN15
PEG_RXN14
PEG_RXN13
PEG_RXN12
PEG_RXN11
PEG_RXN10
PEG_RXN9
PEG_RXN8
PEG_RXN7
PEG_RXN6
PEG_RXN5
PEG_RXN4
PEG_RXN3
PEG_RXN2
PEG_RXN1
PEG_RXN0

PEG_RXP15
PEG_RXP14
PEG_RXP13
PEG_RXP12
PEG_RXP11
PEG_RXP10
PEG_RXP9
PEG_RXP8
PEG_RXP7
PEG_RXP6
PEG_RXP5
PEG_RXP4
PEG_RXP3
PEG_RXP2
PEG_RXP1
PEG_RXP0

PEG_TXN15
PEG_TXN14
PEG_TXN13
PEG_TXN12
PEG_TXN11
PEG_TXN10
PEG_TXN9
PEG_TXN8
PEG_TXN7
PEG_TXN6
PEG_TXN5
PEG_TXN4
PEG_TXN3
PEG_TXN2
PEG_TXN1
PEG_TXN0

PEG_TXP15
PEG_TXP14
PEG_TXP13
PEG_TXP12
PEG_TXP11
PEG_TXP10
PEG_TXP9
PEG_TXP8
PEG_TXP7
PEG_TXP6
PEG_TXP5
PEG_TXP4
PEG_TXP3
PEG_TXP2
PEG_TXP1
PEG_TXP0

PEG_COMP

R21 24.9_1R21 24.9_1

+1.5V

PEG_RXN[15..0] 30

PEG_RXP[15..0] 30

PEG_TXN[15..0] 30

PEG_TXP[15..0] 30

Modify 32

DELAY_VR_PWRGOOD

+2.5V

+1.05V

R35 10KR35 10K

R33 10KR33 10K

R34 10KR34 10K

CFG0

PM_EXTTS#0

PM_EXTTS#1

4

+1.8VS

R334

R334

80.6_1

80.6_1

R335

R335

80.6_1

80.6_1

M_RCOMPN
M_RCOMPP

5

A A

C696 0.1uC696 0.1u

Host

CFG2

1

0

Clock
frequency

100

133

2

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

3145

3145

3145

Date: Sheet

Date: Sheet

Date: Sheet

M50EA0

M50EA0

M50EA0

NB DDRCLK_VGA_PCIEXPR-2/5

NB DDRCLK_VGA_PCIEXPR-2/5

NB DDRCLK_VGA_PCIEXPR-2/5

1

of

931Monday, June 06, 2005

of

931Monday, June 06, 2005

of

931Monday, June 06, 2005

B

B

B

CFG1

CFG0

1

0

1

0

3

5

4

3

2

1

D D

C C

B B

MA_DQ[63:0]13

MA_DQ0
MA_DQ1
MA_DQ2
MA_DQ3
MA_DQ4
MA_DQ5
MA_DQ6

MA_DQ8
MA_DQ9
MA_DQ10
MA_DQ11
MA_DQ12
MA_DQ13
MA_DQ14
MA_DQ15
MA_DQ16
MA_DQ17
MA_DQ18
MA_DQ19
MA_DQ20
MA_DQ21
MA_DQ22
MA_DQ23
MA_DQ24
MA_DQ25
MA_DQ26
MA_DQ27
MA_DQ28
MA_DQ29 MA_DQS#7
MA_DQ30
MA_DQ31
MA_DQ32
MA_DQ33
MA_DQ34
MA_DQ35
MA_DQ36
MA_DQ37
MA_DQ38
MA_DQ39
MA_DQ40
MA_DQ41
MA_DQ42
MA_DQ43
MA_DQ44
MA_DQ45
MA_DQ46
MA_DQ47
MA_DQ48
MA_DQ49
MA_DQ50
MA_DQ51
MA_DQ52
MA_DQ53
MA_DQ54
MA_DQ55
MA_DQ56
MA_DQ57
MA_DQ58
MA_DQ59
MA_DQ60
MA_DQ61
MA_DQ62

AG35
AH35

AL35
AL37

AH36

AJ35

AK37

AL34
AM36
AN35
AP32
AM31
AM34
AM35

AL32
AM32
AN31
AP31
AN28
AP28

AL30
AM30
AM28

AL28
AP27
AM27
AM23
AM22

AL23
AM24
AN22
AP22

AM9

AP11
AP10

AM7
AN5
AN6
AN3

AM6
AM3

AG2
AG1

AM2
AH3
AG3

AD6
AC4

AD4
AD5

U34C

U34C

SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SADQ8
SADQ9
SADQ10
SADQ11
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SADQ26
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32

AL9

SADQ33

AL6

SADQ34

AP7

SADQ35
SADQ36
SADQ37

AL7

SADQ38
SADQ39
SADQ40
SADQ41
SADQ42

AP3

SADQ43

AP6

SADQ44
SADQ45

AL4

SADQ46
SADQ47

AK2

SADQ48

AK3

SADQ49
SADQ50
SADQ51

AL3

SADQ52
SADQ53
SADQ54
SADQ55

AF3

SADQ56

AE3

SADQ57
SADQ58
SADQ59

AF2

SADQ60

AF1

SADQ61
SADQ62
SADQ63

915PM

915PM

SA_BS0#
SA_BS1#
SA_BS2#

SA_DM0
SA_DM1
SA_DM2
SA_DM3
SA_DM4
SA_DM5
SA_DM6
SA_DM7

SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7

SA_DQS0#
SA_DQS1#
SA_DQS2#
SA_DQS3#
SA_DQS4#
SA_DQS5#
SA_DQS6#
SA_DQS7#

SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA8

SA_MA9
SA_MA10
SA_MA11
SA_MA12
SA_MA13

SA_CAS#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

SA_RAS#

SA_RCVENIN#

SA_RCVENOUT#

SA_WE#

AK15
AK16
AL21

AJ37
AP35
AL29
AP24
AP9
AP4
AJ2
AD3

AK36
AP33
AN29
AP23
AM8
AM4
AJ1
AE5

AK35
AP34
AN30
AN23
AN8
AM5
AH1
AE4

AL17
AP17
AP18
AM17
AN18
AM18
AL19
AP20
AM19
AL20
AM16
AN20
AM20
AM15

AN15
AP16
AF29
AF28
AP15

MA_BA0
MA_BA1
MA_BA2

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS0
MA_DQS1
MA_DQS2
MA_DQS3

MA_DQS5
MA_DQS6
MA_DQS7

MA_DQS#0
MA_DQS#1
MA_DQS#2
MA_DQS#3
MA_DQS#4
MA_DQS#5
MA_DQS#6

MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13

MA_BA[2:0] 13,14

MA_DM[7:0] 13

MA_DQS[7:0] 13

MA_DQS#[7:0] 13

MAA_A[13:0] 13,14

MA_CAS# 13,14
MA_RAS# 13,14

MA_WE# 13,14

MB_DQ[63:0]13

MB_DQ0
MB_DQ1
MB_DQ2
MB_DQ3
MB_DQ4
MB_DQ5
MB_DQ6
MB_DQ7MA_DQ7
MB_DQ8
MB_DQ9
MB_DQ10
MB_DQ11
MB_DQ12
MB_DQ13
MB_DQ14
MB_DQ15
MB_DQ16
MB_DQ17MA_DQS4
MB_DQ18
MB_DQ19
MB_DQ20
MB_DQ21
MB_DQ22
MB_DQ23
MB_DQ24
MB_DQ25
MB_DQ26
MB_DQ27
MB_DQ28
MB_DQ29
MB_DQ30
MB_DQ31
MB_DQ32
MB_DQ33
MB_DQ34
MB_DQ35
MB_DQ36
MB_DQ37
MB_DQ38
MB_DQ39
MB_DQ40
MB_DQ41
MB_DQ42
MB_DQ43
MB_DQ44
MB_DQ45
MB_DQ46
MB_DQ47
MB_DQ48
MB_DQ49
MB_DQ50
MB_DQ51
MB_DQ52
MB_DQ53
MB_DQ54
MB_DQ55
MB_DQ56
MB_DQ57
MB_DQ58
MB_DQ59
MB_DQ60
MB_DQ61
MB_DQ62
MB_DQ63MA_DQ63

AE31
AE32
AG32
AG36
AE34
AE33
AF31
AF30
AH33
AH32
AK31
AG30
AG34
AG33
AH31

AJ31

AK30

AJ30
AH29
AH28
AK29
AH30
AH27
AG28
AF24
AG23

AJ22
AK22
AH24
AH23
AG22

AJ21
AG10

AG9
AG8

AH8
AH11
AH10

AK9

AK6

AH5

AK8

AK4

AG5

AG4

AD8

AD9

AH4

AG6

AE8

AD7

AC5

AB8

AB6

AA8

AC8

AC7

AA4

AA5

U34D

U34D

SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
SBDQ6
SBDQ7
SBDQ8
SBDQ9
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
SBDQ24
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
SBDQ33
SBDQ34
SBDQ35
SBDQ36
SBDQ37

AJ9

SBDQ38
SBDQ39

AJ7

SBDQ40
SBDQ41

AJ4

SBDQ42
SBDQ43
SBDQ44

AJ8

SBDQ45

AJ5

SBDQ46
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63

915PM

915PM

SB_BS0#
SB_BS1#
SB_BS2#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6
SB_DQS7

SB_DQS0#
SB_DQS1#
SB_DQS2#
SB_DQS3#
SB_DQS4#
SB_DQS5#
SB_DQS6#
SB_DQS7#

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13

SB_CAS#

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

SB_RAS#

SB_RCVENIN#

SB_RCVENOUT#

SB_WE#

AJ15
AG17
AG21

AF32
AK34
AK27
AK24
AJ10
AK5
AE7
AB7

AF34
AK32
AJ28
AK23
AM10
AH6
AF8
AB4

AF35
AK33
AK28
AJ23
AL10
AH7
AF7
AB5

AH17
AK17
AH18
AJ18
AK18
AJ19
AK19
AH19
AJ20
AH20
AJ16
AG18
AG20
AG15

AH14
AK14
AF15
AF14
AH16

MB_BA0
MB_BA1
MB_BA2

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS0
MB_DQS1
MB_DQS2
MB_DQS3
MB_DQS4
MB_DQS5
MB_DQS6
MB_DQS7

MB_DQS#0
MB_DQS#1
MB_DQS#2
MB_DQS#3
MB_DQS#4
MB_DQS#5
MB_DQS#6
MB_DQS#7

MBA_A0
MBA_A1
MBA_A2
MBA_A3
MBA_A4
MBA_A5
MBA_A6
MBA_A7
MBA_A8
MBA_A9
MBA_A10
MBA_A11
MBA_A12
MBA_A13

MB_BA[2:0] 13,14

MB_DM[7:0] 13

MB_DQS[7:0] 13

MB_DQS#[7:0] 13

MBA_A[13:0] 13,14

MB_CAS# 13,14
MB_RAS# 13,14

MB_WE# 13,14

A A

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

UNIWILL COMPUTER CORP.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

3145

3145

3145

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

M50EA0

M50EA0

M50EA0

NB DDR_MEM SYSTEM-3/5

NB DDR_MEM SYSTEM-3/5

NB DDR_MEM SYSTEM-3/5

1

10 31Monday, June 06, 2005

10 31Monday, June 06, 2005

10 31Monday, June 06, 2005

B

B

B

of

of

of