Fujitsu Siemens AMILO LI2727 Schematics

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www.laptop-schematics.com

7

6

5

4

3

2

1

Project Code : 91.4V701.001
PCB Number : 07207

LV1 Block Diagram

D D

CLK GEN

ICS 9LPRS502H

71.09502.C0W

DDR2

3

533/667MHz

533/667 MHz

11, 12

C C

DDR2

533/667MHz

533/667 MHz

11, 12

MIC In

B B

INT.SPKR

Codec

ALC268

OP AMP
G1432

OP AMP

Headphone Out

G1412

USB x 4

HDD

CD-ROM

8

7

AZALIA

26

27

27

USB 2.0

21

SATA

20

PATA

20

6

Mobile CPU

Merom 479
2G/2.33G

HOST BUS

Crestline

AGTL+ CPU I/F
DDR Memory I/F
INTEGRATED GRAHPICS
LVDS, CRT I/F

71.CREST.00U

X4 DMI
400MHz

ICH8M

6 PCIe ports
PCI/PCI BRIDGE
ACPI 1.1
3 SATA
1 PATA 66/100
10 USB 2.0/1.1 ports
ETHERNET (10/100/1000MbE)
High Definition Audio
LPC I/F
Serial Peripheral I/F
Matrix Storage Technology(DO)
Active Managemnet Technology(DO)

71.0ICH8.A0U

4, 5

667/800MHz@1.05V

6,7,8,9,10

C-Link0

PCI-E

15, 16, 17

5

G792

18

PCI-E /USB 2.0

LPC BUS

LPC

DEBUG
CONN.

4

PCB Version : -1

LVDS

RGB CRT

S-Video

LAN

10/100/G

RTL8101E

23

KBC

Winbond

WPC8763L

25

Touch
Pad

25

TXFM

Mini Card

802.11/a/b/g/n

SPI I/F

19

3

WXGA
15"LCD

CRT

S-Video

24

14

13

13

RJ45

24

22

BIOS

19

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size

Size

Size

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

Document Number Rev

Document Number Rev

Document Number Rev

2

PCB Layer Stackup

L1: Signal 1
L2: VCC
L3: Inner Signal 2
L4: Inner Signal 3
L5: GND
L6: Signal 4

Battery Charger

MAX8725ETI

INPUT

AD+
BAT+

CPU V_CORE

ISL6262 CRZ-T

INPUT

DCBATOUT

SYSTEM DC/DC

TPS51120

DCBATOUT

SYSTEM DC/DC

SC411 * 2

INPUT

DCBATOUT

SYSTEM DC/DC

TPS51100

INPUTS

0D9V_S0 (1.2A)
DDR_VREF_S3 (10mA)

SYSTEM DC/DC

APL5913

SYSTEM DC/DC

APL5915

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

LV1

LV1

LV1

5V_S5

INPUT

1D8V_S3

INPUT

1D8V_S3

35

OUTPUT

DCBATOUT

30,31

OUTPUT

VCC_CORE_S0

OUTPUT

OUTPUT

of

of

of

32

33

34

34

34

-1

-1

-1

8Friday, August 10, 2007

8Friday, August 10, 2007

8Friday, August 10, 2007

OUTPUTSINPUTS

5V_S5 ,
3D3V_S5,

OUTPUT

1D8V_S3,
1D05V_S0

OUTPUTS

1D5V_S0
(2.66A)

1D25V_S0
(1.7A)

13

13

13

1

A

ICH8M Functional Strap Definitions

www.laptop-schematics.com

Signal

HDA_SDOUT

HDA_SYNC

GNT2#

GPIO20
GNT1#/

GPIO51

GNT3#

GNT0#/
SPI_CS1#

INTVRMEN

LAN100_SLP

SATALED#

SPKR

TP3

GPIO33/
HDA_DOCK
_EN#

Usage/When Sampled

XOR Chain Entrance/
PCIE Port Config1 bit1,
Rising Edge of PWROK

PCIE config1 bit0,
Rising Edge of PWROK.

PCIE config2 bit0,
Rising Edge of PWROK.

Reserved
ESI Strap (Server Only)

Rising Edge of PWROK

Top-Block
Swap Override.
Rising Edge of PWROK.

Boot BIOS Destination
Selection.
Rising Edge of PWROK.

Integrated VccSus1_05,
VccSus1_5 and VccCL1_5
VRM Enable/Disable.
Always sampled.

Integrated VccLAN1_05
and VccCL1_05 VRM
Enable/Disable.
Always sampled.

PCI Express Lane
Reversal. Rising Edge
of PWROK.

No Reboot.
Rising Edge of PWROK.

XOR Chain Entrance.
Rising Edge of PWROK.

Flash Descriptor
Security Override Strap
Rising Edge of PWROK

ICH8-M EDS 20271 1.5V1

Allows entrance to XOR Chain testing when TP3
pulled low.When TP3 not pulled low at rising edge
of PWROK,sets bit1 of RPC.PC(Config Registers:
offset 224h)

This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)

This signal has a weak internal pull-up.
Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)

This signal should not be pulled high.
ESI compatible mode is for server platforms only.

This signal should not be pulled low for desttop
and mobile.

Sampled low:Top-Block Swap mode(inverts A16 for
all cycles targeting FWH BIOS space).
Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.

Controllable via Boot BIOS Destination bit
(Config Registers:Offset 3410h:bit 11:10).
GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC.

Enables integrated VccSus1_05, VccSus1_5 and
VccCL1_5 VRM's when sampled high

Enables integrated VccLAN1_05 and VccCL1_05 VRM's
when sampled high

Signal has weak internal pull-up. Sets bit 27
of MPC.LR(Device 28:Function 0:Offset D8)

If sampled high, the system is strapped to the
"No Reboot" mode(ICH8 will disable the TCO Timer
system reboot feature). The status is readable
via the NO REBOOT bit.

This signal should not be pull low unless using
XOR Chain testing.

This signal has a weak internal pull-up.
Sampled low:the Flash Descriptor Security will be
overridden. If high,the security measures will be
in effect.This should only be used in manufacturing
environments.

Comment

ICH8M IDE Integrated Series
Termination Resistors

DD[15:0], DIOW#, DIOR#, DREQ,
DDACK#, IORDY, DA[2:0], DCS1#,
DCS3#, IDEIRQ

PCI Routing

INT

PCIE Routing

LANE1

LAN
X

LANE2

MiniCard WLAN

LANE3

XLANE4

page 17

REQ GNTIDSEL

approximately 33 ohm

USB Table

USB

Pair

Device

USB1(ON BOARD)

0

USB2(ON BOARD)

1

USB3(ON BOARD)

2

USB4(ON BOARD)

3

MINICARD

4

X

5

X

6

X

7
8

X

9

X

page 16

ICH8M Integrated Pull-up
and Pull-down Resistors

SIGNAL

HDA_BIT_CLK
HDA_RST#
HDA_SDIN[3:0]
HDA_SDOUT
HDA_SYNC
GNT[3:0]
GPIO[20]
LDA[3:0]#/FHW[3:0]#
LAN_RXD[2:0]
LDRQ[0]
LDRQ[1]/GPIO23
PME#
PWRBTN#
SATALED#
SPI_CS1#
SPI_CLK
SPI_MOSI
SPI_MISO
TACH_[3:0]
SPKR
TP[3]
USB[9:0][P,N]
CL_RST#

Release BOM need modify

Location

P3

U39(CLK GEN)

U31(GM965)

P6

U31(GL960)

P11

U29(DDR CNN)
P15 71.0ICH8.A0U 71.ICH8M.A0UU49(ICH8M)
P19

U50 71.08763.00G 71.08763.B0G

U34,U35
P31

U33,U37

71.09365.00W

71.CREST.00U

62.10017.A71 62.10017.B51

ZZ.COMBO.001
ZZ.COMBO.001 84.01412.037

Release Layout need modify

U29(DDR CNN)

Resistor Type/Value

PULL-DOWN 20K
NONE
PULL-DOWN 20K
PULL-DOWN 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-UP 10K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 15K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-UP 20K
PULL-DOWN 20K
PULL-UP 20K
PULL-DOWN 15K
PULL-UP TBD

Schematic

ICH8-M EDS 20271 1.5V1

BOMPage

71.09502.C0W(ICS) 1'st

71.00875.C0W(RTL) 2'nd

71.GM965.A0U

71.GL960.A0U

84.01426.037

Crestline Strapping Signals and
Configuration

Pin Name

CFG[2:0]

CFG[4:3]
CFG5

CFG8

CFG9

CFG[11:10]

CFG[13:12]

CFG[15:14]
CFG16

CFG[18:17]

CFG19

CFG20

SDVOCRTL
_DATA

All strap signals are sampled with respect to the leading

NOTE:

Strap Description

FSB Frequency Select

Reserved
DMI x2 Select
ReservedCFG[7:6]

Low Power PCI Express

PCI Express Graphics
Lane Reversal

Reserved
XOR/ALL Z test

straps

Reserved
FSB Dynamic ODT

Reserved

DMI Lane Reversal

SDVO/PCIE
Concurrent

SDVO Present

edge of the Calistoga GMCH PWORK in signal.

Crestline EDS 19857 0.7a

Configuration

010 = FSB800
011 = FSB667
others = Reserved

0 = DMI x2

1 = DMI x4

0 = Normal mode

1 = Low Power mode

0 = Reverse Lanes,15->0,14->1 ect..

1= Normal operation(Default):Lane
Numbered in order

00 = Reserved
01 = XOR mode enabled
10 = All Z mode enabled

11 = Normal Operation

Reserved

0 = Dynamic ODT Disabled

1 = Dynamic ODT Enabled

0 = Normal operation (Default):lane
Numbered in order

1 =Reverse Lane,4->0,3->1 ect...

0 = Only SDVO or PCIE x1 is
operational (Default)

1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port

0 = No SDVO Card present

1= SDVO Card present

(Default)

Difference between LV1 and LV2

Location

Page

P6
P19

P3

R334
R333
U39 71.09502.C0W 71.00875.C0W

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size

Size

Size

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

LV1

71.GL960.A0U 71.GM965A0UU31

VX
XV

ICS9LPRS502H

Reference

Reference

Reference

Document Number Rev

Document Number Rev

Document Number Rev

LV1

LV1

LV1

page 7

(Default)

(Default)

(Default)

(Default)

LV2

RTM875T-605-VD-GRT

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

-1

-1

238Friday, August 10, 2007

238Friday, August 10, 2007

238Friday, August 10, 2007

-1

of

of

of

R143

www.laptop-schematics.com

R143

3D3V_48MPWR_S0

3D3V_S0

SEL2

SEL1

FSC

FSB

01

1
0

01

0101

PCLKCLK2
PCLKCLK3
PCLKCLK4
PCLKCLK5

SEL0
FSA

01

12

4D99R3F-1-GP

4D99R3F-1-GP

SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

12

R252

R252
10KR2J-3-GP

10KR2J-3-GP

12

R251

R251
10KR2J-3-GP

10KR2J-3-GP

DY

DY

1 2

C434 SC10P50V2JN-4GP

C434 SC10P50V2JN-4GP

1 2

C435 SC10P50V2JN-4GP

C435 SC10P50V2JN-4GP

1 2

C436 SC10P50V2JN-4GP

C436 SC10P50V2JN-4GP

1 2

C437 SC10P50V2JN-4GP

C437 SC10P50V2JN-4GP

1 2

C428 SC10P50V2JN-4GP

C428 SC10P50V2JN-4GP

1 2

C404 SC10P50V2JN-4GP

C404 SC10P50V2JN-4GP

CPU

100M
133M
166M
200M

PIN NAME DESCRIPTION

Byte 5, bit 7
0 = PCI0 enabled (default)

PCI0/CR#_A

PCI1/CR#_B

PCI2/TME
PCI3/RC-5_EN
PCI4/27M_SEL
PCI_F5/ITP_EN

1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair

Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair

0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed

0 = Pin37 as CPU_STOP# , pin 38 as PCI_STOP#.
1 = Pins37,38 as SRC-5 differential pair.

0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96#
1 = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0#

0 =SRC8/SRC8#
1 = ITP/ITP#

C243

C243

12

R256

R256
10KR2J-3-GP

10KR2J-3-GP

DY

DY

12

R257

R257
10KR2J-3-GP

10KR2J-3-GP

PCLK_CARD

DY

DY

PCLK_FWH

DY

DY

PCLK_KBC

DY

DY

PCLK_ICH

DY

DY

CLK48_ICH

DY

DY

CLK_ICH14

DY

DY

FSB

X
533M
667M
800M

12

12

12

12

R255

R255
10KR2J-3-GP

10KR2J-3-GP

DY

DY

R254

R254
10KR2J-3-GP

10KR2J-3-GP

CLK_PCI_ICH

C244

C244
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

3D3V_S0

12

R261

R261
10KR2J-3-GP

10KR2J-3-GP

DY

DY

12

R260

R260
10KR2J-3-GP

10KR2J-3-GP

TP111TP111

PCLK_FWH

PCLK_KBC

CLK48_ICH

CPU_SEL1

CLK_ICH14

CPU_SEL2

CPU_SEL0

SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

PCLK_CARD

1

PCLK_FWH

PCLK_ICH

CLK48_ICH
CPU_SEL1
CLK_ICH14

GEN_XTAL_IN

C415

C415

12

12

C426

C426

C408

C408

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

RN26

RN26

23
1

4

SRN33J-5-GP-U

SRN33J-5-GP-U

RN27

RN27

23
1

4

SRN33J-5-GP-U

SRN33J-5-GP-U

1 2

R249 33R2J-2-GPR249 33R2J-2-GP

1 2

R233 33R2J-2-GPR233 33R2J-2-GP

1 2

R232 2K2R2J-2-GPR232 2K2R2J-2-GP

1 2

R250 2K2R2J-2-GPR250 2K2R2J-2-GP

CL=20pF±0.2pF

R238

R238

DY

DY

1 2

10MR2J-L-GP

10MR2J-L-GP

1 2

12

GEN_XTAL_OUT

X3

X3

X-14D31818M-35GP

X-14D31818M-35GP

82.30005.891

82.30005.891

3D3V_CLKPLL_S0

12

12

C409

C409

C424

C424

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

3D3V_CLKGEN_S0
3D3V_48MPWR_S0

3D3V_CLKPLL_S0

PCLKCLK2
PCLKCLK3
PCLKCLK4PCLK_KBC
PCLKCLK5

GEN_XTAL_OUT
GEN_XTAL_IN

CLK48

CLK14

12

C418

C418
SC27P50V2JN-2-GP

SC27P50V2JN-2-GP

3D3V_S0

12

C407

C407

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

16
53

31
47

12
20
26
37
41

51
52

10
49
54

11
15
19
23
34
44
50

G73G73

1 2

12

C422

C422

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U39

U39

2

VDDPCI

9

VDD48
VDD
VDDREF

VDDSRC
VDDCPU

VDD96I/O
VDDPLL3I/O
VDDSRCI/O
VDDSRCI/O
VDDCPUI/O

1

PCICLK0/CR#_A

3

PCICLK1/CR#_B

4

PCICLK2/LTE

5

PCICLK3

6

PCICLK4/SRC5_EN

7

PCI_F5/ITP_EN
X2

X1
USB_48MHZ/FSLA
FSLB/TEST_MODE
FSLC/TEST_SEL/REF0

8

GNDPCI
GND48
GND
GND
GNDSRC
GNDSRC
GNDCPU
GNDREF

ICS9LPRS502HGLFT-GP

ICS9LPRS502HGLFT-GP

71.09502.C0W

71.09502.C0W

12

C413

C413

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DOTC_96/SRCCLKC0

SRCCLKT2/SATACLKT

SRCCLKC2/SATACLKC

PCI_STOP#/SRCCLKT5

CPU_STOP#/SRCCLKC5

CPUCLKT2_ITP/SRCCLKT8

CPUCLKC2_ITP/SRCCLKC8

DOTT_96/SRCCLKT0

SRCCLKT1/SE1
SRCCLKC1/SE2

SRCCLKT3/CR#_C
SRCCLKC3/CR#_D

SRCCLKT7/CR#_F
SRCCLKC7/CR#_E

CK_PWRGD/PD#

12

C425

C425

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SDATA

SCLK

SRCCLKT4
SRCCLKC4

SRCCLKT6
SRCCLKC6

CPUCLKT1
CPUCLKC1

CPUCLKT0
CPUCLKC0

NC#40

3D3V_CLKGEN_S0

12

12

C423

C423

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

55
56

13
14

17
18

21
22

24
25

27
28

30
29

33
32

36
35

39
38

43
42

46
45

48
40

BOM use 56pin ICS P/N:71.09502.C0W(1'st)
RTL P/N:71.00875.C0W(2'nd)

12

C412

C412

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

12

SMBDAT_ICH
SMBCLK_ICH

C411

C411

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DREFCLK_1
DREFCLK#_1

DREFSSCLK_1
DREFSSCLK#_1

CLK_PCIE_SATA_1
CLK_PCIE_SATA_1#

CLK_MCH_3GPLL_1
CLK_MCH_3GPLL_1#

CLK_PCIE_MINI_11
CLK_PCIE_MINI_11#

CLK_PCIE_ICH_1
CLK_PCIE_ICH_1#

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

CLK_MCH_BCLK_1
CLK_MCH_BCLK_1#

CLK_CPU_BCLK_1
CLK_CPU_BCLK_1#

CLK_PWRGD

C410

C410

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

G74G74

1 2

RN29

RN29
SRN0J-6-GP

SRN0J-6-GP
RN28

RN28
SRN0J-6-GP

SRN0J-6-GP
RN30

RN30
SRN0J-6-GP

SRN0J-6-GP
RN25

RN25
SRN0J-6-GP

SRN0J-6-GP
RN31

RN31
SRN0J-6-GP

SRN0J-6-GP

RN22

RN22
SRN0J-6-GP

SRN0J-6-GP

RN21

RN21
SRN0J-6-GP

SRN0J-6-GP
RN23

RN23
SRN0J-6-GP

SRN0J-6-GP
RN20

RN20
SRN0J-6-GP

SRN0J-6-GP

3D3V_S0

12

2 3
1

2 3
1

2 3
1

2 3
1

2 3
1

1
2 3

1
2 3

1
2 3

1
2 3

CLK_PWRGD

C414

C414

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

4

4

4

4

4

4

DREFCLK_96M
DREFCLK_96M#

DREFSSCLK_100M
DREFSSCLK_100M#

CLK_PCIE_SATA
CLK_PCIE_SATA#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

CLK_PCIE_MINI
CLK_PCIE_MINI#

PM_STPPCI#
PM_STPCPU#

CLK_PCIE_ICH
CLK_PCIE_ICH#

SC

4

4

4

CLK_PCIE_LAN
CLK_PCIE_LAN#

CLK_MCH_BCLK
CLK_MCH_BCLK#

CLK_CPU_BCLK
CLK_CPU_BCLK#

ZZZ

ZZZ

ZZZ

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Clock Generator

Clock Generator

Clock Generator

LV1

LV1

LV1

Hsichih, Taipei

-1

-1

338Saturday, August 11, 2007

338Saturday, August 11, 2007

338Saturday, August 11, 2007

-1

of

of

of

H_ADSTB#0

www.laptop-schematics.com

H_ADSTB#1
H_A20M#

H_FERR#

H_IGNNE#
H_STPCLK#

H_INTR
H_NMI

H_SMI#

TP40TP40
TP37TP37
TP48TP48
TP46TP46
TP43TP43
TP41TP41
TP47TP47
TP32TP32
TP42TP42
TP35TP35

TP53TP53

RSVD_CPU_1

1

RSVD_CPU_2

1

RSVD_CPU_3

1

RSVD_CPU_4

1

RSVD_CPU_5

1

RSVD_CPU_6

1

RSVD_CPU_7

1

RSVD_CPU_8

1

RSVD_CPU_9

1

RSVD_CPU_10

1

RSVD_CPU_11

1

1 OF 4

1 OF 4

U36A

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

U36A

J4

A3#

L5

A4#

L4

A5#

K5

A6#

M3

A7#

N2

A8#

J1

A9#

N3

A10#

P5

A11#

P2

A12#

L2

A13#

P4

A14#

P1

A15#

R1

A16#

M1

ADSTB0#

K3

REQ0#

H2

REQ1#

K2

REQ2#

J3

REQ3#

L1

REQ4#

Y2

A17#

U5

A18#

R3

A19#

W6

A20#

U4

A21#

Y5

A22#

U1

A23#

R4

A24#

T5

A25#

T3

A26#

W2

A27#

W5

A28#

Y4

A29#

U2

A30#

V4

A31#

W3

A32#

AA4

A33#

AB2

A34#

AA3

A35#

V1

ADSTB1#

A6

A20M#

A5

FERR#

C4

IGNNE#

D5

STPCLK#

C6

LINT0

B4

LINT1

A3

SMI#

M4

RSVD#M4

N5

RSVD#N5

T2

RSVD#T2

V3

RSVD#V3

B2

RSVD#B2

C3

RSVD#C3

D2

RSVD#D2

D22

RSVD#D22

D3

RSVD#D3

F6

RSVD#F6

B1

KEY_NC

BGA479-SKT6-GPU3

BGA479-SKT6-GPU3

62.10079.001

62.10079.001

1st source : 62.10079.001
2nd source : 62.10053.401

ADDR GROUP 0

ADDR GROUP 0

ADDR GROUP 1

ADDR GROUP 1

XDP/ITP SIGNALS CONTROL

XDP/ITP SIGNALS CONTROL
THERMAL

THERMAL

PROCHOT#

ICH

ICH

THERMTRIP#

HCLK

HCLK

RESERVED

RESERVED

ADS#
BNR#
BPRI#

DEFER#

DRDY#
DBSY#

BR0#

IERR#

INIT#

LOCK#

RESET#

RS0#
RS1#
RS2#

TRDY#

HIT#

HITM#

BPM0#
BPM1#
BPM2#
BPM3#
PRDY#
PREQ#

TCK

TDO
TMS

TRST#

DBR#

THRMDA
THRMDC

BCLK0
BCLK1

TDI

TP50TP50

H1
E2
G5

H5
F21
E1

F1

H_IERR#

D20
B3

H4
C1

H_RS#0

F3

H_RS#1

F4

H_RS#2

G3
G2

G6
E4

XDP_BPM#0

AD4

XDP_BPM#1

AD3

XDP_BPM#2

AD1

XDP_BPM#3

AC4

XDP_BPM4_PRDY#

AC2

XDP_BPM#5

AC1

XDP_TCK

AC5

XDP_TDI

AA6

XDP_TDO

AB3

XDP_TMS

AB5

XDP_TRST#

AB6

XDP_DBRESET#

C20

CPU_PROCHOT#

D21

H_THERMDA

A24

H_THERMDC

B25

H_THERMTRIP#

C7

A22
A21

1

H_ADS#
H_BNR#
H_BPRI#

H_DEFER#
H_DRDY#
H_DBSY#

H_BREQ#0

H_INIT#

H_LOCK#

H_CPURST#

H_TRDY#

H_HIT#
H_HITM#

TP44TP44

1

TP45TP45

1

TP49TP49

1

TP38TP38

1

TP51TP51

1

TP54TP54

1

TP39TP39

1

TP56TP56

1

TP57TP57

1

TP55TP55

1

TP36TP36

1

TP34TP34

1

H_THERMTRIP#

CPU_PROCHOT#

R127

R127

H_IERR#

R128 56R2F-1-GPR128 56R2F-1-GP

XDP_TMS

R140 54D9R2F-L1-GPR140 54D9R2F-L1-GP

XDP_TDI

R142 54D9R2F-L1-GPR142 54D9R2F-L1-GP

XDP_BPM#5

R139 54D9R2F-L1-GPR139 54D9R2F-L1-GP

XDP_TDO

R141 54D9R2F-L1-GP

R141 54D9R2F-L1-GP

H_CPURST#

R138 54D9R2F-L1-GP

R138 54D9R2F-L1-GP

XDP_DBRESET#

XDP_TCK
XDP_TRST#

R125

R125

R135 54D9R2F-L1-GPR135 54D9R2F-L1-GP
R133 649R2F-GPR133 649R2F-GP

All place within 2" to CPU

CLK_CPU_BCLK
CLK_CPU_BCLK#

1 2
1 2
1 2
1 2
1 2
1 2

DY

DY

1 2

DY

DY

1 2

DY

DY

1 2
1 2

12

Place close to CPU socket

1D05V_S0

68R2-GP

68R2-GP

3D3V_S0

150R2F-1-GP

150R2F-1-GP

H_A#[3..35]
H_REQ#[0..4]

H_D#[0..63]

H_RS#[0..2]

CPU_PROCHOT#
H_THERMDA
H_THERMDC

C183

C183
SC100P50V2JN-3GP

SC100P50V2JN-3GP

DY

DY

U36B

U36B

H_D#0

E22

H_D#1

F24

H_D#2

E26

H_D#3

G22

H_D#4

F23

H_D#5

G25

H_D#6

E25

H_D#7

E23

H_D#8

K24

H_D#9

G24

H_D#10

J24

H_D#11

J23

H_D#12

H22

H_D#13

F26

H_D#14

K22

H_D#15

H23

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31

J26
H26
H25

N22

K25
P26

R23

L23

M24

L22

M23

P25
P23
P22
T24

R24

L25
T25

N25

L26
M26
N24

AD26

C23
D25
C24

AF26

AF1

A26

B22

B23
C21

BGA479-SKT6-GPU3

BGA479-SKT6-GPU3

1KR2F-3-GP

1KR2F-3-GP

2KR2F-3-GP

2KR2F-3-GP

TEST4

1D05V_S0

R222

R222

1 2

12

R221

R221

C188

C188

1 2

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Layout Note:
"CPU_GTLREF0"

0.5" max length.

12

C385

C385

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

DY

DY

H_DSTBN#0
H_DSTBP#0

H_DINV#0

H_DSTBN#1
H_DSTBP#1

H_DINV#1

CPU_GTLREF0

TEST1

TP30TP30

1

TEST2

TP27TP27

1

TP29TP29

1

TEST4
RSVD_CPU_13

TP52TP52

1

RSVD_CPU_14

TP25TP25

1

CPU_SEL0
CPU_SEL1
CPU_SEL2

Net "TEST4" as short as possible,
make sure "TEST4" routing is
reference to GND and away other
noisy signals

CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0

166

200

0

00

1

11

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
DSTBN0#
DSTBP0#
DINV0#

D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
DSTBN1#
DSTBP1#
DINV1#

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

BSEL0
BSEL1
BSEL2

2 OF 4

2 OF 4

D32#
D33#
D34#
D35#

DATA GRP0 DATA GRP1

DATA GRP0 DATA GRP1

D36#
D37#
D38#
D39#
D40#
D41#
D42#

DATA GRP2DATA GRP3

DATA GRP2DATA GRP3

D43#
D44#
D45#
D46#

D47#
DSTBN2#
DSTBP2#

DINV2#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#
DSTBN3#
DSTBP3#

DINV3#
COMP0

MISC

MISC

COMP1
COMP2
COMP3

DPRSTP#

DPSLP#

DPWR#

PWRGOOD

SLP#

PSI#

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

H_D#32

Y22

H_D#33

AB24

H_D#34

V24

H_D#35

V26

H_D#36

V23

H_D#37

T22

H_D#38

U25

H_D#39

U23

H_D#40

Y25

H_D#41

W22

H_D#42

Y23

H_D#43

W24

H_D#44

W25

H_D#45

AA23

H_D#46

AA24

H_D#47

AB25
Y26
AA26
U22

H_D#48

AE24

H_D#49

AD24

H_D#50

AA21

H_D#51

AB22

H_D#52

AB21

H_D#53

AC26

H_D#54

AD20

H_D#55

AE22

H_D#56

AF23

H_D#57

AC25

H_D#58

AE21

H_D#59

AD21

H_D#60

AC22

H_D#61

AD23

H_D#62

AF22

H_D#63

AC23
AE25
AF24
AC20

COMP0

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

R119 27D4R2F-L1-GPR119 27D4R2F-L1-GP

COMP1
COMP2
COMP3RSVD_CPU_12

CPU (1 of 2) AGTL

CPU (1 of 2) AGTL

CPU (1 of 2) AGTL

1 2

R118 54D9R2F-L1-GPR118 54D9R2F-L1-GP

1 2

R136 27D4R2F-L1-GPR136 27D4R2F-L1-GP

1 2

R137 54D9R2F-L1-GPR137 54D9R2F-L1-GP

1 2

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
PSI#

Layout Note:
Comp0, 2 connect with Zo=27.4 ohm, make
trace length shorter than 0.5" .
Comp1, 3 connect with Zo=55 ohm, make
trace length shorter than 0.5" .

LV1

LV1

LV1

H_DSTBN#2
H_DSTBP#2
H_DINV#2

H_DSTBN#3
H_DSTBP#3
H_DINV#3

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

438Saturday, August 11, 2007

438Saturday, August 11, 2007

438Saturday, August 11, 2007

of

of

of

-1

-1

-1

VCC

www.laptop-schematics.com

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

VCCA
VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

VCC_CORE_S0

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCC_SENSE

AF7

VSS_SENSE

AE7

H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6

Ivccp boot= 4.5A
Ivccp stable= 2.5A

12

12

C202

C202

C204

C204

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

VCC_SENSE

VSS_SENSE

3 OF 4

VCC_CORE_S0

3 OF 4

U36C

U36C

A7

VCC

A9

VCC

A10

VCC

A12

VCC

A13

VCC

A15

VCC

A17

VCC

A18

VCC

A20

VCC

B7

VCC

B9

VCC

B10

VCC

B12

VCC

B14

VCC

B15

VCC

B17

VCC

B18

VCC

B20

VCC

C9

VCC

C10

VCC

C12

VCC

C13

VCC

C15

VCC

C17

VCC

C18

VCC

D9

VCC

D10

VCC

D12

VCC

D14

VCC

D15

VCC

D17

VCC

D18

VCC

E7

VCC

E9

VCC

E10

VCC

E12

VCC

E13

VCC

E15

VCC

E17

VCC

E18

VCC

E20

VCC

F7

VCC

F9

VCC

F10

VCC

F12

VCC

F14

VCC

F15

VCC

F17

VCC

F18

VCC

F20

VCC

AA7

VCC

AA9

VCC

AA10

VCC

AA12

VCC

AA13

VCC

AA15

VCC

AA17

VCC

AA18

VCC

AA20

VCC

AB9

VCC

AC10

VCC

AB10

VCC

AB12

VCC

AB14

VCC

AB15

VCC

AB17

VCC

AB18

VCC

BGA479-SKT6-GPU3

BGA479-SKT6-GPU3

Layout Note:
VCCSENSE and VSSSENSE lines should be of equal length.

Layout Note:
Provide a test point (with no stub) to connect a differential probe
between VCCSENSE and VSSSENSE at the location where the
two 54.9ohm resistors terminate the 55 ohm transmission line.

1D05V_S0

12

TC6

TC6
SE330U2VDM-L-GP

SE330U2VDM-L-GP

Place close to CPU socket

1D5V_VCCA_S0

12

C187

C187

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

L1

L1

1 2

HCB1608KF121T30-GP

HCB1608KF121T30-GP

12

C178

C178

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C226

C226

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C225

C225

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C214

C214

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C212

C212

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C232

C232

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C215

C215

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C213

C213

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C227

C227

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C208

C208

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C224

C224

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C222

C222

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C233

C233

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C209

C209

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C216

C216

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP

68.00230.041

68.00230.041

VCC_SENSE

VSS_SENSE

1D5V_S0

layout note: "1D5V_VCCA_S0"
as short as possible

H_VID[0..6]

VCC_CORE_S0

R131

R131

12

100R2F-L1-GP-U

100R2F-L1-GP-U

R130

R130

1 2

100R2F-L1-GP-U

100R2F-L1-GP-U

IVCCA = 130mA

VCC_CORE_S0VCC_CORE_S0

1D05V_S0

VCC_CORE_S0

1 2

C229 SCD1U10V2KX-5GPC229 SCD1U10V2KX-5GP

1 2

C205 SCD1U10V2KX-5GPC205 SCD1U10V2KX-5GP

1 2

C223 SCD1U10V2KX-5GPC223 SCD1U10V2KX-5GP

1 2

DY

DY

C211 SCD1U10V2KX-5GP

C211 SCD1U10V2KX-5GP

1 2

C236 SCD1U10V2KX-5GPC236 SCD1U10V2KX-5GP

1 2

C237 SCD1U10V2KX-5GPC237 SCD1U10V2KX-5GP

1 2

C240 SCD1U10V2KX-5GPC240 SCD1U10V2KX-5GP

1 2

DY

DY

C198 SCD1U10V2KX-5GP

C198 SCD1U10V2KX-5GP

1 2

DY

DY

C199 SCD1U10V2KX-5GP

C199 SCD1U10V2KX-5GP

1 2

C242 SCD1U10V2KX-5GPC242 SCD1U10V2KX-5GP

1 2

C239 SC4D7U6D3V3KX-GPC239 SC4D7U6D3V3KX-GP

1 2

C201 SC4D7U6D3V3KX-GPC201 SC4D7U6D3V3KX-GP

C228

C228

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C234

C234

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C218

C218

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP
C203

C203

1 2

SC10U6D3V6KX-4GP

SC10U6D3V6KX-4GP

4 OF 4

4 OF 4

U36D

U36D

A4

VSS

A8

VSS

A11

VSS

A14

VSS

A16

VSS

A19

VSS

A23

VSS

AF2

VSS

B6

VSS

B8

VSS

B11

VSS

B13

VSS

B16

VSS

B19

VSS

B21

VSS

B24

VSS

C5

VSS

C8

VSS

C11

VSS

C14

VSS

C16

VSS

C19

VSS

C2

VSS

C22

VSS

C25

VSS

D1

VSS

D4

VSS

D8

VSS

D11

VSS

D13

VSS

D16

VSS

D19

VSS

D23

VSS

D26

VSS

E3

VSS

E6

VSS

E8

VSS

E11

VSS

E14

VSS

E16

VSS

E19

VSS

E21

VSS

E24

VSS

F5

VSS

F8

VSS

F11

VSS

F13

VSS

F16

VSS

F19

VSS

F2

VSS

F22

VSS

F25

VSS

G4

VSS

G1

VSS

G23

VSS

G26

VSS

H3

VSS

H6

VSS

H21

VSS

H24

VSS

J2

VSS

J5

VSS

J22

VSS

J25

VSS

K1

VSS

K4

VSS

K23

VSS

K26

VSS

L3

VSS

L6

VSS

L21

VSS

L24

VSS

M2

VSS

M5

VSS

M22

VSS

M25

VSS

N1

VSS

N4

VSS

N23

VSS

N26

VSS

P3

VSS

BGA479-SKT6-GPU3

BGA479-SKT6-GPU3

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

CPU (2 of 2) POWER

CPU (2 of 2) POWER

CPU (2 of 2) POWER

LV1

LV1

LV1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

538Saturday, August 11, 2007

538Saturday, August 11, 2007

538Saturday, August 11, 2007

of

of

of

-1

-1

-1

H_SWING routing Trace width and

www.laptop-schematics.com

Spacing use 10 / 20 mil
H_SWING Resistors and

Capacitors close MCH
500 mil ( MAX )

1D05V_S0

12

R208

R208

221R2F-2-GP

221R2F-2-GP

H_SWINGH_SWING

12

1 2

1 2

1 2

12

C352

C352
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

H_SCOMP

54D9R2F-L1-GP

54D9R2F-L1-GP

H_SCOMP#

54D9R2F-L1-GP

54D9R2F-L1-GP

H_RCOMP

24D9R2F-L-GP

24D9R2F-L-GP

R209

R209

100R2F-L1-GP-U

100R2F-L1-GP-U

H_SCOMP and H_SCOMP# Resistors and
Capacitors close MCH 500 mil ( MAX )

1D05V_S0

R206

R206

R205

R205

H_RCOMP routing Trace width and
Spacing use 10 / 20 mil

R207

R207

Place them near to the chip ( < 0.5")

1KR2F-3-GP

1KR2F-3-GP

1D05V_S0

R213

R213

12

H_AVREF

12

R211

R211
2KR2F-3-GP

2KR2F-3-GP

H_CPURST#

H_CPUSLP#

12

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_SWING
H_RCOMP

H_SCOMP
H_SCOMP#

C356

C356
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

U31A

U31A

E2

H_D#0

G2

H_D#1

G7

H_D#2

M6

H_D#3

H7

H_D#4

H3

H_D#5

G4

H_D#6

F3

H_D#7

N8

H_D#8

H2

H_D#9

M10

H_D#10

N12

H_D#11

N9

H_D#12

H5

H_D#13

P13

H_D#14

K9

H_D#15

M2

H_D#16

W10

H_D#17

Y8

H_D#18

V4

H_D#19

M3

H_D#20

J1

H_D#21

N5

H_D#22

N3

H_D#23

W6

H_D#24

W9

H_D#25

N2

H_D#26

Y7

H_D#27

Y9

H_D#28

P4

H_D#29

W3

H_D#30

N1

H_D#31

AD12

H_D#32

AE3

H_D#33

AD9

H_D#34

AC9

H_D#35

AC7

H_D#36

AC14

H_D#37

AD11

H_D#38

AC11

H_D#39

AB2

H_D#40

AD7

H_D#41

AB1

H_D#42

Y3

H_D#43

AC6

H_D#44

AE2

H_D#45

AC5

H_D#46

AG3

H_D#47

AJ9

H_D#48

AH8

H_D#49

AJ14

H_D#50

AE9

H_D#51

AE11

H_D#52

AH12

H_D#53

AJ5

H_D#54

AH5

H_D#55

AJ6

H_D#56

AE7

H_D#57

AJ7

H_D#58

AJ2

H_D#59

AE5

H_D#60

AJ3

H_D#61

AH2

H_D#62

AH13

H_D#63

B3

H_SWING

C2

H_RCOMP

W1

H_SCOMP

W2

H_SCOMP#

B6

H_CPURST#

E5

H_CPUSLP#

B9

H_AVREF

A9

H_DVREF

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

71.CREST.00U

71.CREST.00U

1 OF 10

1 OF 10

H_ADSTB#0
H_ADSTB#1

HOST

HOST

H_BPRI#

H_BREQ#

H_DEFER#

H_DBSY#

HPLL_CLK

HPLL_CLK#

H_DPWR#

H_DRDY#

H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8

H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_ADS#

H_BNR#

H_HIT#

H_RS#0
H_RS#1
H_RS#2

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

K5
L2
AD13
AE13

M7
K3
AD2
AH11

L7
K2
AC2
AJ10

M14
E13
A11
H13
B12

E12
D7
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#0
H_RS#1
H_RS#2

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BREQ#0
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_RS#[0..2]
H_REQ#[0..4]

H_D#[0..63]

H_A#[3..35]

H_REF Decoupling Crestline
close Crestline 100 mil

GM965 ( 71.GM965.00U )
GL960 ( 71.GL960.A0U )

ZZZ

ZZZ

ZZZ

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

GMCH (1 of 5) AGTL

GMCH (1 of 5) AGTL

GMCH (1 of 5) AGTL

LV1

LV1

LV1

Hsichih, Taipei

638Saturday, August 11, 2007

638Saturday, August 11, 2007

638Saturday, August 11, 2007

of

of

of

-1

-1

-1

5

www.laptop-schematics.com

D D

C C

TP8TP8
TP10TP10
TP3TP3
TP16TP16
TP12TP12
TP6TP6
TP7TP7
TP15TP15
TP14TP14
TP4TP4
TP11TP11
TP5TP5
TP13TP13
TP9TP9
TP18TP18
TP20TP20
TP19TP19
TP24TP24

U13

U13

B

VCC

A
GND

DY

DY

R104

R104

10KR2J-3-GP

10KR2J-3-GP

5

CPU_SEL0
CPU_SEL1
CPU_SEL2

CFG3

1

CFG4

1

CFG5

1

CFG6

1

CFG7

1

CFG8

1

CFG9

1

CFG10

1

CFG11

1

CFG12

1

CFG13

1

CFG14

1

CFG15

1

CFG16

1

CFG17

1

CFG18

1

CFG19

1

CFG20

1

PM_BMBUSY#
PM_EXTTS#0

PM_EXTTS#1
VGATE_PWRGD

PLT_RST1#_NB

H_THERMTRIP#
PM_DPRSLPVR

3D3V_S0

5
4

Y

3D3V_S0

CPU_SEL0
CPU_SEL1
CPU_SEL2

B B

PM_BMBUSY#

H_DPRSTP#

VGATE_PWRGD

H_THERMTRIP#

PM_DPRSLPVR

-1

12

R123

R123
47R2J-2-GP

47R2J-2-GP

A A

CLK_3GPLLREQ#

PLT_RST1#

1
2
3

74LVC1G08GW-1-GP

74LVC1G08GW-1-GP

1 2

U31B

U31B

P36

RSVD#P36

P37

RSVD#P37

R35

RSVD#R35

N35

RSVD#N35

AR12

RSVD#AR12

AR13

RSVD#AR13

AM12

RSVD#AM12

AN13

RSVD#AN13

J12

RSVD#J12

AR37

RSVD#AR37

AM36

RSVD#AM36

AL36

RSVD#AL36

AM37

RSVD#AM37

D20

RSVD#D20

H10

RSVD#H10

B51

RSVD#B51

BJ20

RSVD#BJ20

BK22

RSVD#BK22

BF19

RSVD#BF19

BH20

RSVD#BH20

BK18

RSVD#BK18

BJ18

RSVD#BJ18

BF23

RSVD#BF23

BG23

RSVD#BG23

BC23

RSVD#BC23

BD24

RSVD#BD24

BH39

RSVD#BH39

AW20

RSVD#AW20

BK20

RSVD#BK20

B44

RSVD#B44

C44

RSVD#C44

A35

RSVD#A35

B37

RSVD#B37

B36

RSVD#B36

B34

RSVD#B34

C34

RSVD#C34

P27

CFG0

N27

CFG1

N24

CFG2

C21

CFG3

C23

CFG4

F23

CFG5

N23

CFG6

G23

CFG7

J20

CFG8

C20

CFG9

R24

CFG10

L23

CFG11

J23

CFG12

E23

CFG13

E20

CFG14

K23

CFG15

M20

CFG16

M24

CFG17

L32

CFG18

N33

CFG19

L35

CFG20

G41

PM_BM_BUSY#

L39

PM_DPRSTP#

L36

PM_EXT_TS#0

J36

PM_EXT_TS#1

AW49

PWROK

AV20

RSTIN#

N20

THERMTRIP#

G36

DPRSLPVR

BJ51

NC#BJ51

BK51

NC#BK51

BK50

NC#BK50

BL50

NC#BL50

BL49

NC#BL49

BL3

NC#BL3

BL2

NC#BL2

BK1

NC#BK1

BJ1

NC#BJ1

E1

NC#E1

A5

NC#A5

C51

NC#C51

B50

NC#B50

A50

NC#A50

A49

NC#A49

BK2

NC#BK2

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

2 OF 10

2 OF 10

RSVD

RSVD

DDR MUXING

DDR MUXING

SM_RCOMP_VOH

SM_RCOMP_VOL

SM_VREF#AR49

SM_VREF#AW4

DPLL_REF_CLK

DPLL_REF_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

CLK

CLK

DMI

DMI

CFG PM NC

CFG PM NC

SDVO_CTRL_CLK

SDVO_CTRL_DATA

MISC ME GRAPHICS VID

MISC ME GRAPHICS VID

SM_RCOMP

SM_RCOMP#

GFX_VR_EN

CL_PWROK

ICH_SYNC#

SM_CK0
SM_CK1
SM_CK3
SM_CK4

SM_CK#0
SM_CK#1
SM_CK#3
SM_CK#4

SM_CKE0
SM_CKE1
SM_CKE3
SM_CKE4

SM_CS#0
SM_CS#1
SM_CS#2
SM_CS#3

SM_ODT0
SM_ODT1
SM_ODT2
SM_ODT3

PEG_CLK

PEG_CLK#

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3

CL_CLK

CL_DATA
CL_RST#

CL_VREF

CLKREQ#

TEST1
TEST2

4

M_CLK_DDR0

AV29

M_CLK_DDR1

BB23

M_CLK_DDR2

BA25

M_CLK_DDR3

AV23

M_CLK_DDR#0

AW30

M_CLK_DDR#1

BA23

M_CLK_DDR#2

AW25

M_CLK_DDR#3

AW23

M_CKE0

BE29

M_CKE1

AY32

M_CKE2

BD39

M_CKE3

BG37

M_CS#0

BG20

M_CS#1

BK16

M_CS#2

BG16

M_CS#3

BE13

M_ODT0

BH18

M_ODT1

BJ15

M_ODT2

BJ14

M_ODT3

BE16

SM_RCOMP_VOH

BK31

SM_RCOMP_VOL

BL31

M_RCOMPP

BL15

M_RCOMPN

BK14
AR49

AW4

DREFCLK

B42

DREFCLK#

C42

DREFSSCLK

H48

DREFSSCLK#

H47

CLK_MCH_3GPLL

K44

CLK_MCH_3GPLL#

K45

DMI_TXN0

AN47

DMI_TXN1

AJ38

DMI_TXN2

AN42

DMI_TXN3

AN46

DMI_TXP0

AM47

DMI_TXP1

AJ39

DMI_TXP2

AN41

DMI_TXP3

AN45

DMI_RXN0

AJ46

DMI_RXN1

AJ41

DMI_RXN2

AM40

DMI_RXN3

AM44

DMI_RXP0

AJ47

DMI_RXP1

AJ42

DMI_RXP2

AM39

DMI_RXP3

AM43

GFX_VID0

E35

GFX_VID1

A39

GFX_VID2

C38

GFX_VID3H_DPRSTP#

B39

GFX_VR_EN

E36

CL_CLK0

AM49

CL_DATA0

AK50

PWROK

AT43

CL_RST#

AN49

MCH_CLVREF

AM50

H35

SDVO_CRT_DATA

K36

CLK_3GPLLREQ#

G39

MCH_ICH_SYNC#

G40

TEST1_GMCH

A37

TEST2_GMCH

R32

20KR2J-L2-GP

20KR2J-L2-GP

4

R100

R100

1
1
1
1
1

12

DDR_VREF_S3

TP22TP22
TP107TP107
TP106TP106
TP108TP108
TP23TP23

1

12

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

M_CKE0
M_CKE1
M_CKE2
M_CKE3

M_CS#0
M_CS#1
M_CS#2
M_CS#3

M_ODT0
M_ODT1
M_ODT2
M_ODT3

M_RCOMPP

M_RCOMPN

DREFCLK_96M
DREFCLK_96M#
DREFSSCLK_100M
DREFSSCLK_100M#

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

CL_CLK0

CL_DATA0
PWROK
CL_RST#

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

TP21TP21

MCH_ICH_SYNC#

-1

R225

R225
0R0402-PAD

0R0402-PAD

20R2F-GP

20R2F-GP

20R2F-GP

20R2F-GP

C396

C396

1D8V_S3

R212

R212

R210

R210

12

12

1 2

1D25V_S0

12

12

3

R229

R229
1KR2F-3-GP

1KR2F-3-GP

R228

R228
392R2F-GP

392R2F-GP

1D8V_S3

3

GMCH_BL_EN

LDDC_CLK
LDDC_DATA
LCDVDD_EN

GMCH_TXACLK­GMCH_TXACLK+

GMCH_TXAOUT0­GMCH_TXAOUT1­GMCH_TXAOUT2-

GMCH_TXAOUT0+
GMCH_TXAOUT1+
GMCH_TXAOUT2+

TV_DACB
TV_DACC

3D3V_S0

RN13

RN13

2 3
1

SRN2K2J-1-GP

SRN2K2J-1-GP

GMCH_BLUE

GMCH_GREEN

GMCH_RED

GMCH_DDCCLK

GMCH_DDCDATA

GMCH_VSYNC
GMCH_HSYNC

LBKLT_CR

TP26TP26

1

GMCH_BL_EN
LCTLA_CLK
LCTLB_DATA
LDDC_CLK
LDDC_DATA

GMCH_LCDVDD_ON

LIBG
L_LVBG

1

TP28TP28

GMCH_TXAOUT0­GMCH_TXAOUT1­GMCH_TXAOUT2­GMCH_TXAOUT3-

1

TP33TP33

GMCH_TXAOUT0+
GMCH_TXAOUT1+
GMCH_TXAOUT2+
GMCH_TXAOUT3+

1

TP31TP31

TV_DACA
TV_DACB
TV_DACC

TV_DCONSEL0
TV_DCONSEL1

4

GMCH_BLUE
GMCH_GREEN
GMCH_RED

GMCH_DDCCLK
GMCH_DDCDATA

CRT_IREF

R97

R97

1K3R2F-1-GP

1K3R2F-1-GP

1 2

FOR Calero: 255 ohm
Crestline: 1.3k ohm

CRT_IREF routing Trace
width use 20 mil

R218

R218

12

12

12

1KR2F-3-GP

1KR2F-3-GP

C378

C378

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

C381

C381

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

U31C

U31C

J40

L_BKLT_CTRL

H39

L_BKLT_EN

E39

L_CTRL_CLK

E40

L_CTRL_DATA

C37

L_DDC_CLK

D35

L_DDC_DATA

K40

L_VDD_EN

L41

LVDS_IBG

L43

LVDS_VBG

N41

LVDS_VREFH

N40

LVDS_VREFL

D46

LVDSA_CLK#

C45

LVDSA_CLK

D44

LVDSB_CLK#

E42

LVDSB_CLK

G51

LVDSA_DATA#0

E51

LVDSA_DATA#1

F49

LVDSA_DATA#2

C48

LVDSA_DATA#3

G50

LVDSA_DATA0

E50

LVDSA_DATA1

F48

LVDSA_DATA2

D47

LVDSA_DATA3

G44

LVDSB_DATA#0

B47

LVDSB_DATA#1

B45

LVDSB_DATA#2

E44

LVDSB_DATA0

A47

LVDSB_DATA1

A45

LVDSB_DATA2

E27

TVA_DAC

G27

TVB_DAC

K27

TVC_DAC

F27

TVA_RTN

J27

TVB_RTN

L27

TVC_RTN

M35

TV_DCONSEL0

P33

TV_DCONSEL1

H32

CRT_BLUE

G32

CRT_BLUE#

K29

CRT_GREEN

J29

CRT_GREEN#

F29

CRT_RED

E29

CRT_RED#

K33

CRT_DDC_CLK

G35

CRT_DDC_DATA

E33

CRT_VSYNC

C32

CRT_TVO_IREF

F33

CRT_HSYNC

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

R217

R217

3K01R2F-3-GP

3K01R2F-3-GP

1KR2F-3-GP

1KR2F-3-GP

12

R216

R216

3 OF 10

3 OF 10

SM_RCOMP_VOLSM_RCOMP_VOH

12

2

PEG_COMPI

PEG_COMPO

PEG_RX#0
PEG_RX#1
PEG_RX#2
PEG_RX#3
PEG_RX#4
PEG_RX#5
PEG_RX#6
PEG_RX#7
PEG_RX#8

LVDS

LVDS

PEG_RX#9
PEG_RX#10
PEG_RX#11
PEG_RX#12
PEG_RX#13
PEG_RX#14
PEG_RX#15

PEG_RX0
PEG_RX1
PEG_RX2
PEG_RX3
PEG_RX4
PEG_RX5
PEG_RX6
PEG_RX7
PEG_RX8

PEG_RX9
PEG_RX10
PEG_RX11
PEG_RX12
PEG_RX13
PEG_RX14
PEG_RX15

PEG_TX#0
PEG_TX#1
PEG_TX#2
PEG_TX#3

TV VGA

TV VGA

PEG_TX#4
PEG_TX#5
PEG_TX#6
PEG_TX#7
PEG_TX#8
PEG_TX#9

PEG_TX#10

PCI_EXPRESS GRAPHICS

PCI_EXPRESS GRAPHICS

PEG_TX#11
PEG_TX#12
PEG_TX#13
PEG_TX#14
PEG_TX#15

PEG_TX0

PEG_TX1

PEG_TX2

PEG_TX3

PEG_TX4

PEG_TX5

PEG_TX6

PEG_TX7

PEG_TX8

PEG_TX9
PEG_TX10
PEG_TX11
PEG_TX12
PEG_TX13
PEG_TX14
PEG_TX15

GMCH_BLUE
GMCH_GREEN
GMCH_RED
TV_DACA
TV_DACB
TV_DACC

12

C370

C370

SCD01U16V2KX-3GP

SCD01U16V2KX-3GP

2

1 2

R87 150R2F-1-GPR87 150R2F-1-GP

1 2

R93 150R2F-1-GPR93 150R2F-1-GP

1 2

R95 150R2F-1-GPR95 150R2F-1-GP

1 2

R90 150R2F-1-GPR90 150R2F-1-GP

1 2

R91 150R2F-1-GPR91 150R2F-1-GP

1 2

R92 150R2F-1-GPR92 150R2F-1-GP

12

C367

C367

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

1

R117

PEG_CMP

N43
M43

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

R117

12

1D05V_S0

24D9R2F-L-GP

24D9R2F-L-GP

RN14

LCTLA_CLK
LCTLB_DATA
PM_EXTTS#0
PM_EXTTS#1

SRN10KJ-6-GP

SRN10KJ-6-GP

LIBG

GMCH (2 of 5) DMI/LVDS/PEG

GMCH (2 of 5) DMI/LVDS/PEG

GMCH (2 of 5) DMI/LVDS/PEG

LV1

LV1

LV1

1

RN14

1
2
3
4 5

R120

R120

1 2

2K4R2F-GP

2K4R2F-GP

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

738Saturday, August 11, 2007

738Saturday, August 11, 2007

738Saturday, August 11, 2007

of

of

of

3D3V_S0

8
7
6

-1

-1

-1

U31I

www.laptop-schematics.com

U31I

A13

VSS

A15

VSS

A17

VSS

A24

VSS

AA21

VSS

AA24

VSS

AA29

VSS

AB20

VSS

AB23

VSS

AB26

VSS

AB28

VSS

AB31

VSS

AC10

VSS

AC13

VSS

AC3

VSS

AC39

VSS

AC43

VSS

AC47

VSS

AD1

VSS

AD21

VSS

AD26

VSS

AD29

VSS

AD3

VSS

AD41

VSS

AD45

VSS

AD49

VSS

AD5

VSS

AD50

VSS

AD8

VSS

AE10

VSS

AE14

VSS

AE6

VSS

AF20

VSS

AF23

VSS

AF24

VSS

AF31

VSS

AG2

VSS

AG38

VSS

AG43

VSS

AG47

VSS

AG50

VSS

AH3

VSS

AH40

VSS

AH41

VSS

AH7

VSS

AH9

VSS

AJ11

VSS

AJ13

VSS

AJ21

VSS

AJ24

VSS

AJ29

VSS

AJ32

VSS

AJ43

VSS

AJ45

VSS

AJ49

VSS

AK20

VSS

AK21

VSS

AK26

VSS

AK28

VSS

AK31

VSS

AK51

VSS

AL1

VSS

AM11

VSS

AM13

VSS

AM3

VSS

AM4

VSS

AM41

VSS

AM45

VSS

AN1

VSS

AN38

VSS

AN39

VSS

AN43

VSS

AN5

VSS

AN7

VSS

AP4

VSS

AP48

VSS

AP50

VSS

AR11

VSS

AR2

VSS

AR39

VSS

AR44

VSS

AR47

VSS

AR7

VSS

AT10

VSS

AT14

VSS

AT41

VSS

AT49

VSS

AU1

VSS

AU23

VSS

AU29

VSS

AU3

VSS

AU36

VSS

AU49

VSS

AU51

VSS

AV39

VSS

AV48

VSS

AW1

VSS

AW12

VSS

AW16

VSS

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

9 OF 10

9 OF 10

VSS

VSS

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

M_A_DQ[63..0]

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQ[63..0]

U31D

U31D

AR43

SA_DQ0

AW44

SA_DQ1

BA45

SA_DQ2

AY46

SA_DQ3

AR41

SA_DQ4

AR45

SA_DQ5

AT42

SA_DQ6

AW47

SA_DQ7

BB45

SA_DQ8

BF48

SA_DQ9

BG47

SA_DQ10

BJ45

SA_DQ11

BB47

SA_DQ12

BG50

SA_DQ13

BH49

SA_DQ14

BE45

SA_DQ15

AW43

SA_DQ16

BE44

SA_DQ17

BG42

SA_DQ18

BE40

SA_DQ19

BF44

SA_DQ20

BH45

SA_DQ21

BG40

SA_DQ22

BF40

SA_DQ23

AR40

SA_DQ24

AW40

SA_DQ25

AT39

SA_DQ26

AW36

SA_DQ27

AW41

SA_DQ28

AY41

SA_DQ29

AV38

SA_DQ30

AT38

SA_DQ31

AV13

SA_DQ32

AT13

SA_DQ33

AW11

SA_DQ34

AV11

SA_DQ35

AU15

SA_DQ36

AT11

SA_DQ37

BA13

SA_DQ38

BA11

SA_DQ39

BE10

SA_DQ40

BD10

SA_DQ41

BD8

SA_DQ42

AY9

SA_DQ43

BG10

SA_DQ44

AW9

SA_DQ45

BD7

SA_DQ46

BB9

SA_DQ47

BB5

SA_DQ48

AY7

SA_DQ49

AT5

SA_DQ50

AT7

SA_DQ51

AY6

SA_DQ52

BB7

SA_DQ53

AR5

SA_DQ54

AR8

SA_DQ55

AR9

SA_DQ56

AN3

SA_DQ57

AM8

SA_DQ58

AN10

SA_DQ59

AT9

SA_DQ60

AN9

SA_DQ61

AM9

SA_DQ62

AN11

SA_DQ63

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

M_A_DM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]

4 OF 10

4 OF 10

BB19

SA_BS0

BK19

SA_BS1

BF29

SA_BS2

BL17

SA_CAS#

AT45

SA_DM0

BD44

SA_DM1

BD42

SA_DM2

AW38

SA_DM3

AW13

SA_DM4

BG8

SA_DM5

AY5

SA_DM6

AN6

SA_DM7

AT46

SA_DQS0

BE48

SA_DQS1

BB43

SA_DQS2

BC37

SA_DQS3

BB16

SA_DQS4

BH6

SA_DQS5

BB2

SA_DQS6

AP3

SA_DQS7

AT47

SA_DQS#0

BD47

SA_DQS#1

BC41

SA_DQS#2

BA37

SA_DQS#3

BA16

SA_DQS#4

BH7

SA_DQS#5

BC1

SA_DQS#6

AP2

SA_DQS#7

BJ19

SA_MA0

BD20

SA_MA1

BK27

SA_MA2

BH28

SA_MA3

BL24

SA_MA4

BK28

SA_MA5

BJ27

SA_MA6

BJ25

SA_MA7

BL28

SA_MA8

BA28

SA_MA9

BC19

SA_MA10

DDR SYSTEM MEMORRY A

DDR SYSTEM MEMORRY A

SA_RCVEN#

SA_MA11
SA_MA12
SA_MA13
SA_MA14

SA_RAS#

SA_WE#

BE28
BG30
BJ16
BJ29

BE18
AY20

BA19

Place Test PAD Near to Chip
as could as possible

M_B_DM[7..0]
M_B_DQS[7..0]
M_B_DQS#[7..0]
M_B_A[14..0]

M_B_BS#0

AY17

SB_BS0
SB_BS1
SB_BS2

SB_CAS#

SB_DM0
SB_DM1
SB_DM2
SB_DM3
SB_DM4
SB_DM5
SB_DM6
SB_DM7

SB_DQS0
SB_DQS1
SB_DQS2
SB_DQS3
SB_DQS4
SB_DQS5
SB_DQS6

SB_DQS7
SB_DQS#0
SB_DQS#1
SB_DQS#2
SB_DQS#3
SB_DQS#4
SB_DQS#5
SB_DQS#6
SB_DQS#7

SB_MA0
SB_MA1
SB_MA2
SB_MA3
SB_MA4
SB_MA5
SB_MA6
SB_MA7
SB_MA8

SB_MA9
SB_MA10
SB_MA11
SB_MA12
SB_MA13
SB_MA14

SB_RAS#

SB_RCVEN#

SB_WE#

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

M_B_BS#1

BG18

M_B_BS#2

BG36

M_B_CAS#M_A_CAS#

BE17

M_B_DM0

AR50

M_B_DM1

BD49

M_B_DM2

BK45

M_B_DM3

BL39

M_B_DM4

BH12

M_B_DM5

BJ7

M_B_DM6

BF3

M_B_DM7

AW2

M_B_DQS0

AT50

M_B_DQS1

BD50

M_B_DQS2

BK46

M_B_DQS3

BK39

M_B_DQS4

BJ12

M_B_DQS5

BL7

M_B_DQS6

BE2

M_B_DQS7

AV2

M_B_DQS#0

AU50

M_B_DQS#1

BC50

M_B_DQS#2

BL45

M_B_DQS#3

BK38

M_B_DQS#4

BK12

M_B_DQS#5

BK7

M_B_DQS#6

BF2

M_B_DQS#7

AV3

M_B_A0

BC18

M_B_A1

BG28

M_B_A2

BG25

M_B_A3

AW17

M_B_A4

BF25

M_B_A5

BE25

M_B_A6

BA29

M_B_A7

BC28

M_B_A8

AY28

M_B_A9

BD37

M_B_A10

BG17

M_B_A11

BE37

M_B_A12

BA39

M_B_A13

BG13
BE24

M_B_RAS#

AV16

SB_RCVEN#

AY18

M_B_WE#

BC17

Place Test PAD Near to Chip
ascould as possible

GMCH (3 of 5) MEMORY

GMCH (3 of 5) MEMORY

GMCH (3 of 5) MEMORY

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQ[63..0]

AP49

AR51
AW50
AW51

AN51

AN50

AV50

AV49

BA50

BB50

BA49

BE50

BA51

AY49

BF50

BF49

BJ50
BJ44
BJ43

BL43
BK47
BK49
BK43
BK42

BJ41

BL41

BJ37

BJ36
BK41

BJ40

BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12

BG12

BJ10

BL9
BK5
BL5
BK9

BK10

BJ8
BJ6

BF4
BH5
BG1
BC2
BK3
BE4
BD3

BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

5 OF 10

5 OF 10

U31E

U31E

SB_DQ0
SB_DQ1
SB_DQ2
SB_DQ3
SB_DQ4
SB_DQ5
SB_DQ6
SB_DQ7
SB_DQ8
SB_DQ9
SB_DQ10
SB_DQ11
SB_DQ12
SB_DQ13
SB_DQ14
SB_DQ15
SB_DQ16
SB_DQ17
SB_DQ18
SB_DQ19
SB_DQ20
SB_DQ21
SB_DQ22
SB_DQ23
SB_DQ24
SB_DQ25
SB_DQ26
SB_DQ27
SB_DQ28
SB_DQ29
SB_DQ30
SB_DQ31
SB_DQ32
SB_DQ33
SB_DQ34
SB_DQ35
SB_DQ36
SB_DQ37
SB_DQ38
SB_DQ39
SB_DQ40
SB_DQ41
SB_DQ42
SB_DQ43
SB_DQ44
SB_DQ45
SB_DQ46
SB_DQ47
SB_DQ48
SB_DQ49
SB_DQ50
SB_DQ51
SB_DQ52
SB_DQ53
SB_DQ54
SB_DQ55
SB_DQ56
SB_DQ57
SB_DQ58
SB_DQ59
SB_DQ60
SB_DQ61
SB_DQ62
SB_DQ63

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

M_A_DM[7..0]
M_A_DQS[7..0]
M_A_DQS#[7..0]
M_A_A[14..0]

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14 M_B_A14

M_A_RAS#
SA_RCVEN#

M_A_WE#

M_A_BS#0
M_A_BS#1
M_A_BS#2

M_A_CAS# M_B_CAS#

M_A_RAS#

1

TP17TP17

M_A_WE#

M_B_DQ[63..0]

LV1

LV1

LV1

M_B_DM[7..0]

M_B_A[14..0]

M_B_DQS[7..0]
M_B_DQS#[7..0]

M_B_BS#0
M_B_BS#1
M_B_BS#2

M_B_RAS#

1

TP2TP2

M_B_WE#

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

838Saturday, August 11, 2007

838Saturday, August 11, 2007

838Saturday, August 11, 2007

of

of

of

-1

-1

-1

VCC_NCTF + VCC=1573mA

www.laptop-schematics.com

U31F

U31F

AT35
AT34
AH28
AC32
AC31
AK32

AJ31

AJ28
AH32
AH31
AH29
AF32

R30

AU32
AU33
AU35
AV33

AW33
AW35

AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35

BJ32

BJ33

BJ34
BK32
BK33
BK34
BK35

BL33
AU30

R20

T14
W13
W14

Y12

AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31

AJ20

AN14

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

-1

12

1D05V_S0

DY

DY

C143

C143

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1573mA

3138mA

1D8V_S3

1D05V_S0

12

C124

C124

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

6 OF 10

6 OF 10

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC CORE

VCC CORE

VCC

POWER

POWER

VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM
VCC_SM

VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG
VCC_AXG

VCC SM

VCC SM

VCC GFX NCTF

VCC GFX NCTF

VCC GFX

VCC GFX

VCC SM LF

VCC SM LF

VCC_AXG_NCTF + VCC_AXG=7700mA

1D05V_S0

VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF
VCC_AXG_NCTF

VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF
VCC_SM_LF

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

AW45
BC39
BE39
BD17
BD4
AW8
AT6

12

12

SM_LF1_GMCH
SM_LF2_GMCH
SM_LF3_GMCH
SM_LF4_GMCH
SM_LF5_GMCH
SM_LF6_GMCH
SM_LF7_GMCH

C107

C107

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C169

C169

12

12

C122

C122

C357

C357

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

DY

DY

12

C114

C114

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D05V_S0

12

12

C82

C82

C83

C83

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

FOR VCC CORE AND VCC NCTF

308 mils from the Edge
Coupling CAP

DY

DY

1D05V_S0

-1

1D05V_S0

1 2

TC1 ST220U2VDM-5-GP

TC1 ST220U2VDM-5-GP

DY

DY

1 2

C206 SC10U6D3V5KX-1GP

C206 SC10U6D3V5KX-1GP

1 2

C200 SC10U6D3V5KX-1GPC200 SC10U6D3V5KX-1GP

1 2

C91 SCD1U10V2KX-5GPC91 SCD1U10V2KX-5GP

1 2

C81 SCD1U10V2KX-5GPC81 SCD1U10V2KX-5GP

1 2

C139 SCD1U10V2KX-5GP

C139 SCD1U10V2KX-5GP

DY

-1

-1

DY

1 2

C79 SCD1U10V2KX-5GP

C79 SCD1U10V2KX-5GP

DY

DY

1 2

C175 SCD1U10V2KX-5GPC175 SCD1U10V2KX-5GP

1 2

C179 SCD1U10V2KX-5GPC179 SCD1U10V2KX-5GP

1 2

C145 SCD1U10V2KX-5GPC145 SCD1U10V2KX-5GP

1 2

C131 SCD1U10V2KX-5GPC131 SCD1U10V2KX-5GP

1 2

C113 SCD1U10V2KX-5GPC113 SCD1U10V2KX-5GP

1 2

C172 SCD1U10V2KX-5GPC172 SCD1U10V2KX-5GP

VCC_AXM_NCTF + VCC_AXM=540mA

VCC_AXM_S3

G9G9

1 2

12

12

C80

C80

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

C109

C109

SCD22U10V2KX-1GP

SCD22U10V2KX-1GP

12

C182

C182

SCD47U10V3ZY-GP

SCD47U10V3ZY-GP

Place on the Edge

1 2

C152 SC10U6D3V5KX-1GPC152 SC10U6D3V5KX-1GP

1 2

C164 SCD1U10V2KX-5GPC164 SCD1U10V2KX-5GP

1 2

C142 SCD1U10V2KX-5GPC142 SCD1U10V2KX-5GP

1 2

C159 SCD1U10V2KX-5GPC159 SCD1U10V2KX-5GP

1 2

C132 SCD1U10V2KX-5GPC132 SCD1U10V2KX-5GP

1 2

C129 SCD1U10V2KX-5GP

C129 SCD1U10V2KX-5GP

DY

C181

C181

DY

12

C190

C190

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

-1

12

1D05V_S0

7 OF 10

7 OF 10

U31G

U31G

AB33

VCC_NCTF

AB36

VCC_NCTF

AB37

VCC_NCTF

AC33

VCC_NCTF

AC35

VCC_NCTF

AC36

VCC_NCTF

AD35

VCC_NCTF

AD36

VCC_NCTF

AF33

VCC_NCTF

AF36

VCC_NCTF

AH33

VCC_NCTF

AH35

VCC_NCTF

AH36

VCC_NCTF

AH37

VCC_NCTF

AJ33

VCC_NCTF

AJ35

VCC_NCTF

AK33

VCC_NCTF

AK35

VCC_NCTF

AK36

VCC_NCTF

AK37

VCC_NCTF

AD33

VCC_NCTF

AJ36

VCC_NCTF

AM35

VCC_NCTF

AL33

VCC_NCTF

AL35

VCC_NCTF

AA33

VCC_NCTF

AA35

VCC_NCTF

AA36

VCC_NCTF

AP35

VCC_NCTF

AP36

VCC_NCTF

AR35

VCC_NCTF

AR36

VCC_NCTF

Y32

VCC_NCTF

Y33

VCC_NCTF

Y35

VCC_NCTF

Y36

VCC_NCTF

Y37

VCC_NCTF

T30

VCC_NCTF

T34

VCC_NCTF

T35

VCC_NCTF

U29

VCC_NCTF

U31

VCC_NCTF

U32

VCC_NCTF

U33

VCC_NCTF

U35

VCC_NCTF

U36

VCC_NCTF

V32

VCC_NCTF

V33

VCC_NCTF

V36

VCC_NCTF

V37

VCC_NCTF

AL24

VCC_AXM_NCTF

AL26

VCC_AXM_NCTF

AL28

VCC_AXM_NCTF

AM26

VCC_AXM_NCTF

AM28

VCC_AXM_NCTF

AM29

VCC_AXM_NCTF

AM31

VCC_AXM_NCTF

AM32

VCC_AXM_NCTF

AM33

VCC_AXM_NCTF

AP29

VCC_AXM_NCTF

AP31

VCC_AXM_NCTF

AP32

VCC_AXM_NCTF

AP33

VCC_AXM_NCTF

AL29

VCC_AXM_NCTF

AL31

VCC_AXM_NCTF

AL32

VCC_AXM_NCTF

AR31

VCC_AXM_NCTF

AR32

VCC_AXM_NCTF

AR33

VCC_AXM_NCTF

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

FOR VCC SM

Place CAP where LVDS and DDR2 taps

Place on the Edge

1D8V_S3

1 2

TC3 ST220U2VDM-5-GP

TC3 ST220U2VDM-5-GP

1 2

C155 SC10U6D3V5KX-1GPC155 SC10U6D3V5KX-1GP

1 2

C176 SC10U6D3V5KX-1GPC176 SC10U6D3V5KX-1GP

1 2

C161 SCD1U10V2KX-5GPC161 SCD1U10V2KX-5GP

1 2

C162 SCD1U10V2KX-5GPC162 SCD1U10V2KX-5GP

1 2

C160 SCD1U10V2KX-5GPC160 SCD1U10V2KX-5GP

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VSS NCTF

VSS NCTF

VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF
VSS_NCTF

VCC NCTF

VCC NCTF

POWER

POWER

VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB
VSS_SCB

VSS SCBVSS AXM

VSS SCBVSS AXM

VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM
VCC_AXM

VSS AXM NCTF

VSS AXM NCTF

DY

DY

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

A3
B2
C1
BL1
BL51
A51

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

TP105TP105

1

TP102TP102

1

TP103TP103

1

TP104TP104

1

TP110TP110

1

TP109TP109

1

VCC_AXM_S3

10 OF 10

10 OF 10

U31J

U31J

C46

VSS

C50

VSS

C7

VSS

D13

VSS

D24

VSS

D3

VSS

D32

VSS

D39

VSS

D45

VSS

D49

VSS

E10

VSS

E16

VSS

E24

VSS

E28

VSS

E32

VSS

E47

VSS

F19

VSS

F36

VSS

F4

VSS

F40

VSS

F50

VSS

G1

VSS

G13

VSS

G16

VSS

G19

VSS

G24

VSS

G28

VSS

G29

VSS

G33

VSS

G42

VSS

G45

VSS

G48

VSS

G8

VSS

H24

VSS

H28

VSS

H4

VSS

H45

VSS

J11

VSS

VSS

VSS

J16

VSS

J2

VSS

J24

VSS

J28

VSS

J33

VSS

J35

VSS

J39

VSS

K12

VSS

K47

VSS

K8

VSS

L1

VSS

L17

VSS

L20

VSS

L24

VSS

L28

VSS

L3

VSS

L33

VSS

L49

VSS

M28

VSS

M42

VSS

M46

VSS

M49

VSS

M5

VSS

M50

VSS

M9

VSS

N11

VSS

N14

VSS

N17

VSS

N29

VSS

N32

VSS

N36

VSS

N39

VSS

N44

VSS

N49

VSS

N7

VSS

P19

VSS

P2

VSS

P23

VSS

P3

VSS

P50

VSS

R49

VSS

T39

VSS

T43

VSS

T47

VSS

U41

VSS

U45

VSS

U50

VSS

V2

VSS

V3

VSS

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

GMCH (4 of 5) POWER1

GMCH (4 of 5) POWER1

GMCH (4 of 5) POWER1

LV1

LV1

LV1

W11

VSS

W39

VSS

W43

VSS

W47

VSS

W5

VSS

W7

VSS

Y13

VSS

Y2

VSS

Y41

VSS

Y45

VSS

Y49

VSS

Y5

VSS

Y50

VSS

Y11

VSS

P29

VSS

T29

VSS

T31

VSS

T33

VSS

R28

VSS

AA32

VSS

AB32

VSS

AD32

VSS

AF28

VSS

AF29

VSS

AT27

VSS

AV25

VSS

H50

VSS

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

938Friday, August 10, 2007

938Friday, August 10, 2007

938Friday, August 10, 2007

of

of

of

-1

-1

-1

1D25V_S0

www.laptop-schematics.com

1D25V_S0

1D25V_S0

120ohm 100MHz

1D25V_S0

120ohm 100MHz

1D25V_S0

220ohm 100MHz

1D25V_RUN_PEGPLL_R

G13G13

1 2

G66G66

1 2

L15

L15

1 2

BLM18AG121SN-1GP

BLM18AG121SN-1GP

L14

L14

1 2

BLM18AG121SN-1GP

BLM18AG121SN-1GP

D51R3F-2-GP

D51R3F-2-GP

M_VCCA_MPLL_R

L19

L19

1 2

BLM18BB221SN1D-GP

BLM18BB221SN1D-GP

R227

R227

1R3F-GP

1R3F-GP

M_VCCA_DPLLA

12

C194

C194
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

M_VCCA_DPLLB

12

C397

C397
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

M_VCCA_HPLL

12

C346

C346
SC22U6D3V5MX-2GP

SC22U6D3V5MX-2GP

150mA

M_VCCA_MPLL

12

R204

R204

12

C341

C341
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

100mA

1D25V_RUN_PEGPLL

12

12

12

C395

C395
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

80mA

80mA

50mA

-1

C392

C392
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

12

C196

C196
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

-1

12

C393

C393
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

DY

DY

12

C350

C350
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C349

C349
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

L16

L16

1 2

BLM18PG181SN-3GP

BLM18PG181SN-3GP

180ohm 100MHz

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D5V_S0

1D5V_S0

180ohm 100MHz

1D25V_S0

1D8V_S3

1 2

3D3V_S0

0R0402-PAD

0R0402-PAD

1 2

3D3V_S0

0R0603-PAD

0R0603-PAD

1 2

3D3V_S0

0R0402-PAD

0R0402-PAD

1 2

1D8V_S3

0R0603-PAD

0R0603-PAD

1 2

3D3V_S0

0R0402-PAD

0R0402-PAD

12

C374

C374

G63G63

1 2

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

L17

L17

1 2

BLM18PG181SN-3GP

BLM18PG181SN-3GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1 2

R122

R122

1 2

0R0603-PAD

0R0603-PAD

10mA

R98

R98

12

C165

C165
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R223

R223

80mA

12

C389

C389
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R219

R219

5mA

12

C383

C383
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R121

R121

110mA

12

C184

C184

SC1KP50V2KX-1GP

SC1KP50V2KX-1GP

R226

R226

400uA

12

C394

C394
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

120mA

C369

R224

R224

1 2

0R0603-PAD

0R0603-PAD

12

C384

C384

12

12

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C369

250mA

C348

C348
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

C192

C192

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

C379

C379

G61G61

12

60mA

12

C148

C148
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

60mA

12

C387

C387
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

5mA

12

C376

C376
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

150mA

12

C186

C186
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D25V_S0

ST100U4VBM-L-GP

ST100U4VBM-L-GP

1D25V_S0

C398

C398

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

TC2

TC2

C73

C73

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

12

C147

C147

3D3V_SYNC_S0
3D3V_CRTDAC_S0

M_VCCA_DAC_BG

M_VCCA_DPLLA
M_VCCA_DPLLB
M_VCCA_HPLL
M_VCCA_MPLL

1D8V_TXLVDS_S3

3D3V_RUN_PEG_BG

1D25V_RUN_PEGPLL

12

12

C146

C146

C112

C112

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

12

C108

C108
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3VTVDAC

VCCD_CRT
1D5VRUN_TVDAC

1D5VRUN_QDAC

1D25V_SUS_MCH_PLL2

1D25V_RUN_PEGPLL
1D8V_SUS_DLVDS1D8V_SUS_DLVDS

U31H

U31H

J32

VCC_SYNC

A33

VCCA_CRT_DAC

B33

VCCA_CRT_DAC

A30

VCCA_DAC_BG

B32

VSSA_DAC_BG

B49

VCCA_DPLLA

H49

VCCA_DPLLB

AL2

VCCA_HPLL

AM2

VCCA_MPLL

A41

VCCA_LVDS

B41

VSSA_LVDS

K50

VCCA_PEG_BG

K49

VSSA_PEG_BG

U51

VCCA_PEG_PLL

AW18

VCCA_SM

AV19

VCCA_SM

AU19

VCCA_SM

AU18

VCCA_SM

AU17

VCCA_SM

AT22

VCCA_SM

AT21

VCCA_SM

AT19

VCCA_SM

AT18

VCCA_SM

AT17

VCCA_SM

AR17

VCCA_SM_NCTF

AR16

VCCA_SM_NCTF

BC29

VCCA_SM_CK

BB29

VCCA_SM_CK

C25

VCCA_TVA_DAC

B25

VCCA_TVA_DAC

C27

VCCA_TVB_DAC

B27

VCCA_TVB_DAC

B28

VCCA_TVC_DAC

A28

VCCA_TVC_DAC

M32

VCCD_CRT

L29

VCCD_TVDAC

N28

VCCD_QDAC

AN2

VCCD_HPLL

U48

VCCD_PEG_PLL

J41

VCCD_LVDS

H42

VCCD_LVDS

CRESTLINE-GP-U-NF

CRESTLINE-GP-U-NF

8 OF 10

8 OF 10

POWER

POWER

A LVDS PLL CRT

A LVDS PLL CRT

AXD

AXD

VCC_AXD_NCTF

A PEG

A PEG

SM CK

SM CK

TV A CK A SM

TV A CK A SM

DMI

DMI

LVDS TV/CRT

LVDS TV/CRT

1D05V_S0

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VTT

VTT

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD
VCC_AXD

VCC_AXF
VCC_AXF

AXF

AXF

VCC_AXF

VCC_DMI

VCC_SM_CK
VCC_SM_CK
VCC_SM_CK
VCC_SM_CK

VCC_TX_LVDS

VCC_HV

HV

HV

VCC_HV

VCC_PEG
VCC_PEG
VCC_PEG

PEG

PEG

VCC_PEG
VCC_PEG

VCC_RXR_DMI
VCC_RXR_DMI

VTTLF
VTTLF
VTTLF

VTTLF

VTTLF

D8

D8

SS0530-GP

SS0530-GP

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

AT23
AU28
AU24
AT29
AT25
AT30

AR29

B23
B21
A21

AJ50

BK24
BK23
BJ24
BJ23

A43

C40
B40

AD51
W50
W51
V49
V50

AH50
AH51

A7
F2
AH1

1D05V_HV_S0

KA

Place on the edge

850mA

12

1D25V_SUS_AXD

12

SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

1D8V_SUS_SM_CK

12

1D8V_TXLVDS_S3

3D3V_HV_S0

1200mA

250mA

VTTLF1
VTTLF2
VTTLF3

12

C351

C351

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

-1

DY

DY

12

12

C345

C345

C95

C95

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

C133

C133

12

C365

C365
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

1 2

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

C344

C344

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

SC4D7U6D3V3KX-GP

G8G8

1 2

12

C149

C149
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

C366

C366
SC1U6D3V2KX-GP

SC1U6D3V2KX-GP

C217

C217
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

12

C353

C353

C347

C347

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

3D3V_S0

R129

R129

10R3J-3-GP

10R3J-3-GP

GMCH (5 of 5) POWER2

GMCH (5 of 5) POWER2

GMCH (5 of 5) POWER2

12

C126

C126

SC2D2U6D3V3MX-1-GP

SC2D2U6D3V3MX-1-GP

1D25V_S0

12

C363

C363
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

12

C361

C361

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

-1

DY

DY

12

C342

C342

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

G10G10

1 2

LV1

LV1

LV1

12

C118

C118

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

R214

R214

1 2

0R0603-PAD

0R0603-PAD

12

R215

R215
1R3F-GP

1R3F-GP

1D8V_SUS_SM_CK1

12

C358

C358
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D05V_S0

C207

C207
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D05V_S0

C343

C343

SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

12

12

C177

C177

SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

1D25V_S0

12

C360

C360
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

1D8V_S3

100mA

3D3V_HV_S0

12

C180

C180
SCD1U10V2KX-5GP

SCD1U10V2KX-5GP

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

1D05V_S0

C167

C167
SC10U6D3V5KX-1GP

SC10U6D3V5KX-1GP

10 38Friday, August 10, 2007

10 38Friday, August 10, 2007

10 38Friday, August 10, 2007

of

of

of

-1

-1

-1

A

www.laptop-schematics.com

B

C

D

E

M_A_DQ[63..0]
M_A_A[14..0]
M_A_DM[7..0]
M_A_DQS#[7..0]
M_A_DQS[7..0]

4 4

M_A_BS#2
M_A_BS#0

M_A_BS#1

3 3

2 2

M_ODT0

C417

C417

M_ODT1

12

12

DDR_VREF_S3

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

1 1

M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14

M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63

M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7

M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7

C416

C416
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

A

U30

U30

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

/DQS0

29

/DQS1

49

/DQS2

68

/DQS3

129

/DQS4

146

/DQS5

167

/DQS6

186

/DQS7

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

ODT0

119

ODT1

1

VREF

2

VSS

202

GND

DDR2-200P-11-GP-U

DDR2-200P-11-GP-U

62.10017.891

62.10017.891

108

/RAS

109

/WE

113

/CAS

110

/CS0

115

/CS1

79

CKE0

80

CKE1

M_CLK_DDR0

30

CK0

M_CLK_DDR#0

32

/CK0

M_CLK_DDR1

164

CK1

M_CLK_DDR#1

166

/CK1

M_A_DM0

10

DM0

M_A_DM1

26

DM1

M_A_DM2

52

DM2

M_A_DM3

67

DM3

M_A_DM4

130

DM4

M_A_DM5

147

DM5

M_A_DM6

170

DM6

M_A_DM7

185

DM7

SMBDAT_ICH

195

SDA

SMBCLK_ICH

197

SCL

199

VDDSPD

NC#120

NC#163/TEST

Reverse Type Height = 5.2mm

NC#50
NC#69
NC#83

GND

DIMM0_SA0

198

SA0

DIMM0_SA1

200

SA1

50
69
83
120
163

81

VDD

82

VDD

87

VDD

88

VDD

95

VDD

96

VDD

103

VDD

104

VDD

111

VDD

112

VDD

117

VDD

118

VDD

3

VSS

8

VSS

9

VSS

12

VSS

15

VSS

18

VSS

21

VSS

24

VSS

27

VSS

28

VSS

33

VSS

34

VSS

39

VSS

40

VSS

41

VSS

42

VSS

47

VSS

48

VSS

53

VSS

54

VSS

59

VSS

60

VSS

65

VSS

66

VSS

71

VSS

72

VSS

77

VSS

78

VSS

121

VSS

122

VSS

127

VSS

128

VSS

132

VSS

133

VSS

138

VSS

139

VSS

144

VSS

145

VSS

149

VSS

150

VSS

155

VSS

156

VSS

161

VSS

162

VSS

165

VSS

168

VSS

171

VSS

172

VSS

177

VSS

178

VSS

183

VSS

184

VSS

187

VSS

190

VSS

193

VSS

196

VSS

201

M_A_RAS#
M_A_WE#
M_A_CAS#

M_CS#0
M_CS#1

M_CKE0
M_CKE1

M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR1
M_CLK_DDR#1

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

1D8V_S3

B

SMBDAT_ICH
SMBCLK_ICH

C56

C56

Place close DIMM0

12

12

12

3D3V_S0

12

C55

C55
SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

M_CLK_DDR0

C219

C219
SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

DY

M_CLK_DDR#0
M_CLK_DDR1

C77

C77
SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

DY

M_CLK_DDR#1

M_B_DQ[63..0]
M_B_A[14..0]
M_B_DM[7..0]
M_B_DQS#[7..0]
M_B_DQS[7..0]

DDR_VREF_S3

C241

C241

SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

M_B_BS#2
M_B_BS#0

M_B_BS#1

M_ODT2
M_ODT3

12

C

12

C238

C238
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DIMM1DIMM0

U29

M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14

M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63

M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7

M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7

U29

102

A0

101

A1

100

A2

99

A3

98

A4

97

A5

94

A6

92

A7

93

A8

91

A9

105

A10/AP

90

A11

89

A12

116

A13

86

A14

84

A15

85

A16/BA2

107

BA0

106

BA1

5

DQ0

7

DQ1

17

DQ2

19

DQ3

4

DQ4

6

DQ5

14

DQ6

16

DQ7

23

DQ8

25

DQ9

35

DQ10

37

DQ11

20

DQ12

22

DQ13

36

DQ14

38

DQ15

43

DQ16

45

DQ17

55

DQ18

57

DQ19

44

DQ20

46

DQ21

56

DQ22

58

DQ23

61

DQ24

63

DQ25

73

DQ26

75

DQ27

62

DQ28

64

DQ29

74

DQ30

76

DQ31

123

DQ32

125

DQ33

135

DQ34

137

DQ35

124

DQ36

126

DQ37

134

DQ38

136

DQ39

141

DQ40

143

DQ41

151

DQ42

153

DQ43

140

DQ44

142

DQ45

152

DQ46

154

DQ47

157

DQ48

159

DQ49

173

DQ50

175

DQ51

158

DQ52

160

DQ53

174

DQ54

176

DQ55

179

DQ56

181

DQ57

189

DQ58

191

DQ59

180

DQ60

182

DQ61

192

DQ62

194

DQ63

11

DQS0#

29

DQS1#

49

DQS2#

68

DQS3#

129

DQS4#

146

DQS5#

167

DQS6#

186

DQS7#

13

DQS0

31

DQS1

51

DQS2

70

DQS3

131

DQS4

148

DQS5

169

DQS6

188

DQS7

114

OTD0

119

OTD1

1

VREF

2

VSS

202

GND

MH1

MH1

DDR2-200P-23-GP-U1

DDR2-200P-23-GP-U1

62.10017.A71

62.10017.A71

BOM USE 62.10017.B51

DIMM0 DIMM1

Reverse Connector

1

2

3

4

5

6

108

RAS#

109

WE#

113

CAS#

110

CS0#

115

CS1#

79

CKE0

80

CKE1

M_CLK_DDR2

30

CK0

M_CLK_DDR#2

32

CK0#

M_CLK_DDR3

164

CK1

M_CLK_DDR#3

166

CK1#

M_B_DM0

10

DM0

M_B_DM1

26

DM1

M_B_DM2

52

DM2

M_B_DM3

67

DM3

M_B_DM4

130

DM4

M_B_DM5

147

DM5

M_B_DM6

170

DM6

M_B_DM7

185

DM7

SMBDAT_ICH

195

SDA

SMBCLK_ICH

197

SCL

199

VDDSPD

NC#120

NC#163/TEST

Reverse Type Height = 9.2mm

NC#50
NC#69
NC#83

GND

DIMM1_SA0

198

SA0

DIMM1_SA1

200

SA1

50
69
83
120
163

81

VDD

82

VDD

87

VDD

88

VDD

95

VDD

96

VDD

103

VDD

104

VDD

111

VDD

112

VDD

117

VDD

118

VDD

3

VSS

8

VSS

9

VSS

12

VSS

15

VSS

18

VSS

21

VSS

24

VSS

27

VSS

28

VSS

33

VSS

34

VSS

39

VSS

40

VSS

41

VSS

42

VSS

47

VSS

48

VSS

53

VSS

54

VSS

59

VSS

60

VSS

65

VSS

66

VSS

71

VSS

72

VSS

77

VSS

78

VSS

121

VSS

122

VSS

127

VSS

128

VSS

132

VSS

133

VSS

138

VSS

139

VSS

144

VSS

145

VSS

149

VSS

150

VSS

155

VSS

156

VSS

161

VSS

162

VSS

165

VSS

168

VSS

171

VSS

172

VSS

177

VSS

178

VSS

183

VSS

184

VSS

187

VSS

190

VSS

193

VSS

196

VSS

201
MH2

MH2

TPAD79K5TPAD79
K5

1D8V_S3

TPAD79K4TPAD79
K4

1

1

M_B_RAS#
M_B_WE#
M_B_CAS#

M_CS#2
M_CS#3

M_CKE2
M_CKE3

M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR3
M_CLK_DDR#3

TPAD79K2TPAD79
K2

1

SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

TPAD79K1TPAD79
K1

1

12

C53

C53

3D3V_S0

DIMM1_SA1
DIMM1_SA0

Place close DIMM1

M_CLK_DDR2

12

C210

C210
SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

DY

M_CLK_DDR#2
M_CLK_DDR3

12

C76

C76
SC10P50V2JN-4GP

SC10P50V2JN-4GP

DY

DY

M_CLK_DDR#3

1D8V_S3

R231

R231

1KR2F-3-GP

1KR2F-3-GP

DY

DY

R230

R230

1KR2F-3-GP

1KR2F-3-GP

DY

DY

7

8

9

10

11

12
14

13
15

16

17

18

19

20

21

22

23

24

25

26

27

28
29
31

30

32
33

2

34
35

36
37

38
39

40

41

42
43

44
45

46
47

48
49

50
51

52
53

54
55

56
57

58
59

60
61

62
63

64
65

66
67

68
69

70
71

72

CON_SODIMM200_RVS_V1

73

74
75

76
77

78
79

80
81

82
83

84
85

86
87

88
89

90
91

92

93

94
95

96
97

98
99

100
101

102
103

104
105

106
107

108
109

110
111

112
113

114
115

116
117

118
119

120
121

122
123

124
125

126
127
129

128

130
131

132
133

134
135

136
137

138
139

140
141

142
143

144

146

145
147

148
149

150
151

152
153

154
155

156
157

158
159

160
161

162
163

164

165

166
167

168
169

170
171

172
173

174
175

176
177

178
179

200

180
181
183

182

184
185

186
187

188
189

190
191

192
193

194
195

196
197

198
199

200

Height = 5.2mm Height = 9.2mm

3D3V_S0

12

C57

C57
SC2D2U6D3V3KX-GP

SC2D2U6D3V3KX-GP

12

R41

R41
10KR2J-3-GP

10KR2J-3-GP

DDR_VREF

12

12

C400

C400
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

12

12

C399

C399
SCD1U16V2ZY-2GP

SCD1U16V2ZY-2GP

DY

DY

LAYOUT: Locate close to DIMM

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

C

C

C

DDR2_SOCKET

DDR2_SOCKET

DDR2_SOCKET

Reverse Connector

1

200

199

DDR_VREF_S3

LV1

LV1

LV1

E

1

2

3

4

5

6

7

8

9

10

11

12
14

13
15

16

17

18

19

20

21

22

23

24

25

26

27

28
29
31

30

32
33

2

34
35

36
37

38
39

40

41

42
43

44
45

46
47

48
49

50
51

52
53

54
55

56
57

58
59

60
61

62
63

64
65

66
67

68
69

70
71

72

CON_SODIMM200_RVS_V1

73

74
75

76
77

78
79

80
81

82
83

84
85

86
87

88
89

90
91

92

93

94
95

96
97

98
99

100
101

102
103

104
105

106
107

108
109

110
111

112
113

114
115

116
117

118
119

120
121

122
123

124
125

126
127
129

128

130
131

132
133

134
135

136
137

138
139

140
141

142
143

144

146

145
147

148
149

150
151

152
153

154
155

156
157

158
159

160
161

162
163

164

165

166
167

168
169

170
171

172
173

174
175

176
177

178
179

180
181
183

182

184
185

186
187

188
189

190
191

192
193

194
195

196
197

198
199

200

TPAD79K3TPAD79
K3

1

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

11 38Saturday, August 11, 2007

11 38Saturday, August 11, 2007

11 38Saturday, August 11, 2007

1

199

of

of

of

-1

-1

-1

5

A

www.laptop-schematics.com

M_A_A[14..0]
M_B_A[14..0]

Put decap near power(0.9V) and pull-up resistor

DDR_VREF_S0

D D

C C

B B

RN12

RN12

1

8

2

7
6

R77 56R2J-4-GPR77 56R2J-4-GP

1 2

R73 56R2J-4-GPR73 56R2J-4-GP

1 2

R89 56R2J-4-GPR89 56R2J-4-GP

1 2

R83 56R2J-4-GPR83 56R2J-4-GP

1 2

R101 56R2J-4-GPR101 56R2J-4-GP

1 2

R102 56R2J-4-GPR102 56R2J-4-GP

1 2

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

8
7
6

SRN56J-5-GP

SRN56J-5-GP

RN8

RN8

SRN56J-5-GP

SRN56J-5-GP

RN1

RN1

SRN56J-5-GP

SRN56J-5-GP

RN6

RN6

SRN56J-5-GP

SRN56J-5-GP

RN11

RN11

SRN56J-5-GP

SRN56J-5-GP

RN3

RN3

SRN56J-5-GP

SRN56J-5-GP

RN2

RN2

SRN56J-5-GP

SRN56J-5-GP

RN5

RN5

SRN56J-5-GP

SRN56J-5-GP

RN4

RN4

SRN56J-5-GP

SRN56J-5-GP

RN10

RN10

SRN56J-5-GP

SRN56J-5-GP

RN9

RN9

SRN56J-5-GP

SRN56J-5-GP

RN7

RN7

SRN56J-5-GP

SRN56J-5-GP

3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

1
2
3
45

M_B_A12
M_B_A9

M_B_A8
M_B_A5
M_B_A1
M_B_A3

M_B_A13

M_B_A0
M_B_A2
M_B_A4

M_B_A6
M_B_A7
M_B_A11

M_A_A13

M_A_A0
M_A_A2
M_A_A4

M_A_A12
M_A_A9

M_A_A6
M_A_A7
M_A_A11

M_A_A5
M_A_A3
M_A_A1
M_A_A10

M_CKE2
M_B_BS#2

M_A_A8
M_B_A10
M_A_A14
M_B_A14

M_ODT2
M_CS#2

M_B_RAS#

M_B_BS#1

M_CKE3

M_B_BS#0

M_B_WE#

M_B_CAS#

M_CS#3

M_ODT0
M_CS#0

M_A_RAS#

M_A_BS#1

M_A_BS#0

M_A_WE#

M_A_CAS#

M_ODT1

M_CKE0
M_A_BS#2

M_CKE1

M_CS#1
M_ODT3

5

4

3

2

1

Decoupling Capacitor

Put decap near power(0.9V) and pull-up resistor

DDR_VREF_S0 DDR_VREF_S0

1 2

DY

DY

C173 SCD1U16V2ZY-2GP

C173 SCD1U16V2ZY-2GP

1 2

DY

DY

C88 SCD1U16V2ZY-2GP

C88 SCD1U16V2ZY-2GP

1 2

DY

DY

C135 SCD1U16V2ZY-2GP

C135 SCD1U16V2ZY-2GP

-1 -1

1 2

C158 SCD1U16V2ZY-2GPC158 SCD1U16V2ZY-2GP

1 2

DY

DY

C137 SCD1U16V2ZY-2GP

C137 SCD1U16V2ZY-2GP

-1

1 2

C157 SCD1U16V2ZY-2GPC157 SCD1U16V2ZY-2GP

1 2

C174 SCD1U16V2ZY-2GPC174 SCD1U16V2ZY-2GP

1 2

DY

DY

C151 SCD1U16V2ZY-2GP

C151 SCD1U16V2ZY-2GP

-1

1 2

C99 SCD1U16V2ZY-2GPC99 SCD1U16V2ZY-2GP

1 2

C98 SCD1U16V2ZY-2GPC98 SCD1U16V2ZY-2GP

1 2

C136 SCD1U16V2ZY-2GPC136 SCD1U16V2ZY-2GP

1 2

DY

DY

C110 SCD1U16V2ZY-2GP

C110 SCD1U16V2ZY-2GP

1 2

C104 SCD1U16V2ZY-2GPC104 SCD1U16V2ZY-2GP

1 2

C163 SCD1U16V2ZY-2GPC163 SCD1U16V2ZY-2GP

1 2

C138 SCD1U16V2ZY-2GPC138 SCD1U16V2ZY-2GP

1 2

C121 SCD1U16V2ZY-2GPC121 SCD1U16V2ZY-2GP

1 2

C170 SCD1U16V2ZY-2GPC170 SCD1U16V2ZY-2GP

Place these Caps near DM1 Place these Caps near DM2

1D8V_S31D8V_S3

1 2

C140 SCD1U16V2ZY-2GPC140 SCD1U16V2ZY-2GP

1 2

C362 SCD1U16V2ZY-2GPC362 SCD1U16V2ZY-2GP

1 2

C96 SCD1U16V2ZY-2GPC96 SCD1U16V2ZY-2GP

1 2

C368 SCD1U16V2ZY-2GPC368 SCD1U16V2ZY-2GP

1 2

C354 SC2D2U6D3V3MX-1-GPC354 SC2D2U6D3V3MX-1-GP

1 2

C185 SC2D2U6D3V3MX-1-GPC185 SC2D2U6D3V3MX-1-GP

1 2

C388 SC2D2U6D3V3MX-1-GPC388 SC2D2U6D3V3MX-1-GP

1 2

C364 SC2D2U6D3V3MX-1-GPC364 SC2D2U6D3V3MX-1-GP

1 2

DY

DY

C373 SC2D2U6D3V3MX-1-GP

C373 SC2D2U6D3V3MX-1-GP

-1 -1

4

3

1 2

C166 SCD1U16V2ZY-2GPC166 SCD1U16V2ZY-2GP

1 2

C125 SCD1U16V2ZY-2GPC125 SCD1U16V2ZY-2GP

1 2

C156 SCD1U16V2ZY-2GPC156 SCD1U16V2ZY-2GP

1 2

C380 SCD1U16V2ZY-2GPC380 SCD1U16V2ZY-2GP

1 2

C127 SC2D2U6D3V3MX-1-GPC127 SC2D2U6D3V3MX-1-GP

1 2

C355 SC2D2U6D3V3MX-1-GPC355 SC2D2U6D3V3MX-1-GP

1 2

DY

DY

C193 SC2D2U6D3V3MX-1-GP

C193 SC2D2U6D3V3MX-1-GP

-1

1 2

C382 SC2D2U6D3V3MX-1-GPC382 SC2D2U6D3V3MX-1-GP

1 2

DY

DY

C359 SC2D2U6D3V3MX-1-GP

C359 SC2D2U6D3V3MX-1-GP

2

ZZZ

ZZZ

ZZZ

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

A3

A3

A3

Date: Sheet

Date: Sheet

Date: Sheet

DDR_VREF_S0

1 2

C123 SCD1U16V2ZY-2GPC123 SCD1U16V2ZY-2GP

1 2

C171 SCD1U16V2ZY-2GPC171 SCD1U16V2ZY-2GP

1 2

DY

DY

C111 SCD1U16V2ZY-2GP

C111 SCD1U16V2ZY-2GP

1 2

C144 SCD1U16V2ZY-2GPC144 SCD1U16V2ZY-2GP

1 2

DY

DY

C130 SCD1U16V2ZY-2GP

C130 SCD1U16V2ZY-2GP

-1

1 2

C168 SCD1U16V2ZY-2GPC168 SCD1U16V2ZY-2GP

1 2

DY

DY

C102 SCD1U16V2ZY-2GP

C102 SCD1U16V2ZY-2GP

-1

1 2

DY

DY

C115 SCD1U16V2ZY-2GP

C115 SCD1U16V2ZY-2GP

1 2

DY

DY

C101 SCD1U16V2ZY-2GP

C101 SCD1U16V2ZY-2GP

Wistron Incorporated

Wistron Incorporated

Wistron Incorporated

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd

21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei

Hsichih, Taipei

Hsichih, Taipei

DRAM_TERMINATION

DRAM_TERMINATION

DRAM_TERMINATION

LV1

LV1

LV1

12 38Saturday, August 11, 2007

12 38Saturday, August 11, 2007

12 38Saturday, August 11, 2007

1

A

-1

-1

-1

of

of

of