Fujitsu-Siemens LA-1481, Amilo A6600, Amilo A7600 Schematic

A

4 4

B

C

D

E

Confidential

3 3

Schematics
Document

Mobile AMD Athlon XP with ATI
MOBILITY-U1 /ALI 1535+ core logic chip

2 2

2002-08-12

REV: 0.5

1 1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

COVER SHEET

LA-1481 M/B

!"#, $%

14, 2002

147

E

0.5

of

A

File Name : LA-1481 M/B

CPU Bypass &

Fan Control

4 4

page 4

CPUFID/VID

TV-OUT Conn

B

page 5,32,33

CRT Conn

page 14

page 14

C

Mobile AMD AthlonXP

Model-8 OPGA
CPU SOCKET

page 3,4

System Bus

400MHz

HD#(0..63)HA#(3..31)

ATI MOBILITY-U1

596 Graphics embedded

BGA

page6,7,8,9,10

Thermal Sensor

NE1617 ICS951403

Memory
BUS(DDR)

2.5V DDR 200/266 MHz

D

Clock Generator

page 3

DDR-SO - D IMM X 2

BANK 0, 1, 2, 3

E

Block Diagram

page 13

page 11,12

LCD Conn

page 15

IDSEL:AD16
(PIRQC#,GNT#0,REQ#0)

3 3

IEEE 1394
VT6306

page 21

Mini PCI
port

page 25

IDSEL:AD31
(PIRQB#,GNT#1,REQ#1)

RJ11
Conn.&Jack

page 25

PCI BUS

IDSEL:AD17
(PIRQC#,GNT#3,REQ#3)

LAN CTRL

RTL 8100BL

page 20

2 2

RJ45 Jack

page 25

Power On/Off
Reset & RTC

page 26,30,18

DC/DC Interface

IDSEL:AD20
(PIRQA/B#,GNT#2,REQ#2)

CardBus Controller

ENE CB1420

Slot 1

page 23

14M_5V

EC NS87591L

Touch Pad

page 24

page 27

Suspend

page 31

1 1

Power Circuit DC/DC

page 34,35,36,37,38,39

A

EC I/O Buffer

page 28

BIOS

page 28 page 30

B

3.3V 33MHz

page 22

Slot 0

page 23

S/W BD conn

Int.KBD

page 26

page 26

PS/2 conn

AC-LINK

+5VALW

USB

Port 2

page 29

LPC BUS

3.3V 33MHz

ALI 1535+

page 16,17

3.3V 48MHz

+5VALW

Port 0,1

page 29

3.3V 24.576MHz

3.3V ATA100

USB

SERIALPARALLEL

page 29 page 29

FDD

page 26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

D

AC-LINK
CONN

page 24

HDD IDE
Connector

page 19

CDROM IDE
Connector

page 19

Compal Electronics, Inc.

Title

Block Diagram

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

247

E

of

0.3

A

SDATA#[0..63]6

4 4

3 3

SDATAINVAL#

C517
@20PF

1 2

Just for A-TEST

2 2

SDATAINVAL#6

+CPU_CORE

R35 820

1 2

R36 820

1 2

1 1

CLKFWDRST6

CONNECT6

PROCRDY6

SDATA#0
SDATA#1
SDATA#2
SDATA#3
SDATA#4
SDATA#5
SDATA#6
SDATA#7
SDATA#8
SDATA#9
SDATA#10
SDATA#11
SDATA#12
SDATA#13
SDATA#14
SDATA#15
SDATA#16
SDATA#17
SDATA#18
SDATA#19
SDATA#20
SDATA#21
SDATA#22
SDATA#23
SDATA#24
SDATA#25
SDATA#26
SDATA#27
SDATA#28
SDATA#29
SDATA#30
SDATA#31
SDATA#32
SDATA#33
SDATA#34
SDATA#35
SDATA#36
SDATA#37
SDATA#38
SDATA#39
SDATA#40
SDATA#41
SDATA#42
SDATA#43
SDATA#44
SDATA#45
SDATA#46
SDATA#47
SDATA#48
SDATA#49
SDATA#50
SDATA#51
SDATA#52
SDATA#53
SDATA#54
SDATA#55
SDATA#56
SDATA#57
SDATA#58
SDATA#59
SDATA#60
SDATA#61
SDATA#62
SDATA#63

SDATAIN_CLK#0
SDATAIN_CLK#1
SDATAIN_CLK#2
SDATAIN_CLK#3

SDATAINVAL#
SDATAOUTCLK#0

SDATAOUTCLK#1
SDATAOUTCLK#2
SDATAOUTCLK#3

DOVAL#
SADDIN#0

SADDIN#1
SADDIN#2
SADDIN#3
SADDIN#4
SADDIN#5
SADDIN#6
SADDIN#7
SADDIN#8
SADDIN#9
SADDIN#10
SADDIN#11
SADDIN#12
SADDIN#13
SADDIN#14

SADDIN_CLK#

CONNECT
PROCRDY
FILVAL#

A

SADDIN#[2..14]6

SDATAOUTCLK#[0..3]6

U27A

AA35

SDATA0

W37

SDATA1

W35

SDATA2

Y35

SDATA3

U35

SDATA4

U33

SDATA5

S37

SDATA6

S33

SDATA7

AA33

SDATA8

AE37

SDATA9

AC33

SDATA10

AC37

SDATA11

Y37

SDATA12

AA37

SDATA13

AC35

SDATA14

S35

SDATA15

Q37

SDATA16

Q35

SDATA17

N37

SDATA18

J33

SDATA19

G33

SDATA20

G37

SDATA21

E37

SDATA22

G35

SDATA23

Q33

SDATA24

N33

SDATA25

L33

SDATA26

N35

SDATA27

L37

SDATA28

J37

SDATA29

A37

SDATA30

E35

SDATA31

E31

SDATA32

E29

SDATA33

A27

SDATA34

A25

SDATA35

E21

SDATA36

C23

SDATA37

C27

SDATA38

A23

SDATA39

A35

SDATA40

C35

SDATA41

C33

SDATA42

C31

SDATA43

A29

SDATA44

C29

SDATA45

E23

SDATA46

C25

SDATA47

E17

SDATA48

E13

SDATA49

E11

SDATA50

C15

SDATA51

E9

SDATA52

A13

SDATA53

C9

SDATA54

A9

SDATA55

C21

SDATA56

A21

SDATA57

E19

SDATA58

C19

SDATA59

C17

SDATA60

A11

SDATA61

A17

SDATA62

A15

SDATA63

W33

SDATAINCLK0

J35

SDATAINCLK1

E27

SDATAINCLK2

E15

SDATAINCLK3

AN33

SDATAINVAL

AE35

SDATAOUTCLK0

C37

SDATAOUTCLK1

A33

SDATAOUTCLK2

C11

SDATAOUTCLK3

AL31

SDTATOUTVAL

AJ29

SADDIN0

AL29

SADDIN1

AG33

SADDIN2

AJ37

SADDIN3

AL35

SADDIN4

AE33

SADDIN5

AJ35

SADDIN6

AG37

SADDIN7

AL33

SADDIN8

AN37

SADDIN9

AL37

SADDIN10

AG35

SADDIN11

AN29

SADDIN12

AN35

SADDIN13

AN31

SADDIN14

AJ33

SADDINCLK

AJ21

CLKFWDRST

AL23

CONNECT

AN23

PROCRDY

AJ31

SFILLVAL

CPU_SOCKET_OPGA_462

SADDIN#[2..14]
SDATAOUTCLK#[0..3]

B

A20M#

AE1

A20M
FERR

INIT

INTR

IGNNE

NMI

RESET

SMI

STPCLK
PWROK

PICCLK
PICD0/BYPASSCLK
PICD1/BYPASSCLK

COREFB-

COREFB+

CLKIN
CLKIN

RSTCLK
RSTCLK

K7CLKOUT
K7CLKOUT

ANALOG

SYSVREFMODE

VREF_SYS

ZN
ZP

PLLBYPASS
PLLBYPASSCLK
PLLBYPASSCLK

PLLMON1
PLLMON2

PLLTEST

SCANCLK1
SCANCLK2

SCANINTEVAL

SCANSHIFTEN

DBRDY
DBREQ

FLUSH

TCK

TDI
TDO
TMS

TRST

VID0
VID1
VID2
VID3
VID4

FID0
FID1
FID2
FID3

SCHECK0
SCHECK1
SCHECK2
SCHECK3
SCHECK4
SCHECK5
SCHECK6
SCHECK7

SADDOUT0
SADDOUT1
SADDOUT2
SADDOUT3
SADDOUT4
SADDOUT5
SADDOUT6
SADDOUT7
SADDOUT8

SADDOUT9
SADDOUT10
SADDOUT11
SADDOUT12
SADDOUT13
SADDOUT14

SADDOUTCLK

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

AG1
AJ3
AL1
AJ1
AN3
AG3
AN5
AC1

AE3

N1
N3
N5

AG13
AG11

AN17
AL17

AN19
AL19

AL21
AN21

AJ13
AA5

W5
AC5

AE5
AJ25

AN15
AL15

AN13
AL13
AC3

S1
S5
S3
Q5

AA1
AA3
AL3

Q1
U1
U5
Q3
U3

L1
L3
L5
L7
J7

W1
W3
Y1
Y3

U37
Y33
L35
E33
E25
A31
C13
A19

J1
J3
C7
A7
E5
A5
E7
C1
C5
C3
G1
E1
A3
G5
G3

E3

FERR
INIT#
INTR
IGNNE#
NMI
CPURST#
SMI#
STPCLK#

APICCLK0
APICD0
APICD1

COREFB­COREFB+

CPUCK
CPUCK#

CLKOUT
CLKOUT#

VREFMODE
VREF_SYS

ZN
ZP

PLLBP#
PLLCLK
PLLCLK#

PLLMON1
PLLMON2
PLLTEST#

SCANCLK1
SCANCLK2
SINTVAL
SSHIFTEN

DBREQ#
FLUSH#

TCK
TDI

TMS
TRST#

PVID0
PVID1
PVID2
PVID3
PVID4

FID0
FID1
FID2
FID3

SADDOUT#0
SADDOUT#1
SADDOUT#2
SADDOUT#3
SADDOUT#4
SADDOUT#5
SADDOUT#6
SADDOUT#7
SADDOUT#8
SADDOUT#9
SADDOUT#10
SADDOUT#11
SADDOUT#12
SADDOUT#13
SADDOUT#14

SADDOUTCLK#

COREFB­COREFB+

R129

100_1%

15mil
15mil

100_1%

A20M# 16
INIT# 16

INTR 16
IGNNE# 16
NMI 16
CPURST# 6,16
SMI# 16
STPCLK# 16

CPU_PWROK 30

+CPU_CORE

R131
100_1%

R130

R132
100_1%

PVID[0..4] 33

FID[0..3] 32

SADDOUT#[2..14]

SADDOUTCLK# 6

C

Near socket-A

COREFB+
COREFB-

AMD RECOMEND

+CPU_CORE

R187
510

FERR

R530 75

APICCLK0
APICD0
APICD1

0.047UF_0603

VREF_SYS

close to CPU socket

@1UF_0603

THERMDA4

THERMDC4

SADDOUT#[2..14] 6

SDATAINCLK#[0..3]6

SADDINCLK#6

Place these component near middle of
trace.

C

+CPU_CORE

R157 10K
R151 10K

+3VS

R451
510

Q17

2

MMBT2222A

3 1

R190

R450

1K

1K

+CPU_CORE

12

C518

VREF_SYS is set at 50%
of VCC_CORE to CPU

12

C519

10 Miles

10 Miles

C149

0.047UF

ZN
ZP

Change Value by tunning
close to CPU socket

C377 0.1UF

C385
2200PF

1 2

+3VS

AMD recommend

SDATAINCLK#0
SDATAINCLK#1 SDATAIN_CLK#1
SDATAINCLK#2
SDATAINCLK#3
SADDINCLK# SADDIN_CLK#

R140
1K

15mil

FERR#

15mil

12

R192 40.2_1%_0603
R191 40.2_1%_0603

12

R422

1 2

1K

FERR# 16

+CPU_CORE

SMI#

C528

@560PF

Reduce NMI
noise for
C3

+CPU_CORE

12

C147
@0.1UF

+CPU_CORE

R552 150

1 2

15mil

U26

1

NC

2

VCC

3

DXP

4

DXN

5

NC

6

ADD1

7

GND

8 9

GND NC

NE1617DS

RESERVE FOR MOBILE K7

10nH

L23 NL252018T-010J
L27 NL252018T-010J
L32 NL252018T-010J
L35 NL252018T-010J
L20 0_0805

C40
@5PF

D

NMI

Reduce NMI
noise for
C3

R441

60.4_1%

R442

60.4_1%

SMBCLK

SMBDATA

C46

12

C57

D

+CPU_CORE +CPU_CORE

A20M#
IGNNE#

INIT#

DBREQ#
TCK
TMS
TDI
TRST#
PLLTEST#
FLUSH#
PLLBP#

C145

@560PF

RP24

1
2
3
4
5

10P8R_820

AMD recomend

R146 820
R448 820
R449 820
R185 820
R443 820
R445 820
R173 820
R75 820

10
9
8
7
6

INTRCPURST#
NMI
SMI#
STPCLK#

Near socket-A U1

CPUCK
CPUCK#

+CPU_CORE

R446

VREFMODE

close to CPU socket

@1K

15mil

R447
@1.5K

VREFMODE=Low=No voltage scaling

+3VS

15mil

12

R419
10K

12

12

R421
10K

+3VS

L24 NL252018T-010J
L28 NL252018T-010J
L33 NL252018T-010J
L36 NL252018T-010J
L21 0_0805

C91
5PF

12

C108
5PF

Title

Size Document Number Rev

Date: Sheet

EC_SMC2 27
EC_SMD2 27

SDATAIN_CLK#0

SDATAIN_CLK#2
SDATAIN_CLK#3

Compal Electronics, Inc.

AMD AthlonXP SOCKET_ A-1

LA-1481 M/B

!"#, $%

STBY

ALERT

ADD0

5PF

5PF

16

NC

15
14
13

NC

12
11
10

R423

1K

12

12

12

E

PLLMON1
PLLMON2
SADDOUT#0
SADDOUT#1
FILVAL#
DOVAL#

+CPU_CORE

+CPU_CORE

C116 680PF
C112 680PF

Trace lengths of CLKOUT and CLKOUT#
are between 2" and 3"

14, 2002

R138 56
R139 56
R452 @1K
R444 @1K
R23 820
R24 820

SSHIFTEN
SINTVAL
SCANCLK2
SCANCLK1

8P4R_1.5K_0804

R127

60.4_1%
R115

301_1%

CLKOUT

close to CPU socket

CLKOUT#

E

RP25

1 8
2 7
3 6
4 5

R112

60.4_1%

CPUCLK 13
CPUCLK# 13

+CPU_CORE

R91
100_1%

15mil

R92
100_1%

+CPU_CORE

R98
100_1%

15mil

R97
100_1%

347

of

0.3

+12VS

R195

3.48K_1%_0603

FAN1

1 2
21

D13
1N4148

31

2

Q18 2SA1036K

Located at Socket-A Cap

0.22UF(0603) X 22
1000PF(0402) X 4

0.1UF(0402) X 4

0.01UF(0402) X 4
1UF(0603) X 8
10UF(1206) X 30
39PF(0402) X 29
330UF(D2_2.5V_15m) X 8

SVID[0..4]33

SVID0
SVID4

SVID2
SVID3

SVID1

Fan1 Control circuit

AD30

AD8
AF10
AF28
AF30
AF32

AF6

AF8
AH30

AH8

AJ9

AK8

AL9

AM8

F30

H10

H28

H30

H32

K30
AJ7

AL7

AN7

G25

G17

AG7
AG15
AG29

AA7

AG9
AG17
AG27

G15

G23

AH6

F8

H6
H8

K8

G9

N7
Y7

G7
Q7

D15 @1SS355

CB41

1 2

2.2UF_16V_0805

H12

H16

H20

H24M8P30R8T30V8X30Z8AB30

VCC_CORE1

VCC_CORE2

VCC_CORE3

VCC_CORE4

VCC_SRAM1
VCC_SRAM2
VCC_SRAM3
VCC_SRAM4
VCC_SRAM5
VCC_SRAM6
VCC_SRAM7
VCC_SRAM8
VCC_SRAM9
VCC_SRAM11
VCC_SRAM13
VCC_SRAM14
VCC_SRAM16
VCC_SRAM17
VCC_SRAM19
VCC_SRAM20
VCC_SRAM21
VCC_SRAM22
VCC_SRAM23
VCC_SRAM24
VCC_SRAM25
VCC_SRAM26
VCC_SRAM27
VCC_SRAM28
VCC_SRAM29
VCC_SRAM30
VCC_SRAM31

KEY4
KEY6
KEY8
KEY10
KEY12
KEY14
KEY16
KEY18

KEY
KEY
KEY
KEY
KEY
KEY
KEY
KEY

AMD

VSS1

VSS2

VSS3

VSS4

H14

H18

H22

H26

FMMT619

2

21

VCC_CORE5

VCC_CORE6

VCC_CORE7

VCC_CORE8

VSS5

VSS6

VSS7

VSS8

M30P8R30T8V30X8Z30

Q19

D14
1N4148

VCC_CORE9

VCC_CORE10

VSS9

VSS10

D33

C17

1SS355

VCC_CORE14

VSS14

40mil

AF22

AF26

VCC_CORE15

VSS15

AF20

AF24

C446
1000PF

AM34

VCC_CORE16

VCC_CORE17

VSS16

VSS17

AM36

@1000PF

+5VFAN1

AK36

AK34

AK30

VCC_CORE18

VCC_CORE19

VSS18

VSS19

AK32

AK28

AK24

VCC_CORE20

VSS20

2 1

3 1

2 1

AF14

AF18

VCC_CORE11

VCC_CORE12

VCC_CORE13

VSS11

VSS12

VSS13

AB8

AF12

AF16

+5VS

JP21

1
2
3

53398-0310

Layout:C3 & C988 must
close to JP1

AK26

AK22

AK18

AK14

AK10

AL5

AH26

AM30

AH22

VCC_CORE21

VCC_CORE22

VCC_CORE23

VCC_CORE24

VCC_CORE25

VCC_CORE26

VCC_CORE27

VCC_CORE28

VCC_CORE29

VSS21

VSS22

VSS23

VSS25

VSS26

VSS27

VSS28

VSS29

VSS30

AK20

AK16

AK12

AK4

AK2

AH36

AM32

AH34

AH32

+3VS

12

R456
10K

FANSPEED1 27

C219
1000PF

AH18

AH14

AH10

AH4

AH2

AF36

AF34

AD6

VCC_CORE30

VCC_CORE31

VCC_CORE32

VCC_CORE33

VCC_CORE34

VCC_CORE35

VCC_CORE36

VCC_CORE37

VSS31

VSS32

VSS33

VSS34

VSS35

VSS37

VSS38

VSS39

AH28

AH24

AH20

AH16

AH12

AF4

AF2

AD36

EN_FAN127

AM26

AD4

AD2

AB36

AB34

AB32Z6Z4Z2X36

VCC_CORE38

VCC_CORE39

VCC_CORE40

VCC_CORE41

VCC_CORE42

VCC_CORE43

VSS40

VSS41

VSS42

VSS43

VSS44

VSS45

AD34

AD32

AB6

AB4

AB2

Z36

Z34

VCC_CORE44

VCC_CORE45

VCC_CORE46

VSS46

VSS47

VSS48

Z32X6AM28X4X2

VCC_CORE47

VSS49

X34

VCC_CORE48

VSS50

12

AM22

X32V6V4V2T36

VCC_CORE49

VCC_CORE50

VSS51

VSS52

V36

C444

0.1UF

1 2

R455

13K_1%_0603

VCC_CORE51

VCC_CORE52

VCC_CORE53

VSS53

VSS54

VSS55

V34

V32T6T4T2R36

T34

VCC_CORE54

VCC_CORE55

VSS56

VSS57

T32R6R4R2AM18

VCC_CORE56

VCC_CORE57

VCC_CORE58

VSS58

VSS59

VSS60

R34

AM24

P36

VCC_CORE59

VCC_CORE60

VCC_CORE61

VSS61

VSS62

VSS63

R32P6P4P2M36

+5VS

1
3

P34

P32M4M6M2K36

VCC_CORE62

VCC_CORE63

VSS64

VSS65

VCC

VEE

2 5

R453

M34

0.1UF

1 2

C443

4

U28

LMV321_SOT23-5

1 2

7.32K_1%_0603

K34

VCC_CORE64

VCC_CORE65

VCC_CORE66

VCC_CORE67

VCC_CORE68

VSS66

VSS67

VSS68

VSS69

VSS70

M32K6K4K2AM20

K32H4H2

VCC_CORE69

VCC_CORE70

VSS71

VSS72

H36

FAN1

AM14

F36

F34

F32

F28

F24

F20

F16

F12

D32

D28

AM10

D24

D20

D16

D12D8D4D2B36

VCC_CORE71

VCC_CORE72

VCC_CORE73

VCC_CORE74

VCC_CORE75

VCC_CORE76

VCC_CORE77

VCC_CORE78

VCC_CORE79

VCC_CORE80

VCC_CORE81

VCC_CORE82

VCC_CORE83

VCC_CORE84

VCC_CORE85

VCC_CORE86

VCC_CORE87

VCC_CORE88

VCC_CORE89

VCC_CORE90

VSS73

VSS74

VSS75

VSS76

VSS77

VSS78

VSS79

VSS80

VSS81

VSS82

VSS83

VSS84

VSS85

VSS86

VSS87

VSS88

VSS89

VSS90

VSS91

VSS92

H34

F26

F22

F18

F14

F10F6F4F2AM16

D36

D34

D30

D26

D22

D18

D14

D10D6B34

+CPU_CORE

12

12

C71

C103

0.1UF

1000PF

+CPU_CORE

12

C30
10UF_10V_1206

+VCCA2.5+CPU_CORE

B32

AM2

B28

B24

B20

B16

B12B8B4

AJ5

AC7

VCC_Z

VCC_CORE91

VCC_CORE92

VCC_CORE93

VCC_CORE94

VCC_CORE95

VCC_CORE96

VCC_CORE97

VCC_CORE98

VCC_CORE99

VCC_CORE100

VCC_CORE101

NC1
NC2
NC3
NC6
NC7

NC8/FSB_Sense

NC9
NC10
NC11
NC12
NC13
NC15
NC16
NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC42
NC43
NC44
NC45

BP0_CUT
BP1_CUT
BP2_CUT
BP3_CUT

VSS93

VSS94

VSS95

VSS96

VSS97

VSS98

VSS99

VSS100

VSS101

VSS102

VSS103

VSS104

AM12

B30

B26

B22

B18

B14

B10B6B2

AM4

AK6

AM6

AE7

OPTION

12

12

C358

C334

1000PF

0.01UF

OPTION

12

C27
10UF_10V_1206

CB106

1 2

4.7UF_10V_0805

>15mil

U27B
CPU_SOCKET_OPGA_462

AJ23

VCC_A

AA31
AC31
AE31
AG23
AG25
AG31
AG5
AJ11

ADD for 133/100MHz select 91.03.15.

AJ15
AJ17
AJ19
AJ27
AL11
AN11
AN9
G11
G13
G27
G29
G31
J31
J5
L31
N31
Q31
S31

THERMDA

S7
U31

THERMDC

U7
W31

9/04/2000 CHANGE BACK

W7
Y31
Y5
AG19
G21
AG21
G19

AN27
AL27
AN25
AL25

+CPU_CORE

VSS_Z

C31

1UF_10V_0603

12

C143

0.01UF

C28
10UF_10V_1206

1 2

FSB_100/133#

C37

1UF_10V_0603

12

C357
1000PF

THERMDA 3
THERMDC 3

12

C94

0.1UF

12

R11 10K

OPTION

12

C98

0.01UF

12

C29
10UF_10V_1206

+3VS

+CPU_CORE

12

C56

0.1UF

C395

1UF_10V_0603

12

12

C72

C82

1000PF

0.01UF

FSB_100/133# 10,13

12

C33

0.1UF

C384
1UF_10V_0603

AMD Socket-A processors will not
implement a pin at location AH6.

VR_ON27,36,39

CONTROL ON/OFF

+5VS

0.22UF_0603

R221 0

C161

C158

0.1UF

VCCA for cpu internal PLL power source!

U9

8

SD#

4

VIN

1

Cnoise

3

GND

SENSE/ADJ

VOUT

ERROR#

DELAY

SI9182DH-25

5
6
7
2

C526

0.22UF_0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

(2.5V Output)

2.5V,if 1GHz need 200mA

@4.7UF_10V_0805

+2.5_A +2.5_B

12

12

C151

C152

39PF

L41 0_0805

>20mil >20mil

1 2

C156
39PF

L40 0_0805

1 2

C160
39PF

+VCCA2.5

>20mil

C155
39PF

+3VALW

Near socket-A
pin AJ23

R74 10
C84
39PF

R292 470K_0603

CPUDET#27

C81
39PF

1 2

C520
39PF

+VCCP2.5

+CPU_CORE

+VCCP2.5 30

Compal Electronics, Inc.

Title

AMD AthlonXP SOCKET_ A-2

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

C35

1UF_10V_0603

14, 2002

OPTION

1UF_10V_0603

C26

C38

1UF_10V_0603

447

of

C39
1UF_10V_0603

0.3

A

Layout note :

Place close to CPU, Use 2~3 vias per PAD.
Place .22uF caps underneath balls on solder side.
Place 10uF caps on the peripheral near balls.
Use 2~3 vias per PAD.

B

C

D

E

Layout note :

Place close to CPU power and
ground pin as possible
(<1inch)

Please place these cap in the socket cavity area

1 1

+CPU_CORE

12

option

CB83
10UF_6.3V_1206

Please place these cap on the socket north side

+CPU_CORE

12

CB25

10UF_6.3V_1206

+CPU_CORE

12

2 2

10UF_6.3V_1206

+CPU_CORE

12

CB12

CB31
10UF_6.3V_1206

12

CB10
10UF_6.3V_1206

12

CB26
10UF_6.3V_1206

12

CB34
10UF_6.3V_1206

12

CB30
10UF_6.3V_1206

12

CB36
10UF_6.3V_1206

12

CB28
10UF_6.3V_1206

12

CB37
10UF_6.3V_1206

12

CB9
10UF_6.3V_1206

option

Please place these cap on the socket south side

+CPU_CORE

12

CB40

10UF_6.3V_1206

+CPU_CORE

3 3

12

10UF_6.3V_1206

+CPU_CORE

12

10UF_6.3V_1206

CB1

CB29

12

CB32
10UF_6.3V_1206

12

CB38
10UF_6.3V_1206

12

CB33
10UF_6.3V_1206

12

CB6
10UF_6.3V_1206

12

CB13
10UF_6.3V_1206

12

CB5
10UF_6.3V_1206

12

CB19
10UF_6.3V_1206

12

CB21
10UF_6.3V_1206

12

CB11
10UF_6.3V_1206

12

CB8
10UF_6.3V_1206

12

CB27
10UF_6.3V_1206

option

+CPU_CORE

12

CE3

+

330UF_D2_2.5V_15m

+CPU_CORE

12

CE11

+

330UF_D2_2.5V_15m

+CPU_CORE +CPU_CORE

12

C114
39PF

+CPU_CORE

12

C111

0.22UF_0603

+CPU_CORE

12

C93

0.22UF_0603

+CPU_CORE

12

C78

0.22UF_0603

+CPU_CORE

12

C45
39PF

Used ESR 15m ohm cap total ESR=1.875m ohm

12

CE16

+

330UF_D2_2.5V_15m

12

CE6

+

330UF_D2_2.5V_15m

12

12

C102
39PF

12

C32
39PF

12

C87

C85

39PF

39PF

12

12

C75

C123

0.22UF_0603

0.22UF_0603

12

12

C117

C131

0.22UF_0603

0.22UF_0603

12

C74

0.22UF_0603

12

12

C137

C361

39PF

39PF

Distribute evenly on approximately
one-inch spacing along the VccCore
plane edge .

12

+

330UF_D2_2.5V_15m

12

+

330UF_D2_2.5V_15m

12

12

C88
39PF

12

C132

0.22UF_0603

12

C76

0.22UF_0603

NOTE: Must put inside
the CPU socket

12

12

C365

C438

39PF

39PF

CE7

CE12

C403
39PF

12

C362

0.22UF_0603

12

C414

0.22UF_0603

12

C415
39PF

12

CE5

+

330UF_D2_2.5V_15m

12

CE15

+

330UF_D2_2.5V_15m

12

12

C416
39PF

12

C405
39PF

12

C392

0.22UF_0603

12

C363

0.22UF_0603

12

C356
39PF

12

C354
39PF

12

C125

0.22UF_0603

12

C378

0.22UF_0603

12

C86
39PF

12

C99
39PF

place close to the bulk
decoupling 330UF CAP per item

C366
39PF

12

C396

0.22UF_0603

12

C387

0.22UF_0603

12

C126

0.22UF_0603

12

C381

0.22UF_0603

12

C77

0.22UF_0603

12

C413

0.22UF_0603

+CPU_CORE

12

12

12

C73

C121

39PF

4 4

39PF

C138
39PF

12

C119
39PF

EMI Clip HOLE for CPU

PT2

1 2

AMD_CPU_EMI_CLIP

A

PT3

1 2

AMD_CPU_EMI_CLIP

PT4

1 2

AMD_CPU_EMI_CLIP

PT5

1 2

AMD_CPU_EMI_CLIP

B

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

12

12

C355
39PF

DISTRIBUTE EVENLY ON BOTTOMSIDE
OF CPU SOCKET-A

C139
39PF

12

C127
39PF

12

12

C34

C124

39PF

39PF

D

place the
components first

Compal Electronics, Inc.

Title

CPU Bypass Cap.

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

E

547

of

0.3

A

B

C

D

E

SDATA#[0:63]

SDATAINCLK#[0..3]

SDATAOUTCLK#[0..3]

+CPU_CORE

PA_216U1E1 Product Advisory

Ball A16 = CAL#

Ball B16 = CAL

A21
A20
B19
A22
B20
B21
C18
C17
A19
D21
D20
B18
C21

C19
E19

N26
P24
P25
R24
N25
U25
P26
R26
V25
U26
T25
T26
U24

R25
F20

D19
E20

V26

AC25

AD6
AE6

Y26

C20
G16
G17
G18
H20
H24

M20
N20
P20

D17
D18
E16
E17
E18
F16
F17
F18
F19

W23

V22

U3A

J20

ATI_U1

SADDIN2#
SADDIN3#
SADDIN4#
SADDIN5#
SADDIN6#
SADDIN7#
SADDIN8#
SADDIN9#
SADDIN10#
SADDIN11#
SADDIN12#
SADDIN13#
SADDIN14#

SADDINCLK#
SDATAINVAL#

SADDOUT2#
SADDOUT3#
SADDOUT4#
SADDOUT5#
SADDOUT6#
SADDOUT7#
SADDOUT8#
SADDOUT9#
SADDOUT10#
SADDOUT11#
SADDOUT12#
SADDOUT13#
SADDOUT14#

SADDOUTCLK#
PROCRDY

CLKFWDRST
CONNECT

CPURST#

POWERGOOD

NRSTIN#
DC_STOP#

S2K_VREF

VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU

K7_NC
K7_NC
K7_NC
K7_NC
K7_NC
K7_NC
K7_NC
K7_NC
K7_NC

THERMALDIODE_P
THERMALDIODE_N

PART 1 OF 5

SDATAOUTCLK0#

SDATAOUTCLK1#

S2K I/F (K7 MOBILE)

SDATAOUTCLK2#

SDATAOUTCLK3#

SDATA0#
SDATA1#
SDATA2#
SDATA3#
SDATA4#
SDATA5#
SDATA6#
SDATA7#
SDATA8#

SDATA9#
SDATA10#
SDATA11#
SDATA12#
SDATA13#
SDATA14#
SDATA15#

SDATAINCLK0#

SDATA16#
SDATA17#
SDATA18#
SDATA19#
SDATA20#
SDATA21#
SDATA22#
SDATA23#
SDATA24#
SDATA25#
SDATA26#
SDATA27#
SDATA28#
SDATA29#
SDATA30#
SDATA31#

SDATAINCLK1#

SDATA32#
SDATA33#
SDATA34#
SDATA35#
SDATA36#
SDATA37#
SDATA38#
SDATA39#
SDATA40#
SDATA41#
SDATA42#
SDATA43#
SDATA44#
SDATA45#
SDATA46#
SDATA47#

SDATAINCLK2#

SDATA48#
SDATA49#
SDATA50#
SDATA51#
SDATA52#
SDATA53#
SDATA54#
SDATA55#
SDATA56#
SDATA57#
SDATA58#
SDATA59#
SDATA60#
SDATA61#
SDATA62#
SDATA63#

SDATAINCLK3#

CAL#

CAL

SDATA#0

A25

SDATA#1

D25

SDATA#2

D26

SDATA#3

C25

SDATA#4

E25

SDATA#5

E24

SDATA#6

F24

SDATA#7

E26

SDATA#8

A23

SDATA#9

B22

SDATA#10

C22

SDATA#11

B23

SDATA#12

C26

SDATA#13

B24

SDATA#14

C23

SDATA#15

F25

SDATAINCLK#0

D24

SDATAOUTCLK#0

A24

SDATA#16

E23

SDATA#17

D22

SDATA#18

G22

SDATA#19

H23

SDATA#20

J23

SDATA#21

J22

SDATA#22

K23

SDATA#23

J21

SDATA#24

E21

SDATA#25

G23

SDATA#26

G21

SDATA#27

F23

SDATA#28

F22

SDATA#29

H22

SDATA#30

L23

SDATA#31

K22

SDATAINCLK#1

H21

SDATAOUTCLK#1

K21

SDATA#32

M21

SDATA#33

N22

SDATA#34

R23

SDATA#35

R21

SDATA#36

U23

SDATA#37

T22

SDATA#38

P21

SDATA#39

T21

SDATA#40

L21

SDATA#41

L22

SDATA#42

M23

SDATA#43

N23

SDATA#44

P23

SDATA#45

N21

SDATA#46

T23

SDATA#47

P22

SDATAINCLK#2

R22

SDATAOUTCLK#2

M22

SDATA#48

H25

SDATA#49

K25

SDATA#50

L24

SDATA#51

J26

SDATA#52

M25

SDATA#53

K26

SDATA#54

M26

SDATA#55

N24

SDATA#56

F26

SDATA#57

G24

SDATA#58

G25

SDATA#59

G26

SDATA#60

H26

SDATA#61

L26

SDATA#62

J24

SDATA#63

J25

SDATAINCLK#3

K24

SDATAOUTCLK#3

L25

C539 0.01UF

R15 30_1%_0603

A16

R14 30_1%_0603

B16

C540 0.01UF

1 2

1 2

SADDIN#[2..14]3

4 4

SADDOUT#[2..14]3

3 3

+CPU_CORE

C533

R150

0.047UF

60.4_1%

C140

R149

0.047UF

60.4_1%

2 2

PLACE CLOSE TO MOBILITY U1

SUS_STAT#17,28

PCIRST#16,19,20,21,22,23,25,26,27

R210

1K

C159 0.1UF

PCIRST# NB_RST#

SADDIN#[2..14]

SADDINCLK#3

SDATAINVAL#3

SADDOUT#[2..14]

SADDOUTCLK#3

PROCRDY3

CLKFWDRST3

CONNECT3

1

U7A

74LVC125

R137 @0
C122
@1UF_10V_0603

CPURST#3,16

NB_PWRGD30

+2.5V

R211
@4.7K

DC_STOP#

R457
1K

NOTE: ROUTE AS DIFF PAIR T O HW M

+3VALW

147

2 3

1 2

+CPU_CORE

SADDIN#2
SADDIN#3
SADDIN#4
SADDIN#5
SADDIN#6
SADDIN#7
SADDIN#8
SADDIN#9
SADDIN#10
SADDIN#11
SADDIN#12
SADDIN#13
SADDIN#14

SADDOUT#2
SADDOUT#3
SADDOUT#4
SADDOUT#5
SADDOUT#6
SADDOUT#7
SADDOUT#8
SADDOUT#9
SADDOUT#10
SADDOUT#11
SADDOUT#12
SADDOUT#13
SADDOUT#14

NB_PWRGD

NB_RST#

NB_VREFSYS

SDATA#[0:63] 3

SDATAINCLK#[0..3] 3

SDATAOUTCLK#[0..3] 3

1 1

+CPU_CORE

CB16

10UF_10V_1206

C442

0.1UF

C340

0.1UF

A

0.1UF

0.1UF

C439

C441

C120

0.1UF

C374

0.1UF

C335

0.1UF

C339

0.1UF

C440

0.1UF

B

C375

0.1UF

C383

0.1UF

0.1UF

C373

C404

0.1UF

C360

0.1UF

C372

0.1UF

C

0.1UF

0.1UF

C412

C367

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C394

0.1UF

D

Compal Electronics, Inc.

Title

ATI MOBILITY U1_S2K BUS

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

647

0.3

of

A

RP* place close to DIMM1

MAA_1 MAA1
MAA_0 MAA0
MAA_3
MAA_2
MAA_5 MAA5

MAA_7
MAA_6
MAA_9 MAA9

4 4

MAA_8 MAA8
MAA_12
MAA_11
MAA_14 MAA12

MAA_10 MAA10

RP93 4P2R_10

RP82

18

8P4R_10_0804

27
36
45

RP94

8P4R_10_0804

18

RP83

27

8P4R_10_0804

36
45

R468 10

MAA[0..14]

MAA3
MAA2

18

MAA4MAA_4

27

MAA7

36

MAA6

45

MAA14
MAA13

14

MAA11MAA_13

23

ATI RECOMEND

RP* PLACE CLOSE TO DIMM

MD4
MD5
MD0
MD1
MD6
RDQS0
MD2

8P4R_22_0804

MD3
MD12
MD8
MD7
MD9
MD13
MD14
MD10
RDQS1

3 3

2 2

1 1

MD11
MD20
MD16
MD15

MD17
RDQS2
MD18

8P4R_22_0804

MD22 MMD22
MD19

MD24
MD28
MD29
MD25

8P4R_22_0804

RDQS3
MD30
MD27
MD31
MD26
MD32
MD37
MD36

8P4R_22_0804

MD33
MD34

MD39
MD38
RDQS4
MD35
MD45
MD44

8P4R_22_0804

MD40
MD42
MD46
MD41
RDQS5
MD48
MD47
MD43

8P4R_22_0804

MD52
MD49
MD54
RDQS6
MD53
MD55
MD60
MD50

8P4R_22_0804

MD51
MD56
MD61
MD57
RDQS7
MD58
MD59

8P4R_22_0804

MD62
MD63

RDQM1
RDQM2

RDQM3
RDQM4

RDQM5
RDQM6

RDQM7

RP99

8P4R_22_0804

1 8

RP87

2 7
3 6
4 5

8P4R_22_0804

1 8
2 7
3 6
4 5

RP97

8P4R_22_0804

1 8
2 7
3 6

RP85

4 5

8P4R_22_0804

RP95

RP84

8P4R_22_0804

1 8

RP92

2 7
3 6
4 5

RP81

8P4R_22_0804

1 8

RP91

2 7
3 6
4 5

8P4R_22_0804

1 8

RP90

2 7
3 6
4 5

8P4R_22_0804

1 8

RP89

2 7
3 6
4 5

RP78
8P4R_22_0804

RP88

1 8
2 7
3 6
4 5

R471 22
R470 22

R476 22
R475 22

R474 22
R473 22

R469 22
R472 22

A

1 8
2 7
3 6
4 5

1 8

RP98

2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8

RP96

2 7
3 6

4 5
1 8
2 7
3 6
4 5

1 8

2 7

3 6

4 5

1 8

2 7

3 6

4 5

1 8

RP80

2 7

3 6

4 5

1 8

RP79

2 7

3 6

4 5

1 8

2 7

3 6

4 5

RP86
8P4R_22_0804

MMD4
MMD5
MMD0
MMD1
MMD6
DQS0
MMD2
MMD3
MMD12
MMD8
MMD7
MMD9
MMD13
MMD14
MMD10
DQS1
MMD11
MMD20
MMD16
MMD15
MMD21MD21
MMD17
DQS2
MMD18

MMD19
MMD23MD23
MMD24
MMD28
MMD29
MMD25
DQS3
MMD30
MMD27
MMD31
MMD26
MMD32
MMD37
MMD36
MMD33

MMD34
MMD39
MMD38
DQS4
MMD35
MMD45
MMD44
MMD40
MMD42
MMD46
MMD41
DQS5
MMD48
MMD47
MMD43
MMD52
MMD49
MMD54
DQS6
MMD53
MMD55
MMD60
MMD50
MMD51
MMD56
MMD61
MMD57
DQS7
MMD58
MMD59
MMD62
MMD63

DQM0RDQM0
DQM1

DQM2
DQM3

DQM4
DQM5

DQM6
DQM7

DDR_CS#011,12
DDR_CS#111,12
DDR_CS#211,12
DDR_CS#311,12

10UF_10V_1206

B

MAA[0..14] 11,12

SRAS#11,12
SCAS#11,12

SWE#11,12

CKE11,12

+2.5V

CB92

B

DDR_CS#0
DDR_CS#1
DDR_CS#2
DDR_CS#3

C426

0.1UF

MAA_0
MAA_1
MAA_2
MAA_3
MAA_4
MAA_5
MAA_6
MAA_7
MAA_8
MAA_9
MAA_10
MAA_11
MAA_12
MAA_13
MAA_14

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7

R_DDRCLK#0
R_DDRCLK#1
R_DDRCLK#2
R_DDRCLK#3
R_DDRCLK#4
R_DDRCLK#5

R_DDRCLK0
R_DDRCLK1
R_DDRCLK2
R_DDRCLK3
R_DDRCLK4
R_DDRCLK5

R454 10K

+2.5V

4P2R_0

4P2R_0

4P2R_0

4P2R_0

4P2R_0

4P2R_0

C434

0.1UF

RAS­CAS-

WE­CKE+

RCS#0
RCS#1
RCS#2
RCS#3

RP28

RP32

RP22

RP31

RP27

RP21

C433

0.1UF

R206 10

SRAS#

R208 10

SCAS#

R207 10

SWE#

R209 10

CKE

RP30 4P2R_10

1 4

2 3
1 4
2 3

RP29 4P2R_10

R_DDRCLK0
R_DDRCLK#0

R_DDRCLK1
R_DDRCLK#1

R_DDRCLK2
R_DDRCLK#2

R_DDRCLK3
R_DDRCLK#3

R_DDRCLK#4 DDRCLK#4
R_DDRCLK5

C437

0.1UF

AC21
AC20
AB20
AA20
AB19
AA19
AC19
AC18
AB18
AA18
AB21
AA17
AA16
AD23
AC22

AF8

AA9
AD12
AA13
AD16
AE20

W21

AA25
AD18

AF24

AE19

AF10

AD8

AC8
AE12
AB12
AE16

AF20

Y23

Y25
AB10

AE23

Y22
AB16
AE26
AB25

AC10
AD22
AA23
AC16
AD25
AC26

AE24
AD26

AF22

AC24

AF23

Y9
Y8
Y7

W20

V20

U20

1 4
2 3

1 4
2 3

1 4
2 3

1 4
2 3

2 3
1 4

1 4
2 3

C436

0.1UF

U3C

DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7

DDR_RAS#
DDR_CAS#

DDR_WE#
DDR_CKE

DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQS4
DDR_DQS5
DDR_DQS6
DDR_DQS7

DDR_CK0#
DDR_CK1#
DDR_CK2#
DDR_CK3#
DDR_CK4#
DDR_CK5#

DDR_CK0
DDR_CK1
DDR_CK2
DDR_CK3
DDR_CK4
DDR_CK5

DDR_CS0#
DDR_CS1#
DDR_CS2#
DDR_CS3#

TESTMODE
VDD_MEM

VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM

ATI_U1

C421

0.1UF

C

PART 3 OF 5

DDRCLK0
DDRCLK#0

DDRCLK1
DDRCLK#1

DDRCLK2
DDRCLK#2

DDRCLK3
DDRCLK#3

DDRCLK4R_DDRCLK4

DDRCLK5
DDRCLK#5R_DDRCLK#5

C

DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46

DDR SDRAM I/F (K7 MOBILE)

DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63

DDR_VREF

C424

0.1UF

DDR_DQ0
DDR_DQ1
DDR_DQ2
DDR_DQ3
DDR_DQ4
DDR_DQ5
DDR_DQ6
DDR_DQ7
DDR_DQ8
DDR_DQ9

VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM

AF6
AF7
AD9
AD10
AE7
AE8
AE9
AF9
AC7
AB9
AB11
AC11
AB8
AA11
AA10
AC9
AF11
AE11
AD13
AE13
AE10
AF12
AF13
AD14
AA12
AC12
AB13
AB14
AC13
AA15
AA14
AC14
AE14
AF15
AF16
AE17
AF14
AE15
AD17
AF17
AE18
AF19
AE21
AF21
AF18
AD19
AD21
AE22
AB23
AA22
V21
V23
W22
Y21
U21
U22
AB24
AA26
W25
V24
AB26
AA24
W26
W24

AD20
AD7
Y24
Y18
Y17
Y14
Y13

AF5

DDRCLK0 11
DDRCLK#0 11

DDRCLK1 11
DDRCLK#1 11

DDRCLK2 11
DDRCLK#2 11

DDRCLK3 11
DDRCLK#3 11

DDRCLK4 11
DDRCLK#4 11

DDRCLK5 11
DDRCLK#5 11

C432

0.1UF

C431

0.1UF

MMD0
MMD1
MMD2
MMD3
MMD4
MMD5
MMD6
MMD7
MMD8
MMD9
MMD10
MMD11
MMD12
MMD13
MMD14
MMD15
MMD16
MMD17
MMD18
MMD19
MMD20
MMD21
MMD22
MMD23
MMD24
MMD25
MMD26
MMD27
MMD28
MMD29
MMD30
MMD31
MMD32
MMD33
MMD34
MMD35
MMD36
MMD37
MMD38
MMD39
MMD40
MMD41
MMD42
MMD43
MMD44
MMD45
MMD46
MMD47
MMD48
MMD49
MMD50
MMD51
MMD52
MMD53
MMD54
MMD55
MMD56
MMD57
MMD58
MMD59
MMD60
MMD61
MMD62
MMD63

D

12

C229

+

150UF_D2_6.3V

CAP-D_E_TAN

MD[0..63]
RDQM[0..7]
RDQS[0..7]

Place near SODIMM1.

+2.5V

12

C231

0.1UF

12

C232

0.1UF

MD[0..63] 11,12
RDQM[0..7] 11,12
RDQS[0..7] 11,12

12

C228

0.1UF

12

C227

0.1UF

E

12

12

C234

C257

0.1UF

0.1UF

Place near SODIMM2

+2.5V

12

12

C230

+

@150UF_D2_6.3V

CAP-D_E_TAN

C435

0.1UF

+2.5V

+2.5V

C150
@0.1UF

NB_DDR_VREF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C430

C429

0.1UF

0.1UF

12

C163

+

150UF_D2_6.3V

CAP-D_E_TAN

R285
1K_ 1%

R279
1K_ 1%

C190

0.1UF
R280 @0_0603

C183

0.1UF

PLACE RPACKS CLOSE TO
1ST SO-DIMM

C428

0.1UF

D

12

C467

0.1UF

Compal Electronics, Inc.

Title

ATI MOBILITY U1_DDR I/F

Size Document Number Rev

LA-1481 M/B

Date: Sheet

C466

0.1UF

SDREF 11,35

!"#, $%

12

C465

0.1UF

14, 2002

12

C464

0.1UF

12

12

C462

C461

0.1UF

0.1UF

E

12

12

C226

C233

0.1UF

0.1UF

12

12

C463

C468

0.1UF

0.1UF

747

0.5

of

A

AD[0..31]10,16,20,21,22,25,32

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

PCI_ACT_REQ#

PCI_SBREQ#
PCI_SBGNT#

REQ#0
REQ#1
REQ#2
REQ#3

GNT#0
GNT#1
GNT#2
GNT#3

C136

0.1UF

AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

4 4

CBE#010,16,20,21,22,25
CBE#116,20,21,22,25
CBE#216,20,21,22,25

DEVSEL#16,20,21,22,25

PCI_ACT_REQ#10,17

PCI_SBREQ#16
PCI_SBGNT#16

+3VS

1 2
1 2

CBE#310,16,20,21,22,25

PAR16,20,21,22,25

FRAME#16,20,21,22,25

IRDY#16,20,21,22,25

TRDY#16,20,21,22,25

PIRQA#16,22

STOP#16,20,21,22,25

SERR#16,20,22,25

REQ#021
REQ#125
REQ#222
REQ#320

GNT#021
GNT#125
GNT#222
GNT#320

+3VS+3VS

+3VS

3 3

2 2

8P4R_8.2K_0804

GNT#3
REQ#3
GNT#2
REQ#2

8P4R_8.2K_0804

GNT#1
REQ#1
REQ#0
GNT#0

PCI_SBGNT#
PCI_SBREQ#

RP77

4 5
3 6
2 7
1 8

RP14

4 5
3 6
2 7
1 8

R424 8.2K
R136 8.2K

U3B

AA7

PCI_AD0

AA8

PCI_AD1

AB7

PCI_AD2

AE5

PCI_AD3

AF4

PCI_AD4

AD5

PCI_AD5

AE4

PCI_AD6

AD4

PCI_AD7

AF3

PCI_AD8

AE1

PCI_AD9

AD2

PCI_AD10

AC3

PCI_AD11

AD1

PCI_AD12

AC6

PCI_AD13

AC5

PCI_AD14

AC2

PCI_AD15

AA2

PCI_AD16

AA1

PCI_AD17

Y2

PCI_AD18

Y6

PCI_AD19

Y5

PCI_AD20

Y4

PCI_AD21

W6

PCI_AD22

W5

PCI_AD23

W4

PCI_AD24

W3

PCI_AD25

W2

PCI_AD26

V6

PCI_AD27

V5

PCI_AD28

V4

PCI_AD29

W1

PCI_AD30

V3

PCI_AD31

AE3

PCI_CBE0#

AC1

PCI_CBE1#

AA3

PCI_CBE2#

Y1

PCI_CBE3#

AB3

PCI_PAR

AB1

PCI_FRAME#

AA4

PCI_IRDY#

AA5

PCI_TRDY#

T5

INTA#

AB4

PCI_DEVSEL#

AB6

PCI_STOP#

AB2

PCI_SERR#

R6

PCI_ACT_REQ#

R2

PCI_SBREQ#

R4

PCI_SBGNT#

V2

PCI_REQ0#

U4

PCI_REQ1#

U6

PCI_REQ2#

T4

PCI_REQ3#/PCI_CLK3

V1

PCI_GNT0#

U5

PCI_GNT1#

T2

PCI_GNT2#

T6

PCI_GNT3#/PCI_CLK4

T1

VDD_5V

AB17

NC

AC15

NC

ATI_U1

B

PART 2 OF 5

VID0/TST_IN0
VID1/TST_IN1
VID2/TST_IN2
VID3/TST_IN3
VID4/TST_IN4
VID5/TST_IN5
VID6/TST_IN6
VID7/TST_IN7

XVID0
XVID1
XVID2

XVID3/TESTCLK1

XVID4

XVID5/TST_ADDR

XVID6/TST_STB

XVID7/TST_WR

VVSYNC/TST_OUT14

VHREF/TST_OUT15

VPCLK0/TST_OUT13

TMDS_D0/TST_OUT12
TMDS_D1/TST_OUT10

TMDS_D2/TST_OUT9
TMDS_D3/TST_OUT8
TMDS_D4/TST_OUT6
TMDS_D5/TST_OUT7
TMDS_D6/TST_OUT5
TMDS_D7/TST_OUT4
TMDS_D8/TST_OUT2

TMDS_D9/TST_OUT3
TMDS_D10/TST_OUT1
TMDS_D11/TST_OUT0
TMDS_DE/TST_OUT11

TMDS_VSYNC/TCK
TMDS_HSYNC/TMS

TMDS_SCL

TMDS_SDA/TDI

PCI/ZV/TMDS (K7 MOBILE)

TMDS_IDCK-

TMDS_IDCK+

TMDS_LCDCNTL0/GPIO8
TMDS_LCDCNTL1/GPIO9

TMDS_LCDCNTL2/GPIO10

TMDS_VREF

TMDS_VOLT_DET

TMDS_HPD

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

CLK27M

LVDS_SSIN

LVDS_SSOUT

NB_VID0

J4

NB_VID1

F4

NB_VID2

E6

NB_VID3

M4

NB_VID4

F5

NB_VID5

G4

NB_VID6

G5

NB_VID7

K5

XVID0

L5

XVID1

J6

XVID2

H6

XVID3

K4

XVID4

K6

XVID5

J5

XVID6

L4

XVID7

G6

VVSYNC

L6

VHREF

M5

VPCLK0

H5
J2

K3
K1
K2
L1
L2
L3
N1
N2
N3
P1
P2
J1

H2
J3

R3
R1

M2
M1

D3
E2
G2

R5

R417 @4.7K

E4

G1
E1

RSV

F3

RSV

F2

RSV

H4

RSV

P3
N4
N6
P4
P6
M6
N5
P5

CLK27M

C1
C2

R414 SS@22

D6

INSTALL IF CLK NOT POPULATED

R418
10K

+3VS

DNI

+3VS

NB_TMDS_VREF

C402

0.1UF

KEEP CLOSE TO TMDS VREF PIN

LVDS_SSIN
LVDS_SSOUT

R77
SS@10K

C

R399
SS@10K

R400
@10K

R426
1K_1%

R425
1K_1%

3
2

+3VS

12

12

SS@10K

X2

OUT
GND

OSC_27MHz

R385

VDD

+3VS

12

12

SS@10

C49

SS@22PF

ST

C60
SS@0.1UF
R398

SS@10K

R32

R34
10K_1%

4
1

12

1

6

1 2

12

+3VS

12

12

+3VS

L22
SS@FBM-L11-201209-221

C50

SS@10UF_10V_0805

2

U25

VDD

X1/CLK

CLK

SDS0

S1

LEE

GND

3

SS@SM560_SO-8

LVDS SPREAD SPECTRUM

R415

1 2

SS@10

Close to U49

XVID7
NB_VID1
NB_VID4
NB_VID2

XVID0
XVID6
NB_VID7
XVID3

VPCLK0
XVID2
NB_VID5
NB_VID6

XVID4
XVID1
NB_VID0
XVID5

VHREF
NB_VID3
VVSYNC

C43

0.1UF_16V

12

4

87
5

LVDS_SSOUT

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

1 8
2 7
3 6
4 5

D

+3VS

12

R19
@0

LVDS_SSIN

@10

Close to U49

12

R5
@0

RP5
8P4R_10K_0804

RP12
8P4R_10K_0804

RP10
8P4R_10K_0804

RP11
8P4R_10K_0804

RP13
8P4R_10K_0804

R10

12

C21

1 2

@22PF

+1.8VS

+3VS

K10
K11
K12
K15
K16
K17

L10
L11
L12
L15
L16

L17
M10
M11
M12
M15
M16
M17
R10
R11
R12
R15
R16
R17
T10
T11
T12
T15
T16
T17
U10
U11
U12
U15
U16
U17

G10
G11

W7

B15
C15
D15
E15
F15
G15

T13
T14
T20
T24
U13
U14
Y10
Y11
Y12
Y15
Y16
Y19
Y20

C7

T3
U7
V7

Y3

G7

K7
L7

H3
P7

U3E

VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE

VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V

VDD_VID
VDD_VID
VDD_VID

VDD_TMDS
VDD_TMDS

NC
NC
NC
NC
NC
NC

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

ATI_U1

E

PART 5 OF 5

A1

GND

A26

GND

AA6

GND

AA21

GND

AB5

GND

AB15

GND

AB22

GND

AC23

GND

AC4

GND

AC17

GND

AD3

GND

AD11

GND

AD15

GND

AD24

GND

AE2

GND

AE25

GND

AF1

GND

AF2

GND

AF25

GND

AF26

GND

B1

GND

B2

GND

B25

GND

B26

GND

C3

GND

C24

GND

D4

GND

D23

GND

E5

GND

E22

GND

F6

GND

F21

GND

G8

GND

G9

GND

G12

GND

G13

GND

G14

GND

G19

GND

G20

GND

H7

GND

J7

GND

K13

GND

K14

GND

K20

GND

L13

GND

L14

GND

L20

GND

POWER (K7 MOBILE)

M3

GND

M7

GND

M13

GND

M14

GND

M24

GND

N7

GND

N10

GND

N11

GND

N12

GND

N13

GND

N14

GND

N15

GND

N16

GND

N17

GND

P10

GND

P11

GND

P12

GND

P13

GND

P14

GND

P15

GND

P16

GND

P17

GND

R7

GND

R13

GND

R14

GND

R20

GND

T7

GND

+1.8VS

C386

0.1UF

C401

0.1UF

C390

0.1UF

C400

0.1UF

1 1

CB90
10UF_10V_1206

CB91
10UF_10V_1206

C388

0.1UF

C418

0.1UF

A

C389

0.1UF

C391

0.1UF

C411

0.1UF

C398

0.1UF

C420

0.1UF

C407

0.1UF

C409

0.1UF

C397

0.1UF

C410

0.1UF

C399

0.1UF

C422

0.1UF

C408

0.1UF

B

+3VS

CB7
10UF_10V_1206

C419

C427

0.1UF

C425

0.1UF

C417

0.1UF

C369

0.1UF

0.1UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C406

C382

C371

C376

0.1UF

C359

0.1UF

C423

@0.1UF

C393

@0.1UF

D

C370

0.1UF

0.1UF

0.1UF

C

0.1UF

Compal Electronics, Inc.

Title

ATI MOBILITY U1_PCI BUS I/F

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

847

E

of

0.3

A

B

C

D

E

Note: AVSSQ & AVS SN requ ire separate d irect con nectio ns to G ND plan e ( se p a ra te v i as ).
Note: A2VSSQ & A2VSSN require separate direct connections to GND plane (separate vias).

+1.8VS

4 4

3 3

REFCLK1_NB13

CPUCLK_NB_EXT13

PCLK_NB_EXT13

AGPCLK_EXT13

2 2

SDCLK_NB_EXT13

HB-1M2012-121JT

+2.5VS A2VDD

HB-1M2012-121JT

AVDD

L18

1 2

RED14

BLUE14

R29 499_1%

TP14
TP3

TP2

TP1
TP5

TP12

TP4

TP11

C53

C61

0.1UF

0.1UF

C59

0.1UF

C350

C347

0.1UF

0.1UF

R405 0

1 2

R30 0

1 2

1

TST_CPUCLK

1

TST_CPUCLK#

1

SYS_FBCLKOUT

R409 @22

SYS_FBCLKIN
HCLKOUT

1

PCI_CLKF

1

PCLK_NB_EXT_RPCLK_NB_EXT
PCICLK_BUF

1

SDCLK_NB_EXT_R
TST_UCLK48M

1

TST_REFCLK1_SB

1

12

C346
@100PF

CB15

+

AVSS

A2VSS

PLLVSS

10UF_10V_1206

CB14

+

10UF_10V_1206

PLVDD+1.8VS

CB86

+

10UF_10V_1206

R412 0

R410 0
R406 0

SHORT

JOPEN1

L17

1 2

SHORT

JOPEN2

L47

1 2

5.6_0805

SHORT

JOPEN5

CPUCLK_NB_EXT

AGPCLK_EXT AGPCLK_EXT_R
SDCLK_NB_EXT

1UF_10V_0603

1UF_10V_0603

1 2

R27 0

1 2

R408 0

1 2

1 2
1 2

C48

C47
1UF_10V_0603

C344

GREEN14
VSYNC14

HSYNC14

1 2

B11

C9

B13
F11

C11

A8

D10
C12

E13

D13
F13

A11
A12
A13
D12
E12

B12

OSC_NBREFCLK1_NB

A18
B17

D16
A15
C16

D14
C13

B14
A14

E14

C14

B9
A9

U2

U1

+2.5VS

C55

0.1UF

U3D

AVDD
A2VDDQ

AVSSQ
AVSSN

A2VDD

A2VSSN
A2VSSQ

PLLVDD0
PLLVDD1

PLLVSS0
PLLVSS1

RED
GREEN
BLUE
DACVSYNC
DACHSYNC

RSET

XTLIN
XTLOUT

SYSCLK
SYSCLK#

SYS_FBCLKOUT
SYS_FBCLKIN/HCLKIN
HCLKOUT

PCI_CLKF
PCI_CLK1

PCI_CLK2
AGP_FBCLKIN/AGP_CLKIN

AGP_FBCLKOUT/EXT_MEM_CLK
USBCLK

APICCLK

OSC

ATI_U1

A17

PART 4 OF 5

VDD_2.5V

CRT

CLK.

Remove if testing CLK_RUN# using SB GPIO

CLK, DISPLAY (K7 MOBILE)

GEN.

TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P

TXCLK_UN
TXCLK_UP

TXOUT_L0N

TXOUT_L0P

TXOUT_L1N

TXOUT_L1P

TXOUT_L2N

TXOUT_L2P

TXOUT_L3N

TXOUT_L3P

TXCLK_LN
TXCLK_LP

LVDS

LVDS_DIGON/TDO

LVDS_BLON#

LVDS_BIASON

LPVDD

LPVSS

LVDDR
LVDDR

LVSSR
LVSSR

C_R
Y_G

COMP_B

SVID

R2SET

DACSCL

DACSDA

PCICLK_STP#

CPUCLK_STP#

AGP_BUSY#

AGP_STP#
CLK_RUN#

RSV
RSV

WAIT CHECK ATI LVDS EVEN/ODD DEFINE

D7
D8
B7
A7
E8
E9
C8
B8
D9
E10

B3
A3
B4
A4
B5
A5
C5
C6
B6
A6

D1
D2
E3

F9
F10

E7
F7
F8
A2

A10
B10
C10

R413 715_1%_0603

D11

R31 0

E11

R404 0

F12

PCICLK_STP#

U3

CPU_STP#

F14

AGPBUSY#

C4

AGPSTP#

D5
F1

G3
H1

R96

10K

1 2
1 2

TXOUT_U0- 15
TXOUT_U0+ 15
TXOUT_U1- 15
TXOUT_U1+ 15
TXOUT_U2- 15
TXOUT_U2+ 15

TXCLKOUT_U- 15
TXCLKOUT_U+ 15

TXOUT_L0- 15
TXOUT_L0+ 15
TXOUT_L1- 15
TXOUT_L1+ 15
TXOUT_L2- 15
TXOUT_L2+ 15

TXCLKOUT_L- 15
TXCLKOUT_L+ 15

LCD_DIGON 15,27
LVDS_BLON# 15

CRMA 14
LUMA 14
COMPS 14

R403 @0

1 2

AGP_BUSY# 16
AGP_STP# 16

R90 @0

R83
10K

1

TP13

C349

C343

0.1UF

1UF_10V_0603

C352

0.1UF

DDCCLK 14,15
DDCDATA 14,15

CPUCLK_STP#

PM_CLKRUN# 16,18,22,25,27

DNI

Install if testing CLK_RUN# using SB GPIO

AGPBUSY#
AGPSTP#
PCICLK_STP#
CPU_STP#

C351

C353

1UF_10V_0603

0.1UF

PCICLK_STP# 13,17
CPUCLK_STP# 13,17

R416 4.7K
R60 4.7K
R178 10K
R21 10K

LVDD

+

LVDDR

+

1 2
1 2
1 2
1 2

L46

1 2

5.6_0805
CB85
10UF_10V_1206

LVSS

L48

1 2

HB-1M2012-121JT
CB87
10UF_10V_1206

LVSSR

SHORT
JOPEN7

+3VS

JOPEN6
SHORT

+1.8VS

+1.8VS

C341 22PF

1 2

C342 22PF

1 2

C348 22PF

1 2

C345 22PF

1 2

EMI request

R401 @10

1 2

R402 @10

1 2

R411 @10

1 2

R407 @10

1 2

SYS_FBCLKIN
PCLK_NB_EXT_R
AGPCLK_EXT_R
SDCLK_NB_EXT_R

LAYOUT:Close to NB(U5)

1 1

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

ATI MOBILITY U1_CLK GEN/LVDS

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

947

E

of

0.3

A

B

C

D

E

R154 @10K_0603

AD15

AD31

R61 3.3K_0603

1 2

4 4

FSB_100/133#4,13

AD30

2

@2N7002

1 2

R40 10K_0603

1 2

R64 @4.7K_0603

AD29

AD28

AD27

3 3

AD26

AD25

AD24

1 2

R37 5.6K_0603

13

Q6

1 2

R39 @10K_0603

1 2

R63 4.7K_0603

1 2

R38 @10K_0603

1 2

R62 4.7K_0603

1 2

R42 @10K_0603

1 2

R66 4.7K_0603

1 2

R43 @10K_0603

1 2

R67 4.7K_0603

R41 @10K_0603
R65 4.7K_0603

R45 10K_0603
R69 @4.7K_0603

ATI 5/27

1 2
1 2

1 2
1 2

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

AD[31..30] : CLK SPEED

DEFAULT

00: 66 MHZ (1:1)
01: 100 MHZ (1.5:1)
10: 166MHZ (2.5:1)
11: 133 MHZ (2:1)

AD29: STRAP SET SELECTION

DEFAULT

0: USE FULL STRAPPING SET
1: USE REDUCED STRAPPING SET

AD28: SPREAD SPECTRUM ENABLE

0: DISABLE

DEFAULT

1: ENABLE

AD[27..26] : CPU S2K BUS LENGTH

DEFAULT

00: SHORT, NON-S2K INTERFACE
01: SINGLE S2K INTERFACE, CLOSE
10: FAR S2K INTERFACE, DUAL CPU
11: FARTHEST S2K INTERFACE, DUAL CPU

AD25: RESERVED

DEFAULT

0: ???
1: ???

AD24: INCLK_DELAY_ENABLE

DEFAULT

0: DISABLE
1: ENABLE

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7
AD6
AD5
AD4

R155 4.7K_0603

R437 @10K_0603
R438 4.7K_0603

R435 @10K_0603
R436 4.7K_0603

R160 @10K_0603

1 2

R161 4.7K_0603

1 2

R147 @10K_0603

1 2

R148 4.7K_0603

1 2

R166 @10K_0603
R167 4.7K_0603

R174 @10K_0603
R175 4.7K_0603

R193 10K_0603
R194 @4.7K_0603

R103 10K_0603

1 2

R102 10K_0603

1 2

R117 10K_0603

1 2

R118 10K_0603

1 2

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

PID3 15,28
PID2 15,28
PID1 15,28
PID0 15,28

AD[15..14] :S2K/SLOT1 SELECT & CALIBRATION

DEFAULT

00: S2K INTERFACE (MOBILE)
01: S2K INTERFACE (DESKTOP)
10: SLOT1 INTERFACE (MOBILE)
11: SLOT1 INTERFACE (DESKTOP)

AD13: RESERVED

DEFAULT

0: ???
1: ???

AD[12] : FLAT PANEL ID MSB
ID4

AD11 : INTERAL CLOCK GENERATOR

0: DISABLE

DEFAULT 1: ENABLE

AD[10..9] : RESERVED[4..3]

DEFAULT

0: ???
1: ???

DEFAULT

0: ???
1: ???

AD8: ENABLE K7 OUTCLK DELAY

0: DISABLE
1: ENABLEDEFAULT

AD[7..4] : FLAT PANEL ID

DEBUG MODE ONLY

1 2

AD23

2 2

AD22

AD21

1 1

AD[0..31]8,16,20,21,22,25,32

A

R44 @10K_0603

1 2

R68 4.7K_0603

1 2

R47 @10K_0603

1 2

R71 4.7K_0603

1 2

R48 @10K_0603

1 2

R72 4.7K_0603

1 2

R49 @10K_0603

1 2

R73 4.7K_0603

AD[0..31]

+3VS

+3VS

+3VS

+3VS

B

AD[23..21] : SKEW ADJUST

DEFAULT

AD20: PCICLK EXPANSION

DEFAULT

R439 @10K_0603

000: ??? DETERMINE DURING

BRING-UP & FIX FOR
PRODUCTION

AD3

AD2

R440 4.7K_0603

R431 @10K_0603
R432 4.7K_0603

R429 @10K_0603

AD1

R430 4.7K_0603

R433 @10K_0603

0: REQ/GNT3 USED AS REQ/GNT
1: REQ/GNT3 USED AS PCICLKS

AD0AD20

ATI 6/19

R434 4.7K_0603

R46 10K_0603

CBE#38,16,20,21,22,25

CBE#3

R70 @4.7K_0603

R183 @10K_0603

CBE#08,16,20,21,22,25

PCI_ACT_REQ#8,17

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

CBE#0

PCI_ACT_REQ#

R184 4.7K_0603
R428 @10K_0603
R427 2.2K_0603

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

+3VS

D

AD3: PCI66 MODE

0: 33MHzDEFAULT
1: 66MHz

AD2: CAL DEFAULTS FOR CPU

0: DISABLEDEFAULT
1: ENABLE

AD1: RESERVED

0: ???DEFAULT
1: ???

AD0 : INTERAL GRAPHICS ENABLE

DEFAULT 0: IF NO EXTERNAL, USE INTERNAL

DEFAULT

DEFAULT

DEFAULT

1: USE INTERNAL BY DEFAULT

PCI_CBE#3 : PRODUCTION TEST

0: SHORT TIMERS FOR PROD TEST
1: NORMAL OPERATION

PCI_CBE#0 : EXTERNAL SIP ROM ENABLE

0: DISABLE
1: ENABLE

PCI_ACT_REQ# : INTERNAL CLOCK GENERATOR(A21 ASIC)

0: DISABLE
1: ENABLE

Compal Electronics, Inc.

Title

ATI MOBILITY U1_STRAP IN PUT

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

10 47

of

0.2

A

B

C

D

E

+2.5V

JP23

4 4

MAA_11
MAA_12

MAA_13
MAA_14

DDR_CS#27,12
DDR_CS#37,12

RDQM[0..7]7,12

3 3

SWE#7,12
SCAS#7,12
SRAS#7,12

CKE7,12

DDRCLK37

DDRCLK#37

DDRCLK47

DDRCLK#47

DDRCLK57

DDRCLK#57

RDQS07,12
RDQS17,12
RDQS27,12
RDQS37,12
RDQS47,12
RDQS57,12
RDQS67,12

2 2

RDQS77,12

SMB_CK_DAT13,17
SMB_CK_CLK13,17

+3VS

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA13
MAA14

MAA11
MAA12

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

SWE#
SCAS#
SRAS#

CKE CKE

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6

SMB_CK_DAT
SMB_CK_CLK

R482 4.7K

1 2

MVREF_DIM2

112
111
110
109
108
107
106
105
102
101
115
100

99
97

117
116

98

121
122

12
26
48

62
134
148
170
184

78
119

120
118

96

95

35

37
160
158

89

91

11

25

47

61
133
147
169
183

77
193

195
194

196
198

1

2
199
197

86

85
123
124
200

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13

BA0
BA1
DU/BA2

CS0
CS1

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8

WE
CAS
RAS

CKE0
CKE1

CK0
CK0
CK1
CK1
CK2
CK2

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

SDA
SCL

SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD

NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU

3

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

GND

GND

GND

GND

GND

15273951637587

VDDQ

VDDQ

GND

GND

VDDQ

GND

103

921334557698193113

131

VDDQ

VDDQ

GND

GND

125

143

VDDQ

GND

137

155

VDDQ

GND

149

157

VDDQ

GND

159

167

VDDQ

GND

161

179

173

1911022343646587082

VDD

VDD

VDD

VDD

VDD

VDD

VDD

GND

GND

GND

GND

GND

VDD

GND

VDDQ

GND

GND

GND

1854162838405264768890

9294114

VDD

VDD

GND

GND

VDD

GND

104

+2.5V

12

R464

1 1

1K_1%

R466

866_1%

C454

0.1UF

MVREF_DIM2

12

C457

0.1UF

MVREF_DIM2

A

R465 @0

C458

0.047UF

close to DIMM2

-CS/-RAS/-CAS/-WE
R - 0101
W - 0100

SDREF 7,35

PC2100 - CL2 = 15 to Data 2-2-2/2.5-3-3

CL2.5 = 18.75 to Data

DDR266 256MB 4Bks Pmax = 8W

64MB/128MB/256MB - 500MB/s - 1.0W

B

192

132

144

156

168

180

Lower Upper

VDD

VDD

VDD

VDD

VDD

VDD

VDDQ

GND

GND

GND

GND

GND

GND

GND

138

150

162

174

126

186

201

Ptyp = 7W

- 1000MB/s - 1.65W

- 1500MB/s - 2.5W

- 2000MB/s - 3.2W

921334557698193113

MAA_11
MAA_12

MAA_13
MAA_14

+3VS

MVREF_DIM1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA13
MAA14

MAA11
MAA12

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

SWE#
SCAS#
SRAS#

RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7

SMB_CK_DAT
SMB_CK_CLK

MVREF_DIM1

R533 @0_0603

C523

0.047UF

close to DIMM1

112
111
110
109
108
107
106
105
102
101
115
100

99
97

117
116

98

121
122

12
26
48

62
134
148
170
184

78
119

120
118

96

95

35

37
160
158

89

91

11

25

47

61
133
147
169
183

77
193

195
194

196
198

1

2
199
197

86

85
123
124
200

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
DU/A13

BA0
BA1
DU/BA2

CS0
CS1

DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
DQM8

WE
CAS
RAS

CKE0
CKE1

CK0
CK0
CK1
CK1
CK2
CK2

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

SDA
SCL

SA0
SA1
SA2
VREF
VREF
VDDID
VDDSPD

NC//DU/RESET
NC/DU
NC/DU
NC/DU
NC/DU

3

SDREF 7,35

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

GND

GND

GND

GND

GND

15273951637587

D

VDDQ

GND

VDDQ

VDDQ

GND

GND

MD0

5

D0

MD1

7

D1

MD2

13

D2

MD3

17

D3

MD4

6

D4

MD5

8

D5

MD6

14

D6

MD7

18

D7

MD8

19

D8

MD9

23

D9

MD10

29

D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

GND

202

MD11

31

MD12

20

MD13

24

MD14

30

MD15

32

MD16

41

MD17

43

MD18

49

MD19

53

MD20

42

MD21

44

MD22

50

MD23

54

MD24

55

MD25

59

MD26

65

MD27

67

MD28

56

MD29

60

MD30

66

MD31

68

MD32

127

MD33

129

MD34

135

MD35

139

MD36

128

MD37

130

MD38

136

MD39

140

MD40

141

MD41

145

MD42

151

MD43

153

MD44

142

MD45

146

MD46

152

MD47

154

MD48

163

MD49

165

MD50

171

MD51

175

MD52

164

MD53

166

MD54

172

MD55RDQS7

176

MD56

177

MD57

181

MD58

187

MD59

189

MD60

178

MD61

182

MD62

188

MD63

190
71

73
79
83
72
74
80
84

GND

DDR_200P_STD_H5.2

1K_1%_0603

866_1%_0603

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

R532

R534

C

+2.5V

MD[0..63] 7,12MAA[0..14]7,12

DDR_CS#07,12
DDR_CS#17,12

CKE7,12

DDRCLK07

DDRCLK#07

DDRCLK17

DDRCLK#17

DDRCLK27

DDRCLK#27

12

C521

0.1UF

MVREF_DIM1

12

C522

0.1UF

103

+2.5V

JP5

VDD

GND

132

126

VDD

GND

192

144

156

168

180

VDD

VDD

VDD

VDD

VDDQ

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

GND

GND

GND

GND

GND

GND

GND

138

150

162

174

186

201

202

DDR_200P_RVS_H4.0

InsightOutsight

E

179

131

143

155

157

167

1911022343646587082

VDD

VDD

VDD

VDDQ

GND

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

GND

GND

GND

GND

GND

GND

GND

GND

GND

125

137

149

159

161

173

1854162838405264768890

Compal Electronics, Inc.

Title

DDR SODIMM Modules

Size Document Number Rev

LA-1481 M/B

Date: Sheet

VDD

VDD

VDD

GND

GND

GND

!"#, $%

VDD

GND

9294114

VDD

VDD

GND

GND

14, 2002

VDD

GND

VDD

GND

104

MD0

5

MD1

7

MD2

13

MD3

17

MD4

6

MD5

8

MD6

14

MD7

18

MD8

19

MD9

23

MD10

29

MD11

31

MD12

20

MD13

24

MD14

30

MD15

32

MD16

41

MD17

43

MD18

49

MD19

53

MD20

42

MD21

44

MD22

50

MD23

54

MD24

55

MD25

59

MD26

65

MD27

67

MD28

56

MD29

60

MD30

66

MD31

68

MD32

127

MD33

129

MD34

135

MD35

139

MD36

128

MD37

130

MD38

136

MD39

140

MD40

141

MD41

145

MD42

151

MD43

153

MD44

142

MD45

146

MD46

152

MD47

154

MD48

163

MD49

165

MD50

171

MD51

175

MD52

164

MD53

166

MD54

172

MD55

176

MD56

177

MD57

181

MD58

187

MD59

189

MD60

178

MD61

182

MD62

188

MD63

190
71

73
79
83
72
74
80
84

11 47

of

0.5

A

B

C

D

E

Decoupling capacitors

(Place near DDR SODIMM)

+2.5V

CB75 1UF_10V_0603
CB76 1UF_10V_0603
CB72 1UF_10V_0603

4 4

3 3

2 2

1 1

CB74 1UF_10V_0603
CB77 1UF_10V_0603

+2.5V

10UF_10V_1206

CB65

10UF_10V_1206CB73
10UF_10V_1206CB70
10UF_10V_1206CB71

Place these decoupling capacitors close to
VTT_MEM termination resistors.

+1.25VS

0.1UFC276

0.1UFC277

0.1UFC278 C266 @47PF

0.1UFC279

0.1UFC280

0.1UFC281

0.1UFC282

0.1UFC283

+1.25VS

C292 0.015UF
C293 0.015UF
C294 0.015UF
C295 0.015UF
C296 0.015UF
C297 0.015UF

A

+2.5V

+1.25VS

+

CE17 100UF_D_16V

+

CE10 100UF_D_16V

0.1UFC242

0.1UFC241

0.1UFC243

0.1UFC244

0.1UFC249

0.1UFC250

0.1UFC252

0.1UFC251

0.1UFC254

0.1UFC253

+1.25VS

C289
C290

1000PFC284
1000PFC285
1000PFC286
1000PFC287
1000PFC288
1000PF
1000PF
1000PFC291

RDQS07,11

RDQS17,11

RDQS27,11

RDQS37,11

RDQS47,11

RDQS57,11

RDQS67,11

B

Termianation Network place closely to DIMM

MD0
MD4
MD1
MD5
RDQS0
MD6
MD2
MD3
MD7
MD8
MD12
MD9
MD13
RDQS1
MD10
MD14
MD11
MD15
MD16
MD20
MD17
MD21
RDQS2
MD18
MD22
MD19
MD23
MD24
MD28
MD25
MD29
RDQS3
MD26
MD30
MD27
MD31
MD32
MD36
MD33
MD37
RDQS4
MD38
MD34
MD39
MD35
MD44
MD40
MD45
MD41
RDQS5
MD42
MD46
MD43
MD47
MD48
MD52
MD49
MD53
RDQS6
MD54

MAA10
MAA12

RP60

1 8
2 7
3 6
4 5

RP59

1 8
2 7
3 6
4 5

RP58

1 8
2 7
3 6
4 5

RP57

1 8
2 7
3 6
4 5

RP56

1 8
2 7
3 6
4 5

RP55

1 8
2 7
3 6
4 5

RP54

1 8
2 7
3 6
4 5

RP53

1 8
2 7
3 6
4 5

RP52

1 8
2 7
3 6
4 5

RP51

1 8
2 7
3 6
4 5

RP50

1 8
2 7
3 6
4 5

RP49

1 8
2 7
3 6
4 5

RP62

1 8
2 7
3 6
4 5

RP48

1 8
2 7
3 6
4 5

RP61

1 8
2 7
3 6
4 5

C272 10UF_0805
C273 10UF_0805
C275 10UF_0805
C274 10UF_0805

Layout:average placement the CAP
near the +1.25VS power plane .

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

RP444P2R_33

1 2
1 2
1 2
1 2

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

1 4
2 3

+1.25VS

C318

0.1UF

C317

0.1UF

C315

0.1UF

C313

0.1UF

C320

0.1UF

C310

0.1UF

C308

0.1UF

+2.5V+1.25VS

C

+1.25V Island
> 150ml

C319
1000PF

C316
1000PF

C314
1000PF

C312
1000PF

C311
1000PF

C309
1000PF

C307
1000PF

MD[0..63]7,11
MAA[0..14]7,11

RDQS77,11

RDQM07,11
RDQM17,11
RDQM27,11
RDQM37,11
RDQM47,11
RDQM57,11
RDQM67,11
RDQM77,11

CKE7,11

SRAS#7,11

SWE#7,11

SCAS#7,11
DDR_CS#27,11
DDR_CS#37,11
DDR_CS#07,11
DDR_CS#17,11

D

MD[0..63]
MAA[0..14]

MD50
MD55
MD51
MD60
MD56
MD61
MD57
RDQS7
MD62
MD58
MD63
MD59

MAA14
MAA13
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MAA11

RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
RDQM7

CKE
SRAS#
SWE#
SCAS#
DDR_CS#2
DDR_CS#3
DDR_CS#0
DDR_CS#1

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
MAA14

SRAS#
SCAS#
SWE#
CKE
DDR_CS#0
DDR_CS#1
DDR_CS#2
DDR_CS#3

ATI recomend .

+1.25VS

RP47

1 8
2 7
3 6
4 5

RP46

1 8
2 7
3 6
4 5

RP45

1 8
2 7
3 6
4 5

RP65

1 8
2 7
3 6
4 5

RP63

1 8
2 7
3 6
4 5

RP64

1 8
2 7
3 6
4 5

R503 56

R512 56
R511 56
R514 56
R513 56
R505 56
R504 56
R510 56
R509 56

R508 56
R359 56
R501 56
R506 56
R507 56
R360 56
R361 56
R502 56

C264 @47PF

1 2
1 2

C268 @47PF

1 2

C246 @47PF

1 2

C270 @47PF

1 2

C239 @47PF

1 2

C247 @47PF

1 2

C259 @47PF

1 2

C236 @47PF

1 2

C261 @47PF

1 2

C238 @47PF

1 2

Title

Size Document Number Rev

Date: Sheet

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

8P4R_56_0804

C258 @47PF

1 2

C265 @47PF

1 2

C267 @47PF

1 2

C245 @47P

1 2

C269 @47PF

1 2

C263 @47PF

1 2

C262 @47PF

1 2

C248 @47PF

1 2

C235 @47PF

1 2

C240 @47PF

1 2

C237 @47PF

1 2

C260 @47PF

1 2

Compal Electronics, Inc.

DDR SDRAM Terminations

LA-1481 M/B

!"#, $%

14, 2002

C306

0.1UF

C304

0.1UF

C302

0.1UF

C301

0.1UF

C299

0.1UF

E

C305
1000PF

C303
1000PF

C321
1000PF

C300
1000PF

C298
1000PF

12 47

0.5

of

A

Note: Overlap common pads where
possible for dual-op resistors.

L43

HB-1M2012-121JT

CB44

C211

0.1UF

+

PCICLK_STP#9,17

CPUCLK_STP#9,17

+3VS

C176

0.1UF

4 4

CLK_VDD

3 3

CB43
10UF_10V_1206

10UF_10V_1206

C182

0.1UF

C178

C203

0.001UF

0.1UF

CLK_VDD

SMB_CK_DAT11,17

SMB_CK_CLK11,17

+3VS

R313 @0

1 2

R312 10K

1 2

C188

C191

0.1UF

0.1UF

R321 10K
R305 10K

B

CLK_AVDD

L53
HB-1M2012-121JT

1 2
1 2

C207

0.1UF

Main Clock Generator

+3VS

(ICS:ICS951403)

U13

SMB_CK_DAT

SMB_CK_CLK

FS2
SPREAD#

34
45

18

9
15
22
48

27

26

30
32

31
28
29
44
35

33
41
38
47
21
12

6
25

AVDD
VDDSD

VDDAGP
VDDPCI
VDDPCI
VDD48
VDDREF

SDATA

SCLK

PWR_DWN#
PCI_STOP#

CPU_STOP#
FS2
SPREAD#
RSVD
RESET#

AVSS
GNDCPU
GND
GNDSD
GNDAGP
GNDPCI
GNDPCI
GND48

CPUCLKC0
CPUCLKC1
CPUCLKC2
CPUCLKT0
CPUCLKT1
CPUCLKT2

SDRAM_OUT

AGP0

AGP1
PCICLK0
PCICLK1
PCICLK2
PCICLK3

PCICLK4

PCICLK5

PCICLK6

PCICLK_F

48MHz

24-48MHz

FS0/REF0
FS1/REF1GNDREF

37
40
43
36

R_CPUCLK_NB_EXT

39
42
46

19
20

8

PCI1 PCLK_MINI

10

PCI2

11

PCI3

13

PCI4

14

16

17

PCICLKF_EXT PCICLKF_EXT_SB

7
23

USBIOCLK_EXT

24

FS0

1

FS1

23

C

Damping Resistors
Place near to the
Clock Generator

R297

R300
R294

R282
R318

R284
R293
R296
R299

R302

R310

R281
R331

24/48MHz select

R272
R276

+2.5VS

12

R290

68

CPUCLK#R_CPUCLK#

10

CPUCLKR_CPUCLK

10

CPUCLK_NB_EXT

10

SDCLK_NB_EXTR_SDCLK_NB_EXT

39

AGPCLK_EXTR_AGPCLK_EXT

22

PCLK_NB_EXTR_PCLK_NB_EXT

22
22

PCLK_PCM

22

PCLK_1394

22

PCLK_LAN

22

EC_PCLKR_EC_PCLK

22

22

UCLK48MR_UCLK48M

22

REFCLK1_NB

75

CLK_14M_SIO

33

Close to NB ATI-U1

D

CPUCLK# 3

CPUCLK 3
CPUCLK_NB_EXT 9

SDCLK_NB_EXT 9
AGPCLK_EXT 9

PCLK_NB_EXT 9
PCLK_MINI 25
PCLK_PCM 22
PCLK_1394 21

PCLK_LAN 20

EC_PCLK 27

PCICLKF_EXT_SB 16
UCLK48M 16

REFCLK1_NB 9
CLK_14M_SIO 17

By-Pass Capacitors
Place near to the Clock Generator

CPUCLK
CPUCLK#
CPUCLK_NB_EXT
SDCLK_NB_EXT
AGPCLK_EXT
PCLK_NB_EXT
PCLK_MINI
PCLK_PCM
PCLK_1394
PCLK_LAN
EC_PCLK
PCICLKF_EXT_SB
UCLK48M
REFCLK1_NB
CLK_14M_SIO

ICS RECOMMEND

C201 5PF_0.25%

C197 5PF_0.25%

C194 @10PF

C185 @10PF

C210 @10PF

C187 @10PF

C193 @10PF

C196 @10PF

C199 @10PF

C202 @10PF
C208 27PF

C184 @10PF

C214 @10PF

C172 100

C179 @10PF

E

Brian 6/27

XTALIN

C180
12PF

4

14.318MHz

+3VS

12

R332
10K

FS2

13

D

Q5

2 2

FSB_100/133#4,10

2

G

@2N7002

S

+3VS

2

G

Q3
@2N7002

12

R4
@10K

R12 @10K

1 2

13

D

Q4
@2N7002

S

+3VS

12

R3
@100K

13

D

2

G

S

ICS951403

FS0

XTALOUT

5

X5

C186
12PF

Jason recommend

+3VS

Frequency Selection

R275 @10K

1 2

R273 @10K

1 2

R333 @10K

1 2

R329 @10K

1 2

R327 @10K

1 2

R277 8.2K

1 2

R274 8.2K

1 2

R334 @8.2K

1 2

R330 8.2K

1 2

R328 8.2K

1 2

FS0/FS2 define by EC

FS0
FS1
FS2
USBIOCLK_EXT
SPREAD#

ICS951403 FREQUENCY SELECTION

FS2 FS1 FS0 CPU SDRAM PCICLK AGP

0 0 1 100 133.33 33.33 66.67
1 0 0 133.33 133.33 33.33 66.67

0 0 0 100 100 33.33 66.67
0 1 0 100 150 30 60
0 1 1 100 66.67 33.33 66.67
1 0 1 125 100 31.25 62.50
1 1 0 124 124 31 62
1 1 1 133.33 100 33.33 66.67

OTHER CONFIGURATION OPTIONS

24/48MHZ SELECTION ON = 48MHZ OFF = 24MHZ

ON = ENABLEDSPREAD SPECTRUM OFF = DISABLED

Place near to the CLK GEN CHIP (U13) .

1 1

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Clock Generator

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

13 47

of

0.3

A

1 1

RED9

GREEN9

BLUE9

R392

75_1%_0603

HSYNC9

VSYNC9

CRTVDD

2 2

R387
@10K

12

75_1%_0603

12

12

12

R393

75_1%_0603

12

R389
@10K

+12VS

@@ @

12

12

C338

R394

@22PF

S

Q44

G

2N7002

2

1 2

R388 100K

C337
@22PF

D

13

Q45
2N7002

S

G

2

L3

1 2

FCM2012C-800_0805

L4

1 2

FCM2012C-800_0805

L5

1 2

FCM2012C-800_0805

12

C336
@22PF

1 2

FBM-11-160808-121

D

1 2

13

FBM-11-160808-121

B

+5VS

D27

DAN217

1

2

R_RED

R_GREEN

R_BLUE

12

C1
18PF

L1

L2

D28

DAN217

1

2

3

12

C4
68PF

3

12

C2
18PF

12

C5
68PF

CRTVDD

D29

DAN217

1

2

12

C3
18PF

POLYSWITCH_0.5A

3

C329
100PF

F1

12

CRTVDD_1

DDC_MD2

C

MSEN#27,28

C6
220PF

12

D1

2 1

RB411D

12

C7
220PF

C11

0.1UF

D

W=40mils

12

11

12

13

14
10

15

6
1

7
2

8
3

9
4

5

JP15
CRT-15P

R8

2.2K

CRTVDD

12

12

R9

2.2K

+3VS

12

12

R536

R535

2.2K

2.2K

Q1
2N7002

D

S

Q2
2N7002

D

1 3

2

G

1 3

S

G

2

1 2

R7 0

DDCDATA 9,15

DDCCLK 9,15

+3VS

E

CRT Connector

TV-Out Connector

3 3

1 2

C23 47PF

LUMA9

CRMA9

COMPS9

4 4

LUMA

CRMA R_CRMA

COMPS

12

R13

75_1%_0603

A

12

R2

75_1%_0603

12

R6

75_1%_0603

12

C25
150PF

12

1 2

FBM-11-160808-121

1 2

C13 47PF

1 2

FBM-11-160808-121

C14
150PF

L11

L6

12

C42
150PF

B

D4

DAN217

2

R_LUMA

D3

DAN217

1

1

3

2

D2

DAN217

1

+3VS

3

2

3

S-Video

JP14

1
2
3
4
5
6
7

S CONN._suyin

12

C12
270PF

12

C15
270PF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

C

EMI PAD around RAM DOOR

PAD4

PAD-2.5X3

H1
HOLEA

1

H16
HOLEA

1

1

1

1

FM1

CF2

CF9

H4
HOLEA

H17
HOLEA

1

1

PAD5

1

PAD-2.5X3

H3
HOLEA

1

1

H10

H13

HOLEA

HOLEA

1

FM2

FM3

1

CF4

1

CF10

CF11

1

1

1

1

1

H2
HOLEA

1

FM4

1

PAD2

PAD-2.5X3

H5
HOLEA

1

H6
HOLEA

1

FM5

1

CF31CF61CF7

CF12

1

H9
HOLEA

H8
HOLEA

1

FM6

PAD1

PAD-2.5X3

1

H7
HOLEA

1

H12
HOLEA

1

1

H18
HOLEA

1

CF8

1

H15
HOLEA

1

H19
HOLEA

1

1

H11
HOLEA

1

1

1

CF13

D

Cable guide

PAD6

PAD-3X3.5

PAD3

1

PAD-2.5X3

H14
HOLEA

1

H20
HOLEB

1

CF1

1

1

CF5

Compal Electronics, Inc.

Title

CRT & TVout Connector

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

1

14, 2002

PAD7

PAD-3X3.5

1

PAD-3X3.5

E

PAD8

14 47

1

0.3

of

10

DDCCLK9,14

H H

DDCCLK

TXOUT_L0+9

TXOUT_L1+9
TXOUT_U0-9

TXOUT_U0+9

TXCLKOUT_U-9

TXCLKOUT_U+9

G G

PID0

PID010,28

PID1 PID2

PID110,28

PID2

PID210,28

PID3

PID310,28

F F

9

LCDVDD_C

R25 @0

TXOUT_L0-9

TXOUT_L1-9

+3VS

RP2

4 5
3 6
2 7
1 8

8P4R_10K_0804

1 2

TXOUT_L0­TXOUT_L0+

TXOUT_L1­TXOUT_L1+

TXOUT_U0­TXOUT_U0+

TXCLKOUT_U­TXCLKOUT_U+

PID3
PID2
PID1
PID0

+12VS

PID3
PID1

PID0

8

JP2

1

21

2

22

3

23

4

24

5

25

6

26

7

27

8

28

9

29

10

30

11

31

12

32

13

33

14

34

15

35

16

36

17

37

18

38

19

39

20

40

JST BM40B-SRDS

SW3

4
3
2
1

SW DIP-4

R1 @0

5
6
7
8

7

TXOUT_L2­TXOUT_L2+

TXCLKOUT_L­TXCLKOUT_L+

TXOUT_U1­TXOUT_U1+

TXOUT_U2­TXOUT_U2+

DISPOFF#

L25

HB-1M2012-121JT

L26 HB-1M2012-121JT

CB3 1UF_10V_0603
CB2 4.7UF_10V_0805

TXOUT_L2- 9
TXOUT_L2+ 9

TXCLKOUT_L- 9
TXCLKOUT_L+ 9

TXOUT_U1- 9
TXOUT_U1+ 9

TXOUT_U2- 9
TXOUT_U2+ 9

1 2

LCDVDD_C

DAC_BRIG 27

INVT_PWM 27

1 2
1 2

C448 0.1UF

1 2
1 2

+

EMI request

H

DDCDATA

B+

LCDVDD

DDCDATA 9,14

BKOFF#27

LVDS_BLON#9

6

HB-1M2012-121JT

HB-1M2012-121JT

D9

FB1

FB2

CB22

10UF_10V_1206

+3VS

RB751V

21

13

2

G

Q60

2N7002

R110
10K

DISPOFF#

D

S

12

+

5

CB4
1UF_10V_0603

12

LCDVDD_C

C16

0.1UF

4

12

C41

3

2

1

0.1UF

+3VSLCDVDD

LCDVDD +12VS

12

R33
1K

E E

Q10

2N7002

13

D

2

G

S

R58
100K

100K

Q12
2N7002

C70

0.047UF

C51

0.1UF

R52
150K

13

D

2

G

S

R59

13

Q9
SI2302DS

2

+

CB18

4.7UF_10V_0805

+

CB17

4.7UF_10V_0805

13

2

Q11

DTC124EK

22K

22K

Compal Electroni c s, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

9

8

7

6

5

4

Title

LVDS & PID CONN.

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet of

3

14, 2002

2

15 47

1

0.3

LCD_DIGON9,27

D D

C C

B B

A A

LCD_DIGON

10

A

RP20

8P4R_33_0804

1 8

RP18

8P4R_33_0804

1 8

PCICLKF_EXT_SB13

1 2

Put near SB
ALI1535+
Chip.

1 2

C547

PM_CLKRUN#
PAR

18
27
36
45

18
27
36
45

C142 @10PF

34

100PF

+3VALW

USB0_D+29

USB0_D-29

USB1_D+29

USB1_D-29

RP19

8P4R_15K_0804

4 4

USB2_D+29

USB2_D-29

USB3_D+26

USB3_D-26

RP17

8P4R_15K_0804

ALI 5/28

3 3

2 2

RP9

8P4R_8.2K_0804

PIRQB#

4 5

PIRQA#

3 6

PIRQD#

2 7

PIRQC#

1 8

1 1

SERR#
STOP#
DEVSEL#
TRDY#
IRDY#
FRAME#
PERR#

RP16

8P4R_8.2K_0804

4 5
3 6
2 7
1 8
4 5
3 6
2 7
1 8

RP15

8P4R_8.2K_0804

3 6

4 5

3 6

4 5

R153 10K

+3VS

PCIRST#6,19,20,21,22,23,25,26,27

+3VS

+3VS

2 7

2 7

A

UV0+
UV0­UV1+
UV1-

CP2
8P4C-47P

1 8

2 7

3 6

4 5

UV2+
UV2­UV3+
UV3-

CP1
8P4C-47P

1 8

2 7

3 6

4 5

R163 @33

12

1

2

U5
7SH08

5

AD[0..31]8,10,20,21,22,25,32

CBE#[0..3]8,10,20,21,22,25

PERR#20,21,22,25

R182 10K

1 2

R152 2.2K

1 2

C110 10PF

+3VS

IGNNE#3

CPURST#3,6

FERR#3

12

R159

4.7K

AD[0..31]

FRAME#8,20,21,22,25

TRDY#8,20,21,22,25

IRDY#8,20,21,22,25
STOP#8,20,21,22,25

DEVSEL#8,20,21,22,25

SERR#8,20,22,25

PAR8,20,21,22,25
PIRQA#8,22
PIRQB#20,22,25

PIRQC#21
PIRQD#25

+3VS
PCI_SBGNT#8
PCI_SBREQ#8

AGP_BUSY#9

AGP_STP#9

PERR#

1 2

INIT#3

12

+3VS

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

B

OVCUR#129
OVCUR#029

R109 33

1 2

UCLK48M13

SMI#3

R198 10K

STPCLK#3

1 2

A20M#3

NMI3

INTR3

R205 0

FERR#

E8
C5

G2

F1
F2
F3
E1
E2
E3
D1
D3
C1
B1
A1
C2
B2
A2
C3
E6
D6
C6
B6
A6
E7
D7
C7
A7
D8
C8
B8
A8
C9
B9
A9

CBE#3
CBE#2
CBE#1
CBE#0
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
SERR#
PAR
PIRQA#
PIRQB#
PIRQC#
PIRQD#

R126 8.2K

R108 8.2K

PCI_SBGNT#
PCI_SBREQ#

A20M#

1 2

C14

U6A

PCICLK
PCIRSTJ
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

D2

A12

FERRJ

PCI

CBEJ2

CBEJ1

CBEJ0

FRAMEJ

TRDYJ

IRDYJ

CBEJ3

B3A5B7A3C4D4A4B4D5B5F4F5G3G4G5H4A10

1 2
1 2

B

B13

INIT

CPURST

STOPJ

DEVSELJ

C13

B12

IGNNEJ

HOST

SERRJ

INTEJ
INTFJ

INTR

PAR

C12

NMI

UV3­UV3+
UV2­UV2+
UV1­UV1+
UV0­UV0+

L2_ZZ

A14

B14

A20MJ

INTAJ_M1

C

LAYOUT:RP78,RP80,CP1,CP2 close to SB(U10)
LAYOUT:RP79,RP81 close to USB Conn.

OVCUR#2 29

OVCUR#3

R143 10K

1 2

+3VALW

+3VS+3VS+5VALW

D12

E12

A13

H5W8V8U9Y7

ZZ

SMIJ

USBP0-

SLEEPJ

USBP0+

USBCLK

STPCLKJ

W7V7U8T8T6U5U6

USBP1-

USBP2-

USBP1+

USBP2+

USBP3+

T5

R6

USBP3-

OVCRJ0

OVCRJ1

OVCRJ2

OVCRJ3

F15

R13

R7

R14

R8

VCCR_3E

VCCR_3E

VCCR_3E

VCCR_5D

VCCR_5D

P15

F14

F6

P6N6F7

VCC_G

VCC_3C

VCC_3C

VCC_3C

VCC_3C

+3VS +5VS

G15

K16

VCC_F

VCC_F

VCC_3B

+5VS

IDEDA8

IDEDA4

IDEDA7

IDEDA9

IDEDA5

IDEDA3

IDEDA13

IDEDA12

IDEDA15

IDEDA14

G18

G16

E10

R15

G6

N15

VCC_5A

VCC_5A

VCC_5A

F19

VCC_5A

VCC_5A

PIDED15

PIDED14

PIDED13

IDEDA6

IDEDA10

IDEDA11

F17

E20

E18

D19

C20

B20

D18

D20

E19

PIDED9

PIDED8

PIDED7

PIDED6

PIDED5

PIDED12

PIDED11

PIDED10

PIDED4

USB

PRIMARY IDE

ALI M1535

SECONDARY IDE

INTBJ_S0

INTCJ_S1

INTDJ_S2

INTEJ

INTFJ

PHLDAJ

PHOLDJ

C11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

AGPBUSYJ

AGPSTPJ

D11

E11D9E9

SIDEIOWJ

SLOWDOWN

GPI25

CLKRUNJ

D17

A11

PM_CLKRUN#

+3VS

12

R169
330

SIDECS1J

SIDEDRQ

SIDEDAKJ

SIDERDY

SIDEIORJ

C19

C17

B18

A18

E17

R181 @0

R168 10K

SIDECS3J

GND

GND

A20

H10

H9

IDEREQB

1 2

C

GND

GND

H12

H11

ACIN_SYS

H13

GND

J8

GND

J9

GND

GND

J10

GND

GND

J11

J12K9K10

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

K11

K12L9L10

L11

L8

K13

K8

J13

IDECS#B3 19
IDECS#B1 19
IDEREQB 19
IDACK#B 19
ICHRDYB 19
IDEIOR#B 19
IDEIOW#B 19
PM_CLKRUN# 9,18,22,25,27

GND

GND

GND

L12M9M10

M8

L13

GND

GND

GND

GND

GND

GND

M11

M12

D

IDEDA2

F16

F18

PIDED3

PIDED2

PIDECS3J
PIDECS1J

PIDEDRQ

PIDEDAKJ

PIDERDY
PIDEIORJ

PIDEIOWJ

GND

GND

N9N8M13

H8

D

IDEDA0

IDEDA1

F20

G17

PIDED1

PIDED0

PIDEA2
PIDEA1
PIDEA0

SIDED15
SIDED14
SIDED13
SIDED12
SIDED11
SIDED10

SIDED9
SIDED8
SIDED7
SIDED6
SIDED5
SIDED4
SIDED3
SIDED2
SIDED1
SIDED0

SIDEA2
SIDEA1
SIDEA0

GND
GND
GND
GND

IDEDA[0..15]

J16
H19
H20
J18
J17
G19
H18
H17
H16
G20

B17
E16
C16
A16
D15
B15
E14
D13
E13
D14
A15
C15
E15
B16
D16
A17
B19
C18
A19
N13
N12
N11
N10

M1535+

IDESAB[0..2]
ACIN_SYS

E

IDEDA[0..15] 19

+3VS +3VS

+3VS+3VS

Put near SB
ALI1535+
Chip.

IDESAA[0..2]

IDESAA2
IDESAA1
IDESAA0

IDEREQA

IDEDB15
IDEDB14
IDEDB13
IDEDB12
IDEDB11
IDEDB10
IDEDB9
IDEDB8
IDEDB7
IDEDB6
IDEDB5
IDEDB4
IDEDB3
IDEDB2
IDEDB1
IDEDB0
IDESAB2
IDESAB1
IDESAB0

12

C541

0.1UF

IDECS#A3 19
IDECS#A1 19
IDEREQA 19
IDACK#A 19
ICHRDYA 19
IDEIOR#A 19
IDEIOW#A 19

2 1

@RB751VD19

Compal Electronics, Inc.

Title

ALI 1535+ SOUTH BRIDGE -1

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

12

12

C542

0.1UF

IDESAA[0..2] 19

IDEDB[0..15]

IDESAB[0..2] 19
ACIN 27,34,37

14, 2002

C543

0.1UF

+5VS +5VS

12

C544

0.1UF

IDEDB[0..15] 19

E

12

C545

0.1UF

16 47

of

12

C546

0.1UF

0.3

R164 4.7K

+3VALW

R171 10K

+3VALW

RTCX2

12

C130
12PF

SCKP4
SDAP4

@2N7002

+3VS

SCKP4
SDAP4 SMB_CK_DAT

PWRGD18,30

R135 100K

+3VS

+5VS

+5VS

R128 4.7K

+5VS

1 2

1 2

X4

32.768KHZ

RTCX1

R133
10M_0603

1 3

Q14

@2N7002

2

1 3

Q13

2

R82 @10K

1 2

R89 @10K

1 2

R84 0

1 2

R81 0

1 2

R266 4.7K
R257 @4.7K
R239 @4.7K

GPO34
GPO35

12

PWRBTN_OUT#27

R213 4.7K

1 2

1 2

C148
@0.1UF

1 2

1 2

R544

R545 10K

1 2

R546 10K

1 2

R547 10K

1 2

R119 2.2K

1 2

R120 2.2K

1 2

R548 10K

1 2

R549 1K

1 2

SD718
SD618
SD518
SD418
SD318
SD218
SD118
SD018

12

12

R87 @100K

R113
20M_0603

C113
12PF

SMB_CK_CLK
SMB_CK_DAT

SDAP4
SCKP4
SMB_CK_CLK

IOCHRDY
LDRQ#0
LFRAME#

IDERST_CD# 19
IDERST_HD# 19

R242 10K

+5VS

3MODE#26

INDEX#26

TRACK0#26

WP#26
MTR0#26
DRV0#24,26

DSKCHG#26

STEP#26
FDDIR#26
HDSEL#26

WDATA#26

RSM_RST

R197 10K

+5VALW

LRCLK

TESTJ
SDAP4 LLBJ
SCKP4
SMBALT#

R202 10K
R219 10K

SLP_S5#27
SLP_S3#27
SLP_S1#27

SUS_STAT#6,28

PCI_ACT_REQ#8,10

CPUCLK_STP#9,13

PCICLK_STP#9,13

RSM_RST27

C146 0.1UF

U6B

E5

1K

+12VS

LRCLK

E4

SCLK

T3

PCMDATA

U3

ACGP_UP

R5

ACGP_DOWN

U2

ACGP_MUTE

Y2

ACGAME7

Y1

ACGAME6

W3

ACGAME5

W2

ACGAME4

W1

ACGAME3

V3

ACGAME2

V2

ACGAME1

V1

ACGAME0

R4

ACMID_TXD

T4

ACMID_RXD

W5

FANOUT1

V5

FANOUT2

Y5

FANIN2

U4

TESTJ

U7

SMBDATA

T7

SMBCLK

T2

SMB_ALERT

W19

XD7

Y19

XD6

V20

XD5

W20

XD4

Y20

XD3

U18

XD2

U19

XD1

U20

XD0

SMB_CK_CLK 11,13
SMB_CK_DAT 11,13 LFRAME# 27

SA[4..18]18
LAD[0..3]18,27

SMB_CK_DAT
SMB_CK_CLK
LFRAME#
LDRQ#0

AC97_SDIN0
AC97_SDIN1

RUNENT2

RUNENT3

WGATE#26

RDATA#26

PWRBTN_OUT#
OFF_PWR2
OFF_PWR1
OFF_PWR0

SLPBTNJ
RSM_RST

W10

U10

V10

B10

PWG

PCISTPJ

SLPBTNJ

RSM_RSTJ

ZV

VOLUME CONTROL

GAME PORT/MIDI PORT

SM BUS

BIOSA18

BIOSA17

BIOSA16

SA15

SA14

SA13

T15

U15

V15

W15

T16

U16

SA14

SA13

SA18

SA17

SA16

SA15

SA[4..18]
LAD[0..3]

R86 10K

1 2

R88 10K

1 2

R256 10K

1 2

R309 10K

1 2

R170 @4.7K
R165 @4.7K

R269

R263

10K

2 1

10K

2 1

C10

B11

PCIREQJ

CPUSTPJ

SA12

SA11

V16

W16

SA12

SA11

RB751VD21

RB751VD20

INDEX#
TRACK0#
WP#
MTR0#
DRV0#
DSKCHG#
STEP#
FDDIR#
HDSEL#
WDATA#
WGATE#
RDATA#

W14

Y14

V14

W13

SUSPENDJ

OFF_PWR0

OFF_PWR1

OFF_PWR2

ISA BUS

SA10

SA9

SA8

SA7

Y16

R17

T17

U17

SA9

SA10

SA7

SA8

MEMR#18
MEMW#18

FLASH#28

IDEIRQA19
IDEIRQB19

+3VS

12

M18

Y15

RDATAJ

PWRBTNJ

SA6

SA5

SA4

SA3

V17

W17

Y17

V18

LAD3

SA6

SA5

SA4

IOR#18

IOW#18

SIRQ18,22,27

ACPWR

+3VS

PM_BATLOW# 27

+3VS

EC_THERM# 27

L19

W18

LAD2

L18

M19

L16

L17

M20

K19

K20

K17

K18

M16

L20

J20

WGATEJ

WDATAJ

STEPJ

HDSELJ

FD_DIRJ

DSKCHGJ

TRK0J

DRV0J

DRV1J

MOT0J

MOT1J

WPROTJ

ALI M1535

SA2

SA1

SA0

IORJ

Y18

V19

T13

LAD1

LAD0

SIRQ
IDEIRQA
IDEIRQB

R270

MEMRJ

MEMWJ

IOWJ

T14

U14

U13

2 1

APICREQJ

APICCSJ

M17

N17

N18

IOCHRDY

AEN

GPO29

10K

RB751VD22

APICGNTJ

RXDA
TXDA
RTSA#
DTRA#
CTSA#
DSRA#
DCDA#
RIA#

PD0

LPTAFD#
LPT_INIT#
LPTSLCTIN#
LPTSTB#
LPTBUSY
LPTACK#
LPTPE
LPTSLCT
LPTERR#
LPD[0..7]

12

R106
1K

DTR#2

DSR#2

RXD2

CTS#2

RTS2J

J19H2K4J5K2H1K3J3L2J4K1H3K5G1J1J2L1

SIN2

RTS2J

CTS2J

DTR2J

DSR2J

SOUT2

INDEXJ

DENSEL

LPD7
LPD6
LPD5
LPD4
LPD3
LPD2
LPD1

PD6

PD5

PD4

PD3

PD2

LPD0

PD1

DCD#2

RI#2

R1R2R3P1M4M3M5L5T1M2N5N4N3N2N1P3P2

PE

RI2J

SIN1

DCD2J

SOUT1

RI1J

RTS1J

CTS1J

DTR1J

DSR1J

DCD1J

PRINITJ

STROBJ

SLCTINJ

AUTOFDJ

BUSY

PRNACKJ

SLCT

ERRORJ

PD7

SIO/PIOFDD

IR

ACSDATA_IN1

AC LINK

IRQSER

N19

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

PCS1J

SIRQI

SIRQII

THRMJ

SQWO

N16

P16

T18

V6

R16

SQWO

PCS1J

12

R254

4.7K

+5VALW
AC_IN 27

OSC14M

OSC32KI

OSC32KII

CLK32KO

PCS0J

D10W6Y6

V13

P20

PCS0J

RTCX1

RTCX2

CLK_14M_SIO

R172
33

1 2

C144
10PF

1 2

ROMKBCSJ

LDRQJ

LFRAMEJ

GPIRJ

GPOW

T20

P17

N20

P18

P19

LDRQ#0

GPO35

BIOSCS#

GPO34

LFRAME#

OFFCDPWR

PCS0J

R20

RTCAS

RTCAS

R19

RTCRW

RTCRW

R18

RTCDS

RTCDS

KBCLK

KBDATA

KBINH

MSCLK

U11

U12

V12

T11

CLK_14M_SIO 13
RTCCLK 22

R142 4.7K

Disable 4Mb ROM

R238 @10K
R255 1K

Enable 4Mb ROM

MSDATA

T12

MSCLK
KBDATA
KBCLK
IRQ1

ACSDATA_IN0

ACBIT_CLK

ACSDATA_OUT

USBP_PWRENJ

OFF_CDPWR

+5VS

M1

IRTX

L3

IRRX

L4

IRRXH

Y8
Y9

ACRESETJ

P4

ACSYNC

W9
P5
U1
T19

SPKR

Y13

SPLED

Y12

IRQ8J

Y10

ACPWR

W12

PMEJ

V11

RIJ

W11

LBJ

Y11

LLBJ

T10

UPSPWR

V9
T9

Y4

RUN_ENT3

W4

RUN_ENT2

V4

RUN_ENT1

Y3

RUN_ENT0

M1535+

IRQ12 18

IRQ1 18

LDRQ#0 27

KBDATA
MSCLK
KBCLK
RUNENT0

EXTSMI#

SET OFF_PWR 0,1,2 ACTIVE
LOW

IRRX

AC97_SDIN1
AC97_RST#
AC97_SYNC
AC97_SDIN0
AC97_BCLK
AC97_SDOUT

SPLED
IRQ8#
ACPWR

SWI#
EXTSMI#

OFFCDPWR

RUNENT3
RUNENT2

RUNENT0

8P4R_4.7K_0804

RXDA 29
TXDA 29
RTSA# 29
DTRA# 29
CTSA# 29
DSRA# 29
DCDA# 29
RIA# 29
LPTAFD# 29
LPTINIT# 29
LPTSLCTIN# 29
LPTSTB# 29
LPTBUSY 29
LPTACK# 29
LPTPE 29
LPTSLCT 29
LPTERR# 29
LPD[0..7] 29

RI#2

1 8

CTS#2

2 7

DSR#2

3 6

DCD#2

4 5

1 2

R104 1K

+3VALW

R226 10K

C168

10PF

RP23

18
27
36
45

R179 4.7K

+3VS

RP8

@8P4R_4.7K_0804

AC97_SDIN1 25
AC97_RST# 24,25
AC97_SYNC 24,25
AC97_SDIN0 24
AC97_BCLK 24,25
AC97_SDOUT 24,25
SPKR 24

R186 @4.7K

1 2

R201 10K

1 2

SWI# 27
EXTSMI# 27

1 2

R229

33

RTCAS
RTCRW
RTCDS

2 1

12

RB751VD18

AC97_BCLK

RTCAS 18
RTCRW 18
RTCDS 18

SWI#

R123 4.7K

CTS#2

R122 4.7K

RI#2

LLBJ

RTS2J

Disable Int. KBC

Title

Size Document Number Rev

Date: Sheet

IRQ8# 18,27

Build in when RTC IC used

+5VALW
+3VALW

LID_OUT# 27

+3VS

SCI# 27

GPO34

CHIP TEST MODE

SQWO

Pentium II CPU

DTR#2

PS/2 MODE

BIOSCS#
PCS1J

ENABLE IOCHRDY

GPO35

No LPC ROM

GPO29
AEN
IOCHRDY

+3VALW

R196 10K

12
12

R177 10K

NORMAL MODE

R105 1K

+5VALW

RTSA#

ATX MODE

SPLED
RTCCLK

TESTJ

Compal Electronics, Inc.

ALI 1535+ SOUTH BRIDGE -2

LA-1481 M/B

!"#, $%

14, 2002

R265 10K

1 2

R144 1K
R121 10K
R236 10K
R237 1K

1 2

R259 1K
R200 10K

1 2

R240 10K

1 2

R124 1K

370H

R212 1K
R218 1K

12

R116 1K

17 47

of

+5VS

@1KR251

+5VS

0.3

5

4

3

2

1

ISA

RP36

6
7
8
9

10

10P8R_10K
RP26

6
7
8
9

10

10P8R_10K
RP34

1
2
3
4
5

10P8R_10K

RP33

8P4R_10K_0804

1 2
1 2

SD[0..7]
SA[4..18]

45
36
27
18

5
4
3
2
1

5
4
3
2
1

10
9
8
7
6

10KR214
10KR180

SD6
SD3
SD7
SD4

SA5
SA7
SA6
SA4

SA15
SA12
SA14
SA11

IOW# 17
IOR# 17
MEMR# 17
MEMW# 17

IRQ12 17
IRQ1 17

+5VS

+3VS

+5VS

+5VS

SD[0..7]17

SA[4..18]17

+5VS

+5VS

+5VS

SD0
SD1
SD2
SD5

SA16
SA17
SA18

SA13
SA9
SA10
SA8

+5VALW

+5VS

D D

C C

1 2

R188 @10K

1 2

R189 @1K

+3VS

LAD1
LAD2
LAD3
LAD0

LAD[0..3]17,27

PCI

NOTE: +3V 8.2K

1 2

R527 10K

RP35

4 5
3 6
2 7
1 8

8P4R_10K_0804

PM_CLKRUN# 9,16,22,25,27

SIRQ 17,22,27

+3VS

LAD[0..3]

TP16
TP18
TP20
TP22
TP24
TP26
TP28

TP31
TP33
TP35
TP37
TP39
TP41
TP43

1
1
1
1
1
1
1

1
1
1
1
1
1
1

U34

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

NC

8 9

GND NC

TEST_CHIP

U35

1

NC

2

NC

3

NC

4

NC

5

NC

6

NC

7

NC

8 9

GND NC

TEST_CHIP

NC
NC
NC
NC
NC
NC
NC

PLACE ON TOP SIDE

NC
NC
NC
NC
NC
NC
NC

PLACE ON BOTTOM
SIDE

16
15
14
13
12
11
10

16
15
14
13
12
11
10

TP17

1

TP19

1

TP21

1

TP23

1

TP25

1

TP27

1

TP29

1

TP30

1

TP32

1

TP34

1

TP36

1

TP38

1

TP40

1

TP42

1

TP44

1

TP15

1

+5VALW

12

B B

A A

CHGRTC +RTCVCC

W=30mils

R141
200_0603

1 2

I

W=30mils

21

D10

RB751V

W=30mils

+RTCVCC

D11

RB751V

2 1

R145
470

1 2
12

5

K

J

BATT1

RTCBATT

12

C141

0.1UF

W=30mils

12

+

CB39
10UF_6.3V_1206

If no use RTC IC ,
change to 22UF_10V_1206

@MMBT3906
Q15

3 1

W=30mils

R162 @10K

2

1 2

+3VALW

R156
@51K

1 2

R158
@10K

1 2

D38 RB751V

Q16

2

@3904

3 1

4

+3VALW

21

SD[0..7]17

SD[0..7]

OSC32O
OSC32I
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7

PWRGD17,30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

+3VS

U17D

14

74LVC14

9 8

3

R554 @0

10
11
12

1
2
3
4
5
6
7
8
9

U32

PWR#
X1
X2
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND

@DS1685

R567

1 2

@0

12

24

VCC

23

SQW

22

VBAUX

21

RCLR#

20

VBAT

19

IRQ#

18

KS#

17

RD#

16

GND

15

WR#

14

ALE

13

CS#

+3VALW

R562
10K

1 2

All parts no build in until RTC IC build in .
R560 no build in , even if RTC IC build .

C529

0.1UF

+RTCVCC

R560 @0
R566 @0

R561
1K

1 2

+5VALW+5VS

+RTCVCC +RTCVCC

12

C530

0.1UF

12
12

R556

R557

1K

1K

1 2

1 2

RCLR#

IRQ8# 17,27

12

J4

2

OSC32O

@32.768KHZ_10PPM

12

C531
10PF

Compal Electronics, Inc.

Title

PULL UP/DOWN RESISTOR&RTC

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

J3

R558
10K

X8

14, 2002

12

1 2

OSC32I

R555
0

1 2

R559
10K

1 2

RTCDS 17
RTCRW 17

RTCAS 17

12

C532
10PF

0.3

of

1

18 47

5

4

3

2

1

+5VS

+5VS

R204
10K

IDERST_CD#17

D D

IDEREQA16
IDEIOW#A16
IDEIOR#A16

ICHRDYA16

IDACK#A16
IDEIRQA17

C C

IDEDA[0..15]16
IDESAA[0..2]16
IDESAB[0..2]16

B B

A A

5

IDEREQB16
IDEIOW#B16

IDEIOR#B16
ICHRDYB16
IDACK#B16
IDEIRQB17

IDEDA[0..15]
IDESAA[0..2]
IDESAB[0..2]

IDEREQB
IDEIOW-B
IDEIOR-B
ICHRDYB
IDACK-B
IDEIRQB

IDEDB[0..15]16

PCIRST#6,16,20,21,22,23,25,26,27

IDERST_HD#17

R245 82_1%_0603
R244 33
R252 33
R253 33
R243 33
R260 82_1%_0603

R241

4.7K

R261 82_1%_0603
R235 33
R228 33
R248 33
R231 33
R203 82_1%_0603

R215

4.7K

IDEDB[0..15]

4

+5VS

+3VS

R258

5.6K

R537
10K

R249
10K

+3VS

R264

5.6K

SD_DREQ
SD_SIOW#
SD_SIOR#

SD_DACK#
SD_IRQ15

147

U8A

1
2

74HCT08

U8B

4
5

74HCT08

R267
10K

PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA

IDECS#B316

IDECS#B116

IDEDB5
IDEDB9
IDEDB4
IDEDB11

IDEDB15
IDEDB1
IDEDB14 SD_D14

IDEDB6
IDEDB10
IDEDB8
IDEDB7

IDEDB3
IDEDB12

IDEDB13

3

6

4 5
3 6
2 7
1 8

8P4R_47_0804

4 5
3 6
2 7
1 8

8P4R_47_0804

4 5
3 6
2 7
1 8

8P4R_47_0804

4 5
3 6
2 7
1 8

8P4R_47_0804

CD_IDERST#

HD_IDERST#

RP3

RP6

IDESAB0
IDESAB1

R99

ACT_LED#24

SD_D5
SD_D9
SD_D4
SD_D11

SD_D0IDEDB0
SD_D15
SD_D1

RP1

SD_D6
SD_D10
SD_D8
SD_D7

RP4

SD_D3
SD_D12
SD_D2IDEDB2
SD_D13

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

3

RP7

4 5
3 6
2 7
1 8

8P4R_33_0804

IDECS#A316

IDECS#A116

SD_SBA0
SD_SBA1
SD_SBA2IDESAB2
SD_SCS3#IDECS#B3

SD_SCS1#IDECS#B1

33

IDESAA0 PD_A0
IDESAA1
IDESAA2 PD_A2
IDECS-A1

IDECS-A0

IDEDA1
IDEDA14
IDEDA0
IDEDA15

IDEDA11
IDEDA4
IDEDA10
IDEDA5

IDEDA9 PD_D9
IDEDA6 PD_D6
IDEDA8 PD_D8
IDEDA7 PD_D7

IDEDA3 PD_D3
IDEDA12 PD_D12
IDEDA2 PD_D2
IDEDA13 PD_D13

U8C

8

74HCT08

9
10

8P4R_33_0804

R370

8P4R_47_0804

8P4R_47_0804

8P4R_47_0804

8P4R_47_0804

HDD_LED#SD_SIORDY
CDLED#

RP70

4 5
3 6
2 7
1 8

RP69

4 5
3 6
2 7
1 8

RP67

4 5
3 6
2 7
1 8

RP66

4 5
3 6
2 7
1 8

RP68

4 5
3 6
2 7
1 8

+5VS

33

PD_D1
PD_D14
PD_D0
PD_D15

PD_D11
PD_D4
PD_D10
PD_D5

PD_A1
PD_CS#3

PD_CS#1

+5VS

R20 @10K

CDLED#

12

R101 330

2

PD_D[0..15]

+5VS

12

C325
1000PF

Place component's closely IDE CONN.

1 2

R369 @10K

HD_IDERST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PD_DREQ#
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQA
PD_A1
PD_A0
PD_CS#1
HDD_LED#

1 2

R371 330

CB84

10UF_10V_1206

R100

@0

1 2

+5VS

+5V_IDE

+5VS

12

12

INT_CD_L

CD_IDERST#

SD_D7
SD_D6 SD_D10
SD_D5
SD_D4 SD_D12
SD_D3
SD_D2
SD_D1
SD_D0

SD_SIOW#
SD_SIORDY
SD_IRQ15
SD_SBA1
SD_SBA0
SD_SCS1#

+5V_IDE
+5V_IDE

SD_CSEL

R111
470

W=100mils

12

CB88
10UF_10V_1206

Place component's closely IDE CONN.

+5V_IDE trace to CONN W=100mils

JP19

12

CD-ROM CONN.

Title

Size Document Number Rev

Date: Sheet

HDD/CD-ROM Modu l e

PD_D[0..15]

JP9

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

HDD CONN

12

CB89
1UF_10V_0603

14, 2002

12

CB80
1UF_10V_0603

INT_CD_R
SD_D8

SD_D9
SD_D11
SD_D13

SD_D14
SD_D15
SD_DREQ
SD_SIOR#

SD_DACK#

SD_SBA2
SD_SCS3#

W=80mils

C109 0.1UF

1 2

R420 100K

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_CSEL

PD_A2
PD_CS#3

R373 100K

12

C364

0.1UF

12

1

12

CB81
10UF_10V_1206

1 2
3 4
5 6
7 8

9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44

12
34
56
78
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50

Compal Electronics, Inc.

HDD & CDROM Connector

LA-1481 M/B

!"#, $%

12

C323

0.1UF

R372 470

1 2

CBLIDA

1 2

+5VS

12

C368
1000PF

CD_AGND 24

CDROM_R 24CDROM_L24

R247

1 2

+5V_IDE
+5V_IDE
+5V_IDE

W=100mils

19 47

+5VS

CBLIDB

100K

of

+5VS

+5VS

0.3

5

4

3

2

1

+3VLAN

31

CB82

Q59

2

2SB1197K

VDD2.5

+VDD2.5

C504

+

0.1UF

F

+VDD2.5 +3VLAN

L51

1 2

0_0805

G

1 2

L52 0_0805

CB105

+VDD2.5

12

12

C477

C478

0.1UF

1000PF

VCTRL

D D

10UF_10V_1206

4.7UF_10V_0805

CB102

LAN_X1 LAN_X2

12

C492
22PF

8

VCC

7

NC

6

NC

5

GND

CBE#0 8,10,16,21,22,25

CB103

4.7UF_10V_0805

4.7UF_10V_0805

X7
25 MHz

+3VLAN

12

C500

0.1UF

12

C499
22PF

LAN_RD+
LAN_RD-

LAN_TD+
LAN_TD-

RJ45_TX-25

RJ45_TX+25

LAN_PME#22,25,27,28

12

12

R498
51

R495
51

12

C495

0.1UF

R499
51

12

12

R496

LAN_DIS#28

51

12

C491

0.1UF

C C

PCLK_LAN

12

12

R488
@22

C475
@10PF

+3VLAN

PIRQB#16,22,25

PCIRST#6,16,19,21,22,23,25,26,27

DEV_RST#22,23

PCLK_LAN13

12

C489

1 2
1 2

GNT#38
REQ#38

F

CBE#38,10,16,21,22,25

R491 100

1 2

AD20

0.1UF

R490@0
R4940

PCLK_LAN

AD31
AD30

AD29
AD28

AD27
AD26
AD25
AD24

AD23

+3VLAN

LAN_DIS#

LAN_RD­LAN_RD+

LAN_TD­LAN_TD+

100

R493 4.7K

ACTIVITY#

12
21

RB751VD34

LINK10_100#

12

8079787776757473727170696867666564636261605958575655545352

LED1NCLED2

GND

GND

AVDD

AVDD25

ISOLATEB

AD21

AD20

AD19

VDD

VDD25

AD18

LED0

81

INTAB

82

RSTB

83

CLK

84

GNTB

85

REQB

86

AD31

87

AD30

88

GND

89

AD29

90

VDD

91

AD28

92

AD27

93

AD26

94

AD25

95

AD24

96

VDD25

97

VDD

98

CBE3B

99

IDSEL
AD23

AD22

GND

TXD-

TXD+

RXIN-

AVDD

RXIN+

RTSET

AVDD25

AD17

AD16

CBE2B

FRAMEB

IRDYB

TRDYB

DEVSELB

GND

R500

5.6K_1%_0603

X1

GND

RTT2

RTT3

STOPB

PERRB

SERRB

PAR

X2

GND

AVDD

PMEB

AVDD25

CBE1B

VDD

AD15

AD14

AD13

1234567891011121314151617181920212223242526272829

B B

PERR#

SERR#

PAR

AD14

AD13

AD15

AD[0..31]8,10,16,21,22,25,32

AD[0..31]

AD22

AD18

AD20

AD16

AD17

AD21

AD19

IRDY#

FRAME#

STOP#

CBE#2

TRDY#

DEVSEL#

AD12

12

C481

0.1UF

LAN_X1
LAN_X2

VCTRL

NCNCNC

VCTRL

AD12

AD11

AD11

12

12

12

12

C502

0.1UF

C483

0.1UF

C486

0.1UF

C488

0.1UF

12

C501

0.1UF

F

+3VLAN

AUX
LAN_EECS
LAN_EECLK
LAN_EEDI
LAN_EEDO

AD0
AD1

AD2
AD3

AD4
AD5
AD6

AD7

12

R520

5.6K
U30

1

CS

2

SK

3

DI

4

DO

9346

+3VLAN

51

U21

VDD25

50

AUX

49

EECS

48

EESK

47

EEDI

46

EEDO

45

AD0

44

AD1

43

GND

42

AD2

41

AD3

40

VDD25

39

VDD

38

AD4

37

AD5

36

AD6

35

VDD25

34

VDD

33

AD7

32

CBE0B

31

GND

AD10

AD9

AD8

30

RTL8100-L

AD8

AD9

AD10

RJ45_RX-25

RJ45_RX+25

12

C459

0.1UF

+3VLAN

12

12

C510

C511

0.1UF

1000PF

U15

1

RD+

RX+

2

RD-

RX-

3

CT

CT

6

CT

CT

7

TD+

TX+

8 9

TD- TX-

Pulse-H0022

@1000PF_1206_2KV

12

C487

0.1UF

+3VALW+3VLAN

16
15
14

11
10

R477

75_1%_0603

C460

12

C479

1000PF

12

12

C476

0.1UF

12

R478
75_1%_0603

1 2

RJ45_GND 25

CBE#28,16,21,22,25

FRAME#8,16,21,22,25

IRDY#8,16,21,22,25

TRDY#8,16,21,22,25

DEVSEL#8,16,21,22,25

STOP#8,16,21,22,25
PERR#16,21,22,25
SERR#8,16,22,25

PAR8,16,21,22,25

CBE#18,16,21,22,25

A A

5

4

+3VLAN

12

C503

0.1UF

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

3

2

+3VALW

R518 560_0603

R492 560_0603

ACTIVITY#

(LAN_100LINK)

LINK10_100#

(LAN_10LINK)

12

12

Compal Electronics, Inc.

Title

LAN Controller

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

LED2_YELN 25

LED1_GRNN 25

LED2_YELP 25

LED1_GRNP 25

1

20 47

of

0.5

A

B

C

D

E

IEEE1394 Controller/PHY

+3VS

L29

HB-1M2012-121JT

CB23

AD[0..31]8,10,16,20,22,25,32

4.7UF_10V_0805

12

R51
@33

12

C63
@22PF

10UF_10V_1206

AD[0..31]

6.34K_1%_0603

1 1

2 2

PCLK_1394

3 3

4 4

+3VA

CB24

CB20

1UF_10V_0603

X3

12

12

12

12

C95

0.1UF

Enable I2C EEPROM

R107 2K

C89

C107

0.1UF

0.1UF

XI

XO

VDDATX0

GNDATX0

PHYRESET

AD25

AD24

CBE3#

IDSEL

AD23

106

107

108

109

AD24

AD23

D5

PVDD2

PGND2

D7/PC2JMP

D6/CMCJMP

CTL0/PC0JMP

CTL1/PC1JMP

LREQ/TSOJMP

LINKON/TSIJMP

AD22

VSS3

AD21

VDD2

VDDC1

VSSC1

AD20

AD19

AD18

AD17

110

111

112

113

114

115

116

117

118

119

120

AD17

AD18

AD21

AD22

AD16

AD20

AD19

C118

0.1UF

39404142434445464748495051525354555657585960616263

D0D1D2D3D4

SCLK

PVDD1

PGND1

MODE1

MODE0

LPS/CMC

PME#
VSSC2
VDDC2

VSS9
VDD6

SCL/EECK

SDA/EEDI

EEDO

EECS

VSS8

RAMVSS

RAMVDD

VDD5

VSS7

CBE0#

AD10
AD11

AD12
VSS6
VDD4

AD13

AD14

AD15

CBE1#
PERR#

VSS5

AD16

VSS4

121

STOP#

CBE2#

FRAME#

IRDY#

VDD3

TRDY#

DEVSEL#

128

122

123

124

125

126

127

R114 0_0603

U2

38
37
36
35
34
33
32
31
30
29
28

AD0

27

AD1

26
25
24
23

AD2

22

AD3

21

AD4

20
19

AD5

18

AD6

17

AD7

16
15
14

AD8

13

AD9

12
11
10
9
8
7
6
5
4
3

PAR

2
1

VT6306

+3VS

+3VS

AD0
AD1

AD2
AD3
AD4

AD5
AD6
AD7

AD8
AD9
AD10
AD11
AD12

AD13

STOP# 8,16,20,22,25
DEVSEL# 8,16,20,22,25
TRDY# 8,16,20,22,25
IRDY# 8,16,20,22,25
FRAME# 8,16,20,22,25
CBE#2 8,16,20,22,25

+3VS

R78

1K

R76

1K

R50

C67
47PF

PIRQC#16

PCIRST#6,16,19,20,22,23,25,26,27

PCLK_139413

GNT#08
REQ#08

+3VA

C62

0.1UF
C69

0.1UF
C65

0.1UF

XTPB0­XTPB0+ EECK_LAN
XTPA0- EEDI_LAN
XTPA0+
XTPBIAS0

C64

0.1UF

PCLK_1394

AD31 AD14
AD30 AD15
AD29
AD28
AD27

C106
10PF

24.576MHz

R94

C92

1M_0603

10PF

C66

0.1UF

64

XCPS

65

VDDARX0

66

XREXT

67

NC

68

GNDARX1

69

GNDATX1

70

XTPB0M

71

XTPB0P

72

XTPA0M

73

XTPA0P

74

XTPBIAS0

75

VDDARX1

76

VDDATX1

77

XTPB1M

78

XTPB1P

79

XTPA1M

80

XTPA1P

81

XTPBIAS1

82

GNDARX2

83

GNDATX2

84

XTPB2M

85

XTPB2P

86

XTPA2M

87

XTPA2P

88

XTPBIAS2

89

VDDARX2

90

VDDATX2

91

INTA#

92

PCIRST#

93

PCICLK

94

VSS1

95

GNT#

96

REQ#

97

AD31

98

AD30

99

AD29

100

AD28

101

AD27

102

VDD1

CBE#38,10,16,20,22,25

AD21

GNDARX0

VSS2

103

1 2

R85 100

AD26

104

105

AD26

AD25

12

C68

0.1UF

CBE#0 8,10,16,20,22,25

CBE#1 8,16,20,22,25
PAR 8,16,20,22,25
PERR# 16,20,22,25

C97

0.1UF

12

C100

0.1UF

U4

1

A0

2

A1

3

A2

4 5

GND SDA

24C02-27

XTPBIAS0
XTPA0+
XTPA0­XTPB0+
XTPB0-

54.9_1%_0603

C115

0.1UF

54.9_1%_0603

R54

C80

270PF

VCC
WC#

SCL

12

12

12

8
7
6

R17

C133

0.1UF

+3VS

EECK_LAN
EEDI_LAN

54.9_1%_0603

12

12

12

R16

R53

54.9_1%_0603

R57

5.1K_1%_0603

C134

0.1UF

12

R134
510

12

C135

0.1UF

12

C44

0.33UF_16V_0805
L15

1
2
3
45

IEEE1394-CMF

+3VS

12

12

C128

C129

0.1UF

0.1UF

JP10

6

6

5

C_XTPA0+

8

C_XTPA0-

7

C_XTPB0+

6

C_XTPB0-

5

4

4

3

3

2

2

1

1

1394_FOXCONN

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

IEEE1394 Controller & PHY

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

21 47

E

of

0.3

RTCCLKA23

SLDATA23

ENE 5/29

R358 @0

RTCCLK17

S1_D[0..15]23
S1_A[0..25]23
S2_D[0..15]23
S2_A[0..25]23

AD[0..31]8,10,16,20,21,25,32

CBE#[0..3]8,10,16,20,21,25

PCLK_PCM13

PCMCLKE27

1 2

+12VS

12

R538
@100K
@2N7002

G

2

Q61

D

S

1 2

R568 0

1 2

R539 @10K

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]
AD[0..31]
CBE#[0..3]

13

RTCCLKA

S2_D0
S2_D1
S2_D2

R483

47

S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15

S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8
S2_A9
S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
SB_A16
S2_A17
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25

S2_BVD1
S2_BVD2
S2_CD1#
S2_CD2#
S2_RDY#
S2_WAIT#
S2_WP
S2_INPACK#

S2_OE#
S2_VS1
S2_VS2

S2_RST

PCLK_PCM1

S2_A16 S1_A16

1 2

Placement near
to PCMCIA
controller

S2_BVD123
S2_BVD223
S2_CD1#23
S2_CD2#23
S2_RDY#23
S2_WAIT#23

S2_WP23

S2_INPACK#23

S2_CE1#23
S2_CE2#23
S2_WE#23

S2_IORD#23

S2_IOWR#23

S2_OE#23
S2_VS123

S2_VS223
S2_REG#23
S2_RST23

GNT#28
REQ#28
CBE#38,10,16,20,21,25
CBE#28,16,20,21,25
CBE#18,16,20,21,25
CBE#08,10,16,20,21,25

FRAME#8,16,20,21,25

DEVSEL#8,16,20,21,25

PCIRST#6,16,19,20,21,23,25,26,27

TRDY#8,16,20,21,25

IRDY#8,16,20,21,25

STOP#8,16,20,21,25
PERR#16,20,21,25
SERR#8,16,20,25

PAR8,16,20,21,25

W10

B_D0/CAD27

U10

B_D1/CAD29

P10

B_D2/RSVD

H2

B_D3/CAD0

J1

B_D4/CAD1

J3

B_D5/CAD3

K1

B_D6/CAD5

K3

B_D7/CAD7

V10

B_D8/CAD28

R10

B_D9/CAD30

W11

B_D10/CAD31

H1

B_D11/CAD2

J2

B_D12/CAD4

J6

B_D13/CAD6

K2

B_D14/RSVD

K5

B_D15/CAD8

R8

B_A0/CAD26

W7

B_A1/CAD25

V7

B_A2/CAD24

W6

B_A3/CAD23

V6

B_A4/CAD22

U6

B_A5/CAD21

V5

B_A6/CAD20

U5

B_A7/CAD18

N1

B_A8/CC/BE1#

M3

B_A9/CAD14

L1

B_A10/CAD9

M1

B_A11/CAD12

T1

B_A12/CC/BE2#

N3

B_A13/CPAR

P1

B_A14/CPERR#

P5

B_A15/CIRDY#

P6

B_A16/CCLK

M6

B_A17/CAD16

N2

B_A18/RSVD

N6

B_A19/CBLOCK#

N5

B_A20/CSTOP#

R1

B_A21/CDEVSEL#

R2

B_A22/CTRDY#

R3

B_A23/CFRAME#

W4

B_A24/CAD17

R6

B_A25/CAD19

V9

B_BVD1/CSTSCHG

W9 J15

B_BVD2/CAUDIO A_BVD2/CAUDIO

H3

B_CD1#/CCD1#

R9

B_CD2#/CCD2#

V8

B_READY/CINT#

W8

B_WAIT#/CSERR#

U9

B_WP/CCLKRUN#

R7

B_INPACK/CREQ#

K6

B_CE1#/CC/BE0#

L2

B_CE2#/CAD10

P3

B_WE#/CGNT#

L5

B_IORD#/CAD13

M2

B_IOWR#/CAD15

L6

B_OE#/CAD11

U8

B_VS1#/CVS1

P7

B_VS2#/CVS2

P8

B_REG#/CC/BE3#

W5

B_RESET/CRST#

RTCCLKA

R521 10

1 2

R522 10

1 2

PCLK_PCM1

C6B6A6F7A7B7A14C7F8

PAR

IRDY#

STOP#

TRDY#

SERR#

PERR#

RSTIN#

DEVSEL#

Slot

FRAME#

B

12

R524

C513

12

10PF

33

A10E2A5C8A15

PCLK

C/BE0#

C/BE1#

B13

C13

GNT#

REQ#

C/BE2#

C/BE3#

Interface

PCI

E19

F14

DATA

+3V_PCMCIA

G15

F17

LATCH

CLOCK

SPKOUT

SLATCH 23
PCM_SPK# 24

R515 0_0805

L

12

C498

0.1UF

L3

E11

D1

F3

F18

VCC

VCCI

VCCP

VCCP

Power

Slot

IRQ/DMA

1 2

R526

1 2

@0_0805

12

C493

0.1UF

+3V_PCMCIA

W12

N15

U7

VCC

VCC

VCC

VCC

A

CARDBUS

+3V_PCMCIA

+3VS

G19

VCC

B14

C9

E7

VCC

VCC

VCC

M5

VCCB

M17

VCCA

A11

C471

W=40mils

W=40mils

C480

1 2

0.1UF

A_D0/CAD27

GRST#

A_D1/CAD29

A_D2/RSVD

A_D3/CAD0
A_D4/CAD1
A_D5/CAD3
A_D6/CAD5

A_D7/CAD7
A_D8/CAD28
A_D9/CAD30

A_D10/CAD31

A_D11/CAD2
A_D12/CAD4
A_D13/CAD6
A_D14/RSVD
A_D15/CAD8

A_A0/CAD26
A_A1/CAD25
A_A2/CAD24
A_A3/CAD23
A_A4/CAD22
A_A5/CAD21
A_A6/CAD20
A_A7/CAD18

A_A8/CC/BE1#

A_A9/CAD14
A_A10/CAD9

A_A11/CAD12

A_A12/CC/BE2#

A_A13/CPAR

A_A14/CPERR#

A_A15/CIRDY#

A_A16/CCLK

A_A17/CAD16

A_A18/RSVD

A_A19/CBLOCK#

A_A20/CSTOP#

A_A21/CDEVSEL#

A_A22/TRDY#

A_A23/CFRAME#

A_A24/CAD17
A_A25/CAD19

A_BVD1/CSTSCHG

A_CD1#/CCD1#
A_CD2#/CCD2#

A_READY/CINT#
A_WAIT#/CSERR#
A_WP/CCLKRUN#
A_INPACK/CREQ#

A_CE1#/CC/BE0#

A_CE2#/CAD10
A_WE#/CGNT#

A_IORD#/CAD13

A_IOWR#/CAD15

A_OE#/CAD11

A_VS1#/CVS1
A_VS2#/CVS2

A_REG#/CC/BE3#

A_RESET/CRST#

S2_VCC
S1_VCC

CBRST#

U29

H14
G18
G14
U11
R11
U12
R12
V13
H15
G17
F19
P11
V12
P12
W13
U13

J19
K14
K15
K19
L15
L17
L19
M15
W16
R14
W14
P14
N18
R17
N14
M14
P18
U15
T19
P15
R18
P17
P19
N17
N19
M18

H19
V11

H17
J17
J14
H18
L14

P13
R13
R19
W15
V15
U14
J18
M19
K17
L18

S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
SA_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25

S1_BVD1
S1_BVD2
S1_CD1#
S1_CD2#
S1_RDY#
S1_WAIT#
S1_WP
S1_INPACK#

S1_OE#
S1_VS1
S1_VS2

S1_RST

0.1UF

1 2

GND

PCI1420

DEV_RST# 20,23

+3V_PCMCIA +3V_PCMCIA +3V_PCMCIA

12

1 2

R486 47

Placement near
to PCMCIA
controller

S1_BVD1 23
S1_BVD2 23
S1_CD1# 23
S1_CD2# 23
S1_RDY# 23
S1_WAIT# 23
S1_WP 23
S1_INPACK# 23

S1_CE1# 23
S1_CE2# 23
S1_WE# 23
S1_IORD# 23
S1_IOWR# 23
S1_OE# 23
S1_VS1 23
S1_VS2 23
S1_REG# 23
S1_RST 23

C512

0.1UF

12

C509

0.1UF

+3V_PCMCIA

S1_A23
S1_WP
S1_OE#
S1_RST

PCM_INTA#

CB104

4.7UF_10V_0805

12

12

C494

C484

1000PF

1000PF

R487 22K

1 2

R497 22K

1 2

R480 @22K

1 2

R489 @22K

1 2

R525

1 2

22K

D37

RB751V

+3V_PCMCIA

12

12

+3V_PCMCIA

21

C482

0.1UF

C496
1000PF

+3VALW+3V_PCMCIA

PIRQA# 8,16

12

C472

0.1UF

12

C490
1000PF

S1_VCC

AD4

AD5

AD3

AD2

AD1

AD0

G5

H6G3G1

AD0

H5

AD4

AD1

AD5

AD2

AD3

R481 22K

S2_WP
S2_A23
S2_OE#
S2_RST

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

1 2

R484 22K

1 2

R485 @22K

1 2

R479 @22K

1 2

S2_VCC

AD6

AD11

AD10

AD9

AD8

AD7

AD6

F2

AD7

AD9

AD12

AD11

AD10

AD8

AD29

AD28

AD27

AD26

AD12

AD18

AD16

E13

F11

E10

F10A9B9

F9

A8F1F6B5E6A4C12E3F5G6E1

E9

B8

AD15

AD14

AD13

AD21

AD25

AD17

AD18

AD16

AD24

AD23

AD22

AD19

AD20

AD31

AD30

B12

A12

B11

C11

E12

AD28

AD27

AD26

AD29

AD30

INTA#/MFUNC0

IDSEL

INTB#/MFUNC1

SUSPEND#

DMAREQ#/MFUNC2

A13

F15

C10

E17

D19

A16

PCM_INTA#

PCM_INTB#

12

R523

AD31

100

AD22

AD25

AD24

AD23

AD22

AD21

AD20

AD19

AD17

AD15

AD14

AD13

DMAGNT#/MFUNC5

LOCK#/MFUNC4

IRQSER/MFUNC3

F13

E14

C15

PCM_RI#

1 2

R519 10

CLKRUN#/MFUNC6

C14

B15

1 2

R543 @0

RIOUT#/PME#

GND

GND

GND

J5

P2

G2

PCM_PME# 20,25,27,28

PCM_RI# 29
SIRQ 17,18,27

GND

GND

GND

GND

GND

GND

P9

V14

K18

E18

F12

B10

PM_CLKRUN# 9,16,18,25,27

GND

GND

E8

C5

R516 22K

1 2

PCI1420-GHK

+3V_PCMCIA

PCM_SUSP# 27

R517

1 2

PCM_INTB#

D36 RB751V

Compal Electronics, Inc.

Title

CARD BUS ENE CB-1420

Size Document Number Rev

B

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

22K

+3V_PCMCIA

21

PIRQB# 16,20,25

22 47

of

0.3

PCMCIA POWER CTRL.

SOCKETCARDBUS

JP22

A77

a68

A76

S1_CD2#22

S1_WP22

S1_BVD122

S1_BVD222

S1_REG#22

S1_INPACK#22

S1_WAIT#22

S1_RST22
S1_VS222

S1_VPP S2_VPP

S1_VCC

S1_RDY#22

S1_WE#22

S1_IOWR#22

S1_IORD#22

S1_VS122
S1_OE#22

S1_CE2#22

S1_CE1#22

S1_CD1#22

S1_CD2#
S1_WP

S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1

S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3

S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25

S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22

S1_A16

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13

S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#

S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10

S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6

S1_D12 S2_D12
S1_D5
S1_D11

S1_D4

S1_CD1#

S1_D3

A75
A74
A73
A72
A71
A70
A69
A68
A67
A66
A65
A64
A63
A62
A61
A60
A59
A58
A57
A56
A55
A54
A53
A52
A51
A50
A49
A48
A47
A46
A45
A44
A43
A42
A41
A40
A39
A38
A37
A36
A35
A34
A33
A32
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10

a34
a67
a33
GND
a66
a32
a65
a31
a64
a30
a63
GND
a29
a62
a28
a61
a27
a60
a26
GND
a59
a25
a58
a24
a57
a23
a56
GND
a22
a55
a21
a54
a20
a53
GND
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
GND
a46
a12
a45
a11
a44
GND
a10
a43
a9
a42
a8
GND
a41
a7
a40
a6
a39
a5

A9

GND

A8

a38

A7

a4

A6

a37

A5

a3

A4

a36

A3

a2

A2

a35

A1

a1

157

157

158

158

159

b68
b34
b67
b33

GND

b66
b32
b65
b31
b64
b30
b63

GND

b29
b62
b28
b61
b27
b60
b26

GND

b59
b25
b58
b24
b57
b23
b56

GND

b22
b55
b21
b54
b20
b53

GND

b19
b52
b18
b51
b17
b50
b16
b49
b15
b48
b14
b47
b13

GND

b46
b12
b45
b11
b44

GND

b10
b43

b9

b42

b8

GND

b41

b7

b40

b6

b39

b5

GND

b38

b4

b37

b3

b36

b2

b35

b1

159

160

PCMC154PIN

160

B77
B76
B75
B74
B73
B72
B71
B70
B69
B68
B67
B66
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B49
B48
B47
B46
B45
B44
B43
B42
B41
B40
B39
B38
B37
B36
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1

S2_CD2#
S2_WP

S2_D10
S2_D2
S2_D9
S2_D1
S2_D8
S2_D0
S2_BVD1

S2_A0
S2_BVD2
S2_A1
S2_REG#
S2_A2
S2_INPACK#
S2_A3

S2_WAIT#
S2_A4
S2_RST
S2_A5
S2_VS2
S2_A6
S2_A25

S2_A7
S2_A24
S2_A12
S2_A23
S2_A15
S2_A22

S2_A16

S2_A21
S2_RDY#
S2_A20
S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13

S2_A17
S2_A8
S2_IOWR#
S2_A9
S2_IORD#

S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10

S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6

S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

S2_CD2# 22
S2_WP 22

S2_BVD1 22

S2_BVD2 22
S2_REG# 22

S2_INPACK# 22

S2_WAIT# 22
S2_RST 22
S2_VS2 22

S2_VCC

S2_RDY# 22
S2_WE# 22

S2_IOWR# 22
S2_IORD# 22

S2_VS1 22
S2_OE# 22
S2_CE2# 22

S2_CE1# 22

S2_CD1# 22

S1_D[0..15]22
S1_A[0..25]22
S2_D[0..15]22
S2_A[0..25]22

JP22A

PCMCIA_SOCKET

S1_VCC

S2_VCC

S1_D[0..15]
S1_A[0..25]
S2_D[0..15]
S2_A[0..25]

C474

0.1UF

C470

0.1UF

S1_CD1#
S1_CD2#
S2_CD1#
S2_CD2#

12

CB99

C473

4.7UF_10V_0805

0.01UF

CB56

C469

4.7UF_10V_0805

0.01UF

C455 1000PF

1 2

C505 1000PF

1 2

C507 1000PF

1 2

C506 1000PF

1 2

CB63 2.2UF_16V_0805

CB67 4.7UF_10V_0805
CB66 4.7UF_10V_0805
CB69 4.7UF_10V_0805

CB55 4.7UF_10V_0805
CB57 4.7UF_10V_0805
CB53 4.7UF_10V_0805

S1_VPP

S2_VPP

+3VALW

C220

0.01UF

C221

0.01UF

+3VALW

SLDATA22

RTCCLKA22

R340 @100K

12

CB60

4.7UF_10V_0805

12

CB100

4.7UF_10V_0805

+12VALW

+5VALW

R353

8.2K

U18

25

NC

7

12V

24

12V

1

5V

2

5V

30

5V

15

3.3V

16

3.3V

17

3.3V

3

DATA

5

LATCH

4

CLOCK

13

NC

19

STBY#

18 12

OC# GND

TPS2216AI

R350

8.2K

+3VALW

C154

0.1UF

+3VALW POWER

AVPP
AVCC
AVCC
AVCC

BVPP
BVCC
BVCC
BVCC

RESET

RESET#

MODE

12

8
9
10
11

23
20
21
22

6
14

26

NC

27

NC

28

NC

29

10

9 8

U7C

74LVC125

S1_VPP

S2_VPP

TPAD1

TP

12

CB101

4.7UF_10V_0805

12

DEV_RST#

R217

10K

S1_VPP
S1_VCC

S2_VPP
S2_VCC

CB62

4.7UF_10V_0805

MODIFY BY
10/27/2000

PCMRST# 27

+3VALW

DEV_RST# 20,22SLATCH22

DEV_RST# 20,22PCIRST#6,16,19,20,21,22,25,26,27

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

Title

CARD BUS SOCKET

Size Document Number Rev

B

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

23 47

of

0.3

A

BEEP#27

1 1

2 2

13

U7D

74LVC125

12 11

+3VALW POWER

PCM_SPK#22

+3VS

12

R342
100K_1%_0603

1 2

10K_1%_0603

SPKR17

R339

C215

0.22UF_0603

B

12

+3VS

14

1 2

U17A
74LVC14

+3VALW POWER

+3VS

14

3 4

U17B
74LVC14

+3VALW POWER

+3VS

14

5 6

U17C
74LVC14

+3VALW POWER

CB51

1UF_10V_0603

CB50
1UF_10V_0603

CB52
1UF_10V_0603

1 2

12

R304 560

12

1 2

R324 560

12

1 2

R335 560

C

MONO_IN

12

R303
10K

2 1

D26

RB751V

D

E

F

G

H

AC97 CODEC ALC202 CONN

MOD_AUDIO_MON25

3 3

INT_MIC26

Q41

@2N7002

4 4

A

R363 0

R365 0

Q42
@SI2304DS

S

G

2

13

D

S

12

12

D

13

2

G

12

R364
@33K

INTMIC

R368

1 2

@100K

DRV0#17,26

+12VS

MIC_MUTE 27

B

MOD_AUDIO_MONR

Q62

DTC124EK

+3VS

2

DRV_0#

22K

22K

DRV0#

13

AC97_BCLK17,25

HPLUG27

AC97_RST#17,25

AC97_SYNC17,25

AC97_SDOUT17,25

AC97_SDIN017

MOD_AUDIO_MONR

CHARGING_LED#28

POWER1_LED#28
POWER2_LED#28

0_0805

1 2

L45

C

MD_MIC25

CD_AGND19
CDROM_L19

CDROM_R19

PS2_DATA27

PS2_CLK27

EC_MUTE27

FULL_LED#28

ACT_LED#19

+5VALW

+3VALW

MONO_IN
MOD_AUDIO_MONR

+3VS

INTMIC

EC_MUTE

DRV_0#

+5VS

12

R351

D

0

JP6

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27

27

28

28

29

29

30

30

CODEC CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

E

F

Compal Electronics, Inc.

Title

AC97 Codec

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

G

24

47

of

H

0.3

A

B

C

D

E

+5VS

12

12

C153
1000PF

1 1

12

C173
1000PF

Wireless_OFF#27

W=40mils

+3VS

2 2

3 3

AC97_SYNC17,24

AC97_SDIN117

AC97_BCLK17,24

12

C209 15PF

W=30mils

+5VS

4 4

PIRQD#16

REQ#1 GNT#1

R220 0_0603

PCLK_MINI13

REQ#18

100

1 2
CBE#38,10,16,20,21,22

CBE#28,16,20,21,22

IRDY#8,16,20,21,22

PM_CLKRUN#9,16,18,22,27 TRDY# 8,16,20,21,22

SERR#8,16,20,22

PERR#16,20,21,22
CBE#18,16,20,21,22

W=30mils

+5VS

MOD_AUDIO_MON24
MD_MIC24

+3.3VAUX

MODEM_RI#29

CB61

C204

4.7UF_10V_0805

0.1UF

+3VS

12

CB47

C165

4.7UF_10V_0805

0.1UF

RB751V

PIRQD#

1 2

PCLK_MINI
REQ#1
AD31

AD29
AD27

R234

AD25
LAN_IDSELAD31

AD23
AD21

AD19
AD17

PM_CLKRUN#

AD14
AD12

AD10
AD8

AD7
AD5
AD3
AD1

R311 22
R320 22

PCLK_MINI

12

R222
@10

12

C162
@15PF

12
12

MD_AUDIO_MON

TIP RING

D12

21

Mini-PCI Slot

12

C212
1000PF

AD[0..31]

JP4

1 2

12

KEY KEY

3 4

34

5 6

56

7 8

78

9 10

910

11 12

11 12

13 14

13 14

15 16

15 16

17 18

17 18

19 20

19 20

21 22

21 22

23 24

23 24

25 26

25 26

27 28

27 28

29 30

29 30

31 32

31 32

33 34

33 34

35 36

35 36

37 38

37 38

39 40

39 40

41 42

41 42

43 44

43 44

45 46

45 46

47 48

47 48

49 50

49 50

51 52

51 52

53 54

53 54

55 56

55 56

57 58

57 58

59 60

59 60

61 62

61 62

63 64

63 64

65 66

65 66

67 68

67 68

69 70

69 70

71 72

71 72

73 74

73 74

75 76

75 76

77 78

77 78

79 80

79 80

81 82

81 82

83 84

83 84

85 86

85 86

87 88

87 88

89 90

89 90

91 92

91 92

93 94

93 94

95 96

95 96

97 98

97 98

99 100

99 100

101 102

101 102

103 104

103 104

105 106

105 106

107 108

107 108

109 110

109 110

111 112

111 112

113 114

113 114

115 116

115 116

117 118

117 118

119 120

119 120

121 122

121 122

123 124

123 124

127 129

127 129

Mini-PCI SLOT

+3.3VAUX

+3.3VAUX

12

CB54

C171

4.7UF_10V_0805

0.1UF

AD[0..31] 8,10,16,20,21,22,32

R176 0_0603

1 2

PCIRST#
GNT#1

1 2

AD30
AD28

AD26
AD24
MINI_IDSEL

AD22
AD20

AD18
AD16

AD15
AD13
AD11

AD9

AD6
AD4
AD2
AD0

MD_AUDIO_MON

+3VALW

the channel width 50 mils

PIRQB#

PCIRST# 6,16,19,20,21,22,23,26,27

GNT#1 8

R232
0

1 2

R230 100

PAR 8,16,20,21,22

FRAME# 8,16,20,21,22
STOP# 8,16,20,21,22
DEVSEL# 8,16,20,21,22

CBE#0 8,10,16,20,21,22

AC97_SDOUT 17,24
AC97_RST# 17,24

DIGITAL GND

MOD_RING
MOD_TIP

12

C445
@220PF_3KV_1808

PIRQB# 16,20,22

MINI_PME# 20,22,27,28
LAN_PME# 20,22,27,28

AD27

W=40mils

MINI_GNDA

12

C449
@220PF_3KV_1808

W=40mils

W=40mils

W=40mils

12

C200
1000PF

+3.3VAUX

+5VS

+3.3VAUX

+3VS

JP3

1
2

HEADER 2

12

C157

0.01UF

RJ45_GND20

MOD_TIP

VH1

@DSSA-P3100SB

MOD_RING

Modify on 6/19

R550 0_0603

+5VS

12

CB42
10UF_10V_1206

RJ45_TX+20

RJ45_TX-20

RJ45_RX+20

RJ45_RX-20

1 2

TX+
TX-

R462

75_1%_0603

RX-

R461

75_1%_0603

12

C166
220PF_3KV_1808

12

12

Modify for
modem layout
7/26

JP20

8

TX+

7

TX-

6

RX+

5

N/C1

4

N/C2

3

RX-

2

N/C3

1

N/C4

9

N/C5

10

RING

11

TIP

12

N/C6

RJ-45 & RJ-11

GND1

CATHODE1

ANODE1

CATHODE2

ANODE2

GND2

13

16

15

17

18

14

LED1_GRNN

LED1_GRNP

LED2_YELP

LED2_YELN

12

12

C452
47PF

12

C450

47PF

C453

47PF

12

C451
47PF

LED1_GRNN 20

LED1_GRNP 20

LED2_YELP 20

LED2_YELN 20

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Mini PCI Slot & SPR D oc king

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

25 47

E

of

0.3

+3VALW+3VS

FDD CONN.

+5VS

INDEX#17

DRV0#17,24

DSKCHG#17

MTR0#17

FDDIR#17

3MODE#17

STEP#17
WDATA#17
WGATE#17

TRACK0#17

WP#17
RDATA#17
HDSEL#17

INDEX#
DRV0#
DSKCHG#

MTR0#
FDDIR#

3MODE#
STEP#

WDATA#
WGATE#
TRACK0#
WP#
RDATA#
HDSEL#

+5VS

12

12

C515

C516

0.1UF

0.1UF

JP25

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES 85203-2602

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

ON/OFF BUTTON

SW2

3

4

HCH SMT1-02

1

R26

4.7K

1 2

R18
0

2

G

@2N7002

Q8

D5

3

DAN202U

2

DTC124EK

ON/OFF

2

+3VALW

12

EC_ON27

13

D

S

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

22K

B

22K

+3VALW

12

1
2

13

C

+5VS

R22
100K

51ON#

Q7

E

INDEX#

DRV0#

DSKCHG#

MTR0#

FDDIR#

3MODE#

STEP#
WDATA#
WGATE#

TRACK0#

WP#
RDATA#
HDSEL#

+5VS

+5VALW

ON/OFFBTN# 27
51ON# 34

12

C52

1000PF

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

DSKCHG#
INDEX#
WP#
TRACK0#

GND-MIC need around INT_MIC

WDATA#
WGATE#
HDSEL#
FDDIR#

12

C497

0.1UF

D6

12

RLZ20A

2 1

6
7
8
9

10

1 8
2 7
3 6
4 5

RP102

10P8R_1K

ON/OFFBTN#ON/OFFBTN#

12

C332

0.1UF

+5VS

RP101

8P4R_1K_0804

5
4
3
2
1

12

J1

12

STEP#
MTR0#
RDATA#
DRV0#

C333

0.1UF

SCROLLED#27

CAPSLED#27

SWITCH BOARD CONN.

+3VALW

+3VS

1
2
3

NUMLED#27

51ON#34

EC_ACT#27,28

INT_MIC24

4
5
6
7
8
9

10

SW BD CONN

GND-MIC

+5VS

Place in Closest JP20 Place in Closest JP20

R384

1 2

0

GND-MIC

AGND

4 IN 1 CONN

+5VS +5VS

USB3_D+16

USB3_D-16
PCIRST#6,16,19,20,21,22,23,25,27

USB3_D+
USB3_D­PCIRST#

JP1

11

1

12

2

13

3

14

4

15

5

16

6

17

7

18

8

19

9

20

10

R386

1 2

@0

11
12
13
14
15
16
17
18
19
20

JP24

1

1

2

2

3

3

4

4

5

5

6

6

4 in1 CONN

GND

7
8

9
10
11
12

USER_BTN3#

7
8

USB3_D+

9

USB3_D-

10

PCIRST#

11
12

USER_BTN0# 28
USER_BTN1# 28
USER_BTN2# 28
USER_BTN3# 28

INT_KBD CONN.

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

KSO[0..15]
KSI[0..7]

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

INT_KB-85201-2405

KSO6

1 8

KSO3

2 7

KSO12

3 6

KSO13

4 5

KSO14

1 8

KSO11

2 7

KSO10

3 6

KSO15

4 5

KSO2

1 8

KSO4

2 7

KSO7

3 6

KSO8

4 5

KSO9

1 8

KSO0

2 7

KSO5

3 6

KSO1

4 5

JP8

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

CP4

8P4C-100PF

CP3

8P4C-100PF

CP5

8P4C-100PF

CP6

8P4C-100PF

KSO[0..15]27

KSI[0..7]27

NEED CLOSEST JP18 ADD BY EMI REQUEST

LID SW

LID_SW#27,28

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

LID_SW#

SW1

3

4

HORNG CHIH

1

2

Compal Electronics , Inc.

Title

System Connector

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

26 47

of

0.3

A

+3VALW +3VALW

CB59

4.7UF_10V_0805

1 1

2 2

3 3

4 4

+5VS

G20
KBRST#
BT_OFF#

570SCI#

EXT_CLK
EXT_DATA
PS2_CLK
PS2_DATA

L42

1 2

BLM11A20

L44

1 2

BLM11A20

EC_PCLK

12

R291
@10

12

C192
@15PF

ADB[0..7]
KBA[0..18]

RP39

1 8
2 7
3 6
4 5

8P4R_10K_0804

12

C217

0.1UF

10

9
8
7
6

+3VALW

12

C205

0.1UF

C175

0.1UF

1 2

ECAGND

RP37

10P8R_4.7K

EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

FSEL#
SELIO#
FRD#

12

C177
1000PF

EC_AVCC+3VALW

12

C174
1000PF

R341 100K

+3VALW

ADB[0..7] 28

KBD_CLK

1

KBD_DATA

2
3
4
5

+5VS

RP42

1 8
2 7
3 6
4 5

8P4R_10K_0804

+3VALW

RP41

1 8
2 7
3 6
4 5

8P4R_10K_0804

R336 20M_0603

1 2

12

32.768KHZ_10PPM

C216
10PF

X6

+3VS

+3VS

KSI[0..7]26

KSO[0..15]26

+5VALW

12

C218
10PF

R337

LFRAME#17

EC_PCLK13

KBD_CLK30

KBD_DATA30

EXT_CLK30

EXT_DATA30

PS2_CLK24

PS2_DATA24

LID_SW#26,28

MIC_MUTE24

120K

PCM_SUSP#22

Wireless_OFF#25

LCD_DIGON9,15

SIRQ17,18,22

LDRQ#017

LAD017,18
LAD117,18
LAD217,18
LAD317,18

SCI#17

12

EXTSMI#17

MSEN#14,28
HPLUG24

PCMRST#23

SYSON31

SUSP#29,31,38

VR_ON4,36,39
RSM_RST17
CPUDET#4

BKOFF#15

1 2

R298

SWI#17

FSEL#28

B

0_0603
CB48

4.7UF_10V_0805

KSI[0..7]
KSO[0..15]

CRY1
CRY2

1 2

R308

EC_PCLK

570SCI#

G20
KBRST#

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

KBD_CLK
KBD_DATA
EXT_CLK
EXT_DATA
PS2_CLK
PS2_DATA
LID_SW#

EXTSMI#
MSEN#

SYSON

BT_OFF#

FSEL#

C

VCC2

136

VCC3

157

166

VCC4

VCC5

PORTB

PORTD-1

PORTE

EC_AVCC

VCC6

AD Input

DA output

PWM
or
PORTA

PORTC

PORTH

95

AVCC

IOPB2/USCLK

IOPB7/RING/PFAIL/LRESET2

IOPC4/TB1/EXWINT22
IOPC6/TB2/EXWINT23

IOPC7/CLKOUT

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21

IOPD2/EXWINT24/LRESET2

IOPE5/EXWINT40

IOPE6/LPCPD/EXWIN45

IOPE7/CLKRUN/EXWINT46

IOPH0/A0/ENV0

IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1

IOPH4/A4/TRIS

IOPH5/A5/SHBM

PORTI

PORTJ-1

PORTD-2

PORTK

IOPK5/A13/BE0
IOPK6/A14/BE1

IOPK7/A15/CBRD

PORTL

EC_3VDD

12

C195

0.1UF

7
8
9

@0

15
14
13
10
18
19
22
23

31

5
6

KSI0

71

KSI1

72

KSI2

73

KSI3

74

KSI4

77

KSI5

78

KSI6

79

KSI7

80
49

50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

105
106
107
108
109

110
111
114
115
116
117
118
119

158
160

62
63
69
70
75
76 143

148
149
155
156

3

4
27
28

173
174

47

16

VDD

SERIRQ
LDRQ
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
LREST1
SMI
PWUREQ

IOPD3/ECSCI

GA20/IOPB5
KBRST/IOPB6

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

TINT
TCK
TDO
TDI
TMS

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

32KX1/32KCLKOUT
32KX2

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

SEL0
SEL1
CLK

3445123

VCC1

Host interface

Key matrix scan

JTAG debug port

PS2 interface

PORTJ-2

PORTM

VBAT

1UF_10V_0603

161

VBAT

AD0
AD1
AD2
AD3

IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7

DP/AD8
DN/AD9

DA0
DA1
DA2
DA3

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

IOPB0/URXD

IOPB1/UTXD

IOPB3/SCL1

IOPB4/SDA1

IOPC0

IOPC1/SCL2

IOPC2/SDA2

IOPC3/TA1
IOPC5/TA2

IOPE4/SWIN

IOPH6/A6
IOPH7/A7

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

IOPJ0/RD

IOPJ1/WR0

SELIO
IOPD4

IOPD5
IOPD6
IOPD7

IOPK0/A8

IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19

IOPL4/WR1

CB58

1 2

U12

81
82
83
84
87
88
89
90
93
94

99
100
101
102

32
33
36
37
38
39
40
43

153
154
162
163
164
165

168
169
170
171
172
175
176
1

26
29
30

2
44
24

R286 @0

25
124

125
126
127
128
131
132
133

138
139
140
141
144
145
146
147

150
151

152
41

42
54
55

142
135
134
130
129
121
120

113
112
104
103
48

D

R345 0_0603

1 2

21

12

@RB751VD39

BATT_TEMP
ADP_I_R

BD_ID0
BD_ID1
BD_ID2
EC_SMC_1
EC_SMD_1

R199 0

EC_SMC_2
EC_SMD_2

EC_ACT#

PC7
AC_IN AC_IN

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

FRD#
FWR#

SELIO#

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

KBA16
KBA17
KBA18

J5

BATT_TEMP 36
BATT_OVP 35
LI/NIMH# 36

DAC_BRIG 15
EN_FAN1 4
IREF 35

INVT_PWM 15
BEEP# 24
PCMCLKE 22
ACOFF 35
PM_BATLOW# 17
EC_ON 26
LID_OUT# 17
EC_THERM# 17

SMB_EC_CK1 28,36
SMB_EC_DA1 28,36KBA[0..18] 28

12

PCIRST# 6,16,19,20,21,22,23,25,26
PWRBTN_OUT# 17

EC_SMC2 3
EC_SMD2 3
FANSPEED1 4

EC_ACT# 26,28

EC_MUTE 24

R565 0

1 2

R325 10K

RING# 29
SLP_S3# 17

ON/OFFBTN# 26
SLP_S5# 17
SLP_S1# 17

12

PM_CLKRUN# 9,16,18,22,25

FREAD# 28
FWR# 28

SELIO# 28
SCROLLED# 26

NUMLED# 26
CAPSLED# 26

FSTCHG 35

+RTCVCC

12

J2

K

BADDR1-0

*

ADP_I_R

R233 2M_0603
C169

0.22UF_0603

1 2

12

C170 0.01UF

1 2

00
01
10
11

Index Data

4E 4F

(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1

ADP_I 35

IRE
OBD

*

DEV
PROG

SHBM=1: Enable shared memory with host BIOS
TRIS=1: While in IRE and OBD, float all the

signals for clip-on ISE use

KBA1

KBA2

KBA3

JP7

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

@96212-1011S

KBA5

12
12
12

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

BD_ID0
BD_ID1
BD_ID2

PCI_PME# 20,22,25,28

+3VALW

IRQ8# 17,18

+3VALW

R343 @10K
R250 @10K
R262 10K

12

ECAGNDBATT_TEMP

I/O Address

Reserved

ENV0 ENV1

00
0011

11

(ENV1)

(BADDR0)

(BADDR1)

(SHBM)

2 1

BD_ID0
BD_ID1
BD_ID2

+5VALW

E

2F2E

TRIS

0
0
0
0

+3VALW

R30610K

R31410K

R323@10K

R32610K

RB751VD23

R338 10K
R246 10K
R268 @10K

ACIN 16,34,37AC_IN17

12
12
12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

PC87591VPC

GND1

173546

GND2

GND3

GND4

122

GND5

159

GND6

167

GND7

137

AGND

96

11

ECAGND

C

NC2

NC3

NC4

NC5

NC6

NC1

NC7

122021858691929798

NC8

NC9

NC10

D

Compal Electronics, Ltd.

Title

EC PC87591

Size Document Number Rev
Custom

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

27 47

of

0.5

INPUT OUTPUT

USER_BTN0#26
USER_BTN1#26
USER_BTN2#26
USER_BTN3#26

PID010,15
PID110,15
PID210,15
PID310,15

U24D

147

KBA1

SELIO#27

SELIO#

74LVC32

12
13

11

+3VALW

PCM_PME#20,22,25,27
MINI_PME#20,22,25,27
LAN_PME#20,22,25,27

+3VALW

1 2

20

1A1 1Y1
1A2 1Y2

VCC
1A3 1Y3
1A4 1Y4
2A1 2Y1
2A2 2Y2
2A3 2Y3
2A4 2Y4

1G
2G

GND

10

EC_ACT#

MSEN#

+3VALW

12

R366
20K

U22

74LVC244

PME_51#

2 18
4 16
6 14

8 12
11 9
13 7
15 5
17 3

1
19

RP43

1 8
2 7
3 6
4 5

8P4R_20K_0804

C322

0.1UF

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

EC_ACT# 26,27
LID_SW# 26,27

MSEN# 14,27

PCI_PME# 20,22,25,27

KBA2
SELIO#CC

+5VALW

C271

1 2

0.1UF

20

D0
D1 Q1

VCC
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7

CLK
CLR

U23

Q0

GND

74HCT273

10

2

1

TP45

1

TP10

FULL_LED# 24
POWER1_LED# 24
POWER2_LED# 24
CHARGING_LED# 24

LAN_DIS# 20
CPU_DECT 33

8

ADB0

ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

AA
LARST#

CB79

1 2

1UF_10V_0603

+3VALW

C3260.1UF

12

+5VALW

10

9

U24C

147

74LVC32

1 2

R367

20K

3
4 5
7 6

8 9
13 12
14 15
17 16
18 19

11

1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

KBA[0..18]
ADB[0..7]

U20

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

SST39VF040

U20A

KBA[0..18]27

ADB[0..7]27

KBA18
KBA16
KBA15 KBA17
KBA12 KBA14
KBA7 KBA13
KBA6 KBA8
KBA5 KBA9
KBA4 KBA11
KBA3
KBA2 KBA10
KBA1
KBA0
ADB0 ADB6
ADB1
ADB2

BIOS_PLCC_IC

Only A-test built .

10UF_10V_1206

C224

1 2

0.1UF

32

VCC

31

WE*

30

A17

29

A14

28

A13

27

A8

26

A9

25

A11

24

OE*

23

A10

22

CE*

21

DQ7

20

DQ6

19

DQ5

18

DQ4

17

DQ3

CB64

12

FWE#

ADB7
ADB5

ADB4
ADB3

+3VALW

FREAD# 27
FSEL# 27

6

U24B
74LVC32

+3VALW

12

147

4
5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

R348
20K

2

1 3

Q36

R346

1 2

1K

2N7002

FWR# 27

SUS_STAT# 6,17

FLASH# 17

SMB_EC_CK127,36
SMB_EC_DA127,36

+5VALW

C225

1 2

0.1UF

Title

Size Document Number Rev

Date: Sheet

U19

8

VCC

7

WC

6

SCL

5

SDA

NM24C164

GND

12

R355
1K

Compal Electronics , Inc.

BIOS & EC I/O Po rt

LA-1481 M/B

!"#, $%

14, 2002

+5VALW

12

R357
10K

1

A0

2

A1

3

A2

4

12

R356
1K

28 47

0.3

of

A

B

C

D

E

Printer Port / U SB

USB2_D­USB2_D+

USB_2

F2

+5VALW

OVCUR#216

EVERFUSE_1.1A

12

C79
1000PF

1 1

L19

1 2

FBM-11-451616-800T

12

R56
470K_0603

12

R55
560K_0603

12

C24

0.1UF

USB2_D- 16
USB2_D+ 16

USB2_VCC
USB2_D- R_USB2_D-

+

CE1
150UF_10V_E

FBM-11-451616-800T

USB Port

12

C20

0.1UF

1
2
3
4

JP11

VCC
D­D+
GND

2551A-04G2T

L14 FBM-11-160808-121

12

R_USB2_D+USB2_D+ R_USB1_D+

12

L13FBM-11-160808-121

USBGND2

12

L16

JP13

VCC

D-

D+

GND

2551A-04G2T

1
2
3
4

USBGND1

12

C22

0.1UF

USB1_D+16

USB1_D-16

L7 FBM-11-160808-121

12

L10
FBM-11-451616-800T

USB1_D-R_USB1_D-

12

USB1_D+

12

L12 FBM-11-160808-121

USB1_D+
USB1_D-

USB1_VCC

CE2

150UF_10V_E

+

L30

FBM-11-451616-800T

12

C8

0.1UF

560K_0603

USB_1

12

EVERFUSE_1.1A

R80

470K_0603

12

12

C83
1000PF

F5

+5VALW

OVCUR#1 16

12

R79

USB0_D­USB0_D+

JP12

1

VCC

D+

GND

2551A-04G2T

2 2

3 3

+5V_PRN

SLCTIN#
LPT_INIT#
LPTERR#
AFD/3M#

+5V_PRN

4 4

R_USB0_D-

2

D-

R_USB0_D+

3

USBGND0

4

12

C18

0.1UF

LPD[0..7]17

LPTINIT#17

LPTSLCTIN#17

RP72

FD0

1

FD1

2

FD2

3

FD3

4
5

10P8R_2.7K

RP73

1
2
3
4
5

10P8R_2.7K

10
11
12
13
14
15
16

RP71

16P8R_68

LPD3
LPD2
LPD1
LPD0
LPD7 FD7
LPD6
LPD5
LPD4

1 2
1 2

12

LPD[0..7]

1 2

R380 33

1 2

R379 33

FD3

89

FD2

7

FD1

6

FD0

5
4

FD6

3

FD5

2

FD4

1

L9

FBM-11-160808-121

L8

FBM-11-160808-121

L31
FBM-11-451616-800T

+5V_PRN

10
9
8
7
6

+5V_PRN

10
9
8
7
6

LPT_INIT#

SLCTIN#

FD7
FD6
FD5
FD4

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

USB0_D- 16
USB0_D+ 16

USB0_D­USB0_D+

Parallel Port

LPTSTB#17

LPTAFD#17

USB0_VCC

CE4

+

150UF_10V_E

L34

FBM-11-451616-800T

12

C19

0.1UF

+5VS

LPTSTB#

1 2

R382 33

1 2

R383 33

LPTERR#17

LPTACK#17

LPTBUSY17

LPTPE17

LPTSLCT17

USB_0

12

12

12

D30

2 1

RB420D

+5V_PRN_1
AFD/3M#

FD0
LPTERR#
FD1
LPT_INIT#
FD2
SLCTIN#
FD3

FD4
FD5
FD6
FD7
LPTACK#
LPTBUSY
LPTPE
LPTSLCT

EVERFUSE_1.1A

R93
470K_0603

R95

560K_0603

+5V_PRN

w=40mils

F6

12

12

R381
1K

w=40mils

+5VALW

C101

1000PF

JP16
LPTCN-25-SUYIN

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9
22
10
23
11
24
12
25
13

OVCUR#0 16

+5V_PRN

12

AFD/3M#
LPTERR#
LPT_INIT#
SLCTIN#

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

FD0
FD1
FD2
FD3

FD4
FD5
FD6
FD7

C328

0.1UF

CP8

1 8
2 7
3 6
4 5

8P4C-220PF

CP7

1 8
2 7
3 6
4 5

8P4C-220PF

CP9

1 8
2 7
3 6
4 5

8P4C-220PF

CP10

1 8
2 7
3 6
4 5

8P4C-220PF

DCDA#17
DSRA#17

DTRA#17
RTSA#17

CTSA#17

TXDA17

RIA#17

RXDA17

12

R288
10K

PCM_RI#22

RING#27

MODEM_RI#25

C331

0.1UF_0805
C9

25V

0.47UF_0805

DTRA# DTR#1
TXDA

CTSA#
RIA#
RXDA
DCDA#
DSRA#
RIA1

SUSP#27,31,38

D24

RB751V

D25

RB751V

Q23

2N7002

+5VALW

C330

0.1UF

28

C1+

24

C1-

1

C2+

2

C2-

14

TIN1

13

TIN2

12

TIN3

19

ROUT1

18

ROUT2

17

ROUT3

16

ROUT4

15

ROUT5

20

ROUTB2

23

FORCEON

22

FORCEOFF#

U1 MAX3243

+3VALW+3VALW

12

R271
10K

21

21

13

RIA1

2

DCDA#
RIA#
CTSA#
DSRA#

SERIAL PORT

26

25V

C327

27

V+

VCC

0.47UF_0805

25V

C10

3

V-

0.47UF_0805

9

TOUT1

RTS#1RTSA#

10

TOUT2

TXD1

11

TOUT3

CTS#1

4

RIN1

RI#1

5

RIN2

RXD1

6

RIN3

DCD#1

7

RIN4

DSR#1

8

RIN5

21

INVLD#

25

GND

(1)

DCD#1

(6)

DSR#1

(2)

RXD1

(7)

RTS#1

(3)

TXD1

(8)

CTS#1

(4)

DTR#1

(9)

RI#1

(5)

RTS#1
RXD1
DSR#1
DCD#1

DTR#1
CTS#1
TXD1
RI#1

R125 1K

RXDA

RP74

1 8
2 7
3 6
4 5

@8P4R_4.7K_0804

JP17

COM-DB9

1
6
2
7
3
8
4
9
5

CP12

1 8
2 7
3 6
4 5

8P4C-220PF

CP11

1 8
2 7
3 6
4 5

8P4C-220PF

1 2

+3VS

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Printer/COM/USB Port

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

29 47

E

of

0.5

+VCCP2.5

+CPU_CORE

1 2

R576

1 2

R577

10K_0603

12

C537

0.047UF_0603

10K_0603

12

C538

0.047UF_0603

R572

4.7K_0603

2

2

+5VS

12

3 1

3 1

R569

4.7K_0603

Q64
MMBT2222A

Q65
MMBT2222A

+3VS

12

13

D

Q63

2

G

2N7002

S

+3VS+3VS

+3VS +3VS +3VS

12

C534

0.47UF_0603

14

1 2

U33A
74LVC14

14

3 4

+2.5VS

13

D

2

G

S

U33B
74LVC14

R216
1K

Q20

2N7002

R573

1 2

20K_0603

12

R579

47K

5 6

12

C535

0.47UF_0603

NB_PWRGD 6

14

U33C
74LVC14

+3VS

14

9 8

+CPU_CORE

12

13

D

2

G

S

R354
820

R571

47_0603

U33D
74LVC14

Q39
2N7002

VR_POK_1

12

R574

1 2

20K_0603

CPU_PWROK 3

+3VS +3VS

14

11 10

12

C536

0.47UF_0603

U33E
74LVC14

14

13 12

U33F
74LVC14

R575

1 2

47_0603

PWRGD 17,18

12

R578

10K

13 12

C222

0.047UF_0603

14

U17F

74LVC14

14

U17E

VR_POK_1 CPU_SVID

74LVC14

11 10

12

CPU_SVID 33

+5VS

EVERFUSE_1.1A

2

D8
DAN217

4516

D32
DAN217

L39

1

1

3

2

3

KB_AS

12

C96
1000PF

1 2

CB-1608D-800T

1 2

CB-1608D-800T

+5VS

+5VS

EXT_CLK27

EXT_DATA27

F8

+5VS

+5VS

KB_VCC

W=40mils W=40mils

1 2

CHB4516G750

KBD_DATA27

KBD_CLK27

2

D31
DAN217

3

2

D7
DAN217

3

1

1

L50

1 2

CB-1608D-800T

1 2

L38

CB-1608D-800T

12

L49

L37

0603

C90
220PF

PS2 CONN.

12

CB35

4.7UF_10V_0805

12

12

C105

220PF

JP18

KBD/PS2_6

4
2
1

C379

220PF

12

C380
220PF

C324 1UF_0603

563

1K_0603

12

C104
220PF

1 2

R374

+3VALW

147

1
2

U8D

13
12

74HCT08

U24A

3

74LVC32

11

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics , Inc.

Title

POWER GOOD & PS2 Connector

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

30 47

of

0.5

A

B

C

D

E

+1.8VS+1.8VALW

U16

SI4800

D

S

D

S

D

S

D

G

CB98
10UF_10V_1206

1
2
3
4

8
7
6
5

1 1

12

+2.5V to +2.5VS Transfer

2 2

+12VALW

12

R289
100K

3 3

SUSP

Q55

2N7002

13

2

G

12

R295

12

C456

0.01UF

4.7UF_10V_0805

D

1M_0603

S

+1.8VALW to +1.8VS Transfe r

12

C213

0.1UF

RUNON

12

CB97

22UF_10V_1206

+12VS

12

C206

0.1UF

12

R529
10K

+2.5V

12

CB78

1UF_10V_0603

13

D

Q40

2

G

SI2306DS

S

+2.5VS

12

CB68
1UF_10V_0603

+5VALW to +5VS Transfer

+5VALW

U11

SI4800

D
D
D
D

RUNON

12

S
S
S
G

+5VALW

12

1
2
3
4

CE8

+

100UF_D_16V

CB94

8
7
6
5

+5VALW

+5VS

12

R307
470

Q58

13

2N7002

SUSP

2

SYSON#38

R542 0

SYSON27

+12VALW TO +12VS
Transfer

2

+12VALW

1 3

12

CB96
1UF_25V_0805

12

CB46
1UF_25V_0805

Q57
NDS352P

+12VS

+12VALW

12

C223

0.1UF

SUSP#

12

12

C189

CB45
22UF_10V_1206

0.1UF

12

R463
470

Q22

13

2N7002

SUSP

2

12

R349
100K

VON

12

R352
51K

13

Q38

2

2N7002

1 2

@0.1UF

SUSP#27,29,38

SYSON#

C525

+3VALW

+12VALW

12

R287
47K

13

Q53

2

2N7002

12

+12VALW

12

R283

R528
@10K

10K

SUSP

13

Q54

2

2N7002

12

+3VALW +3VS

U14

SI4800

8

D

S

7

D

S

6

D

S

4 4

12

CE9

+

100UF_D_16V

5

D

G

12

CB95
10UF_10V_1206

A

+3VALW to +3VS Transfer

1
2
3

12

4

CB49

22UF_10V_1206

RUNON

12

12

R301

C198

15_0603

0.1UF

Q56

13

2N7002

SUSP

2

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

B

C

D

Title

DC/DC Circuit s

Size Document Number Rev

LA-1481 M/B

Date: Sheet

!"#, $%

14, 2002

31

47

E

of

0.3

CPU FID ISOLATION

+3VS

+3VS

SUSPEN POWER

Place near

AD16

AD17

AD18

AD19

NB ATI-U1

R396 3.3K

R395 3.3K

R397 3.3K

R391 3.3K

ClkDiv[3]

FID[3]

0000
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1111

AD[0..31]8,10,16,20,21,22,25

AD[0..31]

RP76
8P4R_10K_0804

1 8

2 7

3 6

4 5

ClkDiv[2]

ClkDiv[1]

FID[2]

FID[1]

00
0
0
1
1
1
1
0
0
0
0
1
1
11

1
1
0
0
1
1
0
0
1
1
0
0

ClkDiv[0]

FID[0]

1 11.5
0
1
0
1
0
1
0
1
0
1
0
1
0

FIDJMP0

FIDJMP1

FIDJMP2

FIDJMP3

Processor Clock
and SYSCLK
Frequency Ratio

11

12

12.5
5

5.5
6

6.5
7

7.5
8

8.5
9

9.5
10

10.5

R390

10K

2

2

2

FIDEN

2

+2.5VS

RP75
8P4R_3.9K_0804

1 8

2 7

3 6

4 5

13

D

Q46
2N7002

G

S

13

D

Q48
2N7002

G

S

13

D

Q49
2N7002

G

S

13

D

Q47
2N7002

G

S

FID0

FID1

FID2

FID3

FID[0..3] 3

Decoupling Between Planes

+3VS+CPU_CORE

C36

0.1UF

C447

0.1UF

D

1

23

G

S

2N7002

WARNING: PRELIMINARY
SCHEMATICS. FOR REFERENC E
PURPOSES ONLY. DESIGN HAS NOT
BEEN BUILT OR VERIFIED.

NOTE: All resistors are 5% 0603, and all capacitors are 10% 0603 unless otherwise noted.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPART MENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

Compal Electronics, Inc.

Title

FID

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet of

14, 2002

32 47

0.3

A

B

C

D

E

VID[4:0] Code to Voltage Definition

VID[4:0]

1 1

00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101

2 2

3 3

4 4

01110
01111

VCC_CORE(V)

2.000V

1.950V

1.900V

1.850V

1.800V

1.750V

1.700V

1.650V

1.600V

1.550V

1.500V

1.450V

1.400V

1.350V

1.300V
NO CPU

VID[4:0]

10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111

VCC_CORE(V)

1.275V

1.250V

1.225V

1.200V

1.175V

1.150V

1.125V

1.100V

1.075V

1.050V

1.025V

1.000V

0.975V

0.950V

0.925V
NO CPU

CPU_DECT28

CPU_SVID30

SUSPEN POWER

PVID[0..4]3 VID0 39

FROM
PROCESSOR

CPU_DECT

CPU_SVID

For Mobil Athl on Model 6
& Mobil Duron Model 7
For Mobile Duron Model 3
Athlon/Duron

4

U7B

74LVC125

5 6

R317 3.9K R319

RP38

1 8
2 7
3 6
4 5

8P4R_3.9K_0804

PVID0

PVID1

PVID2

PVID3

PVID4

R316 0

SVID_GATE

R315

1K

SVID_GATE : HI GH
SVID_GATE : LOW

+3VS

13

D

Q29

2

2N7002

G

S

+2.5VS

SVID[0..4]4

K7 PGA IO only 2.5 volt. tolerant

+5VALW+2.5VS

R467 @10K

3.9K

G

2

13

D

S

Q24

2N7002

G

2

13

D

S

Q25

2N7002

G

2

13

D

S

Q26

2N7002

G

2

13

D

S

Q27

2N7002

G

2

13

D

S

Q28

2N7002

This disables the
CPU's VIDs from
being passed
through during
sleep state.

2

G

RP40

1 8
2 7
3 6
4 5

8P4R_3.9K_0804

R344 3.9K

RP100 @8P4R_10K_0804

13

D

Q31

2N7002

S

SVID0

1 2

1 8
2 7
3 6
4 5

VID0

VID1

VID2

VID3

VID4

13

D

Q32

2

G

S

SVID1

2N7002

13

D

Q33

2

G

S

SVID2

2N7002

13

D

Q34

2

G

S

SVID3

2N7002

13

D

2

G

S

SVID4

VID1 39

VID2 39

VID3 39

VID4 39

Q35

2N7002

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

VID

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

33 47

of

0.3

A

B

C

D

Vin Detector

P1

PCN1

3

1

3

2

2DC-S315-B01

PD2
IN4148

1 1

2 2

VIN

P1

1

2

EC10QS04

VIN+

12

PD1

PR8
1K_1206

1 2

PR10
1K_1206

1 2

PR11
1K_1206

1 2

12

1000PF_0603_50V

FBM-L18-453215-900LMA 90T_1812

PC1

B++

PL1

1 2

PC2

100PF_0402_50V

PC3

1000PF_0603_50V

VIN

PC4

100PF_0402_50V

PC6

1000PF_0603_50V

84.5K_0402_1%

12

VIN

PD4
IN4148

1 2

PD5

2 1

PZD3

RLZ4.3B

RB751V

100K_0402

1 2

PR21
22K_0402

12

PR20

VS+

12

TP0610T

12

ON_G

PC12

0.22UF_1206_25V

PQ1

13

2

VMB

3 3

CHGRTCP

51ON#26

VIN_L

PR18
33_1206

1 2

12

PC11

0.1UF_0603_50V

VS

MAINPWO N36,37

ACON35

PD3

1
2

3

RB715F

High 18.784 17.901 17.077 V
Low 17.877 17.043 16.195 V

VIN

0.01UF_0603_50V

12

PR3

PR5

12

22K_0402_1%

1 2

PC7

0.01UF_0402_16V

12

DIN

PR6

20K_0402_1%

VS

12

PR13

10K_0402

PRG

(6.0V)

PZD2
RLZ6.2C

2 1

12

ACIN

Precharge detector

16.6 15.9 15.2

13.48 12.93 12.09

BAT ONLY

PR1
1M_0402_1%

1 2

VS

PC5

3
2

12

PR9

10K_0402

PU1B
LM393M

7

PC9

1000PF_0603_50V

PU1A

84

LM393M

+

-

RTCVREF

(3.3V)

PR12
1M_0402_1%

5

+

6

-

12

1

12

PC10

0.01UF_0402_16V

PR16
10K_0402

1 2

RTCVREF

3.3V

PQ2
2N7002

VS

12

PR2

10K_0402

12

12

PRG++

13

D

S

PQ3

DTC115EUA

PZD1
RLZ4.3B

PR17
215K_0402_1%

2

G

12

PR7
10K_0402

13

PR4
1K_0402

1 2

B++

12

PR14
499K_0402_1%

PRG+

12

PR15
499K_0402_1%

PR19
47K_0402

100K

100K

PACIN

2

12

ACIN 16,27,37

PACIN 35

12

PC8
1000PF_0603_50V

PACINPRG+_G

+5VALWP

Precharge detector

(3.3V)

RTCVREF

4 4

CHGRTC

1 2

PR23
200_0805

PC14
10UF_1206_10V

A

S-81233SG(SOT-23)

3

3

PU2

2

2

1

1

CHGRTCP

PR22
200_0805

CHGRTCP+

PC13
1UF_0805_50V

2 1

PZD4
RLZ16B

B

8.597 8.247 7.904

6.310 6.101 5.683

C

Title

DCIN & DETECTOR

Size Document Number Rev

B

BFY260 0.2

!"#, $%

Date: Sheet of

14, 2002

D

34 47

A

B

C

D

1 1

PQ4

SI4835DY

ACOFF#

8
7

5

PD6

1SS355

1 2

PR33

10K_0402

1 2

VIN

12

PR25

20K_0402

2 2

PACIN34

ACON34

IREF=1.235*Ich arge

P2 P3

PQ5

1
2
36

4

SI4835DY

1
2
3 6

12

4

PR26
200K_0402

L_1

12

PR30
150K_0402

8
7

5

ADP_I27

L_1T

13

D

PQ9
2N7002

2

G

S

PC20

0.1UF_0402_10V

12

12

PR35
13K_0603_1%

12

(1.73V)

12

PR34
24K_0402_1%

(5.0V)

PC23

0.1UF_0402_10V

1 2

IREF=0.6175 ~ 3.3V

12

PR53

2.2K_0402

1 2

PR39

147K_0603_0.1%

PU4A
LM358A

1

PR43

100K_0402_1%

VS

84

3

+

2

-

12

PC30

0.1UF_0603_50V

L_8

PR54

200K_0402_1%

12

PC27

0.1UF_0402_10V

VMB

12

L_7

12

12

PR48

604K_0402_1%

PR49

1M_0402_1%

IREF27

3 3

OVP voltage : LI-MH 8 CELL(4S2P)

VMB : 18.0V--> BATT_OVP : 2.0V

(BAT_OVP voltage = 0.110865 *VMB)

BATT_OVP27

4 4

0.1UF_0402_10V

PC33

12

A

PR127
0_0402

4700PF_0603_50V

Iadp=0~3.5A

PR24

0.02_2512_1%

PR32
10K_0603_1%

PR36 10K_0603_1%

1 2

1 2

PC21

PR37 10K_0603_1%

1 2

1 2

PC24

2200PF_0603_50V

PR41 10K_0603_1%

PC34

0.01UF_0603_50V

B

B+

1 2

24

0_0603_5%

23

22

21

20

0.1UF_0603_50V

VH

19

18

1 2

17

PR38 68K_0402

16

PR42 47K_0603_1%

15

1 2

CHARGE

14

13

PL2

PR31

PC22

1 2

12

12

PR29

12

0_0603_5%

L_3

L_4

1 2

PC26

1 2

1500PF_50V

1 2

PR44
1K_0402

PR46

49.9K_0603_0.1%

PC15
10UF_1210_25V

PC18
2200PF_0402_25V

1 2

1 2

PC19

0.1UF_0603_50V

PC25

0.1UF_0603_50V

(4.2V)

12

12

PC16

4.7UF_1210_25V

L_5

12

PR45
47K_0402

PC17

0.1UF_0603_50V

1 2

FSTCHG27

PD8

EC31QS04

12

PU3
MB3878

1

-INC2

12

12

2

OUTC2

3

+INE2

4

-INE2

5

FB2

6

VREF

7

FB1

8

-INE1

9

+INE1

10

OUTC1

11

OUTD

12

-INC1

FBM-L18-453215-900LMA 90T_1812

+INC2

GND

CS

VCC(o)

OUT

VH

VCC

RT

-INE3

FB3

CTL

+INC1

B++

36

241

PQ7
FDS4435

578

LXCHRG

PL3

SLF12565T-22uH

1 2

12

L_6

12

PR47

150K_0603_0.1%

1 2

PC112 @22P_0603_50V

ACOFF#

1 2

0.02_2512_1%

PR40

PQ6

SI4835DY

1
2
3 6

1 2

13

100K

100K

4

L_2

PR27
10K_0402

2

PQ8
DTC115EKA

8
7

5

1 2

PR28
47K_0402

ACOFF27

CC=0(0.5 A) ~ 2.5 A
CV=16.825V (8 CELLS )

12

PC28

10UF_1210_25V

VIN

BATT+

12

PC29

4.7UF_1210_25V

CHARGE 36

+2.5VP

(1.25V)

SDREF7,11

PR51
0_0402

PC32

10UF_1206_10V

12

PR50

L_9

C

10K_0603_0.5%

12

PR52

10K_0603_0.5%

PU4B
LM358A

5

+

7

12

6

-

SDREF_L

PC121

0.1UF_0402_10V

PC31

0.1UF_0402_10V

Title

CHARGER

Size Document Number Rev

B

BFY260 0.2

!"#, $%

Date: Sheet of

14, 2002

D

35 47

A

B

C

D

PJP1
3MM

21

+5VALW+5VALWP +12VALW

+12VALWP

PJP4
3MM

+3VALWP

1 1

21

+1.8VALWP +1.25VS

+3VALW

PJP2

2MM

PJP5

2MM

21

+1.8VALW

21

+1.25VP

PJP3

4MM

PJP6

3MM

21

+2.5V+2.5VP

PH1 under CPU botten side :

CPU thermal protection at 90(91)+-3 degree C

21

Recovery at 50(51)+-3 degree C

RTCVREF

PC84

0.1UF_0402_10V

PR57

1000PF_0603_50V

7

PR76

470K_0402

3
2

VS

84

+

-

VS

PR73
10K_0402

1

PU5A
LM393M

PR64

470K_0402

OTP_B

21

PZD6
RLZ3.6B

PR59

10K_0402

OTP_C

21

PZD5

RLZ3.6B

PD13
1SS355

PC43

0.1UF_0402_10V

PQ11

DTC115EKA

12

PC35

0.1UF_0603_50V

PD9

OTP

12

1SS355

PC40

0.1UF_0402_10V

100K

2

100K

OTP

100K

2

VR_ON

13

PQ12

DTC115EKA

100K

2

4,27,39

100K

100K

PTH1
10K_1%

L_10

PR55

100K_0402_1%

PR60
1K_0402_1%

47K_0402_1%

rev

PC37

1000PF_0603_50V

VMB

FBM-L18-453215-900LMA 90T_1812

12

PL4

1 2

BATT+

12

PC36

0.1UF_0603_50V

+3VALWP

PR56
@100K_0402_1%

CPU

*

PR58

3.65K_0402_1%

LI/NIMH# 27

PR61

2 2

PR66
1K_0402

1 2

PR67

1K_0402

PCN2

1
2
3
4
5
6
7
8

SUYIN_25037A-08G1-C

3 3

4 4

VMB

AB/I

VSB
TS

1 2

PR68

25.5K_0402_1%

12

*

PR69

100_0402

*

1 2

PR70
100_0402

1

PD12
@BAS40-04

@1K_0402_1%

12

PR63

BATT_TEMP

1

3

3

1

3

2

2

2

@1K_0402_1%

PD10

@BAS40-04

PD11
@BAS40-04

SMB_EC_DA1 27,28

SMB_EC_CK1 27,28

+3VALWP

BATT_TEMP 27

+3VALWP

0.1UF_0402_10V

BATTERY

PC42

0.1UF_0402_10V

3.65K_0402_1%

PC38

PR71

L_11T

L_10T

PH2 near main Battery CONN :

BAT. thermal protection at 85(86)+-3 degree C
Recovery at 50(51) degree C

RTCVREF

L_11

19.1K_0402_1%

PTH2
10K_1%

PR75

PR62

18.2K_0402_1%

249K_0402_1%

PR74
1K_0402_1%

PR65

PC41

0.1UF_0402_10V

PR72 47K_0402_1%

rev

PC39

84

5

+

6

-

PU5B
LM393M

CHARGE

13

PQ10
DTC115EKA

MAINPWON

13

35

34,37

Title

BATTERY CONN / OTP

Size Document Number Rev

B

BFY260 0.2

!"#, $%

A

B

C

Date: Sheet of

14, 2002

D

36 47

A

1 1

B++

12

PC47

0.1UF_0603_50V

12

PC48

PC49

2200PF_50V

10UF_1210_25V

SI4814DY

1
2
3
4

G1

D1
D1

S1/D2

G2

S1/D2
S1/D2

S2

PQ13

+3.3V Ipeak = 6.66A ~ 10A

12

12

PL5

SLF12565T-100M

2 2

12

PR82

+3VALWP

12

+

PC59

150UF_D_6.3V_FP

3 3

0.012_2512_1%

12

PD16

+

EP10QY03

PC60

2 1

150UF_D_6.3V_FP

1 2

1 2

PR87

3.57K_0402_1%

PR90

10K_0402_1%

PC57
47PF_0402_50V

L_BT3

PR83
1M_0402

1 2

12

PC61

FB3_L

33PF_0402_50V

0.1UF_0603_50V

8
7
6
5

DH3

B

PC46

1 2

DL3

LX3

ACIN16,27,34

PR78
0_0603_5%

1 2

CSH3

1 2

PR86
10K_0402

@300K_0402

VS

12

PR120
47K_0402

12

PC67

0.047UF_0603_50V

DAP202U

1 2

L_12 L_13

12

22

V+

PU6

MAX1632

PD15

2

3

1

12

PC51

4.7UF_1206_10V

21

4

12OUT

VL

5

VDD

18

BST5

16

DH5

17

LX5

19

DL5

20

PGND

14

CSH5

13

CSL5

12

FB5

15

SEQ

9

REF

6

SYNC

11

RST#

GND

8

VL

BST31 BST51

L_14

12

PR88

12

PD25

1SS355

PR79
10_1206

12

PC55

0.1UF_0603_50V

25

BST3

27

DH3

26

LX3

24

DL3

1

CSH3

2

CSL3

3

FB3

10

SKIP#

23

SHDN#

7

TIME/ON5

28

RUN/ON3

PC65
680PF_0402_50V

PR121
47K_0402

VS

12

MAINPWON

12

PC68

0.047UF_0402_16V

C

VL

+12VALWP

PC56

4.7UF_1210_25V

MAINPWON 34,36

12

12

PR92
@0_0402

1 2

PR137
0_0402

BST51+

LX5

2.5VREF

PC62

4.7UF_1206_10V

12

PC50

0.1UF_0603_50V

1 2

PR80

0_0603_5%

1 2

L_15

VL

FB5_L

PC52

2200PF_50V

1 2

PR81
0_0603_5%

12

D

PC45

470PF_0805_100V

B++

12

PC53

0.1UF_0603_50V

DH5

CSH5

33PF_0402_50V

1 2

PC54

DL5

PC66

12VDD

10UF_1210_25V

12

PR77
22_1206

12

SI4814DY

1

D1

2

D1

S1/D2

3

G2

S1/D2

4

S1/D2

S2

PR89

10.5K_0402_1%

G1

PQ14

FLYBACKSNB

12

12

E

PR126

2.7K_1206

12

PC44

2.2UF_1206_25V

1 2

12

PD14
EC11FS2

1 4

3 2

PT1

CST12057T-100M5R0-T

8
7
6
5

12

PC58
47PF_0402_50V

L_BT5

12

PR84
2M_0402

PD17

EP10QY03

PR91

10K_0402_1%

2 1

12

12

12

+

+

150UF_D_6.3V_FP

PC63

+5V Ipeak = 6.66A ~ 10A

PR85

0.012_2512_1%

+5VALWP

47UF_D_6.3V_PC

PC64

4 4

Title

3.3V / 5V / 12V

Size Document Number Rev

BFY260

Date: Sheet

!"#, $%

A

B

C

D

14, 2002

37 47

E

0.2

of

A

D

S

S

1

12

PR149
10K_0402

PU11A
LM393M

3

3

6
2

1

G

D

6
2

1

G

PQ16
SI3445DV

EC31QS04

L_16

VL

84

3

+

2

-

PQ21
SI3445DV

S

4 5

G

3

L_17

1

4700PF_0402_25V

PQ15
@SI3445DV

PD19

PC74

0.1UF_0402_10V

D

6
2

1

PD23

EC31QS04

VL

84

3

+

2

-

PC118

LX2.5

12

12

PD28
@EC31QS04

LA3

LA2

12

PC75

4700PF_0402_25V

PQ19

DTC115EUA

LX1.8

12

PC103

0.1UF_0402_10V

12

SLF12565T-4R2N

12

PR150
@2M

12

PC73

@0.1UF_0603_50V

13

100K

100K

TPRH6D38-5R0M

1 2

12

PR145
@2M

191K_0402_1%

12

PC115

@0.1UF_0603_50V

LB3

12

*

PR151
261K_0402_1%

PL6

191K_0402_1%

PL9

LB2

+5VALWP

1 1

PD18

PC72

PQ18

2SA1036K

+3VALWP

1 2

12

31

12

PC104

PQ23

2SA1036K

RB751V

1 2

12

PC71

10UF_1210_25V

2200PF_0402_25V

2 2

3 3

PC117

4.7UF_1206_16V

2200PF_0402_25V

4 4

PR152
1K_0402

2

PD22
RB751V

1 2

1 2

12

31

PQ17

HMBT2222A

2

HMBT2222A

PR111
1K_0402

2

PU11B
LM393M

A

13

PU7B
LM393M

PQ22

2

LB1

7

7

LA1

12

13

+

-

4 5

4 5

PR114
10K_0402

*

PU7A
LM393M

5

+

6

-

5
6

12

PR148

PR115

47K_0402

1 2

2

PR146

B

12

13

100K

B

12

PC69

VL

12

PR147
@47K

1 2

100K

2

PQ24
@DTC115EKA

(+2.5V +-5%)

+2.5VP

12

12

+

PC70

470PF_0402_50V

220UF_D_4V_FP

2.5VREF

1 2

PR116
0_0402

SYSON#LA2_G

(+1.8V+-5%)

+1.8VALWP

12

PR113
100K_0402_1%

PC116

470PF_0402_50V

SYSON#

12

+

PC119

150UF_D_4V_FP

2.5VREF

C

D

+2.5VP

PR112
10_0805

PC76

0.1UF_0402_10V

12

12

1.5VCC

1

VCC1

VCC2

16

1 2

SYSON#31

PVDD2

PGND2

AGND2

VFB

VCCQ

AGND

15

13

12

11

10

9

12

PC79

4.7UF_1206_16V

+2.5VP

12

PC82

0.1UF_0402_10V

Title

Size Document Number Rev

B

Date: Sheet of

SUSP#27,29,31

+2.5VP

12

4.7UF_1206_16V

1 2

PR109
100K_0402

2

PQ20

DTC115EUA

PC78

100K

100K

2

PVDD1

PU8

3 14

VL1 VL2

CM8500IT

4

PGND1

5

AGND1

SD

6

SD

7

VIN/2

12

PC83

1000PF_0603_50V

8

AGSEN

13

Layout : "Compensation network close to FB pin"

C

21

PD20

@EP10QY03

PC77

0.1UF_0402_10V

+1.25VP

PL8

LX1.25

TPRH6D38-5R0M

12

PD21
@EP10QY03

1 2

PC81
1000PF_0603_50V

PR108
100K_0402

PR110
1K_0402

12

12

+

PC80

12

12

DDR /2.5V / 1.8V
BFY260 0.2

!"#, $%

14, 2002

D

38 47

220UF_D_4V_FP

A

B

C

D

E

F

G

H

PQ33

IR7811A

SI4362DY

PQ25

IR7811A

L_21

PQ29

CPUB+

578

3 6

578

578

CPUB+

PC109

2200PF_0603_50V

578

3 6

578

3 6

578

1 2

241

241

1 2

PR100
100_0402

PQ34

IR7811A

241

PQ30

SI4362DY

3 6

241

PR153
@0_0402

1 2

CPUB+

PQ26

IR7811A

PL10

SSC-1206-0R5

12

PD27

EC31QS04

12

+

PC105

PC106

10UF_1210_25V

100UF_EC_25V

CM+

12

PC120

10PF_0402_50V

CPUB+

PC107

4.7UF_1210_25V

PR97

0_0402

1 2

12

+CPU_CORE

PR117

0.001_2512_5%

COREFB+

PC108

4.7UF_1210_25V

+CPU_CORE

PC95

2200PF_0603_50V

1 2

+5VALWP

PC150

1UF_0805_16V

CPUVDD

1 1

VR_ON4,27,36

120K_0603_1%

PR107

1 2

470PF_0603_50V

PC99

2 2

12

@0.47UF_0805_10V

VGATE

VID033

VID133

VID233

VID333
VID433

PC114

PR130

100K_0603

12

PC101

1 2

0.22UF_0603_16V

PR134
0_0603

PR132

PR131

100K_0603

1 2

PR139

100K_0402_1%

+2VREF

12

100K_0603

1 2

PR119

+5VS

PR133

100K_0603

1 2

100K_0603

1 2

143K_0603_1%

PR142
@0_0402

+3VALWP

PR135 100K_0603

+5VALWP COREFB-

1 2

PC113

PR138

220K_0603_1%

1 2

PR141

12

2

3

0_0402

21

12

PR125

0_0402

12

20

PR122

0_0402

12

19

PR94
0_0402

12

18

PR123

17

12

0_0402
PR124

6

12

8

16 12

12

PR95
0_0402

@1000PF_0603_50V

2 1

PR144

12

20_0805

15

7

VDD

VCC

SKP/SDN#

TIME

D0

D1

D2

D3
D4

CC

TON

A/B# VGATE

BST

PU10

MAX1717A

GND

FBSREF

GNDS

ILIM

10

PC100

0.22UF_0603_16V

1 2

1

V+

22

24

DH

23

LX

14

DL

13

4

FB

59

11

PD24

1SS355

B++

FBM-L18-453215-900LMA 90T_1812

PC102

1 2

0.1UF_0603_50V

PC91

1 2

0.1UF_0603_50V

PC93

1000PF_0603_50V

+2VREF

12

12

PR143

@0_0402

PR154

@0_0603

PR140

12

0_0402

PL7

PC85

10UF_1210_25V

PC90

@2200PF_0402_25V

12

PC86

4.7UF_1210_25V

12

PR96

2.2_0603_1%

12

4.7UF_1210_25V
PC87

3 6

3 6

241

578

3 6

L_24

241

E

+2VREF

*

*

PR102

3 3

PC96

0.1UF_0402_10V

PR103
200_0402

1 2

PR104
200_0402

1 2

1 2

PR105
200_0402

1 2

PR106
200_0402

4 4

A

48.7K_0402_1%

PR101
20K_0402_1%

PC97
4700PF_0402_25V

PC98
4700PF_0402_25V

PR136

53.6K_0402_1%

PR99
20K_0402_1%

L_26

L_29

L_30
L_31

B

L_18

PR98
PC94
1000PF_0603_50V

PU9 MAX1887

1
2 15
3
4
5
6
7
8

33K_0402_1%

PC92
270PF_0402_50V

L_25

ILIM
TRIG V+
CM+
CM­CS­CS+
COMP
GND

LIMIT

BST

VDD

PGND

LX

DH

DL

C

16

14
13
12
11
10
9

L_19

CPUVDD

0.1UF_0603_50V

L_28

PC89

L_23

2 1

1UF_0805_16V

PC88

PD26
1SS355

PR93

2.2_0603_1%

1 2

D

PQ27

SI4362DY

*

241

PQ28

SI4362DY

578

3 6

241

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY
OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE
SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE
CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS
AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR
THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY
THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,

SSC-1206-0R5

12

PD7

EC31QS04

PL11

PR118

0.001_2512_5%

CS+

F

12

+CPU_CORE

+CPU_CORE

COMPAL ELECTRONICS, INC

Title

+CPU_CORE

Size Document Number Rev

B

Date: Sheet

BFY260 0.2

!"#, $%

14, 2002

G

H

39 47

of

A

Voltage Rails

VIN

Note : ON* means that this power plane is ON only with AC power a vaila ble, o th erw ise it is OFF .

Adapter power supply (19V)
B+
+CPU_CORE

1 1

2 2

+3VS

Core voltage for CPU

3.3V always on power rail

3.3V switched power rail

B

S1 S3 S5Power Plane Description
N/A
N/A N/A

ON+3VALW
ON

N/A
N/AAC or battery power rail for power circuit.

OFF

C

FUNCTION

Pullhigh,Switch,DOCKING,VL,AC IN.

N/A

Pullhigh,Switch,B1+,PWR MB3887,PWR MAX1718,LCD INVERTER. H,B++,P3,
Pullhigh,Switch,NB,CPU.

OFFOFFON

Pullhigh,Switch,PCMCIA CTRL,PCMCIA Switch,LAN

ON*ON

Pullhigh,1394,NE1617,SM560,NB,DDR,CLK GEN,PID,

OFF

D

RELATED POWER NET NAME

VIN+,VIN_L

CS+,CM+,L_30,L_31

+3V_PCMCIA,S1_VCC,S2_VCC,+3VLAN(+VDD2.5,G),
+3VA

E

External PCI Devices

Device

LAN
CardBus_A SLOT
CardBus_B SLOT
Mini-PCI
Mini-PCI LAN
IEEE-1394 Controller

IDSEL#

AD20

AD22
AD22
AD27
AD31
AD21

3
2
2

1
0PIRQA

InterruptsREQ#/GNT #

PIRQB
PIRQA
PIRQA
PIRQB1
PIRQD

3 3

P.S:Default Resistor & Capacitor's package are 0402.

Default 8P4R package is 0402.

4 4

Compal Electronics, Ltd.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

A

B

C

D

Title

Notes

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

E

40 47

of

0.3

5

4

3

2

1

Power PIR

Item

1

2

D D

3
4

5

6

7

8

C C

9

10

11

Fixed Issue Reason for change Page PhaseMB_Ver.Modify item

12

13

B B

14

15

16

17

18

A A

Title

Power PIR

Size Document Number Rev

LA-1481 M/B

5

4

3

Date: Sheet

!"#, $%

2

14, 2002

41 47

of

1

0.2

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2

1

BCY26 A-TEST Modify <91.05.20.~91.06.27.
>

1.Modify the resistors' value for AMD recommend <Page 3> 91.05.22.

-Change R151,R157 from 10ohm to 10Kohm . (Modify CKT&BOM)

2.Modify the schematic for ATI DC_STOP# related <Page 6> 91.05.22.

D D

-Change R210 from @1Kohm to 1Kohm . (Modify CKT&BOM)

3.Modify the Pull Low/High resistors' value to meet Compal rule <Page 17,18> 91.05.22.

-Change R122,R123,R164,R179,R266 from 10Kohm to 4.7Kohm . (Modify CKT&BOM)

-Change R239,R257 from @10Kohm to @4.7Kohm . (Modify CKT onl y)

-Change R142 from 100Kohm to 4.7Kohm . (Modify CKT&BOM)

-Change R165,R170 from @100Kohm to @4.7Kohm . (Modify CKT onl y)

-Change RP23 from 8P4R_10K_0804ohm to 8P4R_4.7K_0804ohm . (Modify CKT&BOM)

-Change R214 from 4.7Kohm to 10Kohm . (Modify CKT&BOM)

4.Modify the schematic for IDE related <Page 19> 91.05.22.

-Change D16 from RB751V to @RB751V . (Modify CKT&BOM)

-Change R101,R371 from 330ohm to 10Kohm . (Modify CKT&BOM)

5.Modify the material for shortage and layout size <Page 19> 91.05.24.

C C

-Change R14 from 60_1%_0603 to 60.4_1%_0603 . (Modify CKT&BOM)

-Change R441,R442 from 60_1%_0603 to 60.4_1% . (Modify CKT&BOM)

A-TEST SMT BUILT

6.Correct CPU schematic <Page 4> 91.05.20.

-Connect U27.AM6 or U27.AE7 to GND . (Modify CKT& Layout)

7.Modify the schematic for PWRGD timing <Page 30> 91.05.29.

-Remove Q21(2N7002) , and then short Q21.1 and Q2 1.3 . (Modify CKT,BOM and Layout)

8.Modify the schematic for ATI strapping recommend <Page 10> 91.05.29.

-Change R43 from 10K_0603 to @10K_0603 . (Modify CKT&BO M)

-Change R67 from @10K_0603 to 10K_0603 . (Modify CKT&BO M)

-Change R433 from @10K_0603 to 10K_0603 . (Modify CKT&B OM)

-Change R434 from 10K_0603 to @10K_0603 . (Modify CKT&B OM)

B B

9.Add the By-Pass Capacitors for improving CPUCLK differential signals <Page 13> 91.05.29.

-Change C197,C201 from @10PF to 10PF . (Modify CKT&BO M)

10.Add the By-Pass Capacitor to improve SDAT A IN V AL # l ay ou t le ng th is su e < Pa g e 3> 91 .0 5. 29 .

-Add a 20PF Capacitor between CPU socket(U27.AN33) and GND. (Mo dify CKT,BOM and Layout)

11.Modify the schematic for ENE (ENE has internal clock already)<Page 22> 91.05.29.

-Change R358 from 0ohm to @0ohm . (Modify CKT&BOM)

12.Modify the schematic for delay CPURST# timing (Change the signal issued from NB to SB)
<Page 6,16> 91.05.29.

-Change R137 from 0ohm to @0ohm . (Modify CKT&BOM)

-Change R205 from @0ohm to 0ohm . (Modify CKT&BOM)

13.Change the value for powergood related<Page 30> 91.05.29.

-Change R224 from 10K_0603ohm to 20K_0603ohm . (Modify CKT&BOM)

14.Change the power source for ALI recommend . <Page 16> 91.06.01.

A A

-Change R153.1's connection from +3VALW to +3VS . (Modi fy CKT&Layout)

15.Change the power source of DDCDATA/DDCCLK for ATI recommen d . < P a g e 14> 91.06 . 01 .

-Change R8.2 and R9.2's connection to Q1.1 and Q2.1 . (Modify CKT&Layout)

-Add R? and R? (2.2Kohm) from DDCDATA/CLK to +3VS . (Modify CKT,BOM and Lay out)

-Change R7 from 100K to 33ohm and connection from +12VS to +3VS . (Modify C KT,BOM and Layout)

5

4

16.Change the SUSP# and CLK GEN PWR_DWN# related schematic to improve the
leakage issue . <Page 31,13> 91.06.03.

-Connect to +3VALW by adding R528 10Kohm . (Modify CKT,BOM and Layout)

-Change R322 from 0ohm to @0ohm . (Modify CKT&BOM)

-Change R321 from @10Kohm to 10Kohm . (Modify CKT&BOM)

17.Modify LVDS_BLON# related schematic for LCD backlight issue . <Page 15,27> 91.06.03.

-Disconnect U12.4 and LVDS_BLON# and then jump a wire from U12.4 t o Q11. 2 .
(Temp solution for A-TEST rework)

18.Modify the signal RUNON related schematic for ATI recommend power sequence
(+1.8VS early to +3VS) . <Page 31> 91.06.03.

-Cut RUNON signal to C213.1 and then connect to +12VS by ad ding R529 10Kohm .
(Modify CKT,BOM and Layout)

19.Modify the signal DC_STOP# related schematic for ATI recommend . <Page 6> 91.06.03.

-Change Q51 from 2N7002 to @2N7002 . (Modify CK T&BOM)

-Change R211 from 4.7Kohm to @4.7Kohm . (Modify CKT&BOM)

20.Modify the schematic for AMD recommend and layout improve . <Page 3,4> 91.06.07.

-Change R451 from 1Kohm to 510ohm . (Modify CKT&BOM)

-Add R530 75ohm between Q17.2 and the signal FERR . (Modi fy CKT,BOM and Layout)

-Add C518 1UF_0603 from VREF_SYS to +CPUCORE . (Modify CKT,BOM and Layout)

-Add C519 @1UF_0603 from VREF_SYS to GND . (Modify CKT&Layout )

-Add CB106 4.7UF_0805 from U27.AJ23(+VCCA2.5) to GND . (Modify CKT,BOM and Layout)

-Add C520 39PF from +VCCP2.5 to GND . (Modify CKT,BOM and Layout)

-Del Q50(@MMBT3904) . (Modify CKT,BOM and Layout)

21.Modify the schematic for the signal "LVDS_BLON#" related . <Page 9,27> 91.06.08.

-Change the netname from LVDS_BLON to LVDS_BLON# . (Modify CKT onl y)

-Add Q60(2N7002) and R531(10Kohm) pull high bet ween U3.D2 and
LVDS_BLON# . (Modify CKT,BOM and Layout)

22.Cut the MVREF_DIM to MVREF_DIM1 and MVREF_DIM2 for ATI recommend . <Page 11>

91.06.08.

-Add the MVREF_DIM1 related schematic(R532,R533,R534,C521,C522,C523)
. (Modify CKT,BOM and Layout)

23.Modify ISA pull high resistors' value . <Page 18> 91.06.08.

-Change RP36,RP26,RP34 from 10P8R_10K to 10P8R_47K . (Modify CKT,BOM and Layout )

24.Modify IDERST# related schematic . <Page 19> 91.06.08.

-Del D16,D17(RB751V) and then short the location . (Modify CKT, BOM and Layout)

-Disconnect U8.1 and U8.5 and then add R537 (10Kohm ) from U8.5 to +5VS .
(Modify CKT,BOM and Layout)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

----PLEASE SEE NEXT PAGE

3

2

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(1)

Size Document Number Rev

LA-1481 M/B

!"#, $%

Date: Sheet

14, 2002

1

42 47

0.3

of

5

4

3

2

1

BCY26 A-TEST Modify <91.05.20.~91.06.27.
>

25.Modify PCLK_PCM related schematic . <Page 22,27> 91.06.08.

-Add the 2N7002 related schematic (add Q61,R538,R539) between the signal PCLK_PCM and
U29.A10/R524.1 . (Modify CKT,BOM and Layout)

D D

-Del R199(@0ohm) and reconnect U12.165 to PCMCLKE . (Modify CKT,BOM and Layout)

26.Modify PM_CLKRUN# related schem at ic . <P ag e 22 > 91 .0 6.0 8.

-Add R543 (@0ohm) between U29.B15 and PM_CLKRUN# . (Modify CKT,BOM and Layout)

27.Modify PCM_SUSP# related schematic . <Page 22> 91.06.08.

-Del D35(RB751V) and then short the location . (Modify CKT, BOM and Layout)

28.Modify PWRGD related schematic . <Page 30> 91.06.08.

-Del U10(MAX809SEUR) . (Modify CKT,BOM and Layout)

-Add U31(7SH08) related schematic (Add R540,R541,C524) . (Modify CKT,BOM an d Layout)

29.Modify SYSON related schematic for 2.5V and 3V timing delay . <Page 31> 91.06.08.

-Add R542(0ohm) from SYSON to Q53.2 and add C525(@0.1UF) between Q53.2 and GND .
(Modify CKT,BOM and Layout)

30.Modify CPU internal PLL power source related schematic . <Page 4> 91.06.08.

C C

-Change U9 from SI9183BT-25 to SI9182DH-25 and the related sc hematic (Add
C526,Del C164,C158) . (Modify CKT,BOM and Layo ut)

31.Modify SB Pull High/Low related schematic for ALI updated . <Page 17> 91.06.10.

-Add R545,R546,R547,R548(10Kohm) from U6.U3/R5/U2/T4 to +5VS .
(Modify CKT,BOM and Layout)

-Add R544,R549(1Kohm) from U6.E4/Y5 to GND . (Modify CKT,BOM an d Layout)

32.Modify NB Pull Low resistors' value related schematic. <Page 10> 91.06.11.

-Change R62,R63,R65,R66,R67,R68,R71,R72,R73,R155R148,R161,R167,R175,R184,R427,
R430,R432,R436,R438,R440 from 10K_0603 to 4.7K_0603 . (Modify CKT&BO M)

-Change R64,R69,R70,R194,R434 from @10K_0603 to @4.7K_0603 . (Modify CKT &BOM)

33.Modify LAN LED signals related schematic. <Page 20> 91.06.11.

-Change U21.80's connection from LED_YELP to LED2_YELN . (Modify CKT&Layout)

-Change U21.79's connection from LED1_GRNP to LED1_GRNN . (Modify CKT&Layo ut)

B B

-Change R518.1's connection from LED2_YELN to LED2_YELP . (Modify CKT&Layout )

-Change R492.1's connection from LED1_GRNN to LED1_GRNP . (Modify CKT&Layo ut)

34.Modify NB Pull High/Low resistors' related schematic. <Page 10> 91.06.11.

-Change R160 from 10K_0603 to @10K_0603 . (Modify CKT&B OM)

35.Modify NB VDD related schematic. <Page 9> 91.06.11.

-Change R391,R395,R396,R397 from 1Kohm to 3.3Kohm . (Modify CKT&BOM)

36.Modify NB strap input related schematic. <Page 10> 91.06.12.

-Change R61 from 2.2K_0603 to 3.3K_0603 . (Modify CKT &BOM)

-Change R37 from 8.2K_0603 to 5.6K_0603 . (Modify CKT &BOM)

37.Modify VGATE related schematic . <Page 30> 91.06.12.

-Change R225 from 10K_0603 to @10K_0603 . (Modify CKT&B OM)

38.Modify CPU VID related schematic . <Page 33> 91.06.12.

A A

-Change R467 from 10Kohm to @10Kohm . (Modify CKT&BOM)

-Change RP100 from 8P4R_10K_0804 to @8P4R_10K_0804 . (Modify CKT&BOM)

39.Modify VR_POK_1 timing related schematic . <Page 30> 91.06.12.

-Change C222 from 0.1UF_0603 to 0.047U F_0603 .
(Modify CKT&BOM)

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

40.Modify RJ-45&11 related schematic for EMI recommend . <Page 25> 91.06.12.

-Change VH1 from DSSA-P3100SB to @DSSA-P3100SB . (Modify CKT&BOM)

-Connect LANGND and GND by add R550(0_0603ohm) . (Modify CKT,BOM an d Layout)

41.Modify BIOS FLASH# related schematic for Compal HW1 recommend . <Page 25> 91.06.12.

-Change R346 from 100Kohm to 1Kohm , and then change its connecti on from +12VS to
SUS_STAT# . (Modify CKT,BOM and Layout)

42.Modify PWRGD related schematic . <Page 30> 91.06.08.

-Add U31(74LVC08) related schematic (Add C527,R551,R541) . (Modify CKT,BOM an d Layout)

43.Modify CPU Bypass Cap. related schematic for cost down . <Page 5> 91.06.14.

-Del CE13,CE14(220UF_D2_4V_25m) . (Modify CKT,BOM and Layout)

-Change CE3,CE16,CE7,CE5,CE11,CE6,CE12,CE15 from 220UF_D2_4V_25m to
330UF_D2_2.5V_15m . (Modify CKT&BOM)

44.Modify NB DC_STOP# related schematic after A-TEST verified . <Page 6> 91.06.14.

-Del DC_STOP# related schematic (Del R458,R459,R460,CB93,Q51,Q 52) .
(Modify CKT,BOM and Layout)

45.Modify NB XTLOUT related schematic after A-TEST verified . <Page 9> 91.06.14.

-Del U3.A9(XTLOUT) related schematic (Del R28,X1,C54,C58,JOPEN3 ) .
(Modify CKT,BOM and Layout)

46.Modify IRQ8# power source . <Page 17> 91.06.14.

-Change R186.2's connection from +5VALW to +3VALW . (Mo dify CKT&Layout)

47.Modify CODEC Connector's related schematic for FDD active LED function . <Page 24>

91.06.14.

-Change JP6.16 from AGND to GND . (Modify CKT&Layout)

-Change JP6.27 from LED2 to DRV_0# . (Modify CKT&Lay out)

-Add Q62(DTC124EK) . (Modify CKT,BOM and La yout)

-Change Q41 from 2N7002 to @2N7002 . (Modify CKT &BOM)

-Change Q42 from SI2304DS to @SI2304DS . (Modify CKT& BOM)

-Change R368 from 100Kohm to @100Kohm . (Modify CKT&BOM)

48.Modify JP8's library and related schematic for customer request . <Page 26> 91.06.14.

-Modify the JP8 Internal Keyboard's related schematic (Del Q43,R376,R362,R 375,R377,R378) .
(Modify CKT,BOM and Layout)

49.Modify EC_SMD/EC_SMC related schematic . <Page 27> 91.06.14.

-Change RP42.7/RP42.8's connection from +5VALW to +3VS and RP42.5/ RP42.6 keep +5VALW
still . (Modify CKT&Layout)

50.Modify CPU Thermal related schematic . <Page 3> 91.06.14.

-Add R552(150ohm) between +3VS and C377.1 . (Modif y CKT,BOM and Layout)

-Del Q50(@MMBT3904) . (Modify CKT,BOM and Layout)

51.Modify SMI# related schematic for noise issue . <Page 3> 91.06.14.

-Add C528(@560PF) between SMI# and GND . (Modify CKT,BOM and Layout)

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(2)

Size Document Number Rev

LA-1481 M/B

!"#, $%

3

2

Date: Sheet

14, 2002

1

43 47

0.3

of

5

4

3

2

1

BCY26 A-TEST Modify <91.05.20.~91.06.27.
>

52.Modify VR_POK related schematic . <Page 28,30> 91.06.14.

-Add the 2N7002 related schematic (add R553,Q63) b etween the signal VGATE and
U31.2 . (Modify CKT,BOM and Layout)

D D

-Add the net POK_EN from U23.12 to Q63.2 . (Modify CKT,BOM and Layout)

53.Modify MOD_AUDIO_MONR rel ate d sc hem ati c . < Pag e 24 > 91 .06 .17.

-Change R363 from 20Kohm to 0ohm . (Modify CKT&BOM)

-Change R364 from 33Kohm to @33Kohm . (Modify CKT&BOM)

54.Modify USB ports' power source related schematic . <Page 29> 91.06.17.

-Del F7,F3,F4(@POLYSWITCH_0.75A) to +5VS . (Modify CKT,BO M and Layout)

-Change F2,F5,F6 from POLYSWITCH_0.75A to EVERFUSE_1.1A . (Modify CKT&BOM)

55.Modify RTC related schematic from IRQ8 to SIRQ . <Page 17> 91.06.17.

-Add R554(@0ohm) between RTC and IRQ8# . (Modify CKT,BOM and Layout)

-Change R186.2's connection from +3VALW to GND . (Modi fy CKT&Layout)

56.Modify SCI# related schematic from RUM_EN T 1 t o O FF _C D PW R . < Pa ge 17 > 9 1. 06 .1 7.

-Add R555(0ohm) between SCI# and OFFCDPWR . (Modify C KT,BOM and Layout)

C C

-Change D18 from RB751V to @RB751V . (Modify CKT,BOM and La yout)

-Change R142 from 4.7Kohm to @4.7Kohm . (Modify CKT&BOM)

57.Change the SUSP# related schematic to improve the leakage issue by SW timing delay .
<Page 31> 91.06.17.

-Change R528 from 10Kohm to @10Kohm . (Modify CKT&BOM)

58.Change the VGATE related schematic to avoid the power issue by power team .
<Page 30>91.0 6. 17 .

-Change R553 from @0_0603ohm to 0_0603ohm . (Modify CKT&BOM)

-Change Q63 from 2N7002 to @2N7002 . (Modify CKT &BOM)

59.Change the ATI CAL related schematic for ATI updated . <Page 6>91.06.18.

-Change R14 from 60.4_1%_0603ohm to 30_1%_0603ohm . (Modify CKT&BOM)

60.Change the RJ45 jack related schematic for Safety team request . <Page 25>91.06.19.

-Change JP20.13,JP20.14(RJ-45 & RJ-11)'s connection fro m LANGND to NC .

B B

(Modify CKT&Layout)

-Change JP20.9,JP20.12(RJ-45 & RJ-11)'s connection from NC to LANGND .
(Modify CKT&Layout)

61.Cancel modify RTC related schematic from IRQ8 to SIRQ action . <Page 17> 91.06.19.

-Del R554(@0ohm) , and then short RTC and IRQ8# directly . (Modif y CKT,BOM and Layout)

-Change R186.2's connection from GND to +5VALW . (Modi fy CKT&Layout)

62.Cancel modify SCI# related schematic from RUM_ENT1 to OFF_CDPWR action . <Page 17>

91.06.19.

-Del R555(0ohm) between SCI# and OFFCDPWR . (Modify CKT, BOM and Layout)

-Change D18 from @RB751V to RB751V . (Modify CKT,BOM and La yout)

-Change R142 from @4.7Kohm to 4.7Kohm . (Modify CKT&BOM)

63.Modify ISA BUS pull high resistors' value for RTC related . <Page 18> 91.06.19.

A A

-Change RP36,RP26,RP34 from 10P8R_47K to 10P8R_10K . (Modify CKT&BOM)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

64.Modify RTC related schematic to fix the RTC fail isssue . <Page 17,18,24> 91.06.19.

-Change CB39 from 22UF_10V_1206 to 10UF_6.3V_1206 . (Modify CKT&BOM)

-Del Q15(MMBT3906),Q16(3904),R162(10Kohm),R156(51Kohm),R158(10Kohm) .
(Modify CKT,BOM and Layout)

-Add RTC chip (U32,DS1685) related schematic(Add U32,C529,C530,C531,C532,R554,
R555,R556,R557,R558,R559,R560,R561,R562,J3,J4,X8) . (Modify CKT,BOM an d Layout)

65.Modify ATI strap input related schematic for ATI updated . <Page 10> 91.06.19.

-Change R433 from 10K_0603 to @10K_0603 . (Modify CKT&B OM)

-Change R434 from @4.7K_0603 to 4.7K_0603 . (Modify C KT&BOM)

-Change R427 from 4.7K_0603 to 2.2K_0603 . (Modify CK T&BOM)

66.Modify ATI VDD related schematic . <Page 9> 91.06.19.

-Change L17,L18,L48 from BLM21A601SPT to HB-1M2012-121JT . (Modify CKT&BOM)

67.Modify ATI NB_VREFSYS related schematic for noise issue improved . <Page 6> 91.06.20.

-Change C140 from 0.047UF to 0.1UF . (Modify CKT& BOM)

-Add C533(0.1UF) between +CPU_CORE and NB_VREFSYS . (Modify CKT,BOM a nd Layout)

68.Del some +2.5VDD related CAP for cost down and free space . <Page 20> 91.06.20.

-Del C508(1000PF),C514 and C485(0.1UF) . (Modify CKT,BOM and Layout)

69.Modify RTC related schematic for ALI recommend . <Page 17,18,27> 91.06.21.

-Change RP8 from 8P4R_4.7K_0804 to @8P4R_4.7K_0804 . (Modify CKT&BOM)

-Change the net name from RTC to IRQ8# . (Modify CKT&Layout)

-Change R186 from 4.7Kohm to @4.7Kohm . (Modify CKT&BOM)

-Add Q15(MMBT3906),Q16(3904),R162,R156,R158 . (Modify CKT,BOM an d Layout)

-Add "@" mark to D38,U32,C529,R530,C531,C532,R554,R555,R558,R559,R556,R 557,
R561,R562,R566,X8 for SMT no build in . (Modify CKT&BOM)

-Del RTC net to U12.23 . (Modify CKT&Layout)

-Add R565(0ohm) between the net PC7 and IRQ8# . (Modify CKT,BOM and Layout)

-Change R325 from 100Kohm to 10Kohm . (Modify CKT&BOM)

70.Modify LREST1# related schematic for EC recommend . <Page 27> 91.06.21.

-Del Q30(@2N7002) . (Modify CKT&Layout)

71.Modify +3VS transfer related schematic . <Page 31> 91.06.21.

-Change R301 from 75ohm to 15_0603ohm . (Modify CKT,BOM and La yout)

72.Modify LAN power related schematic . <Page 20> 91.06.21.

-Change L51,L52 from 4.7UH_80mA to 0_0805ohm . (Modify CKT&BOM)

73.Modify RTC related schematic for SW team request . <Page 18> 91.06.24.

-Add R567(@0ohm) between U32.13 and U17.8 . (Modify CKT&Layout)

-Del "@" mark to D38,U32,C529,R530,C531,C532,R555,R558,R559,R556,R557,R561,R562,X8
for SMT no build in . (Modify CKT&BOM)

-Exchange J3 and R555's location and connection . (Modif y CKT&Layout)

-Change CB39 from 22UF_10V_1206 to 10UF_6.3V_1206 . (Modify CKT&BOM)

74.Modify AC97 Codec related schematic for EMI team request . <Page 13> 91.06.24.

-Change C181 from @10PF to 1000PF . (Modify CKT&BO M)

-Change R278 from 22ohm to 0ohm . (Modify CKT&BOM)

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(3)

Size Document Number Rev

LA-1481 M/B

!"#, $%

3

2

Date: Sheet

14, 2002

1

44 47

0.3

of

5

4

3

2

1

BCY26 A-TEST Modify <91.05.20.~91.06.27.
>

75.Modify CLK GEN VDD related schematic for EMI team request to improve 400MHz noise .
<Page 13> 91.06.24.

-Change JOPEN4(Short) to L53(HB-1M2012-121JT) . (Modify CKT,BO M and Layout)

76.Modify VREF_SYS related schematic for ATI recommend . <Page 3> 91.06.25.

D D

-Change C149 from 0.01UF to 0.047UF . (Modify CKT&B OM)

77.Modify S2K_VREF related schematic for ATI recommend . <Page 6> 91.06.25.

-Change R149,R150 from 100_1%ohm to 60.4_1%ohm . (Modify CKT&BOM)

B-TEST BOM RELEASE

BFY26 B-TEST Modify <91.06.27.~91.07.29.
>

78.Modify VREF_SYS related schematic for noise improved . <Page 3> 91.06.25.

-Change C519 from @1UF_0603 to 1UF_0603 . (Modify CKT&BOM )

79.Modify CPU LCL related schematic for timing delay improved . <Page 3> 91.06.25.

-Change C40 from 5PF to @5PF . (Modify CKT&BOM)

80.Modify EC PCMCLKE related schematic for EC team request . <Page 27> 91.06.26.

-Change U12.36's connection from LED2 to PCMCLKE . (Modify CKT&Layout )

C C

-Change U12.165's connection from PCMCLKE to PCRST# and add R199(0ohm) be tween them .
(Modify CKT,BOM and Layout)

81.Modify Serial Port related schematic for CAP size. <Page 29> 91.06.26.

-Change C331 from 0.1UF to 0.1UF_0805 . (Modify CKT,BOM and Layout)

82.Modify VR_POK related schematic. <Page 30> 91.06.26.

-Change R225 from @10K_0603 to 10K_0603 . (Modify CKT&B OM)

-Change R553 from 0_0603 to @0_0603 . (Modify CKT &BOM)

-Change Q63 from @2N7002 to 2N7002 . (Modify CK T&BOM)

83.Modify CLK GEN related schematic for CAP removed because layout improve the timing issue .
<Page 13> 91.06.27.

-Change C201 and C197 from 10PF to @10PF . (Modify CKT& BOM)

84.Modify LVDS spread spectrum chip (SM560) related schematic . <Page 8> 91.06.27.

B B

-Change R400 from @0ohm to SS@10Kohm . (Modify CKT&BOM)

-Change R10 from SS@10ohm to @10ohm . (Modify CKT&BOM)

-Change C21 from SS@22PF to @22PF . (Modify CKT&BOM )

85.Modify CLK GEN related schematic for AC97 Codec clock signal disable . <Page 13> 91.06.27.

-Change R278 from 0ohm to @22ohm . (Modify CKT&BOM)

-Change C181 from 1000PF to @10PF . (Modify CKT&BO M)

86.Modify Crystal CAP value for internal review . <Page 13> 91.06.27.

-Change C180 and C186 from 10PF to 12PF . (Modify CKT&B OM)

87.Modify SODIMM2 CAP for cost down . <Page 7> 91.06.27.

-Change C230 from 150UF_D2_6.3V to @150UF_D2_6.3V . (Modify CKT&BOM)

88.Modify CRT connector related schematic . <Page 14> 91.06.27.

-Change R7 from 33ohm to 0ohm . (Modify CKT&BOM)

A A

89.Modify Crystal CAP value for internal review . <Page 17> 91.06.27.

-Change C130 and C113 from 10PF to 12PF . (Modify CKT&B OM)

90.Modify PCLK_PCM related schematic . <Page 22> 91.06.27.

-Change R538 from 10Kohm to 100Kohm . (Modify CKT&BOM)

5

4

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

91.Modify BD_ID setting related schematic . <Page 27> 91.06.27.

-Change R343,R250,R268 from 10Kohm to @10Kohm . (Modify CKT&BOM)

92.Modify CAP value for cost down . <Page 6,7,8,13,20,21,25> 91.06.28.

-Change CB20,CB42,CB16,CB92,CB7,CB90,CB91,CB43,CB44,CB82 from 22U_10V_1206
to 10U_10V_1206 . (Modify CKT&BOM)

B-TEST BOM EN1 RELEASE

93.Modify Spread Spectrum for Pin Define Error on S0/S1 . <Page 8> 91.07.03.

-Change R400 from SS@10Kohm to @10Kohm . (Modify CKT&BOM)

-Change R385 from @10Kohm to SS@10Kohm . (Modify CKT&BOM)

*Must modify schematic and layout w h e n C-TEST .

94.Modify Crystal PPM value because of R TC f un ct io n . <P a ge 18 > 9 1. 07 .0 3.

-Change X8 from 32.768KHZ to 32.768KHZ_10PPM . (Modify CKT&BOM)

95.Modify +RTCVCC power source related schematic . <Page 18> 91.07.03.

-Change D38 from RB751V to @RB751V . (Modify CKT&BOM)

96.Modify IDE connector related schematic . <Page 19> 91.07.03.

-Change R369,R20 from 10Kohm to @10Kohm . (Modify CKT&BOM)

-Change R373,R247 from @100Kohm to 100Kohm . (Modify CKT&BOM)

97.Modify DDR related resistors' val ue f or A TI r ec om men d . <Pa ge 12> 91. 07 .17 .

-Change R359,R360,R361,R501,R502,R503,R506,R507,R508 from 33ohm to 56ohm .
(Modify CKT&BOM)

-Change RP63,RP64,RP65 from 33ohm_8P4R_0804 to 56ohm_8P4R_0804 .
(Modify CKT&BOM)

98.Modify VREF_SYS related schematic to improve the noise issue for ATI recommend .
<Page 3> 91.07.18.

-Change C518 from 1UF_0603 to 0.047UF_0603 . (Modify CKT&BOM )

-Change C519 from 1UF_0603 to @1UF_0603 . (Modify CKT&BOM )

-Change C147 from 0.1UF to @0.1UF . (Modify CKT&BOM)

99.Modify NB_VREFSYS related schematic to improve the noise issue for ATI recommend .
<Page 6> 91.07.18.

-Change C533,C140 from 0.1UF to 0.047UF . (Modify CKT&B OM)

100.Modify SDCLK_NB _ EX T r e la te d s ch em at ic to im p ro ve th e c lo ck qu al it y fo r A T I r ec om me nd .
<Page 9,13> 91.07.18.

-Change C346 from 100PF to @100PF . (Modify CKT&BO M)

-Change R294 from 22ohm to 10ohm . (Modify CKT&BOM)

101.Modify LCD_DIGON r el at e d s ch em at ic to f ix th e w hi te sc r ee n i ss ue te mp or a ry . < P ag e 9 >

91.07.22.

-Change R531 from 10Kohm to @10Kohm . (Modify CKT&BOM)

-Change Q60 from 2N7002 to @2N7002 . (Modify CK T&BOM)

-Jump a wire from U3.D1 to Q60.1 . (REWORK)

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(4)

Size Document Number Rev

LA-1481 M/B

!"#, $%

3

2

Date: Sheet

14, 2002

1

45 47

of

0.3

5

4

3

2

1

BFY26 B-TEST Modify <91.06.27.~91.07.29.
>

102.Modify CP UC L K r e la te d s ch e ma ti c f or q ua li t y i mp ro v ed . < Pa ge 13 > 91 .0 7. 22 .

-Change C201,C197 from @10PF to 5PF_0.25% . (Modify CK T and BOM)

103.Modify +RTCVCC rel at ed sc he ma ti c t o f i x t he po we r s ou r ce is su e t em po ra r y . <P ag e 2 7>

91.07.22.

D D

-Del R345(0ohm_0603) and jump a wire from R345.1 to D10.1 . (Modif y BOM and REWORK)

104.Modify PW R GD r el at ed s ch em at ic f or B -T E ST im pr o ve d t e mp or ar y . < P ag e 3 0> 91 .0 7. 22 .

-Jump the Q20.1's pin and connect Q20.1's pin to R224.1 . (REWORK)

B-TEST BOM EN2 RELEASE

105.Correct SPECTRUM IC OrCAD library . <Page 8 > 9 1 . 07 . 2 2 .

-Change Pin7's define from S1 to S0 .

-Change Pin6's define from S0 to S1 .

106.Modify LCD_DIGON rel at ed s ch em at i c t o f ix t he wh it e s cr e en is s ue te mp o ra r y . <P ag e 9, 15 ,2 7>

91.07.22.

-Change Q60 from @2N7002 to 2N7002 . (Modify CK T&BOM)

-Cancel the wire from U3.D1 to Q60.1 . ( REWORK)

-Del R531 and redefine the Q60's related connection . (Modify CKT,BOM and Layout)

C C

-Change U12.4's connection from LVDS_BLON# to LCD_DIGON . (Modify CK T&Layout)

107.Modify HDD related s ch ema ti c f or C -T ES T i mp ro ve . < Pa ge 19 > 9 1.0 7. 23 .

-Change JP9.44's connection from +5VS to NC . (Modify CKT&Layout)

108.Modify ENE CardBus Ct r l I C r e la te d s ch ema t ic f o r n ew ver s io n p ha se in pr ep ar ed .
<Page 22> 91.07.23.

-Add R568(0ohm) between Q61.3 and Q61.1 . (Modify CKT,BOM and Layout)

-Change R538 from 100Kohm to @100Kohm . (Modify CKT&BOM)

-Change Q61 from 2N7002 to @2N7002 . (Modify CK T&BOM)

-Change R539 from 10Kohm to @10Kohm . (Modify CKT&BOM)

109.Modify CPUCLK related CA P va lu e f or q ua li t y i mp ro ve d . < Pa ge 13 > 9 1. 0 7. 23 .

-Change C201,C197 from 5PF_0.25% to 10PF . (Modify CKT& BOM)

110.Modify SDCLK_NB_EX T d a mp in g r es is t or 's va lu e f or q ua li ty im pr o ve d . <P ag e 13 > 9 1. 07 .2 3.

B B

-Change R282 from 51ohm to 39ohm . (Modify CKT& BOM)

111.Del REFCLK0_AC97 related signal net on M/B for EM I r eq ue st . <P ag e 1 3, 24 > 9 1. 07 .2 3.

-Del R278(@22ohm) and C181(@10PF) . (Modify CKT&Laout )

-Del REFCLK0_AC97 related signal net on M/B . (Modify CKT and Layout)

112.Modify m o de m r e la te d s c he ma ti c fo r EM I r e qu es t . < Pa ge 2 5> 91 .0 7. 2 3.

-Change C445,C449 from 220PF_3KV_1808 to @220PF_3KV_1808 . (Modify CKT and BOM )

113.Modify +RTCVCC relate d s ch em at ic to fi x t h e p ow er so ur ce is su e . < Pa ge 27 > 9 1. 07 .2 3.

-Add D39(RB751V) between U12.161 and K . (Modi fy CKT,BOM and Layout)

-Change R345 from 0ohm_0603 to @0ohm_0603 . (Modify CKT and BO M)

114.Modify ADP _I r el at ed sc h em at ic fo r cl ea r . < Pa ge 27 > 91 .0 7. 23 .

-Del ADP_I related signal net on M/B . (Modify CKT and Layout)

-Del R233(@2Mohm_0603) and C169(@0.22UF_0603) . (Modify CKT and Lay out)

A A

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

115.Modify ALi Chip PCIRST# r el at ed sc he ma ti c f o r v ol ta ge le ak ag e i ss ue fi x . <P a ge 16 > 9 1. 07 .2 3.

-Change the part from U31D(74LVC08) to U5(7SH08) and modify the r elated net connection .
(Modify CKT,BOM and Layout)

116.Modify PWRGD related schematic to make time delay meet spec. . <Page 13,30> 91.07.23.

-Del U31(74LVC08),R553(@0_0603),R223(@10K),R227(4.7K),C527(1UF_0603),R224(20K _0603),
C167(1UF_0603),R551(10K),R540(20K),C524(1UF_0603),R541(10K),R3 22(@0) ;
add U33(74LVC14),R576,R577(10K_0603),C537,C538(0.047UF_0603),Q64,Q65(MMBT2222A ),
R569,R572(4.7K_0603),C534,C535,C536(0.47UF_0603),R573,R574(20K_06 03),
R570,R571,R575(47_0603) and modify the related net connection . (Modify CK T,BOM and Layout)

117.Modify FERR related r es is t or 's va lu e . <P a ge 3> 91 .0 7. 23 .

-Change R530 from 75ohm to 33ohm . (Modify CKT and BOM )

118.Modify AMD_CPU_EMI_CLIP 's library for SMT process when C-T E ST . <P a g e 5 > 9 1 .07.23.

-Left PT2,PT3,PT4,PT5 only and update their PCBFootPrint and library . (Modif y CKT,BOM and
Layout)

119.Add TEST_CHIP on TOP/BOTTOM side for te st o n C -T E ST . < P ag e 1 8> 91. 07 .2 3.

-Add U34,U35(TEST_CHIP) ON TOP/BOTTOM SIDE . (Modify CKT&Layou t)

120.Modify CP UC L K r e la te d s ch e ma ti c f or q ua li t y i mp ro v ed . < Pa ge 13 > 91 .0 7. 24 .

-Change C201,C197 from 10PF to 5PF_0.25% . (Modify CKT and BOM)

121.Add J5 for CMOS r ef la sh us ed . < P ag e 2 7> 91 .0 7. 24 .

-Add J5 between K to GND . (Modify CKT&Layout)

122.Del the net 1394_PME# because the fu nc t io n d is ab le . < P ag e 2 1> 91 .0 7. 24 .

-Del the signal net 1394_PME# from U2.37 . (Modify CKT&Layou t)

123.Modify ATI N B c hi p C A L r e la te d s ch em at i c f or A TI re co m me nd . < Pa ge 6> 91 .0 7. 25 .

-Add C539,C540(0.01UF) from U3.A16 and U3.B16 to GND . (Modify CKT, BOM and Layout)

124.Modify FERR related r es is t or 's va lu e . <P a ge 3> 91 .0 7. 25 .

-Change R530 from 33ohm to 75ohm . (Modify CKT and BOM )

125.Modify PWRGD related schematic to make time delay meet spec. . <Page 30> 91.07.25.

-Modify Q20 and Q39 related connection . (Modify CKT and Layout)

-Del R570(47ohm_0603),R347(10Kohm),Q37(DTC124EK) . (Modify CKT,BOM and Layout)

126.Add some C AP f or SB q ua li ty . <P ag e 1 6> 91 .0 7. 25 .

-Add C541,C542,C543,C544(0.1UF) between +3VS and GND . (Mo dify CKT,BOM and Layout)

-Add C545,C546(0.1UF) between +5VS and GND . (Mo dify CKT,BOM and Layout)

127.Add ADP_I relate d s ch em at ic fo r Po we r te am re qu e st . < Pa ge 27 > 9 1. 07 .2 5.

-Add ADP_I related signal net on M/B . (Modify CKT and Layout)

-Add R233(2Mohm_0603) and C169(0.22UF_0603) . (Modify CKT and La yout)

128.Del CPU so c ke t r el at e d t es t p o in t r e la te d t o a vo i d p ow er no i se coupling . <Page 3> 91.07.26.

-Del TP6,TP7,TP8 . (Modify CKT&Layout)

129.Modify MVREF_DIM2 related re si st or s ' s iz e f or l ay ou t s pa ce . < P ag e 1 1> 91 .0 7. 26 .

-Change R464,R466 from @1K_1%_0603 to @1K_1% . (Modify CKT, BOM and Layout)

-Change R465 from 0ohm_0603 to 0ohm . (Modify CKT,BOM and La yout)

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(5)

Size Document Number Rev

LA-1481 M/B

!"#, $%

3

2

Date: Sheet

14, 2002

1

46 47

of

0.4

5

4

3

2

1

BFY26 B-TEST Modify <91.06.27.~91.07.29.
>

130.Modify SADDINCLK# related schematic fo r Jas on r equ es t . <P ag e 3 > 9 1. 07. 29 .

-Change L20,L21 from NL252018T-010J to 0ohm_0805 . (Modify CKT and BOM)

131.Modify NB Clock Termination related schematic to meet chip loading timing with CPU .
<Page 9> 91.07.29.

D D

-Change R401,R402,R411,R407 from 10ohm to @10ohm . (Modify CKT and BO M)

132.Modify Power Good related schematic to meet timing request . <Page 30> 91.07.30.

-Change R216's connection from +2.5V to +2.5VS . (Mo dify CKT&Layout)

-Change R216 from 4.7Kohm to 1Kohm . (Modify CKT&BOM)

-Add R579(47Kohm) between NB_PWRGD and GND . (Modify CK T,BOM and Layout)

-Add R578(10Kohm) between PWRGD and GND . (Modify CKT,BOM and Layout)

133.Modify SB related schematic for power source . <Page 16> 91.07.30.

-Change U5.5s connection from +3VS to +3VALW . (Mod ify CKT&Layout)

C-TEST BOM EN1 R ELEASE

134.Modify Power Good related schematic to meet timing request . <Page 30> 91.07.30.

-Del R224(20Kohm_0603) and R225(10Kohm_0603) . (Modify CKT,BOM and Layout)

135.Modify EC_PCLK by-pass CAP. related for P C IC LK t im in g d el ay . < P ag e 1 3> 91 .0 8. 09 .

C C

-Change C208 from @10PF to 27PF . (Modify CKT a nd BOM)

136.Add PCIRST# by-pass CAP. . <P ag e 1 6> 91 .0 8. 09 .

-Add C547(100PF) between PCIRST# and GND . (Modify CKT,BOM and Layout)

137.Correct Q63(2N70 0 2 ) ' s c onnection . <Page 30> 91.08.09.

-Change Q63.1's connection from GND to R569.2 . (M odify CKT&Layout)

-Change Q63.3's connection from R569.2 to GND . (M odify CKT&Layout)

138.Del the net 1394_PME # f or s ch em at ic cl ea r . <P a ge 28 > 9 1. 08 .0 9.

-Del the net 1394_PME# . (Modify CKT&Layout)

139.Modify +2.5_A's by- p as s C A P. fo r ma te r ia l s av in g . <P a ge 4> 91 .0 8. 09 .

-Change C152 from 4.7UF_10V_0805 to @4.7UF_10V_0805 . (Modify CKT an d BOM)

140.Modify LED_YELP and LED1_GRNP's resistor value fo r SE D re qu es t . <P a ge 20 > 9 1. 08 .09 .

-Change R518,R492 from 200ohm_0603 to 560ohm_0603 . (Modify CKT and BOM)

B B

141.Modify External RT C r el at e d s ch em at ic fo r th e f un ct i on re mo ve d . < Pa ge 18 ,2 7> 91 .0 8. 09 .

-Change U32 from DS1685 to @DS1685 . (Modify CKT and BOM)

-Change X8 from 32.768KHZ_10PPM to @32.768KHZ_10PPM . (Modify CKT and BOM)

-Change D39 from RB751V to @RB751V . (Modify CKT and BO M)

-Change R345 from @0_0603 to 0_0603 . (Modify CK T and BOM)

142.Modify FSB_100/ 1 33# related schematic for the function removed . <Page 10,13> 91.08.11.

-Change R334 from 8.2Kohm to @8.2Kohm . (Modify CKT and BOM)

-Change Q3,Q4,Q5,Q6 from 2N7002 to @2N7002 . (Modify CKT and BOM)

-Change R3 from 100Kohm to @100Kohm . (Modify CKT and BOM)

-Change R4,R12 from 10Kohm to @10Kohm . (Modify CKT and BOM)

143.Change REFCLK1_NB voltage level from +3. 3 V to +1. 8 V to me e t ATI's SPEC . <Page 13>

91.08.11.

A A

-Change R272 from 33ohm to 75ohm . (Modify CKT and BOM )

-Change C172 from @10PF to 100ohm . (Modify CKT and BOM)<Next versi on will relayout to fix that>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION . THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC. NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC.

5

4

144.Modify +RTCV C C r e la te d s ch em at i c f or c le ar . < P ag e 1 8> 91 .0 8. 11 .

-Change Q15 from MMBT3906 to @MMBT3906 . (Modify CKT and BOM)

-Change Q16 from 3904 to @3904 . (Modify CKT and BOM)

-Change D38 from @RB751V to RB751V . (Modify CKT and BO M)

-Change R158,R162 from 10K to @10K . (Modify CKT a nd BOM)

-Change R156 from 51K to @51K . (Modify CKT and BOM)

145.Modify DDR related schematic for quality improved . <Page 7,11,12> 91.08.12.

-Change R279,R285,R464 from @1K_1% to 1K_1% . (Modify CK T and BOM)

-Change R280,R533 from 0ohm_0603 to @0ohm_0603 . (Modify CKT and BO M)

-Change R465 from 0ohm to @0ohm . (Modify CKT and B OM)

-Change R466 from @1Kohm_1% to 866ohm_1% . (Modify CKT and B OM)

-Change R534 from @1Kohm_1%_0603 to 866ohm_1%_0603 . (Modify CKT and B OM)

-Change R532 from @1K_1%_0603 to 1K_1%_0603 . (Modify CK T and BOM)

-Change C235,C236,C237,C238,C239,C240,C245,C246,C247,C248,C258,C259,C260,C261,C262,
C263,C264,C265,C266,C267,C268,C269,C270 from 47PF to @47PF . (Modify CKT and BOM)

146.Modify ENE CB142 0 r el at ed s ch em at ic fo r E N E r e co mm en d . <P ag e 2 2> 91 .0 8. 12 .

-Change R479,R480,R485,R489 from 22Kohm to @22Kohm . (Modify CKT and BOM)

Compal Electronics, Inc.

Title

H/W2 EE Dept. PIR SHEET(6)

Size Document Number Rev

LA-1481 M/B

!"#, $%

3

2

Date: Sheet

14, 2002

1

47 47

0.5

of