Fujitsu MPG3XXXAH User Manual

MPG3xxxAH
DISK DRIVES
PRODUCT MANUAL
C141-E112-01EN
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C141-E112-01EN
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MANUAL ORGANIZATION

MPG3xxxAH
DISK DRIVES
PRODUCT
MANUAL
(C141-E112)
<This manual>
MPG3xxxAH
DISK DRIVES
MAINTENANCE
MANUAL
(C141-F047)
• DEVICE OVERVIEW
• DEVICE CONFIGURATION
• INSTALLATION CONDITIONS
• THEORY OF DEVICE OPERATION
• INTERFACE
• OPERATIONS
• MAINTENANCE AND DIAGNOSIS
• REMOVAL AND REPLACEMENT PROCEDURE
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PREFACE

This manual describes the MPG3xxxAH series, a 3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface.
This manual explains, in detail, how to incorporate the hard disk drives into user systems.
This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems.
This manual consists of the following six chapters:
Chapter 1 DEVICE OVERVIEW
Chapter 2 DEVICE CONFIGURATION
Chapter 3 INSTALLATION CONDITIONS
Chapter 4 THEORY OF DEVICE OPERATION
Chapter 5 INTERFACE
Chapter 6 OPERATIONS
In this manual, disk drives may be referred to as drives or devices.
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Conventions for Alert Messages
This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.
The following are the alert signals and their meanings:
This indicates a hazardous situation likely to result in serious personal injury if the user does not perform the procedure correctly.
This indicates a hazardous situation could result in personal injury if the user does not perform the procedure correctly.
This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. This alert signal also indicates that damages to the product or other property, may occur if the user does not perform the procedure correctly.
This indicates information that could help the user use the product more efficiently.
In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:
(Example)
IMPORTANT
HA (host adapter) consists of address decoder, driver, and receiver. ATA is an abbreviation of "AT attachment". The disk drive is conformed to the ATA-4 interface
The main alert messages in the text are also listed in the “Important Alert Items.”
vi C141-E112-01EN
LIABILITY EXCEPTION
"Disk drive defects" refers to defects that involve adjustment, repair, or replacement. Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.
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CONTENTS

page
CHAPTER 1 DEVICE OVERVIEW
1.1 Features ................................................................................................................................1 - 1
1.1.1 Functions and performance ..................................................................................................1 - 1
1.1.2 Adaptability..........................................................................................................................1 - 2
1.1.3 Interface................................................................................................................................1 - 2
1.2 Device Specifications...........................................................................................................1 - 4
1.2.1 Specifications summary........................................................................................................1 - 4
1.2.2 Model and product number .................................................................................................. 1 - 5
1.3 Power Requirements.............................................................................................................1 - 5
1.4 Environmental Specifications............................................................................................... 1 - 8
1.5 Acoustic Noise...................................................................................................................... 1 - 8
1.6 Shock and Vibration.............................................................................................................1 - 9
1.7 Reliability.............................................................................................................................1 - 9
1.8 Error Rate.............................................................................................................................1 - 10
1.9 Media Defects.......................................................................................................................1 - 10
CHAPTER 2 DEVICE CONFIGURATION
......................................................................................... 1 - 1
............................................................................ 2 - 1
2.1 Device Configuration ........................................................................................................... 2 - 1
2.2 System Configuration...........................................................................................................2 - 3
2.2.1 ATA interface.......................................................................................................................2 - 3
2.2.2 1 drive connection ................................................................................................................2 - 3
2.2.3 2 drives connection...............................................................................................................2 - 3
CHAPTER 3 INSTALLATION CONDITIONS
3.1 Dimensions...........................................................................................................................3 - 1
3.2 Handling Cautions................................................................................................................3 - 3
3.2.1 General notes........................................................................................................................3 - 3
3.2.2 Installation............................................................................................................................3 - 3
3.2.3 Recommended equipments................................................................................................... 3 - 3
3.3 Mounting..............................................................................................................................3 - 4
3.4 Cable Connections................................................................................................................3 - 8
3.4.1 Device connector..................................................................................................................3 - 8
...................................................................... 3 - 1
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3.4.2 Cable connector specifications .............................................................................................3 - 9
3.4.3 Device connection ................................................................................................................3 - 9
3.4.4 Power supply connector (CN1) ............................................................................................ 3 - 10
3.4.5 System configuration for Ultra DMA................................................................................... 3 - 10
3.5 Jumper Settings ....................................................................................................................3 - 13
3.5.1 Location of setting jumpers..................................................................................................3 - 13
3.5.2 Factory default setting ..........................................................................................................3 - 14
3.5.3 Jumper configuration............................................................................................................3 - 14
CHAPTER 4 THEORY OF DEVICE OPERATION.............................................................. 4 - 1
4.1 Outline..................................................................................................................................4 - 1
4.2 Subassemblies....................................................................................................................... 4 - 1
4.2.1 Disk ......................................................................................................................................4 - 1
4.2.2 Head......................................................................................................................................4 - 2
4.2.3 Spindle..................................................................................................................................4 - 3
4.2.4 Actuator................................................................................................................................4 - 3
4.2.5 Air filter................................................................................................................................4 - 3
4.3 Circuit Configuration............................................................................................................ 4 - 4
4.4 Power-on Sequence..............................................................................................................4 - 6
4.5 Self-calibration.....................................................................................................................4 - 8
4.5.1 Self-calibration contents....................................................................................................... 4 - 8
4.5.2 Execution timing of self-calibration.....................................................................................4 - 9
4.5.3 Command processing during self-calibration....................................................................... 4 - 9
4.6 Read/write Circuit ................................................................................................................4 - 10
4.6.1 Read/write preamplifier (PreAMP) ...................................................................................... 4 - 10
4.6.2 Write circuit..........................................................................................................................4 - 10
4.6.3 Read circuit........................................................................................................................... 4 - 11
4.6.4 Synthesizer circuit ................................................................................................................4 - 12
4.7 Servo Control .......................................................................................................................4 - 12
4.7.1 Servo control circuit .............................................................................................................4 - 13
4.7.2 Data-surface servo format ....................................................................................................4 - 16
4.7.3 Servo frame format...............................................................................................................4 - 16
4.7.4 Actuator motor control .........................................................................................................4 - 18
4.7.5 Spindle motor control........................................................................................................... 4 - 19
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CHAPTER 5 INTERFACE........................................................................................................5 - 1
5.1 Physical Interface ................................................................................................................. 5 - 2
5.1.1 Interface signals....................................................................................................................5 - 2
5.1.2 Signal assignment on the connector ..................................................................................... 5 - 3
5.2 Logical Interface...................................................................................................................5 - 6
5.2.1 I/O registers .......................................................................................................................... 5 - 6
5.2.2 Command block registers..................................................................................................... 5 - 8
5.2.3 Control block registers ......................................................................................................... 5 - 13
5.3 Host Commands ................................................................................................................... 5 - 13
5.3.1 Command code and parameters............................................................................................ 5 - 14
5.3.2 Command descriptions......................................................................................................... 5 - 16
5.3.3 Error posting.........................................................................................................................5 - 70
5.4 Command Protocol...............................................................................................................5 - 71
5.4.1 Data transferring commands from device to host................................................................. 5 - 71
5.4.2 Data transferring commands from host to device................................................................. 5 - 73
5.4.3 Commands without data transfer.......................................................................................... 5 - 75
5.4.4 Other commands................................................................................................................... 5 - 76
5.4.5 DMA data transfer commands.............................................................................................. 5 - 76
5.5 Ultra DMA feature set..........................................................................................................5 - 78
5.5.1 Overview ..............................................................................................................................5 - 78
5.5.2 Phases of operation...............................................................................................................5 - 79
5.5.3 Ultra DMA data in commands.............................................................................................. 5 - 79
5.5.3.1 Initiating an Ultra DMA data in burst .................................................................................. 5 - 79
5.5.3.2 The data in transfer...............................................................................................................5 - 80
5.5.3.3 Pausing an Ultra DMA data in burst .................................................................................... 5 - 80
5.5.3.4 Terminating an Ultra DMA data in burst ............................................................................. 5 - 81
5.5.4 Ultra DMA data out commands............................................................................................ 5 - 83
5.5.4.1 Initiating an Ultra DMA data out burst ................................................................................ 5 - 83
5.5.4.2 The data out transfer.............................................................................................................5 - 84
5.5.4.3 Pausing an Ultra DMA data out burst .................................................................................. 5 - 84
5.5.4.4 Terminating an Ultra DMA data out burst ........................................................................... 5 - 85
5.5.5 Ultra DMA CRC rules.......................................................................................................... 5 - 87
5.5.6 Series termination required for Ultra DMA.......................................................................... 5 - 88
5.6 Timing.................................................................................................................................. 5 - 89
5.6.1 PIO data transfer...................................................................................................................5 - 89
5.6.2 Multiword data transfer........................................................................................................ 5 - 90
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5.6.3 Ultra DMA data transfer.......................................................................................................5 - 91
5.6.3.1 Initiating an Ultra DMA data in burst ..................................................................................5 - 91
5.6.3.2 Ultra DMA data burst timing requirements.......................................................................... 5 - 92
5.6.3.3 Sustained Ultra DMA data in burst ......................................................................................5 - 95
5.6.3.4 Host pausing an Ultra DMA data in burst............................................................................5
- 96
5.6.3.5 Device terminating an Ultra DMA data in burst .................................................................. 5 - 97
5.6.3.6 Host terminating an Ultra DMA data in burst......................................................................5 - 98
5.6.3.7 Initiating an Ultra DMA data out burst ................................................................................ 5 - 99
5.6.3.8 Sustained Ultra DMA data out burst .................................................................................... 5 - 100
5.6.3.9 Device pausing an Ultra DMA data out burst ...................................................................... 5 - 101
5.6.3.10 Host terminating an Ultra DMA data out burst .................................................................... 5 - 102
5.6.3.11 Device terminating an Ultra DMA data in burst .................................................................. 5 - 103
5.6.4 Power-on and reset............................................................................................................... 5 - 104
CHAPTER 6 OPERATIONS ..................................................................................................... 6 - 1
6.1 Device Response to the Reset...............................................................................................6 - 1
6.1.1 Response to power-on .......................................................................................................... 6 - 2
6.1.2 Response to hardware reset.................................................................................................. 6 - 3
6.1.3 Response to software reset ...................................................................................................6 - 4
6.1.4 Response to diagnostic command.........................................................................................6 - 5
6.2 Address Translation.............................................................................................................. 6 - 6
6.2.1 Default parameters................................................................................................................ 6 - 6
6.2.2 Logical address..................................................................................................................... 6 - 7
6.3 Power Save........................................................................................................................... 6 - 8
6.3.1 Power save mode..................................................................................................................6 - 8
6.3.2 Power commands.................................................................................................................. 6 - 10
6.4 Defect Management..............................................................................................................6 - 10
6.4.1 Spare area ............................................................................................................................. 6 - 11
6.4.2 Alternating defective sectors................................................................................................ 6 - 11
6.5 Read-Ahead Cache............................................................................................................... 6 - 13
6.5.1 Data buffer configuration..................................................................................................... 6 - 13
6.5.2 Caching operation.................................................................................................................6 - 14
6.5.3 Usage of read segment..........................................................................................................6 - 15
6.6 Write Cache..........................................................................................................................6 - 20
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TABLES
page
1.1 Specifications .......................................................................................................................1 - 4
1.2 Model names and product numbers...................................................................................... 1 - 5
1.3 Current and power dissipation.............................................................................................. 1 - 6
1.4 Environmental specifications ............................................................................................... 1 - 8
1.5 Acoustic noise specification................................................................................................. 1 - 8
1.6 Shock and vibration specification......................................................................................... 1 - 9
3.1 Surface temperature measurement points and standard values.............................................3 - 6
3.2 Cable connector specifications.............................................................................................3 - 9
4.1 Transfer rate of each zone ....................................................................................................4 - 12
5.1 Interface signals....................................................................................................................5 - 2
5.2 Signal assignment on the interface connector ...................................................................... 5 - 3
5.3 I/O registers.......................................................................................................................... 5 - 7
5.4 Command code and parameters............................................................................................ 5 - 14
5.5 Information to be read by IDENTIFY DEVICE command.................................................. 5 - 29
5.6 Features register values and settable modes......................................................................... 5 - 36
5.7 Diagnostic code.................................................................................................................... 5 - 40
5.8 Features Register values (subcommands) and functions...................................................... 5 - 50
5.9 Format of device attribute value data ................................................................................... 5 - 52
5.10 Format of insurance failure threshold value data ................................................................. 5 - 53
5.11 Contents of security password..............................................................................................5 - 57
5.12 Contents of SECURITY SET PASSWORD data................................................................. 5 - 62
5.13 Relationship between combination of Iden tifier and Security level,
and operation of the lock function........................................................................................ 5 - 62
5.14 Command code and parameters............................................................................................ 5 - 70
5.15 Recommended series termination for Ultra DMA................................................................ 5 - 88
5.16 Ultra DMA data burst timing requirements.......................................................................... 5 - 92
5.17 Ultra DMA sender and recipient timing requirements ......................................................... 5 - 94
6.1 Default parameters................................................................................................................ 6 - 6
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5.3 Protocol for command abort................................................................................................. 5 - 73
5.4 WRITE SECTOR(S) command protocol.............................................................................5 - 74
5.5 Protocol for the command execution without data transfer.................................................. 5 - 75
5.6 Normal DMA data transfer................................................................................................... 5 - 77
5.7 Ultra DMA termination with pull-up or pull-down.............................................................. 5 - 88
5.8 PIO data transfer timing ....................................................................................................... 5 - 89
5.9 Multiword DMA data transfer timing (mode 2)................................................................... 5 - 90
5.10 Initiating an Ultra DMA data in burst .................................................................................. 5 - 91
5.11 Sustained Ultra DMA data in burst ...................................................................................... 5 - 95
5.12 Host pausing an Ultra DMA data in burst............................................................................5 - 96
5.13 Device terminating an Ultra DMA data in burst .................................................................. 5 - 97
5.14 Host terminating an Ultra DMA data in burst......................................................................5 - 98
5.15 Initiating an Ultra DMA data out burst ................................................................................ 5 - 99
5.16 Sustained Ultra DMA data out burst .................................................................................... 5 - 100
5.17 Device pausing an Ultra DMA data out burst ...................................................................... 5 - 101
5.18 Host terminating an Ultra DMA data out burst....................................................................5 - 102
5.19 Device terminating an Ultra DMA data out burst ................................................................ 5 - 103
5.20 Power-on Reset Timing........................................................................................................5 - 104
6.1 Response to power-on .......................................................................................................... 6 - 2
6.2 Response to hardware reset.................................................................................................. 6 - 3
6.3 Response to software reset ...................................................................................................6 - 4
6.4 Response to diagnostic command.........................................................................................6 - 5
6.5 Address translation (example in CHS mode).......................................................................6 - 7
6.6 Address translation (example in LBA mode)....................................................................... 6 - 8
6.7 Sector slip processing...........................................................................................................6 - 11
6.8 Alternate cylinder assignment..............................................................................................6 - 12
6.9 Data buffer configuration..................................................................................................... 6 - 13
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C141-E112-01EN

TABLES

page
1.1 Specifications .......................................................................................................................1 - 4
1.2 Model names and product numbers...................................................................................... 1 - 5
1.3 Current and power dissipation.............................................................................................. 1 - 6
1.4 Environmental specifications ............................................................................................... 1 - 8
1.5 Acoustic noise specification................................................................................................. 1 - 8
1.6 Shock and vibration specification......................................................................................... 1 - 9
3.1 Surface temperature measurement points and standard values.............................................3 - 6
3.2 Cable connector specifications.............................................................................................3 - 9
4.1 Transfer rate of each zone ....................................................................................................4 - 12
5.1 Interface signals....................................................................................................................5 - 2
5.2 Signal assignment on the interface connector ...................................................................... 5 - 3
5.3 I/O registers.......................................................................................................................... 5 - 7
5.4 Command code and parameters............................................................................................ 5 - 14
5.5 Information to be read by IDENTIFY DEVICE command.................................................. 5 - 29
5.6 Features register values and settable modes......................................................................... 5 - 36
5.7 Diagnostic code.................................................................................................................... 5 - 40
5.8 Features Register values (subcommands) and functions...................................................... 5 - 50
5.9 Format of device attribute value data ................................................................................... 5 - 52
5.10 Format of insurance failure threshold value data ................................................................. 5 - 53
5.11 Contents of security password..............................................................................................5 - 57
5.12 Contents of SECURITY SET PASSWORD data................................................................. 5 - 62
5.13 Relationship between combination of Iden tifier and Security level,
and operation of the lock function........................................................................................ 5 - 62
5.14 Command code and parameters............................................................................................ 5 - 70
5.15 Recommended series termination for Ultra DMA................................................................ 5 - 88
5.16 Ultra DMA data burst timing requirements.......................................................................... 5 - 92
5.17 Ultra DMA sender and recipient timing requirements ......................................................... 5 - 94
6.1 Default parameters................................................................................................................ 6 - 6
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CHAPTER 1 DEVICE OVERVIEW

1.1 Features

1.2 Device Specifications
1.3 Power Requirements
1.4 Environmental Specifications
1.5 Acoustic Noise
1.6 Shock and Vibration
1.7 Reliability
1.8 Error Rate
1.9 Media Defects
Overview and features are described in this chapter, and specifications and power requirement are described.
The MPG3xxxAH series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is compact and reliable.
1.1 Features

1.1.1 Functions and performance

(1) Compact
The disk has 1 or 2 disks of 95 mm (3.5 inches) diameter, and its height is 26.1 mm (1 inch).
(2) Large capacity
The disk drive can record up to 10.24 GB (formatted) on one disk using the 48/52 EEPR4ML recording method and 15 recording zone technology. The MPG3xxxAH series have a formatted capacity of 10.24 GB to 20.49 GB respectiv ely.
(3) High-speed Transfer rate
The disk drive has an internal data rate up to 50.8 MB/s. The disk drive supports an external data rate up to 16.7 MB/s (PIO mode 4, DMA mode 2), 66.6 MB/s (ultra DMA mode 4) or 100MB/s (ultra DMA mode 5).
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(4) Average positioning time
Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. Th e average positioning time is 8.5 ms (at read).

1.1.2 Adaptability

(1) Power save mode
The power save mode feature for idle operation, stand by and sleep modes makes the disk drive ideal for applications where power consumption is a factor.
(2) Wide temperature range
The disk drive can be used over a wide temperature range (5°C to 55°C).
(3) Low noise and vibr ation
In Ready status, th e noise of the disk drive is on ly about 3.7 bels (MPG3204AH, Typical Sound Power per ISO7779 and ISO9296).

1.1.3 Interface

(1) Connection to interface
With the built-in ATA in terface controller, the disk drive can be con nected to an ATA interface of a personal computer .
(2) 2MB data buffer
The disk drive uses a 2MB data buffer to transfer data between the host and the disk media.
In combination with the read-ahead cache system described in item (3) and the write cache described in item (6), the buffer contributes to efficient I/O processing.
(3) Read - ahea d cache system
After the execution of a disk read command, the disk drive automatically reads the subsequen t data block and writes it to the data buffer (read ahead operation). This cache system enables fast data access. The next disk read comman d would nor mally cause an other disk access. But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.
(4) Master/slave
The disk drive can be connected to ATA interface as daisy chain configuration. Drive 0 is a master device, drive 1 is a slave device.
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(5) Error correction and retry by ECC
If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has improved buffer error correction for correctable data errors.
(6) Write cache
When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer comp letion of writing to the disk media. This feature reduces the access time at writing.
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1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specifications of the disk drive.
Table 1.1 Specifications
MPG3102AH MPG3153AH MPG3204AH Formatted Capacity (*1) 10.2 4 G B 15.3 7 G B 20.4 9 G B Number of Disks 1 2 2 Number of Heads 2 3 4 Number of Cylinders
(User + Alternate & SA) Bytes per Sector 512 Recording Method 48/52 CC2EPRML Track Density 20,800 TPI Bit Density 385,118 BPI Rotational Speed 7,200 rpm Average Latency 4.17 ms Positioning time (Fast)
• Minimum
• Average
• Maximum
Positioning time (Slow)
• Minimum
• Average
• Maximum
Start/Stop time
• Start (0 rpm to Drive Read)
• Stop (at Power Down)
Interface ATA–5
Data Transfer Rate
• To/From Media
• To/From Host
Data buffer 2 MB Physical Dimensions
(Height × Width × Depth) Weight 600 g or less
*1: Capacity under the LBA mode.
Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of sectors are as follows.
(Read) 0.8 ms typical, (Write) 1.0 ms typical (Read) 8.5 ms typical, (Write) 9.5 ms typical
(Read) 16 ms typical, (Write) 17 ms typical
(Read) 0.8 ms typical, (Write) 1.0 ms typical
(Read) 11 ms typical, (Write) 12 ms typical (Read) 20 ms typical, (Write) 21 ms typical
Typical: 8 sec., Maximum: 15 sec. Typical: 20 sec., Maximum: 30 sec.
16.7 MB/s Max. (burst PIO mode 4, burst DMA mode 2),
66.6 MB/s Max. (burst ultra DMA mode 4)
100.0 MB/s Max. (burst ultra DMA mode 5)
26.1 mm max. × 101. 6 mm × 146.0 mm
19,424 + 303 + 15
(Maximum Cable length: 0.46 m)
29.6 to 50.8 MB/s
(1.0” max. × 4.0” × 5.7”)
1 - 4
C141-E112-01EN
Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors MPG3102AH 10,248 MB 16,383 16 63 MPG3153AH 15,371 MB 16,383 16 63 MPG3204AH 20,496 MB 16,383 16 63

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers.
Table 1.2 Model names and product numbers
Model Name
Capacity
(user area)
Mounting
Screw
Order No. Remarks
MPG3102AH 10.24 GB No. 6-32UNC CA05762-B321 — MPG3153AH 15.37 GB No. 6-32UNC CA05762-B331 — MPG3204AH 20.49 GB No. 6-32UNC CA05762-B341

1.3 Power Requirements

(1) Input Voltage
+ 5 V ±5 %
+ 12 V ±8 %
(2) Ripple
+12 V +5 V Maximum 200 mV (peak to peak) 100 mV (peak to peak) Frequency DC to 1 MHz DC to 1 MHz
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(3) Current Requirements and Power Dissipation
Table 1.3 lists the current and power dissipation.
Table 1.3 Current and power dissipation
Mode of Operation
Model MPG
3102AH
Spin up 1950 peak 1950 peak 1950 peak 800 peak 27.4 27.4 27.4
Idle (Ready) (*3) 300 330 330 490 6.1 6.4 6.4
R/W (On Track) (*4) 300 380 380 530 6.3 7.2 7.2
Seek (Random) (*5) 430 490 490 550 7.9 8.6 8.6
Standby 18 18 18 120 0.8 0.8 0.8
Sleep 18 18 18 120 0.8 0.8 0.8
Energy efficiency (rank) (*6) [watt / GB] 0.596 (A) 0.312 (B) 0.312 (B)
*1 Current is typical rms except for spin up.
*2 Power requirements reflect nominal values for +12V and +5V power.
*3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the R/W circuitry is powered down,
the spindle motor is up to speed and the Drive ready condition exists.
*4 R/W mode is defined as 50% read operations and 50% write operations on a single physical track.
*5 Seek/W/R mode is defined as 33% seek operations, 33% write operations, and 33% read operations.
Typical RMS current (*1) [mA]
+12 V +5 V
MPG
3153AH
MPG
3204AH
All
Models
Typical Power (*2) [watts]
MPG
3102AH
MPG
3153AH
MPG
3204AH
*6 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing power consumption by the
storage capacity. (Japan only)
1 - 6
C141-E112-01EN
(4) Current fluctuation (Typ.) when power is turned on
Note:
Maximum current is 1.95A.
Figure 1.1 Current fluctuation (Typ.) when power is turned on
(5) Power on/off sequence
The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be concerned with the power on/off sequence.
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1 - 7

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.
Table 1.4 Environmental specifications
Temperature
• Operating
• Non-operating
• Thermal Gradient
Humidity
• Operating
• Non-operating
• Maximum Wet Bulb
Altitude (relative to sea level)
• Operating
• Non-operating

1.5 Acoustic Noise

5°C to 55°C (ambient) 5°C to 60°C (disk enclosure surface) –40°C to 60°C 20°C/hour or less
8% to 80%RH (Non-condensing) 5% to 85%RH (Non-condensing) 29°C
–60 to 3,000 m (–200 to 10,000 ft) –60 to 12,000 m (–200 to 40,000 ft)
Table 1.5 lists the acoustic noise specification.
Sound Power per ISO 7779 and ISO9296 (Typical at 1m)
(Typical at 1m)
Table 1.5 Acoustic noise specification
Model
Idle mode (DRIVE READY) 3.6 bels 3.7 bels Seek mode (Random) 4.0 bels 4.1 bels Idle mode (DRIVE READY) 31 dBA 32 d BASound Pressure Seek mode (Random) 35 dBA 36 dBA
MPG3102AH
MPG3153AH MPG3204AH
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1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.
Table 1.6 Shock and vibration specification
Vibration (swept sine, one octave per minute)
• Operating
• Non-operating
Shock (half-sine pulse, Operating)
• 2 ms duration 392 m/s
Shock (half-sine pulse, Non-operating)
• 2 ms duration 2940 m/s

1.7 Reliability

(1) Mean time between failures (MTBF)
The mean time between failures (MTBF) is 500,000 POH (power on hours) or more (operation: 24 hours/day, 7 days/week).
This does not include failures occurring during the first three months after installation.
MTBF is defined as follows:
MTBF= (H)
Total operation time in all fields
number of device failure in all fields
2
4.9 m/s (without non-recovered errors)
39.2 m/s
(0.5G0-P); 5 to 300 Hz
2
(4.0G0-P); 5 to 400 Hz (no damage)
2
(40G0-P) (without non-recovered error)
2
(300G0-P) (Typical, no damage)
"Disk drive defects" refers to defects that involve repair, readjustment, or replacement. Disk drive defects do not include failures caused by external factors, such as damage caused by handling, inappropriate operating environments, defects in the power supply host system, or interface cable.
(2) Mean time to repair (MTTR)
The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.
(3) CSS cycle
The number of CSS must be less than 50,000.
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(4) Service life
In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48°C. When the DE surface temperature exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.3 for the measurement point of the DE surface temperature.
(5) Data assurance in the event of power failure
Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative blo ck assignment).

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.
(1) Unrecoverable read error
Read errors that cannot be recovered by read retries without user's retry and ECC corrections shall occur no more than 10 times when reading data of 10 the disk drive's error recovery procedure, and include read retries accompanying head offset operations.
(2) Positioning error
Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in
7
seek operations.
10

1.9 Media Defects

Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the factory (low level format). Thus, the host sees a defect-free device.
Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.
Chapter 6 describes the low level format at shipping.
15
bits. Read retries are executed according to
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CHAPTER 2 DEVICE CONFIGURATION

2.1 Device Configuration

2.2 System Configuration
2.1 Device Configuration
Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors actuators, and a circulating air filter.
Figure 2.1 Disk drive outerview
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(1) Disk
The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used varies with the model, as described below. The disks are rated at over 50,000 start/stop operations.
MPG3102AH: 1 disks MPG3153AH: 2 disks MPG3204AH: 2 disks
(2) Head
The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts.
(3) Spindle motor
The disks are rotated by a direct drive Hall-less DC motor.
(4) Actuator
The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the tip of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock.
(5) Air circulation system
The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the recirculation filter to maintain the cleanliness of the air in the disk enclosure.
(6) Read/write circuit
The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.
(7) Controller circuit
The controller circuit consists of an LSI chip to improve reliability. The high-speed microprocessor unit (MPU) achieves a high-performance AT controller.
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2.2 System Configuration

2.2.1 ATA interface

Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer till 16.7 MB/s (Multiword DMA mode 2), the ultra DMA transfer till 66.6 MB/s (Ultra DMA mode 4), and the ultra DMA transfer till 100 MB/s (Ultra mode 5).

2.2.2 1 drive connection

Host
AT bus
(Host interface)

2.2.3 2 drives connection

Host
AT bus
(Host interface)
HA
(Host adaptor)
Disk drive
ATA interface
Figure 2.2 1 drive system configuration
HA
(Host adaptor)
Disk drive #0
Disk drive #1
ATA interface
Note:
When the drive that is not conformed to ATA is connected to the disk drive is above configuration, the operation is not guaranteed.
Figure 2.3 2 drives configuration
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