Fujitsu MPG3153AH, MPG3204AH, MPG3102AH User Manual

MPG3xxxAH

DISK DRIVES

PRODUCT MANUAL

C141-E112-01EN

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C141-E112-01EN

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MANUAL ORGANIZATION

MPG3xxxAH

DISK DRIVES

PRODUCT

MANUAL

(C141-E112)

<This manual>

MPG3xxxAH

DISK DRIVES

MAINTENANCE

MANUAL

(C141-F047)

• DEVICE OVERVIEW

• DEVICE CONFIGURATION

• INSTALLATION CONDITIONS

• THEORY OF DEVICE OPERATION

• INTERFACE

• OPERATIONS

• MAINTENANCE AND DIAGNOSIS

• REMOVAL AND REPLACEMENT PROCEDURE

C141-E112-01EN

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PREFACE

This manual describes the MPG3xxxAH series, a 3.5-inch hard disk drive with a BUILT-IN controller that
is compatible with the ATA interface.

This manual explains, in detail, how to incorporate the hard disk drives into user systems.

This manual assumes that users have a basic knowledge of hard disk drives and their application in
computer systems.

This manual consists of the following six chapters:

Chapter 1 DEVICE OVERVIEW

Chapter 2 DEVICE CONFIGURATION

Chapter 3 INSTALLATION CONDITIONS

Chapter 4 THEORY OF DEVICE OPERATION

Chapter 5 INTERFACE

Chapter 6 OPERATIONS

In this manual, disk drives may be referred to as drives or devices.

C141-E112-01EN

v

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an
alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a
signal word.

The following are the alert signals and their meanings:

This indicates a hazardous situation likely to result in serious personal
injury if the user does not perform the procedure correctly.

This indicates a hazardous situation could result in personal injury if the
user does not perform the procedure correctly.

This indicates a hazardous situation could result in minor or moderate
personal injury if the user does not perform the procedure correctly. This
alert signal also indicates that damages to the product or other property,
may occur if the user does not perform the procedure correctly.

This indicates information that could help the user use the product more
efficiently.

In the text, the alert signal is centered, followed below by the indented message. A wider line space
precedes and follows the alert message to show where the alert message begins and ends. The following is
an example:

(Example)

IMPORTANT

HA (host adapter) consists of address decoder, driver, and receiver.
ATA is an abbreviation of "AT attachment". The disk drive is
conformed to the ATA-4 interface

The main alert messages in the text are also listed in the “Important Alert Items.”

vi C141-E112-01EN

LIABILITY EXCEPTION

"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.
Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or
mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the
host system, or other causes outside the disk drive.

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CONTENTS

page

CHAPTER 1 DEVICE OVERVIEW

1.1 Features ................................................................................................................................1 - 1

1.1.1 Functions and performance ..................................................................................................1 - 1

1.1.2 Adaptability..........................................................................................................................1 - 2

1.1.3 Interface................................................................................................................................1 - 2

1.2 Device Specifications...........................................................................................................1 - 4

1.2.1 Specifications summary........................................................................................................1 - 4

1.2.2 Model and product number .................................................................................................. 1 - 5

1.3 Power Requirements.............................................................................................................1 - 5

1.4 Environmental Specifications............................................................................................... 1 - 8

1.5 Acoustic Noise...................................................................................................................... 1 - 8

1.6 Shock and Vibration.............................................................................................................1 - 9

1.7 Reliability.............................................................................................................................1 - 9

1.8 Error Rate.............................................................................................................................1 - 10

1.9 Media Defects.......................................................................................................................1 - 10

CHAPTER 2 DEVICE CONFIGURATION

......................................................................................... 1 - 1

............................................................................ 2 - 1

2.1 Device Configuration ........................................................................................................... 2 - 1

2.2 System Configuration...........................................................................................................2 - 3

2.2.1 ATA interface.......................................................................................................................2 - 3

2.2.2 1 drive connection ................................................................................................................2 - 3

2.2.3 2 drives connection...............................................................................................................2 - 3

CHAPTER 3 INSTALLATION CONDITIONS

3.1 Dimensions...........................................................................................................................3 - 1

3.2 Handling Cautions................................................................................................................3 - 3

3.2.1 General notes........................................................................................................................3 - 3

3.2.2 Installation............................................................................................................................3 - 3

3.2.3 Recommended equipments................................................................................................... 3 - 3

3.3 Mounting..............................................................................................................................3 - 4

3.4 Cable Connections................................................................................................................3 - 8

3.4.1 Device connector..................................................................................................................3 - 8

...................................................................... 3 - 1

C141-E112-01EN

ix

3.4.2 Cable connector specifications .............................................................................................3 - 9

3.4.3 Device connection ................................................................................................................3 - 9

3.4.4 Power supply connector (CN1) ............................................................................................ 3 - 10

3.4.5 System configuration for Ultra DMA................................................................................... 3 - 10

3.5 Jumper Settings ....................................................................................................................3 - 13

3.5.1 Location of setting jumpers..................................................................................................3 - 13

3.5.2 Factory default setting ..........................................................................................................3 - 14

3.5.3 Jumper configuration............................................................................................................3 - 14

CHAPTER 4 THEORY OF DEVICE OPERATION.............................................................. 4 - 1

4.1 Outline..................................................................................................................................4 - 1

4.2 Subassemblies....................................................................................................................... 4 - 1

4.2.1 Disk ......................................................................................................................................4 - 1

4.2.2 Head......................................................................................................................................4 - 2

4.2.3 Spindle..................................................................................................................................4 - 3

4.2.4 Actuator................................................................................................................................4 - 3

4.2.5 Air filter................................................................................................................................4 - 3

4.3 Circuit Configuration............................................................................................................ 4 - 4

4.4 Power-on Sequence..............................................................................................................4 - 6

4.5 Self-calibration.....................................................................................................................4 - 8

4.5.1 Self-calibration contents....................................................................................................... 4 - 8

4.5.2 Execution timing of self-calibration.....................................................................................4 - 9

4.5.3 Command processing during self-calibration....................................................................... 4 - 9

4.6 Read/write Circuit ................................................................................................................4 - 10

4.6.1 Read/write preamplifier (PreAMP) ...................................................................................... 4 - 10

4.6.2 Write circuit..........................................................................................................................4 - 10

4.6.3 Read circuit........................................................................................................................... 4 - 11

4.6.4 Synthesizer circuit ................................................................................................................4 - 12

4.7 Servo Control .......................................................................................................................4 - 12

4.7.1 Servo control circuit .............................................................................................................4 - 13

4.7.2 Data-surface servo format ....................................................................................................4 - 16

4.7.3 Servo frame format...............................................................................................................4 - 16

4.7.4 Actuator motor control .........................................................................................................4 - 18

4.7.5 Spindle motor control........................................................................................................... 4 - 19

x

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CHAPTER 5 INTERFACE........................................................................................................5 - 1

5.1 Physical Interface ................................................................................................................. 5 - 2

5.1.1 Interface signals....................................................................................................................5 - 2

5.1.2 Signal assignment on the connector ..................................................................................... 5 - 3

5.2 Logical Interface...................................................................................................................5 - 6

5.2.1 I/O registers .......................................................................................................................... 5 - 6

5.2.2 Command block registers..................................................................................................... 5 - 8

5.2.3 Control block registers ......................................................................................................... 5 - 13

5.3 Host Commands ................................................................................................................... 5 - 13

5.3.1 Command code and parameters............................................................................................ 5 - 14

5.3.2 Command descriptions......................................................................................................... 5 - 16

5.3.3 Error posting.........................................................................................................................5 - 70

5.4 Command Protocol...............................................................................................................5 - 71

5.4.1 Data transferring commands from device to host................................................................. 5 - 71

5.4.2 Data transferring commands from host to device................................................................. 5 - 73

5.4.3 Commands without data transfer.......................................................................................... 5 - 75

5.4.4 Other commands................................................................................................................... 5 - 76

5.4.5 DMA data transfer commands.............................................................................................. 5 - 76

5.5 Ultra DMA feature set..........................................................................................................5 - 78

5.5.1 Overview ..............................................................................................................................5 - 78

5.5.2 Phases of operation...............................................................................................................5 - 79

5.5.3 Ultra DMA data in commands.............................................................................................. 5 - 79

5.5.3.1 Initiating an Ultra DMA data in burst .................................................................................. 5 - 79

5.5.3.2 The data in transfer...............................................................................................................5 - 80

5.5.3.3 Pausing an Ultra DMA data in burst .................................................................................... 5 - 80

5.5.3.4 Terminating an Ultra DMA data in burst ............................................................................. 5 - 81

5.5.4 Ultra DMA data out commands............................................................................................ 5 - 83

5.5.4.1 Initiating an Ultra DMA data out burst ................................................................................ 5 - 83

5.5.4.2 The data out transfer.............................................................................................................5 - 84

5.5.4.3 Pausing an Ultra DMA data out burst .................................................................................. 5 - 84

5.5.4.4 Terminating an Ultra DMA data out burst ........................................................................... 5 - 85

5.5.5 Ultra DMA CRC rules.......................................................................................................... 5 - 87

5.5.6 Series termination required for Ultra DMA.......................................................................... 5 - 88

5.6 Timing.................................................................................................................................. 5 - 89

5.6.1 PIO data transfer...................................................................................................................5 - 89

5.6.2 Multiword data transfer........................................................................................................ 5 - 90

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xi

5.6.3 Ultra DMA data transfer.......................................................................................................5 - 91

5.6.3.1 Initiating an Ultra DMA data in burst ..................................................................................5 - 91

5.6.3.2 Ultra DMA data burst timing requirements.......................................................................... 5 - 92

5.6.3.3 Sustained Ultra DMA data in burst ......................................................................................5 - 95

5.6.3.4 Host pausing an Ultra DMA data in burst............................................................................5

- 96

5.6.3.5 Device terminating an Ultra DMA data in burst .................................................................. 5 - 97

5.6.3.6 Host terminating an Ultra DMA data in burst......................................................................5 - 98

5.6.3.7 Initiating an Ultra DMA data out burst ................................................................................ 5 - 99

5.6.3.8 Sustained Ultra DMA data out burst .................................................................................... 5 - 100

5.6.3.9 Device pausing an Ultra DMA data out burst ...................................................................... 5 - 101

5.6.3.10 Host terminating an Ultra DMA data out burst .................................................................... 5 - 102

5.6.3.11 Device terminating an Ultra DMA data in burst .................................................................. 5 - 103

5.6.4 Power-on and reset............................................................................................................... 5 - 104

CHAPTER 6 OPERATIONS ..................................................................................................... 6 - 1

6.1 Device Response to the Reset...............................................................................................6 - 1

6.1.1 Response to power-on .......................................................................................................... 6 - 2

6.1.2 Response to hardware reset.................................................................................................. 6 - 3

6.1.3 Response to software reset ...................................................................................................6 - 4

6.1.4 Response to diagnostic command.........................................................................................6 - 5

6.2 Address Translation.............................................................................................................. 6 - 6

6.2.1 Default parameters................................................................................................................ 6 - 6

6.2.2 Logical address..................................................................................................................... 6 - 7

6.3 Power Save........................................................................................................................... 6 - 8

6.3.1 Power save mode..................................................................................................................6 - 8

6.3.2 Power commands.................................................................................................................. 6 - 10

6.4 Defect Management..............................................................................................................6 - 10

6.4.1 Spare area ............................................................................................................................. 6 - 11

6.4.2 Alternating defective sectors................................................................................................ 6 - 11

6.5 Read-Ahead Cache............................................................................................................... 6 - 13

6.5.1 Data buffer configuration..................................................................................................... 6 - 13

6.5.2 Caching operation.................................................................................................................6 - 14

6.5.3 Usage of read segment..........................................................................................................6 - 15

6.6 Write Cache..........................................................................................................................6 - 20

xii

C141-E112-01EN

TABLES

page

1.1 Specifications .......................................................................................................................1 - 4

1.2 Model names and product numbers...................................................................................... 1 - 5

1.3 Current and power dissipation.............................................................................................. 1 - 6

1.4 Environmental specifications ............................................................................................... 1 - 8

1.5 Acoustic noise specification................................................................................................. 1 - 8

1.6 Shock and vibration specification......................................................................................... 1 - 9

3.1 Surface temperature measurement points and standard values.............................................3 - 6

3.2 Cable connector specifications.............................................................................................3 - 9

4.1 Transfer rate of each zone ....................................................................................................4 - 12

5.1 Interface signals....................................................................................................................5 - 2

5.2 Signal assignment on the interface connector ...................................................................... 5 - 3

5.3 I/O registers.......................................................................................................................... 5 - 7

5.4 Command code and parameters............................................................................................ 5 - 14

5.5 Information to be read by IDENTIFY DEVICE command.................................................. 5 - 29

5.6 Features register values and settable modes......................................................................... 5 - 36

5.7 Diagnostic code.................................................................................................................... 5 - 40

5.8 Features Register values (subcommands) and functions...................................................... 5 - 50

5.9 Format of device attribute value data ................................................................................... 5 - 52

5.10 Format of insurance failure threshold value data ................................................................. 5 - 53

5.11 Contents of security password..............................................................................................5 - 57

5.12 Contents of SECURITY SET PASSWORD data................................................................. 5 - 62

5.13 Relationship between combination of Iden tifier and Security level,

and operation of the lock function........................................................................................ 5 - 62

5.14 Command code and parameters............................................................................................ 5 - 70

5.15 Recommended series termination for Ultra DMA................................................................ 5 - 88

5.16 Ultra DMA data burst timing requirements.......................................................................... 5 - 92

5.17 Ultra DMA sender and recipient timing requirements ......................................................... 5 - 94

6.1 Default parameters................................................................................................................ 6 - 6

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xv

5.3 Protocol for command abort................................................................................................. 5 - 73

5.4 WRITE SECTOR(S) command protocol.............................................................................5 - 74

5.5 Protocol for the command execution without data transfer.................................................. 5 - 75

5.6 Normal DMA data transfer................................................................................................... 5 - 77

5.7 Ultra DMA termination with pull-up or pull-down.............................................................. 5 - 88

5.8 PIO data transfer timing ....................................................................................................... 5 - 89

5.9 Multiword DMA data transfer timing (mode 2)................................................................... 5 - 90

5.10 Initiating an Ultra DMA data in burst .................................................................................. 5 - 91

5.11 Sustained Ultra DMA data in burst ...................................................................................... 5 - 95

5.12 Host pausing an Ultra DMA data in burst............................................................................5 - 96

5.13 Device terminating an Ultra DMA data in burst .................................................................. 5 - 97

5.14 Host terminating an Ultra DMA data in burst......................................................................5 - 98

5.15 Initiating an Ultra DMA data out burst ................................................................................ 5 - 99

5.16 Sustained Ultra DMA data out burst .................................................................................... 5 - 100

5.17 Device pausing an Ultra DMA data out burst ...................................................................... 5 - 101

5.18 Host terminating an Ultra DMA data out burst....................................................................5 - 102

5.19 Device terminating an Ultra DMA data out burst ................................................................ 5 - 103

5.20 Power-on Reset Timing........................................................................................................5 - 104

6.1 Response to power-on .......................................................................................................... 6 - 2

6.2 Response to hardware reset.................................................................................................. 6 - 3

6.3 Response to software reset ...................................................................................................6 - 4

6.4 Response to diagnostic command.........................................................................................6 - 5

6.5 Address translation (example in CHS mode).......................................................................6 - 7

6.6 Address translation (example in LBA mode)....................................................................... 6 - 8

6.7 Sector slip processing...........................................................................................................6 - 11

6.8 Alternate cylinder assignment..............................................................................................6 - 12

6.9 Data buffer configuration..................................................................................................... 6 - 13

xiv

C141-E112-01EN

TABLES

page

1.1 Specifications .......................................................................................................................1 - 4

1.2 Model names and product numbers...................................................................................... 1 - 5

1.3 Current and power dissipation.............................................................................................. 1 - 6

1.4 Environmental specifications ............................................................................................... 1 - 8

1.5 Acoustic noise specification................................................................................................. 1 - 8

1.6 Shock and vibration specification......................................................................................... 1 - 9

3.1 Surface temperature measurement points and standard values.............................................3 - 6

3.2 Cable connector specifications.............................................................................................3 - 9

4.1 Transfer rate of each zone ....................................................................................................4 - 12

5.1 Interface signals....................................................................................................................5 - 2

5.2 Signal assignment on the interface connector ...................................................................... 5 - 3

5.3 I/O registers.......................................................................................................................... 5 - 7

5.4 Command code and parameters............................................................................................ 5 - 14

5.5 Information to be read by IDENTIFY DEVICE command.................................................. 5 - 29

5.6 Features register values and settable modes......................................................................... 5 - 36

5.7 Diagnostic code.................................................................................................................... 5 - 40

5.8 Features Register values (subcommands) and functions...................................................... 5 - 50

5.9 Format of device attribute value data ................................................................................... 5 - 52

5.10 Format of insurance failure threshold value data ................................................................. 5 - 53

5.11 Contents of security password..............................................................................................5 - 57

5.12 Contents of SECURITY SET PASSWORD data................................................................. 5 - 62

5.13 Relationship between combination of Iden tifier and Security level,

and operation of the lock function........................................................................................ 5 - 62

5.14 Command code and parameters............................................................................................ 5 - 70

5.15 Recommended series termination for Ultra DMA................................................................ 5 - 88

5.16 Ultra DMA data burst timing requirements.......................................................................... 5 - 92

5.17 Ultra DMA sender and recipient timing requirements ......................................................... 5 - 94

6.1 Default parameters................................................................................................................ 6 - 6

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CHAPTER 1 DEVICE OVERVIEW

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

Overview and features are described in this chapter, and specifications and power requirement are
described.

The MPG3xxxAH series are a 3.5-inch hard disk drive with a built-in ATA controller. The disk drive is
compact and reliable.

1.1 Features

1.1.1 Functions and performance

(1) Compact

The disk has 1 or 2 disks of 95 mm (3.5 inches) diameter, and its height is 26.1 mm (1 inch).

(2) Large capacity

The disk drive can record up to 10.24 GB (formatted) on one disk using the 48/52 EEPR4ML
recording method and 15 recording zone technology. The MPG3xxxAH series have a formatted
capacity of 10.24 GB to 20.49 GB respectiv ely.

(3) High-speed Transfer rate

The disk drive has an internal data rate up to 50.8 MB/s. The disk drive supports an external data
rate up to 16.7 MB/s (PIO mode 4, DMA mode 2), 66.6 MB/s (ultra DMA mode 4) or 100MB/s
(ultra DMA mode 5).

C141-E112-01EN

1 - 1

(4) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the
positioning speed. Th e average positioning time is 8.5 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for idle operation, stand by and sleep modes makes the disk drive
ideal for applications where power consumption is a factor.

(2) Wide temperature range

The disk drive can be used over a wide temperature range (5°C to 55°C).

(3) Low noise and vibr ation

In Ready status, th e noise of the disk drive is on ly about 3.7 bels (MPG3204AH, Typical Sound
Power per ISO7779 and ISO9296).

1.1.3 Interface

(1) Connection to interface

With the built-in ATA in terface controller, the disk drive can be con nected to an ATA interface
of a personal computer .

(2) 2MB data buffer

The disk drive uses a 2MB data buffer to transfer data between the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the write cache
described in item (6), the buffer contributes to efficient I/O processing.

(3) Read - ahea d cache system

After the execution of a disk read command, the disk drive automatically reads the subsequen t
data block and writes it to the data buffer (read ahead operation). This cache system enables fast
data access. The next disk read comman d would nor mally cause an other disk access. But, if the
read ahead data corresponds to the data requested by the next read command, the data in the
buffer can be transferred instead.

(4) Master/slave

The disk drive can be connected to ATA interface as daisy chain configuration. Drive 0 is a
master device, drive 1 is a slave device.

C141-E112-01EN1 - 2

(5) Error correction and retry by ECC

If a recoverable error occurs, the disk drive itself attempts error recovery. The 40 bytes ECC has
improved buffer error correction for correctable data errors.

(6) Write cache

When the disk drive receives a write command, the disk drive posts the command completion at
completion of transferring data to the data buffer comp letion of writing to the disk media. This
feature reduces the access time at writing.

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1 - 3

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specifications of the disk drive.

Table 1.1 Specifications

MPG3102AH MPG3153AH MPG3204AH
Formatted Capacity (*1) 10.2 4 G B 15.3 7 G B 20.4 9 G B
Number of Disks 1 2 2
Number of Heads 2 3 4
Number of Cylinders

(User + Alternate & SA)
Bytes per Sector 512
Recording Method 48/52 CC2EPRML
Track Density 20,800 TPI
Bit Density 385,118 BPI
Rotational Speed 7,200 rpm
Average Latency 4.17 ms
Positioning time (Fast)

• Minimum

• Average

• Maximum

Positioning time (Slow)

• Minimum

• Average

• Maximum

Start/Stop time

• Start (0 rpm to Drive Read)

• Stop (at Power Down)

Interface ATA–5

Data Transfer Rate

• To/From Media

• To/From Host

Data buffer 2 MB
Physical Dimensions

(Height × Width × Depth)
Weight 600 g or less

*1: Capacity under the LBA mode.

Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number of heads, and number of
sectors are as follows.

(Read) 0.8 ms typical, (Write) 1.0 ms typical
(Read) 8.5 ms typical, (Write) 9.5 ms typical

(Read) 16 ms typical, (Write) 17 ms typical

(Read) 0.8 ms typical, (Write) 1.0 ms typical

(Read) 11 ms typical, (Write) 12 ms typical
(Read) 20 ms typical, (Write) 21 ms typical

Typical: 8 sec., Maximum: 15 sec.
Typical: 20 sec., Maximum: 30 sec.

16.7 MB/s Max. (burst PIO mode 4, burst DMA mode 2),

66.6 MB/s Max. (burst ultra DMA mode 4)

100.0 MB/s Max. (burst ultra DMA mode 5)

26.1 mm max. × 101. 6 mm × 146.0 mm

19,424 + 303 + 15

(Maximum Cable length: 0.46 m)

29.6 to 50.8 MB/s

(1.0” max. × 4.0” × 5.7”)

1 - 4

C141-E112-01EN

Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors
MPG3102AH 10,248 MB 16,383 16 63
MPG3153AH 15,371 MB 16,383 16 63
MPG3204AH 20,496 MB 16,383 16 63

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers.

Table 1.2 Model names and product numbers

Model Name

Capacity

(user area)

Mounting

Screw

Order No. Remarks

MPG3102AH 10.24 GB No. 6-32UNC CA05762-B321 —
MPG3153AH 15.37 GB No. 6-32UNC CA05762-B331 —
MPG3204AH 20.49 GB No. 6-32UNC CA05762-B341 —

1.3 Power Requirements

(1) Input Voltage

• + 5 V ±5 %

• + 12 V ±8 %

(2) Ripple

+12 V +5 V
Maximum 200 mV (peak to peak) 100 mV (peak to peak)
Frequency DC to 1 MHz DC to 1 MHz

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1 - 5

(3) Current Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation.

Table 1.3 Current and power dissipation

Mode of Operation

Model MPG

3102AH

Spin up 1950 peak 1950 peak 1950 peak 800 peak 27.4 27.4 27.4

Idle (Ready) (*3) 300 330 330 490 6.1 6.4 6.4

R/W (On Track) (*4) 300 380 380 530 6.3 7.2 7.2

Seek (Random) (*5) 430 490 490 550 7.9 8.6 8.6

Standby 18 18 18 120 0.8 0.8 0.8

Sleep 18 18 18 120 0.8 0.8 0.8

Energy efficiency (rank) (*6) [watt / GB] 0.596 (A) 0.312 (B) 0.312 (B)

*1 Current is typical rms except for spin up.

*2 Power requirements reflect nominal values for +12V and +5V power.

*3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any commands. A portion of the R/W circuitry is powered down,

the spindle motor is up to speed and the Drive ready condition exists.

*4 R/W mode is defined as 50% read operations and 50% write operations on a single physical track.

*5 Seek/W/R mode is defined as 33% seek operations, 33% write operations, and 33% read operations.

Typical RMS current (*1) [mA]

+12 V +5 V

MPG

3153AH

MPG

3204AH

All

Models

Typical Power (*2) [watts]

MPG

3102AH

MPG

3153AH

MPG

3204AH

*6 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing power consumption by the

storage capacity. (Japan only)

1 - 6

C141-E112-01EN

(4) Current fluctuation (Typ.) when power is turned on

Note:

Maximum current is 1.95A.

Figure 1.1 Current fluctuation (Typ.) when power is turned on

(5) Power on/off sequence

The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if
either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be
concerned with the power on/off sequence.

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1 - 7

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4 Environmental specifications

Temperature

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

1.5 Acoustic Noise

5°C to 55°C (ambient)
5°C to 60°C (disk enclosure surface)
–40°C to 60°C
20°C/hour or less

8% to 80%RH (Non-condensing)
5% to 85%RH (Non-condensing)
29°C

–60 to 3,000 m (–200 to 10,000 ft)
–60 to 12,000 m (–200 to 40,000 ft)

Table 1.5 lists the acoustic noise specification.

Sound Power
per ISO 7779 and ISO9296
(Typical at 1m)

(Typical at 1m)

Table 1.5 Acoustic noise specification

Model

Idle mode (DRIVE READY) 3.6 bels 3.7 bels
Seek mode (Random) 4.0 bels 4.1 bels
Idle mode (DRIVE READY) 31 dBA 32 d BASound Pressure
Seek mode (Random) 35 dBA 36 dBA

MPG3102AH

MPG3153AH
MPG3204AH

C141-E112-01EN1 - 8

1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6 Shock and vibration specification

Vibration (swept sine, one octave per minute)

• Operating

• Non-operating

Shock (half-sine pulse, Operating)

• 2 ms duration 392 m/s

Shock (half-sine pulse, Non-operating)

• 2 ms duration 2940 m/s

1.7 Reliability

(1) Mean time between failures (MTBF)

The mean time between failures (MTBF) is 500,000 POH (power on hours) or more (operation:
24 hours/day, 7 days/week).

This does not include failures occurring during the first three months after installation.

MTBF is defined as follows:

MTBF= (H)

Total operation time in all fields

number of device failure in all fields

2

4.9 m/s
(without non-recovered errors)

39.2 m/s

(0.5G0-P); 5 to 300 Hz

2

(4.0G0-P); 5 to 400 Hz (no damage)

2

(40G0-P) (without non-recovered error)

2

(300G0-P) (Typical, no damage)

"Disk drive defects" refers to defects that involve repair, readjustment, or replacement. Disk drive
defects do not include failures caused by external factors, such as damage caused by handling,
inappropriate operating environments, defects in the power supply host system, or interface cable.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance
staff member.

(3) CSS cycle

The number of CSS must be less than 50,000.

C141-E112-01EN

1 - 9

(4) Service life

In situations where management and handling are correct, the disk drive requires no overhaul for
five years when the DE surface temperature is less than 48°C. When the DE surface temperature
exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation,
whichever occurs first. Refer to item (3) in Subsection 3.3 for the measurement point of the DE
surface temperature.

(5) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any
power supply abnormalities. This does not include power supply abnormalities during disk media
initialization (formatting) or processing of defects (alternative blo ck assignment).

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate
count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk
media.

(1) Unrecoverable read error

Read errors that cannot be recovered by read retries without user's retry and ECC corrections shall
occur no more than 10 times when reading data of 10
the disk drive's error recovery procedure, and include read retries accompanying head offset
operations.

(2) Positioning error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in

7

seek operations.

10

1.9 Media Defects

Defective sectors are replaced with alternates when the disk is formatted prior to shipment from
the factory (low level format). Thus, the host sees a defect-free device.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned
with access to alternate sectors.

Chapter 6 describes the low level format at shipping.

15

bits. Read retries are executed according to

1 - 10

C141-E112-01EN

CHAPTER 2 DEVICE CONFIGURATION

2.1 Device Configuration

2.2 System Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write
preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle
motors actuators, and a circulating air filter.

Figure 2.1 Disk drive outerview

C141-E112-01EN

2 - 1

(1) Disk

The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used
varies with the model, as described below. The disks are rated at over 50,000 start/stop
operations.

MPG3102AH: 1 disks
MPG3153AH: 2 disks
MPG3204AH: 2 disks

(2) Head

The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the
disk is not rotating and automatically lifts when the disk starts.

(3) Spindle motor

The disks are rotated by a direct drive Hall-less DC motor.

(4) Actuator

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and
generates very little heat. The head assembly at the tip of the actuator arm is controlled and
positioned by feedback of the servo information read by the read/write head. If the power is not
on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk
and is fixed by a mechanical lock.

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure
features a closed loop air circulation system that relies on the blower effect of the rotating disk.
This system continuously circulates the air through the recirculation filter to maintain the
cleanliness of the air in the disk enclosure.

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability
by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The high-speed
microprocessor unit (MPU) achieves a high-performance AT controller.

2 - 2

C141-E112-01EN

2.2 System Configuration

2.2.1 ATA interface

Figures 2.2 and 2.3 show the ATA interface system configuration. The drive has a 40-pin PC AT
interface connector and supports the PIO transfer till 16.7 MB/s (PIO mode 4), the DMA transfer
till 16.7 MB/s (Multiword DMA mode 2), the ultra DMA transfer till 66.6 MB/s (Ultra DMA
mode 4), and the ultra DMA transfer till 100 MB/s (Ultra mode 5).

2.2.2 1 drive connection

Host

AT bus

(Host interface)

2.2.3 2 drives connection

Host

AT bus

(Host interface)

HA

(Host adaptor)

Disk drive

ATA interface

Figure 2.2 1 drive system configuration

HA

(Host adaptor)

Disk drive #0

Disk drive #1

ATA interface

Note:

When the drive that is not conformed to ATA is connected to the disk drive is above
configuration, the operation is not guaranteed.

Figure 2.3 2 drives configuration

C141-E112-01EN

2 - 3

IMPORTANT

HA (host adapter) consists of address decoder, driver, and receiver.
ATA is an abbreviation of "AT attachment". The disk drive is
conformed to the ATA-5 interface.

At high speed data transfer (PIO mode 3, mode 4, DMA mode 2, ultra
DMA mode 4 or ultra DMA mode 5), occurrence of ringing or
crosstalk of the signal lines (AT bus) between the HA and the disk drive
may be a great cause of the obs tructio n o f system relia b ility. Thu s, it is
necessary that the capacitance of the signal lines including the HA and
cable does not exceed the ATA-3, ATA-4 and ATA-5 standard, and the
cable length between the HA and the disk drive should be as short as
possible.

2 - 4

C141-E112-01EN

CHAPTER 3 INSTALLATION CONDITIONS

3.1 Dimensions

3.2 Handling Cautions

3.3 Mounting

3.4 Cable Connections

3.5 Jumper Settings

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes.
All dimensions are in mm.

C141-E112-01EN

3 - 1

Figure 3.1 Dimensions

3 - 2

C141-E112-01EN

3.2 Handling Cautions

ying

p

Please keep the following cautions, and handle the HDD under the safety environment.

3.2.1 General notes

ESD mat

Wrist strap

Shock absorbing mat

Use the Wrist strap.

Place the shock absorbing mat on the
operation table, and place ESD mat on it.

Do not hit HDD each other. Do not stack when carr

Do not place HDD vertically
to avoid falling down.

Do not dro

.

.

Figure 3.2 Handling cautions

3.2.2 Installation

(1) Please use the driver of a low impact when you use an electric driver.

HDD is occasionally damaged by the impact of the driver.

(2) Please observe the tightening torque of the screw strictly.

6-32UNC ······· Max. 0.59 N·m (6 Kg·cm)

3.2.3 Recommended equipments

Contents Model Maker

Wrist strap JX-1200-3056-8 SUMITOMO 3MESD
ESD mat 76000DES (ASK7876) COMKYLE

Shock Low shock driver SS-3000 HIOS

C141-E112-01EN

3 - 3

3.3 Mounting

(1) Direction

Figure 3.3 illustrates normal direction for the disk drive. The disk drives can be mounted in any
direction.

Horizontal mounting with the PCB facing down

(2) Frame

The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also
connected to signal ground. These are electrically shorted.

Note:

Use No.6-32UNC screw for the mounting screw and the screw length should satisfy the
specification in Figure 3.5.

(3) Limitation of side-mounting

When the disk drive is mounted using the screw holes on both side of the disk drive, use two
screw holes shown in Figure 3.4.

Do not use the center hole. For screw length, see Figure 3.5.

Figure 3.3 Direction

3 - 4

C141-E112-01EN

Do not use this screw holes

Figure 3.4 Limitation of side-mounting

Use these screw
holes

Bottom surface mounting

2

A

Frame of system
cabinet

4.5 or
less

DE

Details of A

Figure 3.5 Mounting frame structure

Screw

2.5

2.5

Frame of system
cabinet

5.0 or less

Details of B

Side surface

mounting

PCA

Screw

2.5

DE

B

C141-E112-01EN

3 - 5

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature
at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface
temperature from exceeding 60°C.

Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient
cooling. To check the cooling efficiency, measure the surface temperatures of the DE.
Regardless of the ambient temperature, this surface temperature must meet the standards listed in
Table 3.1. Figure 3.6 shows the temperature measurement point.

1

3 - 6

Figure 3.6 Surface temperature measurement points

Table 3.1 Surface temperature measurement points and standard values

No. Measurement point Temperature

1 DE cover 60°C max

C141-E112-01EN

(5) Service area

Figure 3.7 shows how the drive must be accessed (service areas) during and after installation.

- Mounting screw hole

[Q side]

- Mounting screw hole

[P side]

- Cable connection

- Mode setting switches

(6) External magnetic fields

Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that
the disk drive is not affected by external magnetic fields.

[R side]

- Mounting screw hole

Figure 3.7 Service area

C141-E112-01EN

3 - 7

3.4 Cable Connections

3.4.1 Device connector

The disk drive has the connectors and terminals listed below for connecting external devices.
Figure 3.8 shows the locations of these connectors and terminals.

• Power supply connector (CN1)

• ATA interface connector (CN1)

Power supply
connector (CN1)

Mode
Setting
Pins

ATA
interface
connector

3 - 8

Figure 3.8 Connector locations

C141-E112-01EN

3.4.2 Cable connector specifications

Table 3.2 lists the recommended specifications for the cable connectors for Host system that do
not support Ultra DMA modes greater than mode 2.

For Host system that support Ultra DMA modes greater than mode 2, the 80-conductor cable
assemblies shall be used. The 80-conductor cable assemblies are manufactured by AMP or 3M.

Table 3.2 Cable connector specifications

Name Model Manufacturer

Cable socket

ATA interface cable
(40-pin, CN1)

Power supply cable
(CN1)

Note :

The cable of twisted pairs and neighboring line separated individually is not allowed to use for
the host interface cable. It is because that the location of signal lines in these cables is not
fixed, and so the problem on the crosstalk among signal lines may occur.
It is recommended to use the ribbon cable for ATA interface that cable length is less than 46
cm (18 inch) and cable capacitance is less than 35 pico farad. Also it is recommended to use
AWG18 power supply cable.

(closed-end type)
Cable socket

(through-end type)
Cable socket housing 1-480424-0 AMP
Contact 60617-4 AMP

FCN-707B040-AU/B Fujitsu

FCN-707B040-AU/O Fujitsu

3.4.3 Device connection

Figure 3.9 shows how to connect the devices.

ATA interface cable Power supply cable

Host system

Disk Dri ve #0

Disk Dri ve #1

Figure 3.9 Cable connections

DC
power supply

C141-E112-01EN

3 - 9

3.4.4 Power supply connector (CN1)

Figure 3.10 shows the pin assignment of the power supply connector (CN1).

4321

(Viewed from cable side)

Figure 3.10 Power supply connector pins (CN1)

3.4.5 System configuration for Ultra DMA

Host system that support Ultra DMA transfer modes greater than mode 2 shall not share I/O ports.
They shall provide separate drivers and separate receivers for each cable.

a) The 80-conductor cable assemblies shall be used for systems operating at Ultra DMA modes

greater than 2. The 80-coductor cable assemblies may be used in place of 40-conductor cable
assemblies to improve signal quality for data transfer modes that do not require an 80­conductor cable assembly. And the 80-conductor cable assembly shall meet the following
specifications.

1) The assembly utilizes a fine pitch cable to double the number of conductors available to
the 40-pin connector. The grounds assigned by the interface are commoned with the
additional 40 conductors to provide a ground between each signal line and provide the
effect of a common ground plane.

1
2
3
4

+12VDC
+12V RETURN

+5V RETURN
+5VDC

3 - 10

2) The cable assembly may contain up to 3 connectors which shall be uniquely colored as
follows. All connectors shall have position 20 blocked.

• The System Board Connector shall have a Blue base and Black retainer. Pin 34

(PDIAG-: CBLID-) shall be connected to ground and shall not be wired to the cable
assembly.

• Connector Device “0” shall have a Black base and Black retainer.

• Connector Device “1” shall have a Gray base and Black retainer. Pin 28 (CSEL)

shall not be connected to the cable (contact 28 may be removed to meet this
requirement).

• The cable assembly may be printed with connector identifiers.

3) Typical cable characteristics are shown as follows.

• Cable: AWG 30 (pitch: 0.635 mm)

• Single Ended impedance: typical 80 Ω.

• Cable capacitance: typical 57 pF/m

4) The dimensions are shown in Figure 3.11.

C141-E112-01EN

Pin 40 (Ground)

Pin 34

127.0 to 304.8 mm
(5 to 12 inch)

open

254.0 to 457.2 mm
(10 to 18 inch)

101.6 to 152.4 mm
(4 to 6 inch)

Pin 30 (Ground)
Pin 26 (Ground)

Pin 24 (Ground)
Pin 22 (Ground)
Pin 19 (Ground)

Pin 2 (Ground)

b) Host system that do support Ultra DMA modes greater than mode 2 shall either connect

directly to the device without using a cable assembly, or determine the cable assembly type.
Determining the cable assembly type may be done either by the host sensing the condition of
the PDIAG-:CBLID- signal (see Figure 3.12), or by relying on information from the device
(see Figure 3.13). Hosts that rely on information from the device shall have a 0.047 µF
capacitor connected from the PDIAG-:CBLID- signal to ground. The tolerance on this
capacitor shall be 20% or less.

Connector

Symbolizes Pin 34
Conductor being cut

Position 1

Figure 3.11 Cable configuration

Pin 34 contact
(PDIAG-:CBLID- signal)

Connector 2Connector 1System Board

C141-E112-01EN

3 - 11

Host de tect ed CBLI D - above V

IH

PDIAG-: CBLID- conductor PDIAG-: CBLID- conductor

Host detected CBLID- below V
open

IL

Host Device 0Device 1

Figure 3.12 Cable type detection using CBLID- signal

(Host sensing the condition of the CBLID- signal)

IDENTIFY DEVICE information
word 93 bit13:0
Device detected CBLID- bel ow V

PDIAG-:CBLID- conductor

0.047 µF
±10% or
±20%

Host Device 0Device 1

Figure 3.13 Cable type detection using IDENTIFY DEVICE data

(Device sensing the condition of the CBLID- signal)

Host Device 0Device 1

with 80-conductor cablewith 40-conductor cable

IDENTIFY DEVICE information
word 93 bit13:1

IL

Device detec ted C BL ID- a bove V

open

PDIAG-:CBLID- conductor

0.047 µF
±10% or
±20%

IH

Host Device 0Device 1

with 80-conductor cablewith 40-conductor cable

3 - 12

C141-E112-01EN

3.5 Jumper Settings

3.5.1 Location of setting jumpers

Figure 3.14 shows the location of the jumpers to select drive configuration and functions.

Interface ConnectorDC Power Connector

2

1

Figure 3.14 Jumper location

C141-E112-01EN

40

1

3 - 13

3.5.2 Factory default setting

Figure 3.15 shows the default setting position at the factory. (Master device setting)

DC Power Connector

3.5.3 Jumper configuration

(1) Device type

Master device (device #0) or slave device (device #1) is selected.

Interface Connector

Figure 3.15 Factory default setting

8642

97531

8642

97531

= shorted

(a) Master device

Figure 3.16 Jumper setting of master or slave device

Note:

When the device type is set by the jumper on the device, the device should not be configured
for cable selection.

(2) Cable Select (CSEL)

In Cable Select mode, the device can be configured either master device or slave device. For use
of Cable Select function, Unique interface cable is needed.

3 - 14

(b) Slave device

C141-E112-01EN

8642

97531

CSEL con nected to the int erface cabl e s election
can be done by the special in terface cable.

Figure 3.17 Jumper setting of Cable Select

Figures 3.18 and 3.19 show examples of cable selection using unique interface cables.

By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and
connecting it to ground further, the CSEL is set to low level. The device is identified as a master
device. At this time, the CSEL of the slave device does not have a conductor. Thus, since the
slave device is not connected to the CSEL conductor, the CSEL is set to high level. The device is
identified as a slave device.

CSEL conductor

GND

GND

Host system

Open

Slave devi ceMaster deviceHost system

Figure 3.18 Example (1) of Cable Select

CSEL conductor

Open

Slave devi ce Master d evi ce

Figure 3.19 Example (2) of Cable Select

C141-E112-01EN

3 - 15

(3) Special jumper settings

(a) 2.1 GB clip (Limit capacity to 2.1 GB)

If the drive cannot be recognized by system with legacy BIOS’s which do not allow single
volume sizes greater than approximately 2.1 GB, the following jumper settings should be
applied.

8642

97531

8642

97531

8642

97531

Slave DeviceMaster Device Cable Select

Model No. of cylinders No. of heads No. of sectors
MPG3102AH 4,092 16 63
MPG3153AH 4,092 16 63
MPG3204AH 4,092 16 63

(b) Slave present

If the slave device does not use the Device Active/Slave Present (DASP–) signal to indicate
its presence, the device is configured as a Master with slave present when the following
jumper settings is applied.

8642

97531

Slave presen t

NOTE:

The following Jumper Plug is the recommended specification for jumper setting on this
device.

Parts name Parts number Manufacturer Remarks

2.54 mm Pitch
 0.64 mm

Jumper Plug

3 - 16

IMAS-9251H-GF IRISO ELECTRONICS CO., LTD

206-A-BLK OUPIIN ENTERPRISE CO., LTD

C141-E112-01EN

CHAPTER 4 THEORY OF DEVICE OPERATION

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on sequence

4.5 Self-calibration

4.6 Read/write Circuit

4.7 Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of
the disk drive, each sequence, servo control, and electrical circuit blocks.

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the
disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the
disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator,
read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.

The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details,
see Sections 4.3.

4.2.1 Disk

The DE contains the disks with an outer diameter of 95 mm. The MPG3102AH has 1 disk, and
MPG3153AH and MPG3204AH have 2 disk.

The head contacts the disk each time the disk rotation stops; the life of the disk is 50,000 contacts
or more.

Servo data is recorded on each cylinder (total 96). Servo data written at factory is read out by the
read/write head. For servo data, see Section 4.7.

C141-E112-01EN

4 - 1

4.2.2 Head

3

Figure 4.1 shows the read/write head structures. The Numerals 0 to 3 indicate read/write heads.
These heads are raised from the disk surface as the spindle motor approaches the rated rotation
speed.

MPG3102AH

Spindle Actuator

1

0

MPG3153AH

Spindle Actuator

2
1

0

MPG3204AH

Spindle Actuator

2
1

0

Figure 4.1 Head structure

4 - 2

C141-E112-01EN

4.2.3 Spindle

The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is
activated by the direct drive sensor-less DC spindle motor, which has a speed of 7,200 rpm. The
spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of
the spindle motor at starting. After that, the rotational speed is kept with detecting a servo
information.

4.2.4 Actuator

The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the
head carriage along the inner or outer edge of the disk. The head carriage position is controlled
by feeding back the difference of the target position that is detected and reproduced from the
servo information read by the read/write head.

4.2.5 Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the
spindle when the disk starts or stops rotating. When disk drives are transported under conditions
where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air
continuously through the circulation filter through an enclosed loop air cycle system operated by a
blower on the rotating disk.

C141-E112-01EN

4 - 3

4.3 Circuit Configuration

Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read chann el
(RDC).

The PreAMP consists of the write current switch circuit, that flows th e write current to the head
coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the Extended Partial Response Class 4 (EPR4),
and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base
generator, and data separator circuits. The RDC also contains the 48/52 group coded recording
(GCR) encoder and decoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the
servo information recorded on the data surface. The servo information is an analog signal
converted to digital for processing by a MPU and then reconverted to an analog signal for control
of the voice coil motor.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counter-electromotive voltage
of a motor, or servo mark at the MPU and controls the motor speed comparing target speed.

(4) Controller circuit

Major functions are listed below.

• Data buffer management

• ATA interface control and data transfer control

• Sector format control

• Defect management

• ECC control

• Error recovery and self-diagnosis

4 - 4

C141-E112-01EN

PCA

ATA Interface

Data Buffer

SDRAM

Flash ROM

FROM

SVC

HA13627

HDC & MCU & RDC

CL-SH8671 (Himalaya-2)

MCU

ARM7TDMI

CL-SH7660

RDC

Number-B

Resonator

20MHz

HDC

DE

SP Motor VCM

Media

Figure 4.2 MPG3xxxAH Block diagram

HEAD

Temp.

Sensor

R/W Pre-Amp

SR1756

C141-E112-01EN

4 - 5

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is
described below.

a) After the power is turned on, the disk drive executes the MPU bus test, internal register

read/write test, and work RAM read/write test. When the self-diagnosis terminates
successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to

the ATA bus.

c) After confirming that the spindle motor has reached rated speed, the disk drive releases the

heads from the actuator magnet lock mechanism by applying current to the VCM. This
unlocks the heads which are parked at the inner circumference of the disks.

d) The disk drive positions the heads onto the SA area and reads out the system information.

e) The disk drive executes self-seek-calibration. This collects data for VCM torque and

mechanical external forces applied to the actuator, and updates the calibrating value.

f) The drive becomes ready. The host can issue commands.

4 - 6

C141-E112-01EN

StartPower on

Self-diagnosis 1

a)

• MPU bus test

• Inner register
write/read test

• Wor k RAM write/read
test

The spindle motor starts.

Self-diagnosis 2

b)

• Data buffer write/read
test

Confirming spindle motor

c)

speed

Release heads from
actuator lock

d)

Initial on-track and read
out of system information

Execute self-calibration

e)

Drive ready state

f)

(command waiting state)

End

Figure 4.3 Power-on operation sequence

C141-E112-01EN

4 - 7

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical
external forces on the actuator, and VCM torque. This enables precise seek and read/write
operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.
The torque vary with the disk drive and the cylinder where the head is positioned. To execute
stable fast seek operations, external forces are occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator motor drive current)
that balances the torque for stopping head stably. This includes the current offset in the power
amplifier circuit and DAC system.

The forces are compensated by adding the measured value to the specified current value to the
power amplifier. This makes the stable servo control.

To compensate torque varying by the cylinder, the disk is divided into 28 areas from the
innermost to the outermost circumference and the compensating value is measured at the
measuring cylinder on each area at factory calibration. The measured values are stored in the SA
cylinder. In the self-calibration, the compensating value is updated using the value in the SA
cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies depending on the
cylinder that the head is positioned. To realize the high speed seek operation, the value that
compensates torque constant value change and loop gain change of the whole servo system due to
temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the
head is positioned to any cylinder. The firmware calculates the loop gain from the position signal
and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the
compensation value. By this compensation, loop gain becomes constant value and the stable
servo control is realized.

To compensate torque constant value change depending on cylinder, whole cylinders from most
inner to most outer cylinder are divided into 14 p artitions at calibration in the factory, and the
compensation data is measured for representative cylinder of each partition. This measured value
is stored in the SA area. The compensation value at self-calibration is calculated using the value
in the SA area.

4 - 8

C141-E112-01EN

4.5.2 Execution timing of self-calibration

Self-calibration is executed when:

• The power is turned on.

• The self-calibration execution timechart of the disk drive specifies self-calibration.

The disk drive performs self-calibration according to the timechart based on the time elapsed from
power-on. After power-on, self-calibration is performed about every 30 minutes and when the
host command is not issued for 15 seconds.

4.5.3 Command processing during self-calibration

If the disk drive receives a command execution request from the host while executing self­calibration according to the timechart, the disk drive terminates self-calibration and starts
executing the command precedingly. In other words, if a disk read or write service is necessary,
the disk drive positions the head to the track requested by the host, reads or writes data. Then
restarts calibration if the host command is not issued for 15 seconds.

This enables the host to execute the command without waiting for a long time, even when the disk
drive is performing self-calibration. Only the first command execution wait time is about
maximum 100 ms.

C141-E112-01EN

4 - 9

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, th e read
circuit, and the synthesizer in the read channel (RDC).

4.6.1 Read/write preamplifier (PreAMP)

One PreAMP is mounted on the FPC. The PreAMP consists of an 4-channel read preamplifier
and a write current switch and senses a write error. Each channel is connected to each data head.
The head IC switches the heads by the serial port (SDEN, SCLK, SDATA). The IC generates a
write error sense signal (WUS) when a write error occurs due to head short-circuit or head
disconnection.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent
to the encoder circuit in the RDC with synch ronizing with th e write clock . The N RZ write data is
converted from 48-bits data to 52-bits data by the encoder circuit then sent to the PreAMP, and
the data is written onto the media.

(1) 48/52 GCR

The disk drive converts data using the 48/52 group coded recording (GCR) algorithm.

(2) Write precompensation

Write precompensation compensates, during a write process, for write non-linearity generated at
reading.

4 - 10

C141-E112-01EN

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the variable gain amplifier (VGA) circuit.
Then the output is converted into the sampled read data pulse by the programmable filter circuit
and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 48/52
GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection
circuit, then is sent to the HDC.

(1) VGA circuit

The VGA circuit automatically regulates the output amplitude to a constant value even when the
input amplitude level fluctuates. The VGA output is maintained at a constant level even when the
head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Programmable filter

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high
frequency noise component and a high frequency boost-up function that equalizes the waveform
of the read signal.

Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in
read channel. The MPU optimizes the cut-off frequency and boost-up gain according to the
transfer frequency of each zone.

(3) FIR (Digital Finite Impulse Response Equalization Filter) adaptation circuit

The FIR provides support for changing equalization needs from head to head and zone to zone.
The FIR is a specialized digital filter with ten independently controlled coefficients.

(4) Viterbi detection circuit

The Viterbi detection circuit demodulates data according to the survivor path sequence.

(5) Data separator circuit

The data separator circuit generates clocks in synchronization with the output of the adaptive
equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the
clock signals from a synthesizer.

(6) 48/52 GCR decoder

This circuit converts the 52-bits read data into the 48-bits NRZ data.

C141-E112-01EN

4 - 11

4.6.4 Synthesizer circuit

The drive uses constant density recording to increase to tal capacity. This is different from the
conventional method of recording data with a fixed data transfer rate at all data area. In the
constant density recording method, data area is divided into zones by radius and the data transfer
rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The
drive divides data area into 15 zones to set the data transfer rate. Table 4.1 describes the data
transfer rate and recording density (BPI) of each zone.

Table 4.1 Transfer rate of each zone

Zone 01234567

Cylinder 0

1215

Transfer rate
[MB/s]

50.82 50.82 50.82 50.20 49.41 47.45 45.49 43.92

to

1216

to

2431

2432

to

3743

3744

to

4831

4832

to

5823

5824

to

7743

Zone 8 9 10 11 12 13 14

Cylinder 10816

to

12351

Transfer rate
[MB/s]

41.76 39.53 37.65 36.08 33.73 31.76 29.65

12352

to

13951

13952

to

15231

15232

to

16287

16288

to

17823

17824

to

19071

The MPU transfers the data transfer rate setup data to the RDC that includes the time base
generator circuit to change the data transfer rate.

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is
controlled for moving and positioning the head to the track containing the desired data. To turn
the disk at a constant velocity, the actuator motor is controlled according to the servo data that is
written on the data side beforehand.

7744

to

9631

19072

to

19423

9632

to

10815

4 - 12

C141-E112-01EN

4.7.1 Servo control circuit

Figure 4.4 is the block diagram of the servo control circuit. The following describes the functions
of the blocks:

(1)

(2) (3) (4)

Servo

Head

CSR: Current Sense Resistor
VCM: Voice Coil Motor

burst
capture

Position Sense

Figure 4.4 Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

MPU

DSP
unit

DACADC

Spindle
motor
control

SVC

(5)

P.
Amp.

(7)(6)

Driver

VCM current

CSR

VCM

Spindle
motor

The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the
reference cylinders, seeks the specified cylinder, and executes calibration according to the internal
operations of the MPU.

The major internal operations are listed below.

a. Spindle motor start

Starts the spindle motor and accelerates it to normal speed when power is applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylin der in the data area. The logical initial
cylinder is at the outermost circumference (cylinder 0).

C141-E112-01EN

4 - 13

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces on the actuator,
and stores the calibration value.

Servo frame
(96 servo frames per revolution)

4 - 14

Figure 4.5 Physical sector servo configuration on disk surface

C141-E112-01EN

(2) Servo burst capture circuit

The four servo signals can be synchronously detected by the DEMOD signal (internal), full-wave
rectified integrated.

(3) A/D converter (ADC)

The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and
transfers the digital signal to the DSP unit.

(4) D/A converter (DAC)

The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the
DSP unit into analog values and transfers them to the power amplifier.

(5) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.

(6) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects
number of revolution of the motor by the interrupt generated periodically, compares with the
target revolution speed, then flows the current into the motor coil according to the differentiation
(aberration).

(7) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the spindle motor control
circuit and feeds currents to the spindle motor.

(8) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage
and feeding back.

C141-E112-01EN

4 - 15

4.7.2 Data-surface servo format

Figure 4.5 describes the physical layout of the servo frame. The three areas indicated by (1) to (3)
in Figure 4.6 are described below.

(1) Inner guard band

The head is in contact with the disk in this space when the spindle starts turning or stops, and the
rotational speed of the spindle can be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area and SA area.

(3) Outer guard band

This area is located at outer position of the user data area, and the rotational speed of the spindle
can be controlled on this cylinder area for head moving.

4.7.3 Servo frame format

As the servo information, the drive uses the two-phase servo generated from the gray code and
Pos A to D. This servo information is used for positioning operation of radius direction and
position detection of circumstance direction.

The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, Pos A to D and
PAD. Figure 4.6 shows the servo frame format.

4 - 16

C141-E112-01EN

0.72 µs

0.16 µs

1.81 µs

0.17 µs

0.53 µs

0.56 µs0.56 µs0.74 µs

0.56 µs

0.80 µs

R/W Recovery Field

6.63 µs

Servo

Frame

PA

DATA DATA

SCD

SSMASM

86.81 µs

Pos

A

Pos

B

Pos

C

Pos

D

Servo

Frame

PAD

Figure 4.6 96 servo frames in each track

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark (ASM, SSM)

This area generates a timing for demodulating the gray code and position-demodulating Pos A to
D by detecting the servo mark.

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4 - 17

(3) Preamble

This area is used to synchronize with the PLL, which is used to search the SSM by detecting the
ASM.

(4) Gray code (including index bit) (SCD)

This area is used as cylinder address. The data in this area is converted into the binary data by the
gray code demodulation circuit.

(5) Pos A, Pos B, Pos C, Pos D

This area is used as position signals between tracks, and the device control at on-track so that Pos
A level equals to Pos B level.

(6) PAD

This area is used as a gap between servo and data.

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data
surface. The MPU fetches the position sense data on the servo frame at a constant interval of
sampling time, executes calculation, and updates the VCM drive current.

The servo control of the actuator includes the operation to move the head to the reference
cylinder, the seek operation to move the head to the target cylinder to read or write data, and th e
track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned. The reference
cylinder is in the data area.

When power is applied the heads are moved from the inner circumference shunt zone to the
normal servo data zone in the following sequence:

a) Micro current is fed to the VCM to press the head against the inner circumference.

b) A current is fed to the VCM to move the head toward the outer circumference.

c) When the servo mark is detected the head is moved slowly toward the outer circumference at

a constant speed.

d) If the head is stopped at the reference cylinder from there. Track following control starts.

4 - 18

C141-E112-01EN

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of access to the
disk. If a read or instruction is issued, the MPU seeks the desired track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head.
The MPU calculates the difference (speed error) between the specified target position and the
current position for each sampling timing during head moving. The MPU then feeds the VCM
drive current by setting the calculated result into the D/A converter. The calculation is digitally
executed by the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under the spindle
rotates in steady speed, the MPU does track following control. To position the head at the center
of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM
drive current is determined by filtering the position difference between the target pos ition and the
position clarified by the detected position sense data. The filtering includes servo compensation .
These are digitally controlled by the firmware.

4.7.5 Spindle motor control

Hall-less three-phase eight-pole motor is used for the spindle motor, and the 3-phase full/half­wave analog current control circuit is used as the spindle motor driver (called SVC hereafter).
The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by
sending several signals from the MPU to the SVC. There are three modes for the spindle control;
start mode, acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge the change pump

capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC to the motor start

mode. Then, a starting current flows into the spindle motor.

c) The SVC generates a phase switching signal by itself, and changes the phase of the current

flowed in the motor in the order of (V-phase to U-phase), (W-phase to U-phase), (W-phase to
V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that,
repeating this order).

d) During phase switching, the spindle motor starts rotating in low speed, and generates a

counter electromotive force. The SVC detects this counter electromotive force and reports to
the MPU using a PHASE signal for speed detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period,

the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the
SVC enters the acceleration mode.

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4 - 19

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SV C. The SVC starts a
phase switching by itself based on the counter electromotive force. Then, rotation of the spindle
motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the
PHASE signal from the SVC, and accelerates till the rotational speed reaches 7,200 rpm. When
the rotational speed reaches 7,200 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal
from the SVC. The MPU takes a difference between the current time and a time for one
revolution at 7,200 rpm that the MPU already recognized. Then, the MPU keeps the rotational
speed to 7,200 rpm by charging or discharging the charge pump for the different time. For
example, when the actual rotational speed is 7,400 rpm, the time for one revolution is 8.108 ms.
And, the time for one revolution at 7,200 rpm is 8.333 ms. Therefore, the MPU discharges the
charge pump for 0.225 ms × k (k: constant value). This makes the flowed current into the motor
lower and the rotational speed down. When the actual rotational speed is later than 7,200 rpm, the
MPU charges the pump the other way. This control (charging/discharging) is performed every 1/4
revolution.

4 - 20

C141-E112-01EN

CHAPTER 5 INTERFACE

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Ultra DMA feature set

5.6 Timing

C141-E112-01EN 5 - 1

5.1 Physical Interface

5.1.1 Interface signals

Table 5.1 shows the interface signals.

Cable select see note CSEL
Chip select 0
Chip select 1
Data bus bit 0
Data bus bit 1
Data bus bit 2
Data bus bit 3
Data bus bit 4
Data bus bit 5
Data bus bit 6
Data bus bit 7
Data bus bit 8
Data bus bit 9
Data bus bit 10
Data bus bit 11
Data bus bit 12
Data bus bit 13
Data bus bit 14
Data bus bit 15
Device active or slave present see note DASP–
Device address bit 0
Device address bit 1
Device address bit 2
DMA acknowledge
DMA request
Interrupt request
I/O read
DMA ready during Ultra DMA data in bursts
Data strobe during Ultra DMA data out bursts
I/O ready
DMA ready during Ultra DMA data out bursts
Data strobe during Ultra DMA data in bursts
I/O write
Stop during Ultra DMA data bursts
Passed diagnostics see note PDIAG–
Cable type detection CBLID–
Reset

Note : See signal descriptions

Table 5.1 Interface signals

Description Host Dir Dev Acrorym

CS0–

→

CS1–

→

→
→
→
→

→
→
→

→
→

→

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

DA0
DA1
DA2
DMACK–
DMARQ
INTRQ
DIOR–
HDMARDY–
HSTROBE
IORDY
DDMARDY–
DSTROBE
DIOW–
STOP

RESET–

↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔
↔

←
←

←
←
←

5 - 2

C141-E112-01EN

5.1.2 Signal assignment on the connector

Table 5.2 shows the signal assignment on the interface connector.

Table 5.2 Signal assignment on the interface connector

Pin No. Signal Pin No. Signal

1
3
5
7

9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
DMARQ
DIOW–, STOP
DIOR–, HDMARDY–, HSTROBE
IORDY, DDMARDY–, DSTROBE
DMACK–
INTRQ
DA1
DA0
CS0–
DASP–

10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

2
4
6
8

GND
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
GND
GND
GND
CSEL
GND
reserved
PDIAG–, CBLID–
DA2
CS1–
GND

[signal] [I/O] [Description]

RESET– I Reset sig nal from the host. This signal is low active and is asserted

for a minimum of 25 µs during power on. The device has a 10 kΩ
pull-up resistor on this signal.

DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device.

These signals are used for data transfer

DIOW–, STOP I DIOW– is the strobe signal asserted by the host to write device

registers or the data port.
DIOW– shall be negated by the host prior to initiation of an Ultra
DMA burst. STOP shall be negated by the host before data is
transferred in an Ultra DMA burst. Assertion of STOP by the host
during an Ultra DMA burst signals the termination of the Ultra
DMA burst.

C141-E112-01EN 5 - 3

[signal] [I/O] [Description]

DIOR– I DIOR– is the strobe signal asserted by the host to read device

registers or the data port.

HDMARDY– I HDMARDY– is a flow control signal for Ultra DMA data in bursts.

This signal is asserted by the host to indicate to the device that the
host is ready to receive Ultra DMA data in bursts.
The host may negate HDMARDY- to pause an Ultra DMA data in
burst.

HSTROBE I HSTROBE is the data out strobe signal from the host for an Ultra

DMA data out burst. Both the rising and falling edge of HSTROBE
latch the data from DATA 0-15 into the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data out burst.

INTRQ O Interrupt signal to the host.

This signal is negated in the following cases:
– assertion of RESET– signal
– Reset by SRST of the Device Control register
– Write to the command register by the host
– Read of the status register by the host
– Completion of sector data transfer
(without reading the Status register)
When the device is not selected or interrupt is disabled, the INTRQ
Signal shall be in a high impedance state.

CS0– I Chip select signal decoded from the host address bus. This signal is

used by the host to select the command block registers.

CS1– I Chip select signal decoded from the host address bus. This signal is

used by the host to select the control block registers.

DA 0-2 I Binary decoded address signals asserted by the host to access task

file registers.
KEY – Key pin for prevention of erroneous connector insertion
PIDAG– I/O This signal is an input mode for the master device and an output

mode for the slave device in a daisy chain configuration. This signal

indicates that the slave device has been completed self diagnostics.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.
CBLID– I/O This signal is used to detect the cable type (80 or 40-conductor

cable) installed in the system. This signal is pulled up to +5 V

through 10 kΩ resistor at each device.
DASP– I/O This is a time-multiplexed signal that indicates that the device is

active and a slave device is present.

This signal is pulled up to +5 V through 10 kΩ resistor at each device.

5 - 4

C141-E112-01EN

[signal] [I/O] [Description]

IORDY O This signal is negated to extend the host transfer cycle of any host

register access (Read or Write) when the device is not ready to respond

to a data transfer request.
DDMARDY– O DDMARDY– is a flow control signal for Ultra DMA data out bursts.

This signal is asserted by the device to indicate to the host that the

device is ready to receive Ultra DMA data out bursts. The device may

negate DDMARDY– to pause an Ultra DMA data out burst.
DSTROBE O DSTROBE is the data in strobe signal from the device for an Ultra

DMA data in burst. Both the rising and falling edge of DSTROBE

latch the data from DATA 0-15 into the host. The device may stop

generating DSTROBE edges to pause an Ultra DMA data in burst.
CSEL I This signal to configure the device as a master or a slave device.

When CSEL signal is grounded, the IDD is a master device.

When CSEL signal is open, the IDD is a slave device.

This signal is pulled up with 10 kΩ resistor.
DMACK– I The host system asserts this signal as a response that the host system

receive data or to indicate that data is valid.
DMARQ O This signal is used for DMA transfer between the host system and

the device. The device asserts this signal when the device completes

the preparation of DMA data transfer to the host system (at reading)

or from the host system (at writing).

The direction of data transfer is controlled by the IOR- and IOW-

signals. In other word, the device negates the DMARQ signal after

the host system asserts the DMACK– signal. When there is another

data to be transferred, the device asserts the DMARQ signal again.

When the DMA data transfer is performed, IOCW16–, CS0– and

CS1- signals are not asserted. The DMA data transfer is a 16-bit

data transfer. The device has a 10 kΩ pull-down resistor on this

signal.
GND – Grounded

Note:

"I" indicates input signal from the host to the device.
"O" indicates output signal from the device to the host.
"I/O" indicates common output or bi-directional signal between the host and the device.

C141-E112-01EN 5 - 5

5.2 Logical Interface

The device can operate for command execution in either address-specified mode; cylinder-head­sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information
indicates whether the device supports the LBA mode. When the host system specifies the LBA
mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head
register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder
Low, and Sector Number registers are LBA bits.

The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0
(defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE
PARAMETER command, the sector LBA address is not changed.

LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of sector/track)]
+ (Sector No.) – 1

5.2.1 I/O registers

Communication between the host system and the device is done through input-output (I/O)
registers of the device.

These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the
host system. Table 5.3 shows the coding address and the function of I/O registers.

5 - 6

C141-E112-01EN

Table 5.3 I/O registers

DA0DA1DA2CS1–CS0–

I/O registers

Read operation Write operation

Host I/O

address

Command block registers
1 0 0 0 0 Data Data X'1F0'
1 0 0 0 1 Error Register Features X'1F1'
1 0 0 1 0 Sector Count Sector Count X'1F2'
1 0 0 1 1 Sector Number Sector Number X'1F3'
1 0 1 0 0 Cylinder Low Cylinder Low X'1F4'
1 0 1 0 1 Cylinder High Cylinder High X'1F5'
1 0 1 1 0 Device/Head Device/Head X'1F6'
1 0 1 1 1 Status Command X'1F7'
1 1 X X X (Invalid) (Invalid) —
Control block registers
0 1 1 1 0 Alternate Status Device Control X'3F6'
0 1 1 1 1 — — X'3F7'

Notes:

1. The Data register for read or write operation can be accessed by 16 bit data bus (DATA0
to DATA15).

2. The registers for read or write operation other than the Data registers can be accessed by
8 bit data bus (DATA0 to DATA7).

3. When reading the Drive Address register, bit 7 is high-impedance state.

4. The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector
Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.

C141-E112-01EN 5 - 7

5.2.2 Command block registers

(1) Data register (X'1F0')

The Data register is a 16-bit register for data block transfer between the device and the host
system. Data transfer mode is PIO or LBA mode.

(2) Error register (X'1F1')

The Error register indicates the status of the command executed by the device. The contents of
this register are valid when the ERR bit of the Status register is 1.

This register contains a diagnostic code after power is turned on, a reset, or the EXECUTIVE
DEVICE DIAGNOSTIC command is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ICRC UNC X IDNF X ABRT TK0NF AMNF

X: Unused

- Bit 7: Interface CRC error (ICRC). This bit indicates that an interface CRC error has
occurred during an Ultra DMA data transfer. The content of this bit is not
applicable for Multiword DMA transfers.

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error
has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for, uncorrectable error and
SB not found, and Aborted Command.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was
aborted due to a device status error (e.g. Not Ready, Write Fault) or the command
code was invalid.

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during
RECALIBRATE command execution.

- Bit 0: Address Mark Not Found. This bit indicates that an SB not found error has been
encountered.

5 - 8

C141-E112-01EN

[Diagnostic code]

X'01': No Error Detected.
X'02': HDC Register Compare Error
X'03': Data Buffer Compare Error.
X'05': ROM Sum Check Error.
X'80': Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave)
configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic
code) with its own status (X'01' to X'05').
However, when the host system selects the slave device, the diagnostic code of the slave
device is posted.

(3) Features register (X'1F1')

The Features register provides specific feature to a command. For instance, it is used with SET
FEATURES command to enable or disable caching.

(4) Sector Count register (X'1F2')

The Sector Count register indicates the number of sectors of data to be transferred in a read or
write operation between the host system and the device. When the value in this register is X'00',
the sector count is 256.

When this register indicates X'00' at the completion of the command execution, this indicates that
the command is completed successfully. If the command is not completed successfully, this
register indicates the number of sectors to be transferred to complete the request from the host
system. That is, this register indicates the number of remaining sectors that the data has not been
transferred due to the error.

The contents of this register has other definition for the following commands; INITIALIZE
DEVICE PARAMETERS, FORMAT TRACK, SET FEATURES, IDLE, STANDBY and SET
MULTIPLE MODE.

(5) Sector Number register (X'1F3')

The contents of this register indicates the starting sector number for the subsequent command.
The sector number should be between X'01' and [the number of sectors per track defined by
INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

C141-E112-01EN 5 - 9

(6) Cylinder Low register (X'1F4')

The contents of this register indicates low-order 8 bits of the starting cylinder address for any
disk-access.

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

(7) Cylinder High register (X'1F5')

The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number.
The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

(8) Device/Head register (X'1F6')

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register
defines "the number of heads minus 1".

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X L X DEV HS3 HS2 HS1 HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

3

- Bit 3: HS3 CHS mode head address 3 (2

- Bit 2: HS2 CHS mode head address 3 (2

- Bit 1: HS1 CHS mode head address 3 (2

- Bit 0: HS0 CHS mode head address 3 (2

). LBA bit 27.

2

). LBA bit 26.

1

). LBA bit 25.

0

). LBA bit 24.

5 - 10

C141-E112-01EN

(9) Status register (X'1F7')

The contents of this register indicate the status of the device. The contents of this register are
updated at the completion of each command. When the BSY bit is cleared, other bits in this
register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are
invalid. When the host system reads this register while an interrupt is pending , it is considered to
be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending
interrupt is cleared (negating INTRQ signal) whenever this register is read.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ 0 0 ERR

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then
this bit is cleared when the command is completed. However, even if a command is
being executed, this bit is 0 while data transfer is being requested (DRQ bit =

1).When BSY bit is 1, the host system should not write the command block
registers. If the host system reads any command block register when BSY bit is 1,
the contents of the Status register are posted. This bit is set by the device under
following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control

register, the BSY bit is set. The BSY bit is cleared, when the reset process is
completed.
The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the Command register.
(c) Within 5 µs following transfer of 512 bytes data during execution of the

READ SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE
BUFFER command.

Within 5 µs following transfer of 512 bytes of data and the appropriate number
of ECC bytes during execution of READ LONG or WRITE LONG command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is capable to respond
to a command.

The IDD checks its status when it receives a command. If an error is detected (not
ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is
cleared until the rotational speed of the spindle motor reaches the steady speed.

- Bit 5: The Device W rite Fault (DF) bit. This bit indicates that a device fault (w rite fault)
condition has been detected.

If a write fault is detected during command execution, th is bit is latch ed and retained
until the device accepts the next command or reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are
positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up con tro l is completed.

C141-E112-01EN 5 - 11

- Bit 3: Data Request (D RQ) bit. This bit indicates that the device is ready to transfer data
of word unit or byte unit between the host system and the device.

- Bit 2: Always 0.

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous
command was being executed. The Error register indicates the additional
information of the cause for the error.

(10) Command register (X'1F7')

The Command register contains a command code being sent to the device. After this register is
written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the
necessary parameters for each command which are written to certain registers before the
Command register is written.

5 - 12

C141-E112-01EN

5.2.3 Control block registers

(1) Alternate Status register (X'3F6')

The Alternate Status register contains the same information as the Status register of the command
block register.

The only difference from the Status register is that a read of this register does not imply Interrupt
Acknowledge and INTRQ signal is not reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ 0 0 ERR

(2) Device Control register (X'3F6')

The Device Control register contains device interrupt and software reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XXXXXSRSTnIEN0

- Bit 2: SRST is the host software reset bit. When th is bit is set, the device is held reset
state. When two device are daisy chained on the interface, setting this bit resets both
device simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this
bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled
through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ
signal is in the high-impedance state.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related
registers in the command block and writing a command code in the Command register.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or
software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host
system writes to the command register, the correct device operation is not guaranteed.

C141-E112-01EN 5 - 13

5.3.1 Command code and parameters

Table 5.4 lists the supported commands, command code and the registers that needed parameters
are written.

Table 5.4 Command code and parameters (1 of 2)

Command name

Command code (Bit) Parameters used

76543210FRSCSNCYDH
READ SECTOR(S) 0010000RNYYYY
READ MULTIPLE 11000100NYYYY
READ DMA 1100100RNYYYY
READ VERIFY SECTOR(S) 0100000RNYYYY
WRITE MULTIPLE 11000101NYYYY
WRITE DMA 1100101RNYYYY
WRITE VERIFY 00111100NYYYY
WRITE SECTOR(S) 0011000RNYYYY
RECALIBRATE 0 0 0 1XXXXNNNND
SEEK 0 1 1 1XXXXNNYYY
INITIALIZE DEVICE DIAGNOSTIC 1 0010001NYNNY
IDENTIFY DEVICE 11101100NNNND
IDENTIFY DEVICE DMA 11101110NNNND
SET FEATURES 11101111YN*NND
SET MULTIPLE MODE 11000110NYNND
EXECUTE DEVICE DIAGNOSTIC 1 0010000NNNND*
FORMAT TRACK 01010000NNY*YY
READ LONG 0010001RNYYYY
WRITE LONG 0011001RNYYYY
READ BUFFER 11100100NNNND
WRITE BUFFER 11101000NNNND
IDLE 110101100010111

IDLE IMMEDIATE 110101100010001

STANDBY 110101100010110

5 - 14

C141-E112-01EN

NYNND

1

NNNND

1

NYNND

0

Table 5.4 Command code and parameters (2 of 2)

Command name

Command code (Bit) Parameters used

76543210FRSCSNCYDH
STANDBY IMMEDIATE 110101100010000

SLEEP 110101101001011

CHECK POWER MODE 110101101001000

NNNND

0

NNNND

0

NNNND

1
SMART 10110000YYYYD
FLUSH CACHE 11100111NNNND
SECURITY DISABLE PASSWORD 11110110NNNND
SECURITY ERASE PREPARE 11110011NNNND
SECURITY ERASE UNIT 11110100NNNND
SECURITY FREEZE LOCK 1 1110101NNNND
SECURITY SET PASSWORD 11110001NNNND
SECURITY UNLOCK 11110010NNNND
SET MAX ADDRESS 1 1111001NYYYY
READ NATIVE MAX ADDRESS 1 1111000NNNND

Notes:

FR : Features Register CY: Cylinder Registers
SC : Sector Count Register DH : Drive/Head Register
SN : Sector Number Register

R: R = 0 or 1

Y: Necessary to set parameters
Y*: Necessary to set parameters under the LBA mode.

N: Necessary to set parameters (The parameter is ignored if it is set.)
N*: May set parameters

D: The device parameter is valid, and the head parameter is ignored.

D*: The command is addressed to the master device, but both the master device and the slave

device execute it.

X: Do not care

C141-E112-01EN 5 - 15

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example
indication of the I/O registers at command completion are shown as following in this subsection.

Example: READ SECTOR(S)

At command issuance (I/O registers setting contents)

Bit 76543210
1F7H(CM) 00100000
1F6H(DH)

L

×

DV Head No. / LBA [MSB]

×

1F5H(CH) Start cylinder address [MSB] / LBA

1F4H(CL) Start cylinder address [LSB] / LBA
1F3H(SN) Start sector No. / LBA [LSB]
1F2H(SC) Transfer sector count
1F1H(FR) xx

At command completion (I/O registers contents to be read)

Bit 76543210

1F7H(ST) Error information

1F6H(DH)

L

×

DV End Head No. / LBA [MSB]

×

1F5H(CH) End cylinder address [MSB] / LBA

1F4H(CL) End cylinder address [LSB] / LBA
1F3H(SN) End sector No. / LBA [LSB]
1F2H(SC) X‘00’

5 - 16

1F1H(ER) Error information

CM: Command register FR: Features register
DH: Device/Head register ST: Status register
CH: Cylinder High register ER: Error register
CL: Cylinder Low register L: LBA (logical block address) setting bit
SN: Sector Number register DV: Device address. bit
SC: Sector Count register x, xx: Do not care (no necessary to set)

C141-E112-01EN

Note:

1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH,
CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most
significant bit) and bits of the SN register are the LSB (least significant bit).

2. At error occurrence, the SC register indicates the remaining sector count of data transfer.

3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.

(1) READ SECTOR(S) (X'20' or X'21')

This command reads data of sectors speci fied i n the Sector Count regi ster from t he address specified in
the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can
be specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For the
DRQ, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.1.

If the head is not on the track specified by the host, the device performs an implied seek. After the
head reaches to the specified track, the device reads the target sector.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error
condition.

Upon the completion of the command execution, command block registers contain the cylinder,
head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the
last sector read.

If an error occurs in a sector, the read operation is terminated at the sector where the error occurred.

Command block registers contain the cylinder, the head, and the sector addresses of the sector (in
the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and
remaining number of sectors of which data was not transferred.

At command issuance (I/O registers setting contents)
1F7H(CM) 0010000R
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 or 1

C141-E112-01EN 5 - 17

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

×

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(2) READ MULTIPLE (X'C4')

This command operates similarly to the READ SECTOR(S) command. The device does not
generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is
generated after the transfer of a block of sectors for which the number is specified by the SET
MULTIPLE MODE command.

The implementation of the READ MULTIPLE command is identical to that of the READ
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE
MODE command are transferred without intervening interrupts. In the READ MULTIPLE
command operation, the DRQ bit of the Status register is set only at the start of the data block, and
is not set on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the SET
MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior
to the READ MULTIPLE command.

L

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

When the READ MULTIPLE command is issued, the Sector Count register contains the number of
sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector Count
register is less than the defined block count (the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors
[block count]), as many full blocks as possible are transferred, then a final partial block is
transferred. The number of sectors in the partial block to be transferred is n where n = remainder
of ("number of sectors"/"block count").

If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is
executed or when the READ MULTIPLE command is disabled, the device rejects the READ
MULTIPLE command with an ABORTED COMMAND error.

If an error occurs, reading sector is stopped at the sector where the error occurred. Command
block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the
logical block address (in the LBA mode) of the sector where the error occurred, and remaining
number of sectors that had not transferred after the sector where the error occurred.

An interrupt is generated when the DRQ bit is set at the beginning of each block or a partial block.

5 - 18

C141-E112-01EN

Figure 5.1 shows an example of the execution of the READ MULTIPLE command.

• Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a

block)

• READ MULTIPLE command specifies;

Number of requested sectors = 9 (Sector Count register = 9)

↓

Number of sectors in incomplete block = remainder of 9/4 =1

Parameter

Command Issue

Write

~

BSY
DRDY

INTRQ

DRQ

Sector
transferred

Figure 5.1 Execution example of READ MULTIPLE command

At command issuance (I/O registers setting contents)
1F7H(CM) 11000100
1F6H(DH)

×

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

1 2 3 4

BlockBlock

L

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

Status readStatus readStatus read

95 6 7 8

Partial
block

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00

H

(*1)

Error information

*1 If the command is terminated due to an error, the remaining number of sectors for which data

was not transferred is set in this register.

C141-E112-01EN 5 - 19

(3) READ DMA (X'C8' or X'C9')

This command operates similarly to the READ SECTOR(S) command except for following
events.

• The data transfer starts at the timing of DMARQ signal assertion.

• The device controls the assertion or negation timing of the DMARQ signal.

• The device posts a status as the result of command execution only once at completion of the

data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be
continued is detected, the data transfer is stopped without transferring data of sectors after the erred
sector. The device generates an interrupt using the INTRQ signal and posts a status to the host system.
The format of the error information is the same as the READ SECTOR(S) command.

In LBA mode

The logical block address is specified using the start head No., start cylinder No., and first sector
No. fields. At command completion, the logical block address of the last sector and remaining
number of sectors of which data was not transferred, like in the CHS mode, are set.

The host system can select the DMA transfer mode by using the SET FEATURES command.

1) Multiword DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES com ma nd

2) Ultra DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES com ma nd

At command issuance (I/O registers setting contents)
1F7H(CM) 1100100R
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 or 1

5 - 20

C141-E112-01EN

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(4) READ VERIFY SECTOR(S) (X'40' or X'41')

This command operates similarly to the READ SECTOR(S) command except that the data is not
transferred to the host system.

After all requested sectors are verified, the device clears the BSY bit of the Status register and
generates an interrupt. Upon the completion of the command execution, the command block
registers contain the cylinder, head, and sector number of the last sector verified.

If an error occurs, the verify operation is terminated at the sector where the error occurred. The
command block registers contain the cylinder, the head, and the sector addresses (in the CHS
mode) or the logical block address (in the LBA mode) of the sector where the error occurred. The
Sector Count register indicates the number of sectors that have not been verified.

At command issuance (I/O registers setting contents)
1F7H(CM) 0100000R
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 or 1

C141-E112-01EN 5 - 21

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(5) WRITE SECTOR(S) (X'30' or X'31')

This command writes data of sectors from the address specified in the Device/Head, Cylinder
High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count
register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at
the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols
related to data transfer, see Subsection 5.4.2.

If the head is not on the track specified by the host, the device performs a implied seek. After the
head reaches to the specified track, the device writes the target sector.

The data stored in the buffer, and CRC code and ECC bytes are written to th e data field of the
corresponding sector(s). Upon the completion of the command execution, the command block
registers contain the cylinder, head, and sector addresses of the last sector written.

DV End head No. /LBA [MSB]

×

If an error occurs during multiple sector write operation, the write operation is terminated at the
sector where the error occurred. Command block registers contain the cylinder, the head, the
sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector
where the error occurred. Then the host can read the command block registers to determine what
error has occurred and on which sector the error has occurred.

At command issuance (I/O registers setting contents)
1F7H(CM) 0011000R
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

R = 0 or 1

5 - 22

C141-E112-01EN

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

×

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(6) WRITE MULTIPLE (X'C5')

This command is similar to the WRITE SECTOR(S) command. The device does not generate
interrupts (assertion of the INTRQ signal) on each sector but on the transfer of a block which
contains the number of sectors for which the number is defined by the SET MULTIPLE MODE
command.

The implementation of the WRITE MULTIPLE command is identical to that of the WRITE
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE
MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE
command operation, the DRQ bit of the Status register is required to set only at the start of the
data block, not on each sector.

The number of sectors (block count) to be transferred without interruption is specified by the SET
MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior
to the WRITE MULTIPLE command.

L

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of
sectors requested (not a number of the block count or a number of sectors in a block).

Upon receipt of this command, the device executes this command even if the value of the Sector Count
register is less than the defined block count the value of the Sector Count should not be 0).

If the number of requested sectors is not divided evenly (having the same number of sectors
[block count]), as many full blocks as possible are transferred, then a final partial block is
transferred. The number of sectors in the partial block to be transferred is n where n = remainder
of ("number of sectors"/"block count").

If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is
executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE
MULTIPLE command with an ABORTED COMMAND error.

Disk errors encountered during execution of the WRITE MULTIPLE command are posted after
attempting to write the block or the partial block that was transferred. Write operation ends at the
sector where the error was encountered even if the sector is in the middle of a block. If an error
occurs, the subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the
Status register is set at the beginning of each block or partial block.

C141-E112-01EN 5 - 23

The contents of the command block registers related to addresses after the transfer of a data block
containing an erred sector are undefined. To obtain a valid error information, the host should retry
data transfer as an individual requests.

At command issuance (I/O registers setting contents)
1F7H(CM) 11000101
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00

H

Error information

Note:

When the command terminates due to error, only the DV bit and the error in formation field

are valid.

(7) WRITE DMA (X'CA' or X'CB')

This command operates similarly to the WRITE SECTOR(S) command except for following
events.

• The data transfer starts at the timing of DMARQ signal assertion.

• The device controls the assertion or negation timing of the DMARQ signal.

• The device posts a status as the result of command execution only once at completion of the

data transfer.

When an error, such as an unrecoverable medium error, that the command execution cannot be
continued is detected, the data transfer is stopped without transferring data of sectors after the
erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the
host system. The format of the error information is the same as the WRITE SECTOR(S)
command.

A host system can be select the following transfer mode using the SET FEATURES command.

5 - 24

C141-E112-01EN

1) Multiword DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES com ma nd

2) Ultra DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES com ma nd

At command issuance (I/O registers setting contents)
1F7H(CM) 1100101R
1F6H(DH)

×

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

R = 0 or 1

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

×

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(8) WRITE VERIFY (X'3C')

L

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

L

DV End head No. /LBA [MSB]

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

This command operates similarly to the WRITE SECTOR(S) command except that the device verifies
each sector immediately after being written. The verify operation is a read and check for data errors
without data transfer. Any error that is detected during t he verify operat ion is post ed.

At command issuance (I/O registers setting contents)
1F7H(CM) 00111100
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Start head No. /LBA [MSB]

×

Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx

C141-E112-01EN 5 - 25

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

×

End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

(9) RECALIBRATE (X'1x', x: X'0' to X'F')

This command performs the calibration. Upon receipt of this command, the device sets BSY bit
of the Status register and performs a calibration. When the device completes the calibration, the
device updates the Status register, clears the BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

At command issuance (I/O registers setting contents)
1F7H(CM) 0001xxxx
1F6H(DH)

×××

DV End head No. /LBA [MSB]

DV xx

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

xx
xx
xx
xx
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

×××

DV xx

xx
xx
xx
xx

Error information

5 - 26

C141-E112-01EN

(10) SEEK (X'7x', x : X'0' to X'F')

This command performs a seek operation to the track and selects the head specified in the
command block registers. After completing the seek operation, the device clears the BSY bit in
the Status register and generates an interrupt.

The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.

In the LBA mode, this command performs the seek operation to the cylinder and head position in
which the sector is specified with the logical block address.

At command issuance (I/O registers setting contents)
1F7H(CM) 0111xxxx
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

L

×

DV Head No. /LBA [MSB]

×

Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

L

×

DV Head No. /LBA [MSB]

×

Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
Error information

C141-E112-01EN 5 - 27

(11) INITIALIZE DEVICE PARAMETERS (X'91')

The host system can set the number of sectors per track and the maximum head number
(maximum head number is "number of heads minus 1") per cylinder with this command. Upon
receipt of this command, the device sets the BSY bit of Status register and saves the parameters.
Then the device clears the BSY bit and generates an interrupt.

When the SC register is specified to X'00', an ABORTED COMMAND error is posted. Other
than X'00' is specified, this command terminates normally.

The parameters set by this command are retained even after reset or power save operation
regardless of the setting of disabling the reverting to default setting.

In LBA mode

The device ignores the L bit specification and operates with the CHS mode specification. An
accessible area of this command within head moving in the LBA mode is always within a default area.
It is recommended that the host system refers the addressable user sectors (total number of sectors) in
word 60 to 61 of the parameter information by t he IDENTIFY DEVICE comm and.

At command issuance (I/O registers setting contents)
1F7H(CM) 10010001
1F6H(DH)

×××

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH)

×××

1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

(12) IDENTIFY DEVICE (X'EC')

The host system issues the IDENTIFY DEVICE command to read parameter information (512
bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status
register and sets required parameter information in the sector buffer. The device then sets the
DRQ bit of the Status register, and generates an interrupt. After that, the host system reads the
information out of the sector buffer. Table 5.5 shows the arrangements and values of the
parameter words and the meaning in the buffer.

DV Max. head No.

xx
xx
xx

Number of sectors/track

xx

DV Max. head No.

xx
xx
xx
xx

Error Information

5 - 28

C141-E112-01EN

At command issuance (I/O registers setting contents)
1F7H(CM) 11101100
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(FR)

1F1

H

×××

DV xx

xx
xx
xx
xx
xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information
1F6H(DH)
1F5H(CH)

(CL)

1F4

H

(SN)

1F3

H

(SC)

1F2

H

(ER)

1F1

H

×××

DV xx

xx
xx
xx
xx

Error information

Table 5.5 Information to be read by IDENTIFY DEVICE command (1 of 6)

Word Value Description

0 X‘045A’ General Configuration *1
1 *2 Number of cylinders
2 X‘0000’ Reserved
3 *3 Number of Heads
4 X‘0000’ Retired
5 X‘0000’ Retired
6 X‘003F’ Number of sectors per track

7-9 X‘000000000000’ Retired

10-19 – Serial number (ASCII code) *4

20 X‘0003’ Retired
21 X‘1000’ Buffer size in 512 byte increments

22 X‘0004’ Number of ECC bytes transferred at READ LONG or WRITE LONG command
23-26 – Firmware revision (ASCII code) *5
27-46 – Model number (ASCII code) *6

47 X‘8010’ Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command

48 X‘0000’ Reserved

49 X‘2B00’ Capabilities *7

50 X‘4000’ Reserved

51 X‘0200’ PIO data transfer mode *8

52 X‘0200’ Retired

53 X‘0007’ Enable/disable setting of words 54-58, 64-70 and 88 *9

C141-E112-01EN 5 - 29

Table 5.5 Information to be read by IDENTIFY DEVICE command (2 of 6)

Word Value Description

54 (Variable) Number of current Cylinders

55 (Variable) Number of current Head

56 (Variable) Number of current sectors per track
57-58 (Variable) Total number of current sectors

59 *10 Transfer sector count currently set by READ/WRITE MULTIPLE command
60-61 *11 Total number of user addressable sectors (LBA mode only)

62 X‘0000’ Retired

63 X‘xx07’ Multiword DMA transfer mode *12

64 X‘0003’ Advance PIO transfer mode support status *13

65 X‘0078’ Minimum multiword DMA transfer cycle time per word : 120 [ns]

66 X‘0078’ Manufacturer's recommended DMA transfer cycle time : 120 [ns]

67 X‘00F0’ Minimum PIO transfer cycle time without flow control : 120 [ns]

68 X‘0078’ Minimum PIO transfer cycle time with IORDY flow control : 120 [ns]
69-79 X‘00’ Reserved

80 X‘003E’ Major version number *14

81 X‘0015’ Minor version number ATA/ATAPI5 X3T13 1321D Support of rev 1

82 X‘346B’ Support of command sets *15

83 X‘4108’ Support of command sets *16

84 X‘4000’ Support of com mand set/feature extension (fixed)

85 X‘xxxx’ Enable/disable Com mand set/feature enabled. *17

86 X‘xxxx’ Enable/disable Com mand set/feature enabled. *18

87 X‘4000’ Default of com mand set/feature (fixed)

88 X‘xx3F’ Ultra DMA modes *19

89 X‘00xx’ Time required for security erase unit completion *20

90 X‘0000’ Time required for Enhanced security erase completion

91 X‘00xx’ Current advanced power management value

92 X‘0000’ Reserved

93 X‘xxxx’ CBLID detection results *21

94 X‘00xx’ Automatic Acoustic Management (Slow Seek mode) *22

95-127 X‘00’ Reserved

128 X‘xx’ Security Status

129-255 X‘00’ Reserved

5 - 30

C141-E112-01EN

Table 5.5 Information to be read by IDENTIFY DEVICE command (3 of 6)

*

1 Word 0: General configuration

Bit 15: 0 = ATA device 0
Bit 14-8: Vendor specific
Bit 7: 1 = Removable media device 0
Bit 6: 1 = not removable controller and/or device 1
Bit 5-1: Vendor specific
Bit 0: Reserved 0

*2 Number of Cylinders, *3 Number of Heads,
*11Total number of user addressable sectors (LBA mode only.)

MPF3102AH MPF3153AH MPF3204AH
*2 X‘3FFF’
*3 X‘10’

*11 X‘01316AF0’ X‘01CA1E70’ X‘0262D5E0’

*4 Word 10-19: Serial number; ASCII code (20 characters, right-justified)

*5 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)

*6 Word 27-46: Model number;

ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20')
One of the following model numbers;
Fujitsu MPG3102AH
Fujitsu MPG3153AH
Fujitsu MPG3204AH

*7 Word 49: Capabilities

Bit 15-14: Reserved
Bit 13: Standby timer value 0 = Standby timer values shall be managed by the device
Bit 12: Reserved
Bit 11: IORDY support 1=Supported
Bit 10: IORDY inhibition0=Disable inhibition
Bit 9: LBA support 1=Supported
Bit 8: DMA support 1=Supported
Bit 7-0: Vendor specific

*8 Word 51: PIO data transfer mode

Bit 15-8: PIO data transfer mode X'02'=PIO mode 2
Bit 7-0: Vendor specific

*9 Word 53: Enable/disable setting of word 54-58, 64-70 and 88

Bit 15-3: Reserved
Bit 2: Enable/disable setting of word 88 1=Enable
Bit 1: Enable/disable setting of word 64-70 1=Enable
Bit 0: Enable/disable setting of word 54-58 1=Enable

*10Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command

Bit 15-9: Reserved
Bit 8: Multiple sector transfer 1=Enable
Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without

interrupt supports 2, 4, 8 and 16 sectors.

C141-E112-01EN 5 - 31

Table 5.5 Information to be read by IDENTIFY DEVICE command (4 of 6)

*12 Word 63: Multiword DMA transfer mode

Bit 15-11: Reserved
Bit 10: 1 = Multiword DMA mode 2 is selected

0 = Multiword DMA mode 2 is not selected

Bit 9: 1 = Multiword DMA mode 1 is selected

0 = Multiword DMA mode 1 is not selected

Bit 8: 1 = Multiword DMA mode 0 is selected

0 = Multiword DMA mode 0 is not selected
Bit 7-3: Reserved
Bit 2: 1 = Multiword DMA mode 2 and below are supported
Bit 1: 1 = Multiword DMA mode 1 and below are supported
Bit 0: 1 = Multiword DMA mode 0 is supported

*13 Word 64: Advance PIO transfer mode support status

Bit 15-8: Reserved
Bit 7-0: Advance PIO transfer mode

Bit 1=1 Mode 4
Bit 0=1 Mode 3

*14 Word 80: Major version number

Bit 15-5: Reserved
Bit 5: ATA-5 Supported=1
Bit 4: ATA-4 Supported=1
Bit 3: ATA-3 Supported=1
Bit 2: ATA-2 Supported=1
Bit 1: ATA-1 Supported=1
Bit 0: Undefined

*15 Word 82: Support of command sets

Bit 15: Reserved
Bit 14: NOP command supported = 0
Bit 13: Read Buffer command supported = 1
Bit 12: Write Buffer command supported = 1
Bit 11: Write Verify command supported (Old Spec.) = 0
Bit 10: Host Protected Area feature command supported = 1
Bit 9: Device Reset command supported = 0
Bit 8: SERVICE Interrupt supported = 0
Bit 7: Release Interrupt supported = 0
Bit 6: Lock Ahead supported = 1
Bit 5: Write-cache supported = 1
Bit 4: Packet command feature set supported = 0
Bit 3: Power Management feature set supported=1
Bit 2: Removable feature set supported=0
Bit 1: Security feature set supported=1
Bit 0: SMART feature set supported=1

*16 Word 83: Support of command sets

Bit 15: 0
Bit 14: 1
Bit 13-5: Reserved
Bit 4: Removable Media Status Notification feature set supported = 0
Bit 3: Advanced Power Management feature set supported = 1
Bit 2: CFA feature set supported = 0
Bit 1: READ/WRITE DMA QUEUED supported = 0
Bit 0: DOWNLOAD MICROCODE command supported = 0

5 - 32

C141-E112-01EN

Table 5.5 Information to be read by IDENTIFY DEVICE command (5 of 6)

*17 Word 85: Enable/disable Command set/feature enabled

Bit 15: Reserved
Bit 14: NOP command enabled = 0
Bit 13: READ BUFFER command enabled
Bit 12: WRITE BUFFER command enabled
Bit 11: Reserved
Bit 10: Host Protected Area feature set enabled
Bit 9: DEVICE RESET command enabled = 0
Bit 8: SERVICE interrupt enabled = 0
Bit 7: Release interrupt enabled = 0
Bit 6: Look-ahead enabled
Bit 5: Write cache enabled
Bit 4: PACKET Command feature set enabled = 0
Bit 3: Power Management feature set enabled
Bit 2: Removable Media feature set enabled = 0
Bit 1: Security Mode feature set enabled
Bit 0: SMART feature set enabled

*18 Word 86: Command set/feature enabled

Bit 15-10: Reserved
Bit 9: 1 = Automatic Acoustic Management feature set enabled
Bit 8: 1 = SET MAX security extension enabled by SET MAX SET PASSWORD
Bit 7: Reserved
Bit 6: 0 = SET FEATURES subcommand required to spin-up after power-up
Bit 5: 0 = Power-Up In Standby feature set enabled
Bit 4: 0 = Removable Media Status Notification feature set enabled
Bit 3: 1 = Advanced Power Management feature set enabled
Bit 2: 0 = CFA feature set enabled
Bit 1: 0 = READ/WRITE DMA QUEUED command supported
Bit 0: 0 = DOWNLOAD MICROCODE command supported

*19 Word 88: Ultra DMA modes

Bit 15-14: Reserved
Bit 13: 1 = Ultra DMA mode 5 is selected

0 = Ultra DMA mode 5 is not selected
Bit 12: 1 = Ultra DMA mode 4 is selected

0 = Ultra DMA mode 4 is not selected
Bit 11: 1 = Ultra DMA mode 3 is selected

0 = Ultra DMA mode 3 is not selected
Bit 10: 1 = Ultra DMA mode 2 is selected

0 = Ultra DMA mode 2 is not selected
Bit 9: 1 = Ultra DMA mode 1 is selected

0 = Ultra DMA mode 1 is not selected
Bit 8: 1 = Ultra DMA mode 0 is selected

0 = Ultra DMA mode 0 is not selected
Bit 7-6: Reserved
Bit 5: 1 = Ultra DMA mode 5 and below are supported
Bit 4: 1 = Ultra DMA mode 4 and below are supported
Bit 3: 1 = Ultra DMA mode 3 and below are supported
Bit 2: 1 = Ultra DMA mode 2 and below are supported
Bit 1: 1 = Ultra DMA mode 1 and below are supported
Bit 0: 1 = Ultra DMA mode 0 is supported

*20 Word 89: Time required for SECURITY ERASE UNIT command to complete.

MPG3102AH = 0004H: 8 minutes
MPG3204AH = 0008H: 16minutes
MPG3307AH = 0008H: 16 minutes
MPG3409AH = 0010H: 32 minutes

C141-E112-01EN 5 - 33