Fujitsu MPF50S User Manual

FUJITSU SEMICONDUCTOR

MICROCONTROLLER MANUAL

HARDWARE MANUAL

CM25-10133-2E

F2MC-8L FAMILY

8-BIT MICROCONTROLLER

MB89990 Series

F2MC-8L FAMILY

8-BIT MICROCONTROLLER

MB89990 Series

HARDWARE MANUAL

FUJITSU LIMITED

PREFACE

Preface describes objectives and intended reader.

■

Objectives and Intended Reader

The MB89990 series of microcontrollers are mid-range of microcontroller. They are generalpurpose and high-speed products in the F

microcontrollers operating at low voltages. It has Timer, Remote-control transmission frequency generator.

This manual covers the functions and operations of the MB89990 series of microcontrollers. Refer to the

F2MC-8L Family Software Manual

MC-8L Family series of 8-bit single-chip

for instructions.

1. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

2. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

3. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED.

4. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.).

CAUTION:

Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use witho ut prior approval.

5. Any sem iconductor device s have inherentl y a certain rate of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

6. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.

CONTENTS

CHAPTER 1 GENARAL ..................................................................................................... 1

1.1 Features ................................................................................................................................................ 2

1.2 Product Series ....................................................................................................................................... 3

1.3 Block Diagram ....................................................................................................................................... 5

1.4 Pin Assignment ...................................................................................................................................... 6

1.5 Pin Function Description ........................................................................................................................ 8

1.6 Handling Devices ................................................................................................................................. 12

CHAPTER 2 HARDWARE CONFIGRATION ................................................................... 13

2.1 CPU ..................................................................................................................................................... 14

2.2 Lock Control Block ............................................................................................................................... 19

2.3 Interrupt Controller ............................................................................................................................... 25

2.4 I/O Ports .............................................................................................................................................. 28

2.5 8/16-bit Timer (Timer 1 and Timer 2) ................................................................................................... 32

2.6 External Interrupt 1 .............................................................................................................................. 39

2.7 External Interrupt 2 (Wake Up) ............................................................................................................ 43

2.8 Remote-control Carrier Frequency Generator ..................................................................................... 45

2.9 Time-base Timer .................................................................................................................................. 48

2.10 Watchdog Timer Reset ........................................................................................................................ 51

CHAPTER 3 OPERATION ............................................................................................... 53

3.1 Clock Pulse Generator .................. ...... ....... ...... ....... ...... ....................................... ...... .......................... 54

3.2 Reset ................................................................................................................................................... 55

3.2.1 Reset Operation ............................................................................................................................. 56

3.2.2 Reset Source .................................................................................................................................. 57

3.3 Interrupt ............................................................................................................................................... 58

3.4 Low-power Consumption Modes ......................................................................................................... 60

3.5 Pin States for Sleep, Stop and Reset .................................................................................................. 61

CHAPTER 4 INSTRUCTIONS .......................................................................................... 63

4.1 Transfer Instructions ............................................................................................................................ 64

4.2 Operation Instruction ....................................... ....................................... ...... ....... ...... .......................... 66

4.3 Branch Instructions .............................................................................................................................. 68

4.4 Other Instructions ................................................................................................................................ 69

4.5 F2MC-8L Family Instruction Map ......................................................................................................... 70

CHAPTER 5 MASK OPTIONS ......................................................................................... 71

5.1 Mask Options ....................................................................................................................................... 72

APPENDIX ............................................................................................................................ 73

APPENDIX A I/O Map ................................................................................................................................ 74

APPENDIX B EPROM Setting for MB89P195 ............................................................................................ 76

iii

FIGURES

Figure 1.4-1 Pin Assignment (FPT-28P-M02, DIP-28P-M03) ........................................................................ 6

Figure 1.4-2 Pin Assignment (MQP-48C-P01) ................................................................................................ 7

Figure 2.1-1 Memory Space of MB89990 Series of Microcontrollers ............................................................ 14

Figure 2.1-2 Arrangement of 16 bit Data in Memory ..................................................................................... 16

Figure 2.1-3 Arrangement of 16-bit Data during Execution of Instruction ..................................................... 16

Figure 2.1-4 Structure of Processor Status ...... ...... ....... ...... ....... ...... ....................................... ...... ................ 17

Figure 2.1-5 Rule for Translating Real Addresses at General-purpose Register Area ................................. 17

Figure 2.1-6 Register Bank Configuration ..................................................................................................... 18

Figure 2.3-1 Interrupt-processing Flowcha rt .......................................... ....... ...... ....... ...... ....... ...... ... ............. 27

Figure 2.4-1 Ports 00 to 07 and 30 to 37 ...................................................................................................... 30

Figure 2.4-2 Ports 40 to 45 ........................................................................................................................... 31

Figure 2.5-1 8/16-bit Timer Block Diagram ................................................................................................... 32

Figure 2.5-2 Description Diagram for Internal Clock Mode Operation .......................................................... 36

Figure 2.5-3 Flow Diagram for Timer Setting ................................................................................................ 36

Figure 2.5-4 Initialization of Equivalent Circuit .............................................................................................. 37

Figure 2.5-5 External Cock Mode Operation Description Diagram ............................................................... 37

Figure 2.5-6 Operation Diagram when Timer Stop Bit is Used ..................................................................... 38

Figure 3.1-1 Clock Pulse Generator .............................................................................................................. 54

Figure 3.2-1 Outline of Reset Operation ....................................................... ...... ....... ...... ....... ...................... 56

Figure 3.2-2 Reset Vector Structure ...................... ....... ...... ....... ...... ....................................... ...................... 56

Figure 3.3-1 Interrupt-processing Flowcha rt .......................................... ....... ...... ....... ...... ....... ...... ................ 58

TABLES

Table 1.2-1 Types and Functions of MB89990 Series of Microcontrollers ..................................................... 3

Table 1.5-1 Pin Function Description .............................................................................................................. 8

Table 1.5-2 Pins for External ROM ................................................................................................................. 9

Table 1.5-3 Input/Output Circuit Configurations ........................................................................................... 10

Table 2.1-1 Table of Reset and Interrupt Vectors ......................................................................................... 15

Table 2.2-1 Opeating State of Low-power Consumption Modes .................................................................. 21

Table 2.2-2 Selection of Oscillation Stabilization Time ................................................................................. 22

Table 2.2-3 Sources of Reset ....................................................................................................................... 24

Table 2.4-1 List of Port Functions ................................................................................................................. 28

Table 3.3-1 Interrupt Sources and Interrupt Vectors .................................................................................... 59

Table 3.4-1 Low-power Consumption Mode at Each Clock Mode ................................................................ 60

Table 3.5-1 Pin State of MB89990 ............................................................................................................... 61

Table 5.1-1 Mask Options ............................................................................................................................ 72

CHAPTER 1 GENARAL

The MB89990 series contains microcontrollers with a full range of resources such as timers, external interrupts, and remote-control function, as well as the F2MC-8L CPU

core for low-voltage and high-speed operation. This single-chip microcontroller is suitable for small devices such as remote controllers incorporating compact packages.

1.1 Features

1.2 Product Series

1.3 Block Diagram

1.4 Pin Assignment

1.5 Pin Function Description

1.6 Handling Devices

CHAPTER 1 GENARAL

1.1 Features

This section describes the features .

■

Features

• Minimum instruction execution time: 0.95 µs at 4.2 MHz (V

• CPU core common to F

• Instruction set su itable for controlle r: - M ult ipl y /su btr ac tio n i ns truction, - 16-bit oper ati on,

- Instruction test and branch instruction, - Bit operation instruction

•Two timers

• 8/16-bit timer/counter

• 20-bit time-base counter

• External interrupts

• Edge detection: 3 pins (edge direction enabled)

• Low-level interrupt: 8 pins (wake-up)

• Built-in remote-control carrier frequency generator

• Low-power consumption modes

• Stop mode: Almost no power consumption because oscillation stopped

• Sleep mode: 33% of normal power consumption because CPU stopped

• Package: SOP-28, SH-DIP-28 (mask ROM only)

MC-8L CPU

= 3 V)

1.2 Product Series

This section describes the product series.

■

Product Series

Table 1.2-1 "Types and Functions of MB89990 Series of Microcontrollers"lists the types and functions of the MB89990 series of microcontrollers.

Table 1.2-1 Types and Functions of MB89990 Series of Microcontr ollers

Model Name MB89997 MB89P195* MB89PV190*

Classification Mass-produced product (mask ROM

product)

ROM capacity 32 K × 8 bits

(internal ROM)

RAM capacity 128 × 8 bits 256 × 8 bits CPU functions Number of basic instructions

Instruction bit length Instruction length Data bit length Minimum instruction execution time Interrupt processing time

Port I/O port (N-ch open drain)

I/O port (CMOS)

Total Timer counter 2 channels 8-bit counter or 1 channel 16-bit counte External-interrupt 1 3 independent channels (edge selection, interrupt vector, interrupt source flag)

Interrupt mode selectable from rising edge, falling edge, or both edges

For releasing Stop/Sleep modes (edge detection in Stop mode enabled)

136 instructions 8 bits 1 to 3 bytes 1, 8, 16 bits

0.95 µs/4.2 MHz

8.6 µs/4.2 MHz 6 pins

16 pins (13 used as resource pins) 22 pins

One-time product For evaluation

and development

16 K × 8 bits

(internal ROM,

write enable by

general-purpose

writer)

32 K × 8 bits

(external ROM)

External-interrupt 2 (Wake-up)

Remote-control carrier frequency

Standby mode Sleep and Stop modes Process CMOS Package FPT-28P-M02, DIP-28P-M03 FPT-28P-M02 MQP-48C-P01 Operating voltage 2.2 to 6.0 V** 2.7V to 6.0 V

8 channels (Low-level interrupt enabled)

Pulse width and cycle are programmable

CHAPTER 1 GENARAL

* The MB89P195 microtroller is the one-time product for the MB89190 series which can be also be used

for the MB89990 series.

* The MB89PV190 microtroller is the evaluation and development product for the MB89190 series which

can be also be used for the MB89990 series.

** Operating voltage varies with conditions such as frequency or others. See the data sheet for details.

1.3 Block Diagram

This section describes the block diagram.

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Block Diagram

Internal Bus

1.3 Block Diagram

RST

Main oscillator

circuit

Clock control

Reset circuit

(WDT)

Time-base timer

RAM

(128 x 8 bits)

Remote-control

carrier frequency

8-bit timer/counter

External Interrupt

CMOS I/O port

P34/TO/INT10

P33 / EC

P30 ~ P32

Port 3

P35 / INT11

P36 / INT12

P37 / RCO

MC-8L

CPU

ROM

(32K x 8 bits)

TEST

Vcc, Vss

External Interrupt

(wake-up)

N-ch open drain I/O port

P00 / INT20 to

Port 0Port 4

P07 / INT27

P40 ~ P45

CHAPTER 1 GENARAL

1.4 Pin Assignment

This section describes the pin assignment.

■

Pin Assignment

Figure 1.4-1 Pin Assignment (FPT-28P-M02, DIP-28P-M03)

P04/INT24 P05/INT25 P06/INT26 P07/INT27

TEST

RST

X0 X1

P37/RCO P36/INT12 P35/INT11

P34/TO/INT10

P33/EC

1 2 3 4 5 6 7 8 9 10 11 12 13 14

(TOP VIEW)

28 27 26 25 24 23 22 21 20 19 18 17 16 15

P03/INT23 P02/INT22 P01/INT21 P00/INT20 P45 P44 P43 P42 P41 P40 P30 P31 P32

Figure 1.4-2 Pin Assignment (MQP-48C-P01)

P35/INT11

N.C.

Vss

N.C.

48 47 46 45 44 43 42 41 40 39 38 37

1.4 Pin Assignment

N.C.

P34/TO/INT10

P33/EC

P32 P31 P30 P40 P41 P42 P43 P44 P45

P00/INT20

1 2 3 4 5 6 7 8 9 10 11 12

68 67 66 65 64 63 62 61

69 70 71 72 73 74 75 76

77 78 79 80 49 50 51 52

13 14 15 16 17 18 19 20 21 22 23 24

N.C.

P10/INT21

(TOP VIEW)

N.C.

Vcc

60 59 58 57 56 55 54 53

N.C.

P02/INT22

P30/INT23

36 35 34 33 32 31 30 29 28 27 26 25

N.C. N.C. P36/INT12 P37/RCO X1 X0 RST TEST P07/INT27 P06/INT26 P05/INT25 P04/INT24

* Pin assignment on package top (only for piggyback/evaluation product)

Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol

49 V

PP 57 NC 65 04 73 OE

50A1258A2660574NC 51 A7 59 A1 67 06 75 A11 52 A6 60 A0 68 07 76 A9 53 A5 61 01 69 08 77 A8 54 A4 62 02 70 CE

78 A13 55 A3 63 03 71 A10 79 A14 56 NC 64 GND 72 NC 80 V

CHAPTER 1 GENARAL

1.5 Pin Function Description

This section describes the pin functions.

■

Pin Function Description

Table 1.5-1 "Pin Function Description" and Table 1.5-2 "Pins for External ROM" list the pin function and Table 1.5-3 "Input/Output Circuit Configurations" shows the input/output circuit configurations.

Table 1.5-1 Pin Function Description

Pin No. Pin Name Circuit type Function

7X0 8X1

5TEST B

RST

P00/INT20

24 to 27

1 to 4

17 P30 E 16 P31 E 15 P32 E

14 P33/EC D

P03/INT23 P04/INT24

P07/INT27

Clock oscillator pins

Test input pin

These pins are connected directly to V

Reset I/O pin

This pin consists of an N-ch open-drain output with a pull-up resistor and hysteresis input. A Low level is output from this pin by internal source. The internal circuit is initialized at input of a Low level.

General-purpose I/O port

These ports also serve as external interrupt input pin. The external interrupt input is hysteresis type.

General-purpose I/O port

These ports also serve as external interrupt input pin. The external interrupt input is hysteresis type.

General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port

This port also serves as an external clock input pin for the 8bit timer/counter. The external clock input is hysteresis type with a built-in noise filter.

13 P34/T0/INT10 D

12 P35/INT11

11 P36/INT12

General-purpose I/O port

This port also serves as an overflow output pin and an external interrupt input pin for the 8-bit timer/counter. The external interrupt input is hysteresis type with a built-in noise filter.

General-purpose I/O port

This port also serves as an external interrupt input pin. The external interrupt input is hysteresis type with a built-in noise filter.

Table 1.5-1 Pin Function Description (Continued)

Pin No. Pin Name Circuit type Function

1.5 Pin Function Description

10 P37/RCO E

18 to 23 P40 to P45 F

28 V

— —

General-purpose I/O port

This port also serves as remote-control output pin.

N-ch open-drain type I/O port Power pin Power (GND) pin

Table 1.5-2 Pins for External ROM

Pin No. Pin Name Circuit type Functinon

49 V 79

78 50 75 69 76 77 51 52 53 54 55 58 59 60

A14 A13 A12 A11 A10

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Output

High-level output pin

Address-output pins

61 62 63 65 66 67 68 69

01 02 03 04 05 06 07 08

70 CE

73 OE

80 V 64 V

Intput

Output

Output Output

Data-input pins

Chip-enable pin for ROM

A High level is output in the standby mode.

Output-enable pin for ROM

A Low level is always output.

Power pin for EPROM Power (GND) pin

CHAPTER 1 GENARAL

Table 1.5-3 Input/Output Circuit Configurations

Classification Circuit Remarks

A • Crystal oscillator

• Feedback resistor: About 1 MΩ/5V (1 to 5MHz)

Standby control signal

B • CMOS input

C • Output pull-up resistor (P-ch):

About 50 kΩ (5 V)

• Hysteresi s inp u t

Pch

Nch

D • CMOS input/output

• Hysteresis input (resorce input)

Pch

Nch

• The pull-up resistor is available.

1.5 Pin Function Description

Table 1.5-3 Input/Output Circuit Configurations (Continued)

Classification Circuit Remarks

E • CMOS input/output

• The pull-up resistor is available.

Pch

Nch

F • N-ch open-drain output

• Analog input

Pch

• The pull-up resistor is available. (MB89990 series only)

Nch

Analog input

CHAPTER 1 GENARAL

1.6 Handling Devices

This section describes handling devices.

■

Handling Devices

(1) Preventing latch-up Latch-up may occur if a voltage high er than V

or lower than VSS is applied to the input or

output pins other than middle- and high-level-resistant pins, or if voltage exceeding the rated value is applied between V

and VSS. When latch-up occurs, the supply current increases

rapidly, sometimes r esulting in overheating and destruc tion. Therefore, no voltage exceeding the maximum ratings should be used.

(2) Handling unused input pins Leaving unused inp ut pin s open may cause a malfu nction. Therefore, t hese pin s shoul d be set

to pull-up or pull-down. (3) Variations in supply voltage Although the specif ied V

supply voltage op erating range is assured, a sud den change in the

supply voltage within the specified range may cause a malfunction. Therefore, the voltage supply to the IC should be kept as cons tant as possible. The V

supply frequency (50 to 60 Hz) should be less than 10% of the typical V

ripple (P-P value) at the

value, or the

coefficient of exces sive variati on should be less tha n 0.1 V/ms instantaneous change whe n the power supply is switched.

(4) Precautions for external clocks It takes some time for oscillation to stabilize after changing the mode from power-on reset

(option selection) and stop mode. Consequently, an external clock must be input. (5) Recommended screening conditions The OPTROM product should be screened by high-temperature aging before mounting.

Verify program

High-temperature aging (150°C, 48 H)

Read

Mount

The programming test can not be perform ed for all bi ts of the prep rogr ammed OPTROM product due to its characteristics. Consequently, 100% programming yielding cannot be ensured.

CHAPTER 2 HARDWARE CONFIGRATION

This chapter describes each block of the CPU hardware.

2.1 CPU

2.2 Clock Control Block

2.3 Interrupt Controller

2.4 I/O Ports

2.5 8/16-bit Timer (Timer 1 and Timer 2)

2.6 External Interrupt 1

2.7 External Interrupt 2 (Wake up)

2.8 Remote-control Carrier Frequency Generator

2.9 Time-base Timer

2.10 Watchdog Timer Reset

CHAPTER 2 HARDWARE CONFIGRATION

2.1 CPU

• This section describes the memory space and register composing CPU hardware.

■

Memory Space

The MB89990 series of microc ontroller s have a memo ry area of 64K bytes . All I/O, data area s, and program areas are located in this space. The I/O area is at the lowest address and the data area is immediately above it. The data area may be divided into register, stack, and directaddress areas according to the applications. The program area is located near the highest address and the tables of interrupt and reset vectors and vector-call instructions are at the highest address. Figure 2.1-1 "Memory Space of MB89990 Series of Microc ontrollers" shows the structure of the memory space for the MB89990 series of microcontrollers.

Figure 2.1-1 Memory Space of MB89990 Series of Microcontrollers

0000H

0080H

00C0H

0100H

0140H

8000H

FFFFH

MB89997

I/O

Vacant area

Mask ROM

RAM

0000H

0080H

0100H

0180H

C000H

FFFFH

MB89P195

I/O

RAM

Vacant area

Program PROM

(Mask ROM)

0000

0080H

0100H

0180H

8000H

FFFFH

MB89PV190

I/O

RAM

Vacant area

External ROM

• I/O area

• This area is where various reso urce s such as contr ol and d ata reg ister s are loc ated. T he memory map for the I/O area is given in APPENDIX A .

• RAM area

• This area is where the stati c RAM is lo cat ed. Ad dr es se s from

013F

for the MB89997) are also used as the general-purpose register area.

0100

017F

0100

(

• ROM area

• This area is whe re the in ter nal RO M is lo ca ted. Addresses fro m

FFC0

FFFF

are also

used for the table o f reset and vector-c all instructions. T able 2.1-1 "Table of Reset and Interrupt Vectors " shows the correspondence between each interrupt number or reset and the table addresses to be referenced for the MB89990 series of microcontrollers.

Table 2.1-1 Table of Reset and Interrupt Vectors

Table address

Upper data Lower data

2.1 CPU

CALLV #0 CALLV #1 CALLV #2 CALLV #3 CALLV #4 CALLV #5 CALLV #6 CALLV #7

Interrupt #11 Interrupt #10

Interrupt #9 Interrupt #8

FFC0 FFC2 FFC4 FFC6 FFC8 FFCA FFCC FFCE

FFC1 FFC3 FFC5 FFC7 FFC9 FFCB FFCD FFCF

Table address

Upper data Lower data

FFE4 FFE6 FFE8 FFEA

FFE5 FFE7 FFE9 FFEB

Interrupt #7 Interrupt #6 Interrupt #5 Interrupt #4 Interrupt #3 Interrupt #2 Interrupt #1 Interrupt #0

Reset mode – – – –

Reset vector

Note:

FFFC

Set

is already reserved.

for

FFFD

in the Reset mode.

FFEC FFFE FFF0 FFF2 FFF4 FFF6 FFF8 FFFA

FFFE

FFED FFEF FFF1 FFF3 FFF5 FFF7 FFF9 FFFB FFFD FFFF

CHAPTER 2 HARDWARE CONFIGRATION

■

Arrangement of 16-bit Data in Memory

When the MB89990 ser ies of microcontroller s handle 16-bit data, the data written at the lowe r address is treated as the upper data and tha t written at th e next address is treated as the lower data as shown in Figure 2.1-2 "Arrangement of 16 bit Data in Memory".

Figure 2.1-2 Arrangement of 16 bit Data in Memory

Before execution

1234H

Memory

ABCFH ABCEH ABCDH ABCCH

MOVW ABCDH , A

After execution

1234H

Memory

34H 12H

ABCFH ABCEH ABCDH ABCCH

This is the same as when 16 bits are specified by the operand during execution of an instruction. Bits closer to the OP code are treated as the upper byte and those next to it are treated as the lowe r byte. This is als o the same when the me mory a ddress or 1 6-bit i mmediate data is specified by the operand.

Figure 2.1-3 Arrangement of 16-bit Data during Execution of Instruction

[Example]

MOV A, 5678

H ; Extended address

Assemble

XXXXH XX XX

Data saved in the stack by an interrupt is also treated in the same manner.

■

Internal Registers in CPU

The MB89990 serie s of microcontrollers have dedicated registers specifi ed applications in the CPU and general-purpose registers in memory.

• Program counter (PC) 16-bit long register indicating location where instructions

• Accumulator (A) 16-bit long register where results of operations stored

• Temporary accumulator (T) 16-bit long register where the operations are performed

• Stack pointer (SP) 16-bit long register indicating stack area

XXXX

H 60 56 78 ; Extended address H E4 12 34 ; 16-bit immediate data

XXXX

H XX

XXXX

stored

temporarily. The lower byte is used to execute 8-bit data processing instructions.

between this register and the accumulator. The lower byte is used to execute 8-bit data processing instructions.

2.1 CPU

• Processor status (PS) 16-bit long register where register pointers and condition codes stored

• Index register (IX) 16-bit long register for index modification

• Extra pointer (EP) 16-bit long register for memory addressing

16 bits

P C

Program counter

Accumulator

Temporary accumulator

Index register

Extra pointer

Stack pointer

Processor status

The 16 bits of the processor statu s (PS) can be divided into 8 upper bits for a register bank pointer (RP) and 8 lower bits for a con dition code register (CCR ). (See Fig ure 2.1-4 "S tructure of Processor Status".)

Figure 2.1-4 Structure of Processor Status

1514131211109876543210

RP H I N Z V C

Vacant Vacant Vacant

IL1, 0

CCR

The RP indicates the add ress of the cu rrent regi ster bank. T he contents of the RP and the re al addresses are translated as shown in Figure 2.1-5 "Rule for Translating Real Addresses at General-purpose Register Area" .

Figure 2.1-5 Rule for Translating Real Addresses at General-purpose Register Area

Lower bits of OP code

Source address

R P

'0' '0' '0' '0' '0' '0' '0' '1' R4 R3 R2 R1 R0 b2 b1 b0

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

The CCR has bits indicating the results of operations and transfer data contents, and bits controlling the CPU operation when an interr upt oc curs .

- H-flag H-flag is set when a carry or a borrow out of bit 3 into bit 4 is generated

as a result of operations. It is cleared in other cases. This flag is used for decimal-correction instructions.

CHAPTER 2 HARDWARE CONFIGRATION

- I-flag An interrupt is enabled when this flag is 1 and is disabled when it is 0. The I-flag is 0 at reset.

- IL1 and IL0 These bits indicate the level of the currently-enabled interrupt. The Interrupt Processing executes interrupt processing only when an interrupt with a value smaller than the value indicated by this bit is requested.

IL1 IL0 Interrupt level High and low

0 0 1

- N-flag The N-flag is set when the most significant bit is 1 as a result of operations. It is cleared when the MSB is 0.

- Z-flag Z-flag is set when the bit is 0 as a result of operations. It is cleared in other cases.

0 1 0

2 3

High

Low = No interrupt

- V-flag V-flag is set when a twoís complement overflow occurs as a result of operations. It is reset when an overflow does not occur.

- C-flag C-flag is set when a carry or a borrow out of bit 7 is generated as a result of operations. It is cleared in other cases. When the shift instruction is executed, the value of the C-flag is shifted out.

• General-purpose registers General-purpose registers are 8-bit long registers for storing data. The 8-bit long general- purpose registers are in the register ba nks in memory. One bank has

eight registers and up to 16 b anks are available for the MB89193 (8 banks for the MB89191). The register bank pointer (RP) indicates the currently-used bank.

Figure 2.1-6 Register Bank Configuration

Address = 0100H + 8 (RP)

R0 R1 R2 R3 R4 R5 R6 R7

16 banks

Memory area

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