MPA3017AT
MPA3026AT
MPA3035AT
MPA3043AT
MPA3052AT
DISK DRIVES
PRODUCT MANUAL
C141-E034-02EN
REVISION RECORD
Edition Date published Revised contents
01 Jan., 1997
02 August, 1997
Specification No.: C141-E034-**EN
The contents of this manual is subject to change
without prior notice.
All Rights Reserved.
Copyright
1997 FUJITSU LIMITED
C141-E034-02EN i
PREFACE
This manual describes the MPA3017AT/MPA3026AT/MPA3035AT/MPA3043AT/MPA3052AT, a
3.5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface.
This manual explains, in detail, how to incorporate the hard disk drives into user systems.
This manual assumes that users have a basic knowledge of hard disk drives and their application in
computer systems.
This manual consists of the following six chapters:
Chapter 1 DEVICE OVERVIEW
Chapter 2 DEVICE CONFIGURATION
Chapter 3 INSTALLATION CONDITIONS
Chapter 4 THEORY OF DEVICE OPERATION
Chapter 5 INTERFACE
Chapter 6 OPERATIONS
Chapter 7 MISCELLANEOUS
In this manual, disk drives may be referred to as drives or devices.
C141-E034-02EN iii
Conventions for Alert Messages
This manual uses the following conventions to show the alert messages. An alert message consists of an
alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a
signal word.
The following are the alert signals and their meanings:
This indicates a hazarous situation likely to result in serious personal
injury if the user does not perform the procedure correctly.
This indicates a hazarous situation could result in personal injury if the
user does not perform the porocedure correctly.
This indicates a hazarous situation could result in minor or moderate
personal injury if the user does not perform the procedure correctly. This
alert signal also indicates that damages to the product or other property,
may occur if the user does not perform the procedure correctly.
This indicates information that could help the user use the product more
efficiently.
In the text, the alert signal is centered, followed below by the indented message. A wider line space
precedes and follows the alert message to show where the alert message begins and ends. The following is
an example:
(Example)
IMPORTANT
HA (host adapter) consists of address decoder, driver, and receiver.
ATA is an abbreviation of "AT attachment". The disk drive is
conformed to the ATA-3 interface
The main alert messages in the text are also listed in the “Important Alert Items.”
iv C141-E034-02EN
LIABILITY EXCEPTION
"Disk drive defects" refers to defects that involve adjustment, repair, or replacement.
Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or
mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the
host system, or other causes outside the disk drive.
C141-E034-02EN v
CONTENTS
page
CHAPTER 1 DEVICE OVERVIEW
1.1 Features.................................................................................................................................1 - 1
1.1.1 Functions and performance................................................................................................... 1 - 1
1.1.2 Adaptability ..........................................................................................................................1 - 2
1.1.3 Interface................................................................................................................................ 1 - 2
1.2 Device Specifications ........................................................................................................... 1 - 4
1.2.1 Specifications summary........................................................................................................ 1 - 4
1.2.2 Model and product number................................................................................................... 1 - 5
1.3 Power Requirements.............................................................................................................1 - 5
1.4 Environmental Specifications...............................................................................................1 - 8
1.5 Acoustic Noise...................................................................................................................... 1 - 8
1.6 Shock and Vibration............................................................................................................. 1 - 9
1.7 Reliability............................................................................................................................. 1 - 9
1.8 Error Rate.............................................................................................................................1 - 10
1.9 Media Defects....................................................................................................................... 1 - 10
CHAPTER 2 DEVICE CONFIGURATION
......................................................................................... 1 - 1
............................................................................. 2 - 1
2.1 Device Configuration............................................................................................................2 - 1
2.2 System Configuration ........................................................................................................... 2 - 4
2.2.1 ATA interface....................................................................................................................... 2 - 4
2.2.2 1 drive connection ................................................................................................................ 2 - 4
2.2.3 2 drives connection............................................................................................................... 2 - 5
CHAPTER 3 INSTALLATION CONDITIONS
3.1 Dimensions........................................................................................................................... 3 - 1
3.2 Mounting ..............................................................................................................................3 - 3
3.3 Cable Connections................................................................................................................3 - 7
3.3.1 Device connector..................................................................................................................3 - 7
3.3.2 Cable connector specifications .............................................................................................3 - 8
3.3.3 Device connection ................................................................................................................ 3 - 8
3.3.4 Power supply connector (CN1)............................................................................................. 3 - 9
3.4 Jumper Settings.....................................................................................................................3 - 9
....................................................................... 3 - 1
C141-E034-02EN vii
3.4.1 Location of setting jumpers .................................................................................................. 3 - 9
3.4.2 Factory default setting .......................................................................................................... 3 - 10
3.4.3 Jumper configuration............................................................................................................ 3 - 10
CHAPTER 4 THEORY OF DEVICE OPERATION............................................................... 4 - 1
4.1 Outline.................................................................................................................................. 4 - 1
4.2 Subassemblies....................................................................................................................... 4 - 1
4.2.1 Disk....................................................................................................................................... 4 - 1
4.2.2 Head...................................................................................................................................... 4 - 2
4.2.3 Spindle.................................................................................................................................. 4 - 3
4.2.4 Actuator................................................................................................................................4 - 3
4.2.5 Air filter................................................................................................................................ 4 - 3
4.3 Circuit Configuration............................................................................................................ 4 - 4
4.4 Power-on Sequence ..............................................................................................................4 - 6
4.5 Self-calibration .....................................................................................................................4 - 8
4.5.1 Self-calibration contents ....................................................................................................... 4 - 8
4.5.2 Execution timing of self-calibration......................................................................................4 - 9
4.5.3 Command processing during self-calibration........................................................................ 4 - 9
4.6 Read/write Circuit.................................................................................................................4 - 10
4.6.1 Read/write preamplifier (PreAMP)....................................................................................... 4 - 10
4.6.2 Write circuit.......................................................................................................................... 4 - 10
4.6.3 Read circuit........................................................................................................................... 4 - 12
4.6.4 Time base generator circuit...................................................................................................4 - 14
4.7 Servo Control........................................................................................................................4 - 15
4.7.1 Servo control circuit ............................................................................................................. 4 - 16
4.7.2 Data-surface servo format..................................................................................................... 4 - 19
4.7.3 Servo frame format............................................................................................................... 4 - 19
4.7.4 Actuator motor control ......................................................................................................... 4 - 20
4.7.5 Spindle motor control...........................................................................................................4 - 21
CHAPTER 5 INTERFACE ........................................................................................................ 5 - 1
5.1 Physical Interface.................................................................................................................. 5 - 2
5.1.1 Interface signals.................................................................................................................... 5 - 2
5.1.2 Signal assignment on the connector...................................................................................... 5 - 3
5.2 Logical Interface................................................................................................................... 5 - 6
5.2.1 I/O registers ..........................................................................................................................5 - 6
C141-E034-02ENviii
5.2.2 Command block registers .....................................................................................................5 - 8
5.2.3 Control block registers.......................................................................................................... 5 - 13
5.3 Host Commands....................................................................................................................5 - 13
5.3.1 Command code and parameters............................................................................................5 - 14
5.3.2 Command descriptions ......................................................................................................... 5 - 16
5.3.3 Error posting......................................................................................................................... 5 - 54
5.4 Command Protocol............................................................................................................... 5 - 55
5.4.1 Data transferring commands from device to host ................................................................. 5 - 55
5.4.2 Data transferring commands from host to device ................................................................. 5 - 57
5.4.3 Commands without data transfer .......................................................................................... 5 - 59
5.4.4 Other commands................................................................................................................... 5 - 60
5.4.5 DMA data transfer commands..............................................................................................5 - 60
5.5 Ultra DMA feature set.......................................................................................................... 5 - 62
5.5.1 Overview .............................................................................................................................. 5 - 62
5.5.2 Phases of operation............................................................................................................... 5 - 63
5.5.3 Ultra DMA data in commands.............................................................................................. 5 - 63
5.5.4 Ultra DMA data out commands............................................................................................ 5 - 67
5.5.5 Ultra DMA CRC rules.......................................................................................................... 5 - 71
5.5.6 Series termination required for Ultra DMA.......................................................................... 5 - 72
5.6 Timing ..................................................................................................................................5 - 73
5.6.1 PIO data transfer................................................................................................................... 5 - 73
5.6.2 Single word DMA data transfer............................................................................................ 5 - 75
5.6.3 Multiword data transfer ........................................................................................................5 - 76
5.6.4 Ultra DMA data transfer....................................................................................................... 5 - 77
5.6.5 Power-on and reset ............................................................................................................... 5 - 89
CHAPTER 6 OPERATIONS...................................................................................................... 6 - 1
6.1 Device Response to the Reset............................................................................................... 6 - 1
6.1.1 Response to power-on........................................................................................................... 6 - 2
6.1.2 Response to hardware reset...................................................................................................6 - 3
6.1.3 Response to software reset.................................................................................................... 6 - 4
6.1.4 Response to diagnostic command......................................................................................... 6 - 5
6.2 Address Translation..............................................................................................................6 - 6
6.2.1 Default parameters................................................................................................................6 - 6
6.2.2 Logical address..................................................................................................................... 6 - 7
6.3 Power Save........................................................................................................................... 6 - 8
C141-E034-02EN ix
6.3.1 Power save mode.................................................................................................................. 6 - 8
6.3.2 Power commands..................................................................................................................6 - 10
6.4 Defect Management.............................................................................................................. 6 - 10
6.4.1 Spare area ............................................................................................................................. 6 - 11
6.4.2 Alternating defective sectors.................................................................................................6 - 11
6.5 Read-Ahead Cache ...............................................................................................................6 - 13
6.5.1 Data buffer configuration......................................................................................................6 - 13
6.5.2 Caching operation................................................................................................................. 6 - 14
6.5.3 Usage of read segment..........................................................................................................6 - 15
6.6 Write Cache.......................................................................................................................... 6 - 22
C141-E034-02ENx
FIGURES
page
1.1 Current fluctuation (Typ.) at +5V when power is turned on................................................. 1 - 7
2.1 Disk drive outerview............................................................................................................. 2 - 1
2.2 Configuration of disk media heads ....................................................................................... 2 - 3
2.3 1 drive system configuration................................................................................................. 2 - 4
2.4 2 drives configuration........................................................................................................... 2 - 5
3.1 Dimensions...........................................................................................................................3 - 2
3.2 Orientation............................................................................................................................ 3 - 3
3.3 Limitation of side-mounting ................................................................................................. 3 - 4
3.4 Mounting frame structure ..................................................................................................... 3 - 4
3.5 Surface temperature measurement points ............................................................................. 3 - 5
3.6 Service area .......................................................................................................................... 3 - 6
3.7 Connector locations.............................................................................................................. 3 - 7
3.8 Cable connections.................................................................................................................3 - 8
3.9 Power supply connector pins (CN1)..................................................................................... 3 - 9
3.10 Jumper location..................................................................................................................... 3 - 9
3.11 Factory default setting .......................................................................................................... 3 - 10
3.12 Jumper setting of master or slave device .............................................................................. 3 - 10
3.13 Jumper setting of Cable Select.............................................................................................. 3 - 11
3.14 Example (1) of Cable Select................................................................................................. 3 - 11
3.15 Example (2) of Cable Select................................................................................................. 3 - 11
4.1 Head structure....................................................................................................................... 4 - 2
4.2 MPA30xxAT Block diagram................................................................................................ 4 - 5
4.3 Power-on operation sequence............................................................................................... 4 - 7
4.4 Read/write circuit block diagram.......................................................................................... 4 - 11
4.5 Frequency characteristic of programmable filter..................................................................4 - 12
4.6 PR4 signal transfer................................................................................................................ 4 - 13
4.7 Block diagram of servo control circuit ................................................................................. 4 - 16
4.8 Physical sector servo configuration on disk surface ............................................................. 4 - 17
4.9 Servo frame format............................................................................................................... 4 - 19
5.1 Interface signals.................................................................................................................... 5 - 2
5.2 Execution example of READ MULTIPLE command...........................................................5 - 19
5.3 Read Sector(s) command protocol........................................................................................ 5 - 56
C141-E034-02EN xi
5.4 Protocol for command abort................................................................................................. 5 - 57
5.5 WRITE SECTOR(S) command protocol..............................................................................5 - 58
5.6 Protocol for the command execution without data transfer................................................... 5 - 59
5.7 Normal DMA data transfer................................................................................................... 5 - 61
5.8 Ultra DMA termination with pull-up or pull-down............................................................... 5 - 72
5.9 PIO data transfer timing........................................................................................................5 - 74
5.10 Single word DMA data transfer timing................................................................................. 5 - 75
5.11 Multiword DMA data transfer timing (mode 2).................................................................... 5 - 76
5.12 Initiating an Ultra DMA data in burst................................................................................... 5 - 77
5.13 Sustained Ultra DMA data in burst....................................................................................... 5 - 80
5.14 Host pausing an Ultra DMA data in burst............................................................................. 5 - 81
5.15 Device terminating an Ultra DMA data in burst................................................................... 5 - 82
5.16 Host terminating an Ultra DMA data in burst....................................................................... 5 - 83
5.17 Initiating an Ultra DMA data out burst................................................................................. 5 - 84
5.18 Sustained Ultra DMA data out burst..................................................................................... 5 - 85
5.19 Device pausing an Ultra DMA data out burst....................................................................... 5 - 86
5.20 Host terminating an Ultra DMA data out burst..................................................................... 5 - 87
5.21 Device terminating an Ultra DMA data out burst................................................................. 5 - 88
5.22 Power on Reset Timing.........................................................................................................5 - 89
6.1 Response to power-on...........................................................................................................6 - 2
6.2 Response to hardware reset................................................................................................... 6 - 3
6.3 Response to software reset....................................................................................................6 - 4
6.4 Response to diagnostic command......................................................................................... 6 - 5
6.5 Address translation (example in CHS mode)........................................................................ 6 - 7
6.6 Address translation (example in LBA mode)........................................................................ 6 - 8
6.7 Sector slip processing........................................................................................................... 6 - 11
6.8 Alternate cylinder assignment...............................................................................................6 - 12
6.9 Data buffer configuration...................................................................................................... 6 - 13
C141-E034-02ENxii
TABLES
page
1.1 Specifications........................................................................................................................1 - 4
1.2 Model names and product numbers......................................................................................1 - 5
1.3 Current and power dissipation..............................................................................................1 - 6
1.4 Environmental specifications................................................................................................1 - 8
1.5 Acoustic noise specification ................................................................................................. 1 - 8
1.6 Shock and vibration specification......................................................................................... 1 - 9
3.1 Surface temperature measurement points and standard values.............................................3 - 5
3.2 Cable connector specifications ............................................................................................. 3 - 8
4.1 Self-calibration execution timechart.....................................................................................4 - 9
4.2 Write precompensation algorithm......................................................................................... 4 - 10
4.3 Write clock frequency and transfer rate of each zone........................................................... 4 - 15
5.1 Signal assignment on the interface connector....................................................................... 5 - 3
5.2 I/O registers.......................................................................................................................... 5 - 7
5.3 Command code and parameters............................................................................................ 5 - 14
5.4 Information to be read by IDENTIFY DEVICE command..................................................5 - 30
5.5 Features register values and settable modes.......................................................................... 5 -
5.6 Diagnostic code....................................................................................................................5 - 37
5.7 Features register values (subcommands) and functions........................................................5 - 48
5.8 Format of device attribute value data.................................................................................... 5 - 50
5.9 Format of insurance failure threshold value data.................................................................. 5 - 51
5.10 Command code and parameters............................................................................................ 5 - 54
5.11 Recommended series termination for Ultra DMA................................................................ 5 - 72
5.12 Ultra DMA data burst timing requirements .......................................................................... 5 - 78
6.1 Default parameters................................................................................................................ 6 - 6
34
C141-E034-02EN xiii
CHAPTER 1 DEVICE OVERVIEW
1.1 Features
1.2 Device Specifications
1.3 Power Requirements
1.4 Environmental Specifications
1.5 Acoustic Noise
1.6 Shock and Vibration
1.7 Reliability
1.8 Error Rate
1.9 Media Defects
Overview and features are described in this chapter, and specifications and power requirement are
described.
The MPA3017AT/MPA3026AT/MPA3035AT/MPA3043AT/MPA3052AT is a 3.5-inch hard disk drive
with a built-in ATA controller. The disk drive is compact and reliable.
1.1 Features
1.1.1 Functions and performance
(1) Compact
The disk has 1, 2 or 3 disks of 95 mm (3.5 inches) diameter, and its height is 25.4 mm (1 inch).
(2) Large capacity
The disk drive can record up to 1,750 MB (formatted) on one disk using the (8/9) PRML recording
method and 15 recording zone technology. The MPA3017AT, MPA3026AT, MPA3035AT,
MPA3043AT and MPA3052AT have a formatted capacity of 1,750 MB, 2,625 MB, 3,500 MB,
4,375MB and 5,250MB respectively.
(3) High-speed Transfer rate
The disk drive has an internal data rate up to 14.96 MB/s. The disk drive supports an external data
rate up to 16.7 MB/s or 33.3 MB/s (ultra DMA mode).
C141-E034-02EN 1 - 1
(4) Average positioning time
Use of a rotary voice coil motor in the head positioning mechanism greatly increases the
positioning speed. The average positioning time is 10 ms (at read).
1.1.2 Adaptability
(1) Power save mode
The power save mode feature for idle operation, stand by and sleep modes makes the disk drive
ideal for applications where power consumption is a factor.
(2) Wide temperature range
The disk drive can be used over a wide temperature range (5°C to 55°C).
(3) Low noise and vibration
In Ready status, the noise of the disk drive is only about 35 dBA (measured at 1 m apart from the
drive under the idle mode).
1.1.3 Interface
(1) Connection to interface
With the built-in ATA interface controller, the disk drive can be connected to an ATA interface of
a personal computer.
(2) 128-KB data buffer
The disk drive uses a 128-KB data buffer to transfer data between the host and the disk media.
In combination with the read-ahead cache system described in item (3) and the write cache
described in item (6), the buffer contributes to efficient I/O processing.
(3) Read-ahead cache system
After the execution of a disk read command, the disk drive automatically reads the subsequent data
block and writes it to the data buffer (read ahead operation). This cache system enables fast data
access. The next disk read command would normally cause another disk access. But, if the read
ahead data corresponds to the data requested by the next read command, the data in the buffer can
be transferred instead.
(4) Master/slave
The disk drive can be connected to ATA interface as daisy chain configuration. Drive 0 is a
master device, drive 1 is a slave device.
C141-E034-02EN1 - 2
(5) Error correction and retry by ECC
If a recoverable error occurs, the disk drive itself attempts error recovery. The 18-byte ECC has
improved buffer error correction for correctable data errors.
(6) Write cache
When the disk drive receives a write command, the disk drive posts the command completion at
completion of transferring data to the data buffer completion of writing to the disk media. This
feature reduces the access time at writing.
C141-E034-02EN 1 - 3
1.2 Device Specifications
1.2.1 Specifications summary
Table 1.1 shows the specifications of the disk drive.
Table 1.1 Specifications
MPA3017AT MPA3026AT MPA3035AT MPA3043AT MPA3052AT
Formatted Capacity (*1) 1750.00 MB 2625.00 MB 3500.00 MB 4375.00 MB 5250.01 MB
Number of Heads 23456
Number of Cylinders
(User + Alternate & SA)
Bytes per Sector 512
Recording Method (8/9) PRML
Track Density 9202 TPI
Bit Density 137,285 BPI
Rotational Speed 5400 rpm ± 0.5%
Average Latency 5.56 ms
Positioning time
• Minimum
• Average
• Maximum
Start/Stop time
• Start (0 rpm to Driv e Re ad)
• Stop (at Power Down)
Interface ATA–3
Data Transfer Rate
• To/From Media 8.019 to 14.964 MB/s
• To/From Host 16.7 MB/s Max. (burst PIO mode 4, burst DMA mode 2),
Data buffer 128 MB
Physical Dimensions
(Height × Width × Depth)
Weight 600 g
(Read) 10 ms typical, (Write) 12 ms typical
(Read) 19 ms typical, (Write) 20 ms typical
Typical: 10 sec., Maximum: 16 sec.
Typical: 20 sec., Maximum: 26 sec.
(Maximum Cable length: 0.46 m)
33.3 MB/s Max. (burst ultra DMA mode 2)
25.4 mm × 101.6 mm × 146.0 mm
8,713 + 84
3 ms typical
(1.0” × 4.0” × 5.75”)
*1: Capacity under the LBA mode.
Under the CHS mode (normal BIOS specification), formatted capacity, number of cylinders, number
of heads, and number of sectors are as follows.
Model Formatted Capacity No. of Cylinder No. of Heads No. of Sectors
MPA3017AT 1749.56 3,390 16 63
MPA3026AT 2624.86 5,086 16 63
MPA3035AT 3499.13 6,780 16 63
MPA3043AT 4374.88 9,042 15 63
MPA3052AT 5249.66 10,850 15 63
C141-E034-02EN1 - 4
1.2.2 Model and product number
Table 1.2 lists the model names and product numbers.
Table 1.2 Model names and product numbers
Model Name Capacity
(user area)
MPA3017AT 1749.56 MB No. 6-32UNC CA01602-B321
MPA3026AT 2624.86 MB No. 6-32UNC CA01602-B331
MPA3035AT 3499.13 MB No. 6-32UNC CA01602-B341
MPA3043AT 4374.42 MB No. 6-32UNC CA01602-B351
MPA3052AT 5249.72 MB No. 6-32UNC CA01602-B361
MPA3017AT 1749.56 MB No. 6-32UNC CA01602-B421 UDMA33 version
MPA3026AT 2624.86 MB No. 6-32UNC CA01602-B431 UDMA33 version
MPA3035AT 3499.13 MB No. 6-32UNC CA01602-B441 UDMA33 version
MPA3043AT 4374.42 MB No. 6-32UNC CA01602-B451 UDMA33 version
MPA3052AT 5249.72 MB No. 6-32UNC CA01602-B461 UDMA33 version
1.3 Power Requirements
(1) Input Voltage
Mounting Screw Order No. Others
• + 5 V ±5 %
• + 12 V ±5 %
(2) Ripple
Maximum 200 mV (peak to peak) 100 mV (peak to peak)
Frequency DC to 1 MHz DC to 1 MHz
+12 V +5 V
C141-E034-02EN 1 - 5
(3) Current Requirements and Power Dissipation
Table 1.3 lists the current and power dissipation.
Table 1.3 Current and power dissipation
Mode of
Operation
Model MPA
Spin up 1.3 A
Idle (Ready) (*3) 0.120 A 0.155 A 0.185 A 0.443 A 3.66 watts 4.08 watts 4.44 watts
R/W (On Track)
(*4)
Seek (Random)
(*5)
Standby 0.01 A 0.400 A 2.12 watts
Sleep 0.01 A 0.350 A 1.87 watts
3017AT
0.130 A 0.160 A 0.190 A 0.620 A 4.66 watts 5.02 watts 5.38 watts
0.370 A 0.380 A 0.425 A 0.520 A 7.04 watts 7.16 watts 7.70 watts
Typical RMS current (*1)
+12 V +5 V
MPA
3026AT
MPA
3035AT
1.5 A peak
MPA
3043AT
MPA
3052AT
All Models MPA
0.6 A peak
0.520 A
3017AT
Typical Power (*2)
MPA
3026AT
MPA
3035AT
18.2 watts
MPA
3043AT
MPA
3052AT
*1 Current is typical rms except for spin up.
*2 Power requirements reflect nominal values for +12V and +5V power.
*3 Idle mode is in effect when the drive is not reading, writing, seeking, or executing any
commands.
*4 R/W mode is defined as 50% read operations and 50% write operations on a single physical
track.
*5 Seek mode is defined as continuous random seek operations with minimum controller delay.
C141-E034-02EN1 - 6
(4) Current fluctuation (Typ.) at +5V when power is turned on
Note:
Maximum current is 1.5 A and is continuance is 1.5 seconds
Figure 1.1 Current fluctuation (Typ.) at +5V when power is turned on
(5) Power on/off sequence
The voltage detector circuit monitors +5 V and +12 V. The circuit does not allow a write signal if
either voltage is abnormal. This prevents data from being destroyed and eliminates the need to be
concerned with the power on/off sequence.
C141-E034-02EN 1 - 7
1.4 Environmental Specifications
Table 1.4 lists the environmental specifications.
Table 1.4 Environmental specifications
Temperature
• Operating
• Non-operating
• Thermal Gradient
Humidity
• Operating
• Non-operating
• Maximum Wet Bulb
Altitude (relative to sea level)
• Operating
• Non-operating
1.5 Acoustic Noise
5°C to 55°C (ambient)
5°C to 60°C (disk enclosure surface)
–40°C to 60°C
20°C/h or less
8% to 80%RH (Non-condensing)
5% to 85%RH (Non-condensing)
29°C
–60 to 3,000 m (–200 to 10,000 ft)
–60 to 12,000 m (–200 to 40,000 ft)
Table 1.5 lists the acoustic noise specification.
Sound Pressure
• Idle mode (DRIVE READY)
• Seek mode (Random)
Table 1.5 Acoustic noise specification
35 dBA typical at 1 m
40 dBA typical at 1 m
C141-E034-02EN1 - 8
1.6 Shock and Vibration
Table 1.6 lists the shock and vibration specification.
Table 1.6 Shock and vibration specification
Vibration (swept sine, one octave per minute)
• Operating
• Non-operating
Shock (half-sine pulse, 11 ms duration)
• Operating
• Non-operating
1.7 Reliability
(1) Mean time between failures (MTBF)
The mean time between failures (MTBF) is 500,000 H or more (operation: 24 hours/day, 7
days/week).
This does not include failures occurring during the first three months after installation.
5 to 300 Hz, 0.5G-0-peak
(without non-recovered errors)
5 to 400 Hz, 4G-0-peak (no damage)
10G (without non-recovered errors)
75G (no damage)
MTBF is defined as follows:
MTBF= (H)
"Disk drive defects" refers to defects that involve repair, readjustment, or replacement. Disk drive
defects do not include failures caused by external factors, such as damage caused by handling,
inappropriate operating environments, defects in the power supply host system, or interface cable.
(2) Mean time to repair (MTTR)
The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff
member.
(3) Service life
In situations where management and handling are correct, the disk drive requires no overhaul for
five years when the DE surface temperature is less than 48°C. When the DE surface temperature
exceeds 48°C, the disk drives requires no overhaul for five years or 20,000 hours of operation,
whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement point of the DE
surface temperature.
Total operation time in all fields
number of device failure in all fields
C141-E034-02EN 1 - 9
(4) Data assurance in the event of power failure
Except for the data block being written to, the data on the disk media is assured in the event of any
power supply abnormalities. This does not include power supply abnormalities during disk media
initialization (formatting) or processing of defects (alternative block assignment).
1.8 Error Rate
Known defects, for which alternative blocks can be assigned, are not included in the error rate
count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk
media.
(1) Unrecoverable read error
Read errors that cannot be recovered by maximum 126 times read retries without user's retry and
ECC corrections shall occur no more than 10 times when reading data of 10
executed according to the disk drive's error recovery procedure, and include read retries
accompanying head offset operations.
(2) Positioning error
Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in
7
seek operations.
10
1.9 Media Defects
Defective sectors are replaced with alternates when the disk is formatted prior to shipment from the
factory (low level format). Thus, the host sees a defect-free device.
Alternate sectors are automatically accessed by the disk drive. The user need not be concerned
with access to alternate sectors.
Chapter 6 describes the low level format at shipping.
15
bits. Read retries are
C141-E034-02EN1 - 10
CHAPTER 2 DEVICE CONFIGURATION
2.1 Device Configuration
2.2 System Configuration
2.1 Device Configuration
Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write
preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle
motors actuators, and a circulating air filter.
Figure 2.1 Disk drive outerview
C141-E034-02EN 2 - 1
(1) Disk
The outer diameter of the disk is 95 mm. The inner diameter is 25 mm. The number of disks used
varies with the model, as described below. The disks are rated at over 40,000 start/stop
operations.
MPA3017AT: 1 disk
MPA3026AT: 2 disks
MPA3035AT: 2 disks
MPA3043AT: 3 disks
MPA3052AT: 3 disks
(2) Head
The heads are of the contact start/stop (CSS) type. The head touches the disk surface while the
disk is not rotating and automatically lifts when the disk starts.
Figure 2.2 illustrates the configuration of the disks and heads of each model. In the disk surface,
servo information necessary for controlling positioning and read/write and user da ta are written.
Numerals 0 to 5 indicate read/write heads.
C141-E034-02EN2 - 2
MPA3017 Model
Spindle
1
0
MPA3026AT Model
Spindle
2
1
0
MPA3043AT Model
Spindle
Actuator
Actuator
Actuator
MPA3035AT Model
Spindle
3
2
1
0
MPA3052AT Model
Spindle
Actuator
Actuator
4
3
2
1
0
(3) Spindle motor
The disks are rotated by a direct drive Hall-less DC motor.
(4) Actuator
The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and
generates very little heat. The head assembly at the edge of the actuator arm is controlled and
positioned by feedback of the servo information read by the read/write head. If the power is not on
or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and
is fixed by a mechanical lock.
5
4
3
2
1
0
Figure 2.2 Configuration of disk media heads
C141-E034-02EN 2 - 3
(5) Air circulation system
The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure
features a closed loop air circulation system that relies on the blower effect of the rotating disk.
This system continuously circulates the air through the circulatio n filter to maintain the c leanliness
of the air within the disk enclosure.
(6) Read/write circuit
The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability
by preventing errors caused by external noise.
(7) Controller circuit
The controller circuit consists of an LSI chip to improve reliability. The high-speed
microprocessor unit (MPU) achieves a high-performance AT controller.
2.2 System Configuration
2.2.1 ATA interface
Figures 2.3 and 2.4 show the ATA interface system configuration. The drive has a 40-pin PC AT
interface connector and supports the PIO transfer till 16.7 MB/s (ATA-3, Mode 4), the DMA
transfer till 16.7 MB/s (ATA-3, Multiword mode 2), and the ultra DMA transfer till (ATA-4,
Mode 4).
2.2.2 1 drive connection
Host
AT bus
(Host interface)
HA
(Host adaptor)
Disk drive
ATA interface
Figure 2.3 1 drive system configuration
C141-E034-02EN2 - 4
2.2.3 2 drives connection
Host
HA
(Host adaptor)
Disk drive #0
AT bus
(Host interface)
Disk drive #1
ATA interface
Note:
When the drive that is not conformed to ATA is connected to the disk drive is above
configuration, the operation is not guaranteed.
Figure 2.4 2 drives configuration
IMPORTANT
HA (host adapter) consists of address decoder, driver, and receiver.
ATA is an abbreviation of "AT attachment". The disk drive is
conformed to the ATA-3 interface.
At high speed data transfer (PIO mode 3, mode 4, DMA mode 2 or
ultra DMA mode), occurrence of ringing or crosstalk of the signal lines
(AT bus) between the HA and the disk drive may be a great cause of the
obstruction of system reliability. Thus, it is necessary that the
capacitance of the signal lines including the HA and cable does not
exceed the ATA-3 and ATA-4 standard, and the cable length between
the HA and the disk drive should be as short as possible.
C141-E034-02EN 2 - 5
CHAPTER 3 INSTALLATION CONDITIONS
3.1 Dimensions
3.2 Mounting
3.3 Cable Connections
3.4 Jumper Settings
3.1 Dimensions
Figure 3.1 illustrates the dimensions of the disk drive and po sitions of the mounting screw holes.
All dimensions are in mm.
C141-E034-02EN 3 - 1
Figure 3.1 Dimensions
C141-E034-02EN3 - 2
3.2 Mounting
(1) Orientation
Figure 3.2 illustrates the allowable orientations for the disk drive. The mounting angle can vary
±5° from the horizontal.
gravity
(a) Horizontal mounting (b) Vertical mounting –1 (c) Vertical mounting –2
(2) Frame
The disk enclosure (DE) body is connected to signal ground (SG) and the mounting frame is also
connected to signal ground. These are electrically shorted.
Note:
Use No.6-32UNC screw for the mounting screw and the screw length should satisfy the
specification in Figure 3.4.
(3) Limitation of side-mounting
When the disk drive is mounted using the screw holes on both side of the disk drive, use two screw
holes shown in Figure 3.3.
Do not use the center hole. For screw length, see Figure 3.4.
Figure 3.2 Orientation
C141-E034-02EN 3 - 3
Do not use this screw holes
Figure 3.3 Limitation of side-mounting
Use these screw
holes
Bottom surface mounting
2
A
Frame of system
cabinet
4.5 or
less
DE
Details of A
Figure 3.4 Mounting frame structure
Screw
2.5
2.5
Frame of system
cabinet
5.0 or less
PCA
Details of B
Side surface
mounting
DE
Screw
2.5
B
C141-E034-02EN3 - 4
(4) Ambient temperature
The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature
at a point 3 cm from the disk drive. Pay attention to the air flow to prevent the DE surface
temperature from exceeding 60°C.
Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient
cooling. To check the cooling efficiency, measure the surface temperatures of the DE. Regardless
of the ambient temperature, this surface temperature must meet the standards listed in Table 3.1.
Figure 3.5 shows the temperature measurement point.
1
Figure 3.5 Surface temperature measurement points
Table 3.1 Surface temperature measurement points and standard values
No. Measurement point Temperature
1 DE cover 60°C max
C141-E034-02EN 3 - 5
(5) Service area
Figure 3.6 shows how the drive must be accessed (service areas) during and after installation.
- Mounting screw hole
[P side]
- Cable connection
- Mode setting switches
[Q side]
- Mounting screw hole
[R side]
- Mounting screw hole
(6) External magnetic fields
Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the
disk drive is not affected by external magnetic fields.
Figure 3.6 Service area
C141-E034-02EN3 - 6
3.3 Cable Connections
3.3.1 Device connector
The disk drive has the connectors and terminals listed below for connecting external devices.
Figure 3.7 shows the locations of these connectors and terminals.
• Power supply connector (CN1)
• ATA interface connector (CN1)
Power supply
connector (CN1)
Mode
Setting
Pins
ATA
interface
connector
Figure 3.7 Connector locations
C141-E034-02EN 3 - 7
3.3.2 Cable connector specifications
Table 3.2 lists the recommended specifications for the cable connectors.
Table 3.2 Cable connector specifications
Name Model Manufacturer
ATA interface cable
(40-pin, CN1)
Power supply cable
(CN1)
Note :
The cable of twisted pairs and neighboring line separated individually is not allowed to use for
the host interface cable. It is because that the location of signal lines in these cables is not
fixed, and so the problem on the crosstalk among signal lines may occur.
3.3.3 Device connection
Figure 3.8 shows how to connect the devices.
Cable socket
(closed-end type)
Cable socket
(through-end type)
Signal cable 445-248-40 SPECTERS STRIP
Cable socket housing 1-480424-0 AMP
Contact 60617-4 AMP
Signal cable AWG 18 to 24
FCN-707B040-AU/B Fujitsu
FCN-707B040-AU/O Fujitsu
Host system
ATA interface cable Power supply cable
Disk Dri ve #0
Disk Dri ve #1
Figure 3.8 Cable connections
C141-E034-02EN3 - 8
DC
power supply
3.3.4 Power supply connector (CN1)
Figure 3.9 shows the pin assignment of the power supply connector (CN1).
4321
(Viewed from cable side)
Figure 3.9 Power supply connector pins (CN1)
3.4 Jumper Settings
3.4.1 Location of setting jumpers
Figure 3.10 shows the location of the jumpers to select drive configuration and functions.
CN1
C01
C01
Power
supply
connector
C04
C04
1
2
3
4
+12VDC
+12V RETURN
+5V RETURN
+5VDC
B01
B02
B06B05 B05/06
A01 A02
A39 A40
B01/02
A01/02
A39/40
Mode setting
Connector
pins
Interface
Connector
Figure 3.10 Jumper location
C141-E034-02EN 3 - 9
3.4.2 Factory default setting
Figure 3.11 shows the default setting position at the factory.
B02
C01
C04
B01
3.4.3 Jumper configuration
(1) Device type
Master device (device #0) or slave device (device #1) is selected.
B01 05
06
A02
05
Figure 3.11 Factory default setting
A01
06B02
A40
A39
06B02
05B01
(a) Master device (b) Slave device
Figure 3.12 Jumper setting of master or slave device
(2) Cable Select (CSEL)
In Cable Select mode, the device can be configured either master device or slave device. For use of
Cable Select function, Unique interface cable is needed.
C141-E034-02EN3 - 10
06B02
B01 05
CSEL connected to the interface
Cable selection can be done by the
special interface cable.
Figure 3.13 Jumper setting of Cable Select
Figures 3.14 and 3.15 show examples of cable selection using unique interface cables.
By connecting the CSEL of the master device to the CSEL Line (conductor) of the cable and
connecting it to ground further, the CSEL is set to low level. The device is identified as a master
device. At this time, the CSEL of the slave device does not have a conductor. Thus, since the
slave device is not connected to the CSEL conductor, the CSEL is set to high level. The device is
identified as a slave device.
GND
GND
Host system
CSEL conductor
Open
Slave devi ceMaster deviceHost system
Figure 3.14 Example (1) of Cable Select
CSEL conductor
Open
Slave devi ce Master d evi ce
Figure 3.15 Example (2) of Cable Select
C141-E034-02EN 3 - 11
(3) Special setting 1 (SP1)
The number of cylinders reported by the IDENTIFY DEVICE command is selected.
(a) Default mode
2 4 6
1 3 5
Model No. of cylinders
MPA3017AT 3,390
MPA3026AT 5,086
MPA3035AT 6,780
MPA3043AT 9,042
MPA3052AT 10,850
(b) Special mode
2 4 6
2 4 6
1 3 5
Slave DeviceMaster Device
2 4 6
2 4 6
1 3 5
Cable Select
2 4 6
1 3 5
Model No. of cylinders
MPA3017AT 3,390
MPA3026AT 4,092
MPA3035AT 4,092
MPA3043AT 4,092
MPA3052AT 4,092
1 3 5
Slave DeviceMaster Device
C141-E034-02EN3 - 12
1 3 5
Cable Select
CHAPTER 4 THEORY OF DEVICE OPERATION
4.1 Outline
4.2 Subassemblies
4.3 Circuit Configuration
4.4 Power-on sequence
4.5 Self-calibration
4.6 Read/Write circuit
4.7 Servo Control
This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of
the disk drive, each sequence, servo control, and electrical circuit blocks.
4.1 Outline
This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the
disk drive. Second part (Sections 4.3 thro ugh 4.7) explains a servo information r ecorded in the
disk drive and drive control method.
4.2 Subassemblies
The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).
The DE contains all movable parts in the disk drive, including the disk, spindle, actuator,
read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.5.
The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details,
see Sections 4.3.
4.2.1 Disk
The DE contains the disks with an outer diameter of 95 mm. The MPA3017AT has 1 disk, the
MPA3026AT/MPA3035AT have 2 disks. MPA3043AT/MPA3052AT have 3 disks.
The head contacts the disk each time the disk rotation stops; the life of the disk is 40,000 contacts
or more.
Servo data is recorded on each cylinder (total 60). Servo data written at factory is read out by the
read/write head. For servo data, see Section 4.7.
C141-E034-02EN 4 - 1
4.2.2 Head
Figure 4.1 shows the read/write head structures. The MPA3017AT has 2 read/write heads, the
MPA3026AT has 3, MPA3035AT has 4, MPA3043AT has 5, and MPA3052AT has 6. These
heads are raised from the disk surface as the spindle motor approaches the rated rotation speed.
MPA3017 Model
Spindle
1
0
MPA3026AT Model
Spindle
2
1
0
MPA3043AT Model
Spindle
Actuator
Actuator
Actuator
MPA3035AT Model
Spindle
3
2
1
0
MPA3052AT Model
Spindle
Actuator
Actuator
5
4
3
2
1
0
4
3
2
1
0
Figure 4.1 Head structure
C141-E034-02EN4 - 2
4.2.3 Spindle
The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is
activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±0.5%.
The spindle is controlled with detecting a PHASE signal generated by counter electromotive
voltage of the spindle motor at starting. After that, the rotational speed is kept with detecting a
servo information.
4.2.4 Actuator
The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head
carriage along the inner or outer edge of the disk. The head carriage position is controlled by
feeding back the difference of the target position that is detected and reprod uced from the servo
information read by the read/write head.
4.2.5 Air filter
There are two types of air filters: a breather filter and a circulation filter.
The breather filter makes an air in and out of the DE to prevent unnecessary pr essure around the
spindle when the disk starts or stops rotating. When disk drives are transported under conditions
where the air pressure changes a lot, filtered air is circulated in the DE.
The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air
continuously through the circulatio n filter thr ough an enc losed loop air cycle system operated by a
blower on the rotating disk.
C141-E034-02EN 4 - 3
4.3 Circuit Configuration
Figure 4.2 shows the disk drive circuit configuration.
(1) Read/write circuit
The read/write circuit consists of two LSIs; read/write preamplifier (PreAMP) and read channel
(RDC).
The PreAMP consists of the write current switch circuit, that flows the write current to the head
coil, and the voltage amplifier circuit, that amplitudes the read output from the head.
The RDC is the read demodulation circuit using the partial response class 4 (PR4), and contains
the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, and
data separator circuits. The RDC also contains the 8/9 group coded recording (GCR) encoder and
decoder and servo demodulation circuit.
(2) Servo circuit
The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the
servo information recorded on the data surface. The servo information is an analog signal
converted to digital for processing by a MPU and then reconverted to an analog signal for control
of the voice coil motor.
(3) Spindle motor driver circuit
The circuit measures the interval of a PHASE signal generated by counter-electromotive voltage of
a motor, or servo mark at the MPU and controls the motor speed comparing target speed.
(4) Controller circuit
Major functions are listed below.
• Data buffer (128 KB) management
• ATA interface control and data transfer control
• Sector format control
• Defect management
• ECC control
• Error recovery and self-diagnosis
C141-E034-02EN4 - 4
C141-E034-02EN 4 - 5
Figure 4.2 MPA30xxAT Block diagram
4.4 Power-on Sequence
Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described
below.
a) After the power is turned on, the disk drive executes the MPU bus test, internal register
read/write test, and work RAM read/write test. When the self-diagnosis terminates
successfully, the disk drive starts the spindle motor.
b) The disk drive executes self-diagnosis (data buffer read/write test) after enabling response to
the ATA bus.
c) After confirming that the spindle motor has reached rated speed, the disk drive releases the
heads from the actuator magnet lock mechanism by applying current to the VCM. This
unlocks the heads which are parked at the inner circumference of the disks.
d) The disk drive positions the heads onto the SA area and reads out the system information.
e) The disk drive executes self-seek-calibration. This collects data for VCM torque and
mechanical external forces applied to the actuator, and updates the calibrating value.
f) The drive becomes ready. The host can issue commands.
C141-E034-02EN4 - 6
StartPower on
Self-diagnosis 1
a)
• MPU bus test
• Inner register
write/read test
• Work RAM write/read
test
The spindle motor starts.
Self-diagnosis 2
b)
• Data buffer write/read
test
Confirming spindle motor
c)
speed
Release heads from
actuator lock
d)
Initial on-track and read
out of system information
Execute self-calibration
e)
Drive ready state
f)
(command waiting state)
End
Figure 4.3 Power-on operation sequence
C141-E034-02EN 4 - 7
4.5 Self-calibration
The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical
external forces on the actuator, and VCM torque. This enables precise seek and read/write
operations.
4.5.1 Self-calibration contents
(1) Sensing and compensating for external forces
The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution.
The torque vary with the disk drive and the cylinder where the head is positioned. To execute
stable fast seek operations, external forces are occasionally sensed.
The firmware of the drive measures and stores the force (value of the actuator motor drive current)
that balances the torque for stopping head stably. This includes the current offset in the power
amplifier circuit and DAC system.
The forces are compensated by adding the measured value to the specified current value to the
power amplifier. This makes the stable servo control.
To compensate torque varying by the cylinder, the disk is divided into 12 areas from the innermost
to the outermost circumference and the compensating value is measured at the measuring cylinder
on each area at factory calibration. The measured values are stored in the SA cylinder. In the selfcalibration, the compensating value is updated using the value in the SA cylinder.
(2) Compensating open loop gain
Torque constant value of the VCM has a dispersion for each drive, and varies depending on the
cylinder that the head is positioned. To realize the high speed seek operation, the value that
compensates torque constant value change and loop gain change of the whole servo system due to
temperature change is measured and stored.
For sensing, the firmware mixes the disturbance signal to the position signal at the state that the
head is positioned to any cylinder. The firmware calculates the loop gain from the position signal
and stores the compensation value against to the target gain as ratio.
For compensating, the direction current value to the power amplifier is multiplied by the
compensation value. By this compensation, loop gain becomes constant value and the stable servo
control is realized.
To compensate torque constant value change depending on cylinder, whole cylinders from most
inner to most outer cylinder are divided into 12 partitions at calibration in the factory, and the
compensation data is measured for representative cylinder of each partition. This measured value
is stored in the SA area. The compensation value at self-calibration is calculated using the value in
the SA area.
C141-E034-02EN4 - 8
4.5.2 Execution timing of self-calibration
Self-calibration is executed when:
• The power is turned on.
• The disk drive receives the RECALIBRATE command from the host.
• The self-calibration execution timechart of the disk drive specifies self-calibration.
The disk drive performs self-calibration according to the timechart based on the time elapsed from
power-on. The timechart is shown in Table 4.1. After power-on, self-calibration is performed
about every five or ten minutes for the first 60 minutes or six RECALIBRATE command
executions, and about every 30 minutes after that.
Table 4.1 Self-calibration execution timechart
Time elapsed Time elapsed (accumulated)
1 At power-on Initial calibration
2 About 5 minutes About 5 minutes
3 About 5 minutes About 10 minutes
4 About 10 minutes About 20 minutes
5 About 10 minutes About 30 minutes
6 About 30 minutes About 60 minutes
7
.
.
.
9
4.5.3 Command processing during self-calibration
If the disk drive receives a command execution request from the host while executing selfcalibration according to the timechart, the disk drive terminates self-calibration and starts
executing the command precedingly. In other words, if a disk read or write service is necessary,
the disk drive positions the head to the track requested by the host, reads or writes data, and
restarts calibration.
This enables the host to execute the command without waiting for a long time, even when the disk
drive is performing self-calibration. The command execution wait time is about maximum 100 ms.
Every about 30 minutes
C141-E034-02EN 4 - 9
4.6 Read/write Circuit
The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read
circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of
the read/write circuit.
4.6.1 Read/write preamplifier (PreAMP)
One PreAMP is mounted on the FPC. The PreAMP consists of an 6-channel read preamplifier and
a write current switch and senses a write error. Each channel is connected to each data head. T he
head IC switches the heads by the chip select signals (*CS) and the head select signals (HS0, HS1,
HS2). The IC generates a write error sense signal (WUS) when a write error occurs due to head
short-circuit or head disconnection.
4.6.2 Write circuit
The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to
the encoder circuit in the RDC with synchronizing with the write clock. The NRZ write data is
converted from 8-bit data to 9-bit data by the encoder circuit then sent to the PreAMP, and the data
is written onto the media.
(1) 8/9 GCR
The disk drive converts data using the 8/9 (0, 4, 4) group coded recording (GCR) algorithm. This
code format is 0 to 4 code bit "0"s are placed between "1"s.
(2) Write precompensation
Write precompensation compensates, during a write process, for write non-linearity generated at
reading. Table 4.2 shows the write precompensation algorithm.
Table 4.2 Write precompensation algorithm
Bit Bit Bit Compensation
n – 1 n n + 1 Bit n
0 1 1 None
1 1 0 Late
1 1 0 Late
Late: Bit is time shifted (delayed) from its nominal time position towards the bit
n+1 time position.
C141-E034-02EN4 - 10
C141-E034-02EN 4 - 11
Figure 4.4 Read/write circuit block diagram
4.6.3 Read circuit
The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit.
Then the output is converted into the sampled read data pulse by the programmable filter circuit
and the adaptive equalizer circuit. This clock signal is converted into the NRZ data by the 8/9
GCR decoder circuit based on the read data maximum-likelihood-detected by the Viterbi detection
circuit, then is sent to the HDC.
(1) AGC circuit
The AGC circuit automatically regulates the output amplitude to a constant value even when the
input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even
when the head output fluctuates due to the head characteristics or outer/inner head positions.
(2) Programmable filter
The programmable filter circuit has a low-pass filter function that eliminates unnecessary high
frequency noise component and a high frequency boost-up function that equalizes the waveform of
the read signal.
Cut-off frequency of the low-pass filter and boost-up gain are controlled from each DAC circuit in
read channel by an instruction of the serial data signal from MPU (M1). The MPU optimizes the
cut-off frequency and boost-up gain according to the transfer frequency of each zone.
Figure 4.5 shows the frequency characteristic sample of the programmable filter.
Figure 4.5 Frequency characteristic of programmable filter
(3) Adaptive equalizer circuit
This circuit is 3-tap sampled analog transversal filter circuit that cosine-equalizes the head read
signal to the partial response class 4 (PR4) waveform.
C141-E034-02EN4 - 12
Figure 4.6 PR4 signal transfer
C141-E034-02EN 4 - 13
(4) Viterbi detection circuit
The sample hold waveform output from the adaptive equalizer circuit is sent to the Viterbi
detection circuit. The Viterbi detection circuit demodulates data according to the survivor path
sequence.
(5) Data separator circuit
The data separator circuit generates clocks in synchronization with the output of the adaptive
equalizer circuit. To write data, the VFO circuit generates clocks in synchronization with the clock
signals from a synthesizer.
(6) 8/9 GCR decoder
This circuit converts the 9-bit read data into the 8-bit NRZ data.
4.6.4 Time base generator circuit
The drive uses constant density recording to increase total capacity. This is different from the
conventional method of recording data with a fixed data transfer rate at all data area. In the
constant density recording method, data area is divided into zones by radius and the data transfer
rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The
drive divides data area into 15 zones to set the data transfer rate. Table 4.3 describes the data
transfer rate and recording density (BPI) of each zone.
C141-E034-02EN4 - 14
Table 4.3 Write clock frequency and transfer rate of each zone
Zone 0 1 2 34567
Cylinder 0
to
622
Transfer rate
[MB/s]
Zone 8 9 10 11 12 13 14
Cylinder 4809
Transfer rate
[MB/s]
The MPU transfers the data transfer rate setup data (SDATA/SCLK) to the RDC that includes the
time base generator circuit to change the data transfer rate.
4.7 Servo Control
The actuator motor and the spindle motor are submitted to servo control. The actuator motor is
controlled for moving and positioning the head to the track containing the desired data. To turn
the disk at a constant velocity, the actuator motor is controlled according to the servo data that is
written on the data side beforehand.
14.964 14.111 13.787 13.473 13.155 12.512 12.258 11.702
to
5119
11.443 10.590 10.142 9.623 8.986 8.451 8.019
623
to
1788
5120
to
6107
1789
to
2217
6108
to
6613
2218
to
2618
6614
to
7194
2619
to
3030
7195
to
7891
3031
to
3827
7892
to
8460
3828
to
4141
8461
to
8712
4142
to
4808
C141-E034-02EN 4 - 15
4.7.1 Servo control circuit
Figure 4.7 is the block diagram of the servo control circuit. The following describes the functions
of the blocks:
(1)
(2) (3) (4)
Servo
Head
burst
capture
Position Sense
CSR: Current Sense Resistor
VCM: Voice Coil Motor
Figure 4.7 Block diagram of servo control circuit
(1) Microprocessor unit (MPU)
MPU
DSP
unit
DACADC
Spindle
motor
control
SVC
(5)
P.
Amp.
(7)(6)
Driver
VCM current
CSR
VCM
Spindle
motor
The MPU includes DSP unit, etc., and the MPU starts the spindle motor, moves the heads to the
reference cylinders, seeks the specified cylinder, and executes calibration according to the internal
operations of the MPU.
The major internal operations are listed below.
a. Spindle motor start
Starts the spindle motor and accelerates it to normal speed when power is applied.
b. Move head to reference cylinder
Drives the VCM to position the head at the any cylinder in the data area. The logical initial
cylinder is at the outermost circumference (cylinder 0).
C141-E034-02EN4 - 16
c. Seek to specified cylinder
Drives the VCM to position the head to the specified cylinder.
d. Calibration
Senses and stores the thermal offset between heads and the mechanical forces on the actuator,
and stores the calibration value.
Figure 4.8 Physical sector servo configuration on disk surface
C141-E034-02EN 4 - 17
(2) Servo burst capture circuit
The four servo signals can be synchronously detected by the STROB signal, full-wave rectified
integrated.
(3) A/D converter (ADC)
The A/D converter (ADC) receives the servo signals are integrated, converts them to digital, and
transfers the digital signal to the DSP unit.
(4) D/A converter (DAC)
The D/A converter (DAC) converts the VCM drive current value (digital value) calculated by the
DSP unit into analog values and transfers them to the power amplifier.
(5) Power amplifier
The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.
(6) Spindle motor control circuit
The spindle motor control circuit controls the sensor-less spindle motor. This circuit detects
number of revolution of the motor by the interrupt generated periodically, compares with the target
revolution speed, then flows the current into the motor coil according to the differentiation
(aberration).
(7) Driver circuit
The driver circuit is a power amplitude circuit that receives signals from the spindle motor control
circuit and feeds currents to the spindle motor.
(8) VCM current sense resistor (CSR)
This resistor controls current at the power amplifier by converting the VCM current into voltage
and feeding back.
C141-E034-02EN4 - 18
4.7.2 Data-surface servo format
Figure 4.8 describes the physical layout of the servo frame. The three areas indicated by (1) to (3)
in Figure 4.8 are described below.
(1) Inner guard band
The head is in contact with the disk in this space when the spindle starts turning or stops, and the
rotational speed of the spindle can be controlled on this cylinder area for head moving.
(2) Data area
This area is used as the user data area SA area.
(3) Outer guard band
This area is located at outer position of the user data area, and the rotational speed of the spindle
can be controlled on this cylinder area for head moving.
4.7.3 Servo frame format
As the servo information, the drive uses the two-phase servo generated from the gray code and
servo A to D. This servo information is used for positioning operatio n of radius direction and
position detection of circumstance direction.
The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, servo A to D
and PAD. Figure 4.9 shows the servo frame format.
Write/read
recovery
Servo
mark
Gray code
Servo
A
Servo
B
Servo
C
Servo
D
PAD
1.53 µs2.0 µs2.0 µs2.0 µs2.09 µs3.20 µs0.56 µs8.0 µs
Figure 4.9 Servo frame format
C141-E034-02EN 4 - 19
(1) Write/read recovery
This area is used to absorb the write/read transient and to stabilize the AGC.
(2) Servo mark
This area generates a timing for demodulating the gray code and position-demodulating the servo
A to D by detecting the servo mark.
(3) Gray code (including index bit)
This area is used as cylinder address. The data in this area is converted into the binary data by the
gray code demodulation circuit.
(4) Servo A, servo B, servo C, servo D
This area is used as position signals between tracks, and the IDD control at on-track so that servo
A level equals to servo B level.
(5) PAD
This area is used as a gap between servo and data.
4.7.4 Actuator motor control
The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data
surface. The MPU fetches the position sense data on the servo frame at a constant interval of
sampling time, executes calculation, and updates the VCM drive current.
The servo control of the actuator includes the operation to move the head to the reference cylinder,
the seek operation to move the head to the target cylinder to read or write data, and the trackfollowing operation to position the head onto the target track.
(1) Operation to move the head to the reference cylinder
The MPU moves the head to the reference cylinder when the power is turned. The reference
cylinder is in the data area.
When power is applied the heads are moved fr om the inner circumference shunt zone to the normal
servo data zone in the following sequence:
a) Micro current is fed to the VCM to press the head against the inner circumference.
b) A current is fed to the VCM to move the head toward the outer circumference.
c) When the servo mark is detected the head is moved slowly toward the outer circumference at a
constant speed.
C141-E034-02EN4 - 20
d) If the head is stopped at the reference cylinder from there. Track following control starts.
(2) Seek operation
Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk.
If a read or instruction is issued, the MPU seeks the desired track.
The MPU feeds the VCM current via the D/A converter and power amplifier to move the head.
The MPU calculates the difference (speed error) between the specified target position and the
current position for each sampling timing during head moving. The MPU then feeds the VCM
drive current by setting the calculated result into the D/A converter. The calculation is digitally
executed by the firmware. When the head arrives at the target cylinder, the track is followed.
(3) Track following operation
Except during head movement to the reference cylinder and seek operation under the spindle
rotates in steady speed, the MPU does track following control. To position the head at the center
of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM
drive current is determined by filtering the position difference between the target position and the
position clarified by the detected position sense data. T he filtering includes servo compensation.
These are digitally controlled by the firmware.
4.7.5 Spindle motor control
Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3-phase full/halfwave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The
firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by
sending several signals from the MPU to the SVC. There are three modes for the spindle control;
start mode, acceleration mode, and stable rotation mode.
(1) Start mode
When power is supplied, the spindle motor is started in the following sequence:
a) After the power is turned on, the MPU sends a signal to the SVC to charge the change pump
capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.
b) When the charge pump capacitor is cha rged enough, the MP U sets the SVC to the motor start
mode. Then, a current (approx. 1.3 A) flows into the spindle motor.
c) The SVC generates a phase switching signal by itself, and changes the phase of the current
flowed in the motor in the order of (V-phase to U-phase), (W-phase to U-phase), (W-phase to
V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that,
repeating this order).
d) During phase switching, the spindle motor starts rotating in low speed, and generates a counter
electromotive force. The SVC detects this counter electromotive force and reports to the MPU
using a PHASE signal for speed detection.
C141-E034-02EN 4 - 21
e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a specific period,
the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the
SVC enters the acceleration mode.
(2) Acceleration mode
In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a
phase switching by itself based on the counter electromotive force. Then, rotation of the spindle
motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the
PHASE signal from the SVC, and accelerates till the rotational speed reaches 5,400 rpm. When
the rotational speed reaches 5,400 rpm, the SVC enters the stable rotation mode.
(3) Stable rotation mode
The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal
from the SVC. The MPU takes a difference between the current time and a time for one revolution
at 5,400 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to
5,400 rpm by charging or discharging the charge pump for the different time. For example, when
the actual rotational speed is 5,600 rpm, the time for one revolution is 10.714 ms. And, the time
for one revolution at 5,400 rpm is 11.111 ms. Therefore, the MPU discharges the charge pump for
0.397 ms × k (k: constant value). This makes the flowed current into the motor lower and the
rotational speed down. When the actual rotational speed is later than 5,400 rpm, the MPU charges
the pump the other way. This control (charging/discharging) is performed every 1/6 revolution.
C141-E034-02EN4 - 22
CHAPTER 5 INTERFACE
5.1 Physical Interface
5.2 Logical Interface
5.3 Host Commands
5.4 Command Protocol
5.5 Ultra DMA Feature Set
5.6 Timing
C141-E034-02EN 5 - 1
5.1 Physical Interface
5.1.1 Interface signals
Figure 5.1 shows the interface signals.
DATA 0-15: DATA BUS
DMACK-: DMA ACKNOWLEDGE
DMARQ: DMA REQUEST
IOW-: I/O WRITE
IOR- : I/O READ
INTRQ : INTERRUPT REQUEST
IOCS16-: IOCS 16
PDIAG- : PASSED DIAGNOST I C
IORDY : I/O CHANNEL READY
DASP- : DEVICE AC T I VE / DEVICE 1 PRESENT
IDDHost
DA 0-2: DEVICE ADDRESS
CS0- : CHIP SELECT 0
CS1- : CHIP SELECT 1
RESET-: RESET
CSEL : CABLE SELECT
GND: GROUND
Figure 5.1 Interface signals
C141-E034-02EN5 - 2
5.1.2 Signal assignment on the connector
Table 5.1 shows the signal assignment on the interface connector.
Table 5.1 Signal assignment on the interface connector
Pin No. Signal Pin No. Signal
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
[signal] [I/O] [Description]
RESET– I Reset signal from the host. This signal is low active and is asserted
RESET–
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
GND
DMARQ
IOW–, STOP
IOR–, HDMARDY–, HSTROBE
IORDY, DDMARDY–, DSTROBE
DMACK–
INTRQ
DA1
DA0
CS0–
DASP–
for a minimum of 25 µs during power on.
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
GND
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
(KEY)
GND
GND
GND
CSEL
GND
IOCS16–
PDIAG–
DA2
CS1–
GND
DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device.
These signals are used for data transfer
IOW–, STOP I IOW– is the strobe signal asserted by the host to write device
registers or the data port.
IOW– shall be negated by the host prior to initiation of an Ultra
DMA burst. STOP shall be negated by the host before data is
transferred in an Ultra DMA burst. Assertion of STOP by the host
during an Ultra DMA burst signals the termination of the Ultra DMA
burst.
C141-E034-02EN 5 - 3
[signal] [I/O] [Description]
IOR–,
HDMARDY–,
HSTROBE
INTRQ O Interrupt signal to the host.
IOCS16– O This sig nal i n d icates 1 6 - b it data b us is add r ess e d i n PIO dat a t r a nsf e r.
I IOR– is the strobe signal asserted by the host to read device registers
or the data port.
HDMARDY– is a flow control signal for Ultra DMA data in bursts.
This signal is asserted by the host to indicate to the device that the
host is ready to receive Ultra DMA data in bursts.
The host may negate HDMARDY- to pause an Ultra DMA data in
burst.
HSTROBE is the data out strobe signal from the host for an Ultra
DMA data out burst. Both the rising and falling edge of HSTROBE
latch the data from DATA 0-15 into the device. The host may stop
generating HSTROBE edges to pause an Ultra DMA data out burst.
This signal is negated in the following cases:
– assertion of RESET– signal
– Reset by SRST of the Device Control register
– Write to the command register by the host
– Read of the status register by the host
– Completion of sector data transfer
(without reading the Status register)
When the device is not selected or interrupt is disabled
This signal is an open collector output.
– When IOCS16- is not asserted:
8 bit data is transferred through DATA0 to DATA7 signals.
– When IOCS16- is asserted:
16 bit data is transferred through DATA0 to DATA15 signals.
CS0– I Chip select signal decoded from the host address bus. This signal is
used by the host to select the command block registers.
CS1– I Chip select signal decoded from the host address bus. This signal is
used by the host to select the control block registers.
DA 0-2 I Binary decoded address signals asserted by the host to access task
file registers.
KEY – Key pin for prevention of erroneous connector insertion
PIDAG– I/O This signal is an input mode for the master device and an output
mode for the slave device in a daisy chain configuration. This signal
indicates that the slave device has been completed self diagnostics.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.
DASP– I/O This is a time-multiplexed signal that indicates that the device is
active and a slave device is present.
This signal is pulled up to +5 V through 10 kΩ resistor at each device.
C141-E034-02EN5 - 4
[signal] [I/O] [Description]
IORDY,
DDMARDY–,
DSTROBE
CSEL I This signal to configure the device as a master or a slave device.
DMACK– I The host system asserts this signal as a response that the host system
DMARQ O This signal is used for DMA transfer between the host system and the
O This signal is negated to extend the host transfer cycle of any host
register access (Read or Write) when the device is not ready to
respond to a data transfer request.
DDMARDY– is a flow control signal for Ultra DMA data out bursts.
This signal is asserted by the device to indicate to the host that the
device is ready to receive Ultra DMA data out bursts. The device
may negate DDMARDY– to pause an Ultra DMA data out burst.
DSTROBE is the data in strobe signal from the device for an Ultra
DMA data in burst. Both the rising and falling edge of DSTROBE
latch the data from DATA 0-15 into the host. The device may stop
generating DSTROBE edges to pause an Ultra DMA data in burst.
When CSEL signal is grounded, the IDD is a master device.
When CSEL signal is open, the IDD is a slave device.
This signal is pulled up with 240 kΩ resistor.
receive data or to indicate that data is valid.
device. The device asserts this signal when the device completes the
preparation of DMA data transfer to the host system (at reading) or
from the host system (at writing).
The direction of data transfer is controlled by the IOR- and IOW-
signals. In other word, the device negates the DMARQ signal after
the host system asserts the DMACK– signal. When there is another
data to be transferred, the device asserts the DMARQ signal again.
When the DMA data transfer is performed, IOCW16–, CS0– and
CS1- signals are not asserted. The DMA data transfer is a 16-bit data
transfer.
GND – Grounded
Note:
"I" indicates input signal from the host to the device.
"O" indicates output signal from the device to the host.
"I/O" indicates common output or bi-directional signal between the host and the device.
C141-E034-02EN 5 - 5
5.2 Logical Interface
The device can operate for command execution in either address-specified mode; cylinder-headsector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information
indicates whether the device supports the LBA mode. When the host system specifies the LBA
mode by setting bit 6 in the Device/Head register to 1, HS3 to HS0 bits of the Device/Head
register indicates the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder
Low, and Sector Number registers are LBA bits.
The sector No. under the LBA mode proceeds in the ascending order with the start point of LBA0
(defined as follows).
LBA0 = [Cylinder 0, Head 0, Sector 1]
Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE
PARAMETER command, the sector LBA address is not changed.
LBA = [((Cylinder No.) × (Number of head) + (Head No.)) × (Number of sector/track)]
+ (Sector No.) – 1
5.2.1 I/O registers
Communication between the host system and the device is done through input-output (I/O)
registers of the device.
These I/O registers can be selected by the coded signals, CS0–, CS1–, and DA0 to DA2 from the
host system. Table 5.2. shows the coding address and the function of I/O registers.
C141-E034-02EN5 - 6
Table 5.2 I/O registers
I/O registers
DA0DA1DA2CS1–CS0–
Read operation Write operation
Command block registers
10000Data Data X'1F0'
10001Error Register Features X'1F1'
10010Sector Count Sector Count X'1F2'
10011Sector Number Sector Number X'1F3'
10100Cylinder Low Cylinder Low X'1F4'
10101Cylinder High Cylinder High X'1F5'
10110Device/Head Device/Head X'1F6'
10111Status Command X'1F7'
1 1 X X X (Invalid) (Invalid) —
Control block registers
01110Alternate Status Device Control X'3F6'
01111— — X'3F7'
Host I/O
address
Notes:
1. The Data register for read or write operation can be accessed by 16 bit data bus (DATA0
to DATA15).
2. The registers for read or write operation other than the Data registers can be accessed by
8 bit data bus (DATA0 to DATA7).
3. When reading the Drive Address register, bit 7 is high-impedance state.
4. The LBA mode is specified, the Device/Head, Cylinder High, Cylinder Low, and Sector
Number registers indicate LBA bits 27 to 24, 23 to 16, 15 to 8, and 7 to 0.
C141-E034-02EN 5 - 7
5.2.2 Command block registers
(1) Data register (X'1F0')
The Data register is a 16-bit register for data block transfer between the device and the host
system. Data transfer mode is PIO or LBA mode.
(2) Error register (X'1F1')
The Error register indicates the status of the command executed by the device. The contents of
this register are valid when the ERR bit of the Status register is 1.
This register contains a diagnostic code after power is turned on, a reset , or the EXECUTIVE
DEVICE DIAGNOSTIC command is executed.
[Status at the completion of command execution other than diagnostic command]
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICRC UNC X IDNF X ABRT TK0NF AMNF
X: Unused
- Bit 7: Interface CRC error (ICRC). This bit indicates that an interface CRC error has
occurred during an Ultra DMA data transfer. The content of this bit is not applicable
for Multiword DMA transfers.
- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error
has been encountered.
- Bit 5: Unused
- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad sector,
uncorrectable error and SB not found, and Aborted Command.
- Bit 3: Unused
- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was
aborted due to a device status error (e.g. Not Ready, Write Fault) or the command
code was invalid.
- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during
RECALIBRATE command execution.
- Bit 0: Address Mark Not Found. This bit indicates that an SB not found error has been
encountered.
C141-E034-02EN5 - 8
[Diagnostic code]
X'01': No Error Detected.
X'02': HDC Register Compare Error
X'03': Data Buffer Compare Error.
X'05': ROM Sum Check Error.
X'80': Device 1 (slave device) Failed.
Error register of the master device is valid under two devices (master and slave)
configuration. If the slave device fails, the master device posts X’80’ OR (the diagnostic
code) with its own status (X'01' to X'05').
However, when the host system selects the slave device, the diagnostic code of the slave
device is posted.
(3) Features register (X'1F1')
The Features register provides specific feature to a command. For instance, it is used with SET
FEATURES command to enable or disable caching.
(4) Sector Count register (X'1F2')
The Sector Count register indicates the number of sectors of data to be transferred in a read or
write operation between the host system and the device. When the value in this register is X'00',
the sector count is 256.
When this register indicates X'00' at the completion of the command execution, this indicates that
the command is completed successfully. If the command is not completed successfully, this
register indicates the number of sectors to be transferred to complete the request from the host
system. That is, this register indicates the number of remaining sectors that the data has not been
transferred due to the error.
The contents of this register has other definition for the following commands; INITIALIZE
DEVICE PARAMETERS, FORMAT TRACK, SET FEATURES, IDLE, STANDBY and SET
MULTIPLE MODE.
(5) Sector Number register (X'1F3')
The contents of this register indicates the starting sector number for the subsequent command.
The sector number should be between X'01' and [the number of sectors per track defined by
INITIALIZE DEVICE PARAMETERS command.
Under the LBA mode, this register indicates LBA bits 7 to 0.
C141-E034-02EN 5 - 9
(6) Cylinder Low register (X'1F4')
The contents of this register indicates low-order 8 bits of the starting cylinder address for any diskaccess.
At the end of a command, the contents of this register are updated to the current cylinder number.
Under the LBA mode, this register indicates LBA bits 15 to 8.
(7) Cylinder High register (X'1F5')
The contents of this register indicates high-order 8 bits of the disk-access start cylinder address.
At the end of a command, the contents of this register are updated to the current cylinder number.
The high-order 8 bits of the cylinder address are set to the Cylinder High register.
Under the LBA mode, this register indicates LBA bits 23 to 16.
(8) Device/Head register (X'1F6')
The contents of this register indicate the device and the head number.
When executing INITIALIZE DEVICE PARAMETERS command, the contents of this register
defines "the number of heads minus 1".
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X L X DEV HS3 HS2 HS1 HS0
- Bit 7: Unused
- Bit 6: L. 0 for CHS mode and 1 for LBA mode.
- Bit 5: Unused
- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.
3
- Bit 3: HS3 CHS mode head address 3 (2
- Bit 2: HS2 CHS mode head address 3 (2
- Bit 1: HS1 CHS mode head address 3 (2
- Bit 0: HS0 CHS mode head address 3 (2
). LBA bit 27.
2
). LBA bit 26.
1
). LBA bit 25.
0
). LBA bit 24.
C141-E034-02EN5 - 10
(9) Status register (X'1F7')
The contents of this register indicate the status of the device. The contents of this register are
updated at the completion of each command. When the BSY bit is cleared, other bits in this
register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are
invalid. When the host system reads this register while an interrupt is pending, it is considered to
be the Interrup t Acknowled ge (the host system acknowledge s the inter rup t). Any pend ing inter rup t
is cleared (negating INTRQ signal) whenever this register is read.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ CORR 0 ERR
- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then
this bit is cleared when the command is completed. However, even if a command is
being executed, this bit is 0 while data transfer is being requested (DRQ bit =
1).When BSY bit is 1, the host system should not write the command block registers.
If the host system reads any command block register when BSY bit is 1, the contents
of the Status register are posted. This bit is set by the device under following
conditions:
(a) Within 400 ns after RESET- is negated or SRST is set in the Device Control
register, the BSY bit is set. the BSY bit is cleared, when the reset process is
completed.
The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.
(b) Within 400 ns from the host system starts writing to the Command register.
(c) Within 5 µs following transfer of 512 bytes data during execution of the READ
SECTOR(S), WRITE SECTOR(S), FORMAT TRACK, or WRITE BUFFER
command.
Within 5 µs following transfer of 512 bytes of data and the appropriate number
of ECC bytes during execution of READ LONG or WRITE LONG command.
- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to
a command.
The IDD checks its status when it receives a command. If an error is detected (not
ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is
cleared until the rotational speed of the spindle motor reaches the steady speed.
- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault)
condition has been detected.
If a write fault is detected during command execution, this bit is latched and retained
until the device accepts the next command or reset.
- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are
positioned over a track.
In the IDD, this bit is always set to 1 after the spin-up control is completed.
C141-E034-02EN 5 - 11
- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of
word unit or byte unit between the host system and the device.
- Bit 1: Always 0.
- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous
command was being executed. The Error register indicates the additional
information of the cause for the error.
(10) Command register (X'1F7')
The Command register contains a command code being sent to the device. After this register is
written, the command execution starts immediately.
Table 5.3 lists the executable commands and their command codes. This table also lists the
necessary parameters for each command which are written to certain registers before the Command
register is written.
C141-E034-02EN5 - 12
5.2.3 Control block registers
(1) Alternate Status register (X'3F6')
The Alternate Status register contains the same information as the Status register of the command
block register.
The only difference from the Status register is that a read of this register does not imply Interrupt
Acknowledge and INTRQ signal is not reset.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BSY DRDY DF DSC DRQ CORR 0 ERR
(2) Device Control register (X'3F6')
The Device Control register contains device interrupt and software reset.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
X X X X X SRST nIEN 0
- Bit 2: SRST is the host software reset bit. When this bit is set, the device is held reset state.
When two device are daisy chained on the interface, setting this bit resets both device
simultaneously.
The slave device is not required to execute the DASP- handshake.
- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this
bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled
through a tri-state buffer. W hen this b it is 1 o r the d evice is no t selec ted , the I NT RQ
signal is in the high-impedance state.
5.3 Host Commands
The host system issues a command to the device by writing necessary parameters in related
registers in the command block and writing a command code in the Command register.
The device can accept the command when the BSY bit is 0 (the device is not in the busy status).
The host system can halt the uncompleted command execution only at execution of hardware or
software reset.
When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and the host
system writes to the command register, the correct device operation is not guaranteed.
C141-E034-02EN 5 - 13
5.3.1 Command code and parameters
Table 5.3 lists the supported commands, command code and the registers that needed parameters
are written.
Table 5.3 Command code and parameters (1 of 2)
Command name
76543210FRSCSNCYDH
READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y
READ MULTIPLE 1 1 0 0 0 1 0 0 N Y Y Y Y
READ DMA 1 1 0 0 1 0 0 R N Y Y Y Y
READ VERIFY SECTOR(S) 0 1 0 0 0 0 0 R N Y Y Y Y
WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y
WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y
WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y
WRITE SECTOR(S) 0 0 1 1 0 0 0 R N Y Y Y Y
RECALIBRATE 0 0 0 1 X X X X N N N N D
SEEK 0 1 1 1 X X X X N N Y Y Y
INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y
IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D
IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D
SET FEATURES 1 1 1 0 1 1 1 1 Y N* N N D
Command code (Bit) Parameters used
SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D
EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D*
FORMAT TRACK 0 1 0 1 0 0 0 0 N N Y* Y Y
READ LONG 0 0 1 0 0 0 1 R N Y Y Y Y
WRITE LONG 0 0 1 1 0 0 1 R N Y Y Y Y
READ BUFFER 1 1 1 0 0 1 0 0 N N N N D
WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D
IDLE 110101100010111
IDLE IMMEDIATE 110101100010001
STANDBY 110101100010110
C141-E034-02EN5 - 14
NYNND
1
NNNND
1
NYNND
0
Table 5.3 Command code and parameters (2 of 2)
Command name
76543210FRSCSNCYDH
STANDBY IMMEDIATE 110101100010000
SLEEP 110101101001011
CHECK POWER MODE 110101101001000
SMART 1 0 1 1 0 0 0 0 Y Y Y Y D
Notes:
FR : Features Register CY: Cylinder Registers
SC : Sector Count Register DH : Drive/Head Register
SN : Sector Number Register
R: Retry at error
1 = Without retry 0 = with retry
Y: Necessary to set parameters
Y*: Necessary to set parameters under the LBA mode.
Command code (Bit) Parameters used
NNNND
0
NNNND
0
NNNND
1
N: Necessary to set parameters (The parameter is ignored if it is set.)
N*: May set parameters
D: The device parameter is valid, and the head parameter is ignored.
D*: The command is addressed to the master device, but both the master device and the slave
device execute it.
X: Do not care
C141-E034-02EN 5 - 15
5.3.2 Command descriptions
The contents of the I/O registers to be necessary for issuing a command and the example indication
of the I/O registers at command completion are shown as following in this subsection.
Example: READ SECTOR(S) WITH RETRY
At command issuance (I/O registers setting contents)
Bit 76543210
1F7H(CM) 00100000
1F6H(DH)
1F5H(CH) Start cylinder address [MSB] / LBA
1F4H(CL) Start cylinder address [LSB] / LBA
1F3H(SN) Start sector No. / LBA [LSB]
1F2H(SC) Transfer sector count
1F1H(FR) xx
At command completion (I/O registers contents to be read)
Bit 76543210
1F7H(ST) Error information
1F6H(DH)
1F5H(CH) Start cylinder address [MSB] / LBA
1F4H(CL) Start cylinder address [LSB] / LBA
1F3H(SN) Start sector No. / LBA [LSB]
1F2H(SC) X‘00’
L
×
L
×
DV Head No. / LBA [MSB]
×
DV Head No. / LBA [MSB]
×
1F1H(ER) Error information
CM: Command register FR: Features register
DH: Device/Head register ST: Status register
CH: Cylinder High register ER: Error register
CL: Cylinder Low register L: LBA (logical block address) setting bit
SN: Sector Number register DV: Device address. bit
SC: Sector Count register x, xx: Do not care (no necessary to set)
C141-E034-02EN5 - 16
Note:
1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH,
CL and SN registers indicate the LBA bits (bits of the DH register are the MSB (most
significant bit) and bits of the SN register are the LSB (least significant bit).
2. At error occurrence, the SC register indicates the remainin g s ector count of data trans fer.
3. In the table indicating I/O registers contents in this subsection, bit indication is omitted.
(1) READ SECTOR(S) (X'20' or X'21')
This command reads data of sectors specified in the Sector Count register from the address specified in
the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be
specified to 256 sectors in maximum. To specify 256 sectors reading, '00' is specified. For the DRQ,
INTRQ, and BSY protocols related to data tran sf er, see Su bsecti on 4.4.1.
If the head is not on the track specified by the host, the device performs a implied seek. After the
head reaches to the specified track, the device reads the target sector.
When the command is specified without retry (R bit = 1) or with retry (R bit = 0), the device
attempts to read the target sector up to 126 times.
The DRQ bit of the Status register is always set prior to the data transfer regardless of an error
condition.
Upon the completion of the command execution, command block registers contain the cylinder,
head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the
last sector read.
If an error occurs in a sector, the read operation is term inated at the s ector w here th e error occurred.
Command block registers contain the cylinder, the head, and the sector addresses of the sector (in
the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and
remaining number of sectors of which data was not transferred.
At command issuance (I/O registers setting contents)
1F7H(CM) 0010000R
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 →with Retry
R = 1 →without Retry
C141-E034-02EN 5 - 17
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(2) READ MULTIPLE (X'C4')
This command operates similarly to the READ SECTOR(S) command. The device does not
generate an interrupt (assertion of the INTRQ signal) on each every sector. An interrupt is
generated after the transfer of a block of sectors for which the number is specified by the SET
MULTIPLE MODE command.
The implementation of the READ MULTIPLE command is identical to that of the READ
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE
MODE command are transferred without intervening interrupts. In the READ MULTIPLE
command operation, the DRQ bit of the Status register is set only at the start of the data block, and
is not set on each sector.
The number of sectors (block count) to be transferred without interruption is specified by the SET
MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior
to the READ MULTIPLE command.
L
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
When the READ MULTIPLE command is issued, the Sector Count register contains the number of
sectors requested (not a n um ber of th e block cou nt or a n umber of sectors in a bl ock).
Upon receipt of this command, the device executes this command even if the value of the Sector Count
register is less than the defined block count (the value of the Sector Count should not be 0).
If the number of requested sectors is not divided evenly (having the same number of sectors [block
count]), as many full blocks as possible are transferred, then a final partial block is transferred.
The number of sectors in the partial block to be transferred is n where n = remainder of ("number
of sectors"/"block count").
If the READ MULTIPLE command is issued before the SET MULTIPLE MODE command is
executed or when the READ MULTIPLE command is disabled, the device rejects the READ
MULTIPLE command with an ABORTED COMMAND error.
If an error occurs, reading sector is stopped at the sector where the error occurred. Command
block registers contain the cylinder, the head, the sector addresses (in the CHS mode) or the logical
block address (in the LBA mode) of the sector where the error occurred, and remaining number of
sectors that had not transferred after the sector where the error occurred.
An interrupt is generated w h en the DR Q bit is set at th e begin nin g of each block or a partial block .
C141-E034-02EN5 - 18
Figure 5.2 shows an example of the execution of the READ MULTIPLE command.
• Block count specified by SET MULTIPLE MODE command = 4 (number of sectors in a
block)
• READ MULTIPLE command specifies;
Number of requested sectors = 9 (Sector Count register = 9)
↓
Number of sectors in incomplete block = remainder of 9/4 =1
Parameter
Command Issue
Write
~
BSY
DRDY
INTRQ
DRQ
Sector
transferred
Figure 5.2 Execution example of READ MULTIPLE command
At command issuance (I/O registers setting contents)
1F7H(CM) 11000100
1F6H(DH)
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
1 2 3 4
BlockBlock
L
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
Status readStatus readStatus read
95 6 7 8
Partial
block
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00
H
Error information
C141-E034-02EN 5 - 19
Note:
If the command is terminated due to an error, the remaining number of sectors for which data
was not transferred is set in this register.
(3) READ DMA (X'C8' or X'C9')
This command operates similarly to the READ SECTOR(S) command except for following events.
• The data transfer starts at the timing of DMARQ signal assertion.
• The device controls the assertion or negation timing of the DMARQ signal.
• T he device posts a status as the result of command execution only once at completion of the
data transfer.
When an error, such as an un recoverable m edium error, th at the com m and execution cannot be continued
is detected, the data transfer is stopped without transferring data of sectors after the erred sector. The
device generates an interrupt us ing th e INTRQ sign al and posts a statu s to the h ost sy stem . The f orm at of
the error information is the same as the READ SECTOR(S) command.
In LBA mode
The logical block address is specified using the start head No., start cylinder No., and first sector
No. fields. At command completion, the logical block address of the last sector and remaining
number of sectors of which data was not transferred, like in the CHS mode, are set.
The host system can select the DMA transfer mode by using the SET FEATURES command.
1) Single word DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'12' by the SET FEATURES command
2) Multiword DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command
3) Ultra DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command
At command issuance (I/O registers setting contents)
1F7H(CM) 1100100R
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 → with Retry
R = 1 → without Retry
C141-E034-02EN5 - 20
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(4) READ VERIFY SECTOR(S) (X'40' or X'41')
This command operates similarly to the READ SECTOR(S) command except that the data is not
transferred to the host system.
After all requested sectors are verified, the device clears the BSY bit of the Status register and
generates an interrupt. Upon the completion of the command execution, the command block
registers contain the cylinder, head, and sector number of the last sector verified.
If an error occurs, the verify operation is terminated at the sector where the error occurred. The
command block registers contain the cylinder, the head, and the sector addresses (in the CHS
mode) or the logical block address (in the LBA mode) of the sector where the error occurred. The
Sector Count register indicates the number of sectors that have not been verified.
If a correctable error is found, the device sets the CORR bit of the Status register to 1 after the
command is completed (before the device generates an interrupt).
At command issuance (I/O registers setting contents)
1F7H(CM) 0100000R
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 →with Retry
R = 1 →without Retry
C141-E034-02EN 5 - 21
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(5) WRITE SECTOR(S) (X'30' or X'31')
This command writes data of sectors from the address specified in the Device/Head, Cylinder
High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count
register. Number of sectors can be specified to 256 sectors in maximum. Data transfer begins at
the sector specified in the Sector Number register. For the DRQ, INTRQ, and BSY protocols
related to data transfer, see Subsection 4.4.2.
If the head is not on the track specified by the host, the device performs a implied seek. After the
head reaches to the specified track, the device writes the target sector.
When the command is specified with retry or without retry, the device attempts to retry up to 16
times.
DV End head No. /LBA [MSB]
×
The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the
corresponding sector(s). Upon the completion of the command execution, the command block
registers contain the cylinder, head, and sector addresses of the last sector written.
If an error occurs during multiple sector write operation, the write operation is terminated at the
sector where the error occurred. Command block registers contain the cylinder, the head, the
sector addresses (in the CHS mode) or the logical block address (in the LBA mode) of the sector
where the error occurred. Then the host can read the command block registers to determine what
error has occurred and on which sector the error has occurred.
At command issuance (I/O registers setting contents)
1F7H(CM) 0011000R
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 →with Retry
R = 1 →without Retry
C141-E034-02EN5 - 22
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(6) WRITE MULTIPLE (X'C5')
This command is similar to the WRITE SECTOR(S) command. The device does not generate
interrupts (assertion of the INTRQ) signal) on each sector but on the transfer of a block which
contains the number of sectors for which the number is defined by the SET MULTIPLE MODE
command.
The implementation of the WRITE MULTIPLE command is identical to that of the WRITE
SECTOR(S) command except that the number of sectors is specified by the SET MULTIPLE
MODE command are transferred without intervening interrupts. In the WRITE MULTIPLE
command operation, the DRQ bit of the Status register is required to set only at the start of the data
block, not on each sector.
The number of sectors (block count) to be transferred without interruption is specified by the SET
MULTIPLE MODE command. The SET MULTIPLE MODE command should be executed prior
to the WRITE MULTIPLE command.
L
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
When the WRITE MULTIPLE command is issued, the Sector Count register contains the number of
sectors requested (not a n um ber of th e block cou nt or a n umber of sectors in a bl ock).
Upon receipt of this command, the device executes this command even if the value of the Sector Count
register is less than the defined block count the value of the Sector Count should not be 0).
If the number of requested sectors is not divided evenly (having the same number of sectors [block
count]), as many full blocks as possible are transferred, then a final partial block is transferred. The
number of sectors in the partial block to be transferred is n where n = remainder of ("number of
sectors"/"block count").
If the WRITE MULTIPLE command is issued before the SET MULTIPLE MODE command is
executed or when WRITE MULTIPLE command is disabled, the device rejects the WRITE
MULTIPLE command with an ABORTED COMMAND error.
Disk errors encountered during execution of the WRITE MULTIPLE command are posted after
attempting to write the block or the partial block that was transferred. Write operation ends at the sector
where the error was encountered even if the sector is in the middle of a block. If an error occurs, the
subsequent block shall not be transferred. Interrupts are generated when the DRQ bit of the Status
register is set at the beginn ing of each block or partial block.
C141-E034-02EN 5 - 23
The contents of the command block registers related to addresses after the transfer of a data block
containing an erred sector are undefined. To obtain a valid error information, the host should retry
data transfer as an individual requests.
At command issuance (I/O registers setting contents)
1F7H(CM) 11000101
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00
H
Error information
Note:
When the command terminates due to error, only the DV bit and the error information field are
valid.
(7) WRITE DMA (X'CA' or X'CB')
This command operates similarly to the WRITE SECTOR(S) command except for following
events.
• The data transfer starts at the timing of DMARQ signal assertion.
• The device controls the assertion or negation timing of the DMARQ signal.
• T he device posts a status as the result of command execution only once at completion of the
data transfer.
When an error, such as an unrecoverable medium error, that the command execution cannot be
continued is detected, the data transfer is stopped without transferring data of sectors after the
erred sector. The device generates an interrupt using the INTRQ signal and posts a status to the
host system. The format of the error information is the same as the WRITE SECTOR(S)
command.
A host system can be select the following transfer mode using the SET FEATURES command.
C141-E034-02EN5 - 24
1) Single word DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'12' by the SET FEATURES command
2) Multiword DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'22' by the SET FEATURES command
3) Ultra DMA transfer mode 2:
Sets the FR register = X'03' and SC register = X'42' by the SET FEATURES command
At command issuance (I/O registers setting contents)
1F7H(CM) 1100101R
1F6H(DH)
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
R = 0 →with Retry
R = 1 →without Retry
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(8) WRITE VERIFY (X'3C')
L
DV Start head No. /LBA [MSB]
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
L
DV End head No. /LBA [MSB]
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
This command operates similarly to the WRITE SECTOR(S) command except that the device
verifies each sector immediately after being written. The verify operation is a read and check for
data errors without data transfer. Any error that is detected during the verify operation is posted.
C141-E034-02EN 5 - 25
At command issuance (I/O registers setting contents)
1F7H(CM) 00111100
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
L
×
×
Start cylinder No. [MSB] / LBA
Start cylinder No. [LSB] / LBA
Start sector No. / LBA [LSB]
Transfer sector count
xx
R = 0 →with Retry
R = 1 →without Retry
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
×
End cylinder No. [MSB] / LBA
End cylinder No. [LSB] / LBA
End sector No. / LBA [LSB]
00 (*1)
Error information
*1 If the command is terminated due to an error, the remaining number of
sectors of which data was not transferred is set in this register.
(9) RECALIBRATE (X'1x', x: X'0' to X'F')
DV Start head No. /LBA [MSB]
DV End head No. /LBA [MSB]
This command performs the calibration. Upon receipt of this command, the device sets BSY bit of
the Status register and performs a calibration. When the device completes the calibration, the
device updates the Status register, clears the BSY bit, and generates an interrupt.
This command can be issued in the LBA mode.
At command issuance (I/O registers setting contents)
1F7H(CM) 0001xxxx
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
×××
DV xx
xx
xx
xx
xx
xx
C141-E034-02EN5 - 26
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
(10) SEEK (X'7x', x : X'0' to X'F')
This command performs a seek operation to the track and selects the head specified in the
command block registers. After completing the seek operation, the device clears the BSY bit in
the Status register and generates an interrupt.
The IDD always sets the DSC bit (Drive Seek Complete status) of the Status register to 1.
In the LBA mode, this command performs the seek operation to the cylinder and head position in
which the sector is specified with the logical block address.
At command issuance (I/O registers setting contents)
1F7H(CM) 0111xxxx
1F6H(DH)
×
DV xx
xx
xx
xx
xx
Error information
L
DV Head No. /LBA [MSB]
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
L
×
DV Head No. /LBA [MSB]
×
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
xx
Error information
C141-E034-02EN 5 - 27
(11) INITIALIZE DEVICE PARAMETERS (X'91')
The host system can set the number of sectors per track and the maximum head number (maximum
head number is "number of heads minus 1") per cylinder with this command. Upon receipt of this
command, the device sets the BSY bit of Status register and saves the parameters. Then the device
clears the BSY bit and generates an interrupt.
When the SC register is specified to X'00', an ABORTED COMMAND error is posted. Other than
X'00' is specified, this command terminates normally.
The parameters set by this command are retained even after reset or power save operation
regardless of the setting of disabling the reverting to default setting.
In LBA mode
The device ignores the L bit specification and operates with the CHS mode specification. An accessible
area of this command within head moving in the LBA mode is always within a default area. It is
recommended that the host system refers the addressable user sectors (total number of sectors) in word
60 to 61 of the parameter information by the IDENTIFY DEVICE command.
At command issuance (I/O registers setting contents)
1F7H(CM) 10010001
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
(12) IDENTIFY DEVICE (X'EC')
The host system issues the IDENTIFY DEVICE command to read parameter information (512
bytes) from the device. Upon receipt of this command, the drive sets the BSY bit of Status register
and sets required parameter information in the sector buffer. The device then sets the DRQ bit of
the Status register, and generates an interrupt. After that, the host system reads the information out
of the sector buffer. Table 5.5 shows the arrangements and values of the parameter words and the
meaning in the buffer.
DV Max. head No.
xx
xx
xx
Number of sectors/track
xx
DV Max. head No.
xx
xx
xx
xx
Error Information
C141-E034-02EN5 - 28
At command issuance (I/O registers setting contents)
1F7H(CM) 11101100
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
×××
DV xx
xx
xx
xx
xx
xx
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
×××
DV xx
xx
xx
xx
xx
Error information
C141-E034-02EN 5 - 29
Table 5.4 Information to be read by IDENTIFY DEVICE command (1 of 3)
Word Value Description
0 X‘0C5A’ General Configuration *1
1 X‘0D3E’
X‘13DE’
X‘1A7C’
X‘2352’
X‘2A62’
2 X‘0000’ Reserved
3 X‘0010’ or
X‘000F’
4 X‘0000’ Undefined
5 X‘0000’ Undefined
6 X‘003F’ Number of sectors per track
7-9 X‘000000000000’ Undefined
10-19 – Serial number (ASCII code) *2
20-21 X‘00000000’ Vendor specific
22 X‘0004’ Number of ECC bytes transferred at READ LONG or WRITE LONG command
23-26 – Firmware revision (ASCII code) *3
27-46 – Model number (ASCII code) *4
47 X‘8020’ Maximum number of sectors per interrupt on READ/WRITE MULTIPLE command
48 X‘0000’ Reserved
49 X‘0B00’ Capabilities *5
50 X‘0000’ Reserved
51 X‘0200’ PIO data transfer mode *6
52 X‘0000’ Reserved
53 X‘0003’ or
X‘0007’
54 (Variable) umber of current Cylinders
55 (Variable) Number of current Head
56 (Variable) Number of current sectors per track
57-58 (Variable) Total number of current sectors
59 *8 Transfer sector count currently set by READ/WRITE MULTIPLE command
60-61 X‘00342778’
X‘004E3B34’
X‘00684EF0’
X‘008262AC’
X‘009C7668’
62 X‘0000’ Reserved
63 X‘xx07’ Multiword DMA transfer mode *9
64 X‘0003’ Advance PIO transfer mode support status *10
65 X‘0078’ Minimum multiword DMA transfer cycle time per word : 120 [ns]
66 X‘0078’ Manufacturer's recommended DMA transfer cycle time : 120 [ns]
67 X‘00F0’ Minimum PIO transfer cycle time without flow control : 240 [ns]
68 X‘0078’ Minimum PIO transfer cycle time with IORDY flow control : 120 [ns]
69-79 X‘00’ Reserved
80 X‘000E’ Major version number *11
81 X‘0000’ Minor version number (not reported)
82 X‘0009’ Support of command sets *12
83 X‘4000’ Support of command sets (fixed)
84-87 X‘00’ Reserved
88 X‘0000’ or
X‘0X07’
Number of cylinders MPA3017AT: X‘0D3E’
MPA3026AT: X‘13DE’
MPA3035AT: X‘1A7C’
MPA3043AT: X‘2352’
MPA3052AT: X‘2A62’
Number of Heads MPA3017AT: X‘0010’
MPA3026AT: X‘0010’
MPA3035AT: X‘0010’
MPA3043AT: X‘000F’
MPA3052AT: X‘000F’
Enable/disable setting of words 54-58, 64-70 and 88 *7
Total number of user addressable sectors (LBA mode only) MPA3017AT: X‘00342778’
MPA3026AT: X‘004E3B34’
MPA3035AT: X‘00684EF0’
MPA3043AT: X‘008262AC’
MPA3052AT: X‘009C7668’
Ultra DMA modes *13
C141-E034-02EN5 - 30
Table 5.4 Information to be read by IDENTIFY DEVICE command (2 of 3)
Word Value Description
89-127 X‘00’ Reserved
128 X‘00’ Security status not supported
129-159 X‘00’ Undefined
160-255 X‘00’ Reserved
*1 Word 0: General configuration
Bit 15: 0 = ATA device 0
Bit 14-8: Vendor specific 0
Bit 7: 1 = Removable media device 0
Bit 6: 1 = not removable controller and/or device 1
Bit 5-1: Vendor specific 0
Bit 0: Reserved 0
*2 Word 10-19: Serial number; ASCII code (20 characters, right-justified)
*3 Word 23-26: Firmware revision; ASCII code (8 characters, Left-justified)
*4 Word 27-46: Model number;
ASCII code (40 characters, Left-justified), remainder filled with blank code (X'20')
One of three model numbers;
MPA3017AT, MPA3026AT, MPA3035AT, MPA3043AT, MPA3052AT
*5 Word 49: Capabilities
Bit 15-14: Reserved
Bit 13: Standby timer value 0 = vendor specific
Bit 12: Reserved
Bit 11: IORDY support 1=Supported
Bit 10: IORDY inhibition 0=Disable inhibition
Bit 9: LBA support 1=Supported
Bit 8: DMA support 1=Supported
Bit 7-0: Vendor specific
*6 Word 51: PIO data transfer mode
Bit 15-8: PIO data transfer mode X'02'=PIO mode 2
Bit 7-0: Vendor specific
*7 Word 53: Enable/disable setting of word 54-58 and 64-70
Bit 15-3: Reserved
Bit 2: Enable/disable setting of word 88 1=Enable
Bit 1: Enable/disable setting of word 64-70 1=Enable
Bit 0: Enable/disable setting of word 54-58 1=Enable
C141-E034-02EN 5 - 31
Table 5.4 Information to be read by IDENTIFY DEVICE command (3 of 3)
*8 Word 59: Transfer sector count currently set by READ/WRITE MULTIPLE command
Bit 15-9: Reserved
Bit 8: Multiple sector transfer 1=Enable
Bit 7-0: Transfer sector count currently set by READ/WRITE MULTIPLE without
interrupt supports 2, 4, 8, 16 and 32 sectors.
*9 Word 63: Multiword DMA transfer mode
Bit 15-8: Currently used multiword DMA transfer mode
Bit 7-0: Supportable multiword DMA transfer mode
Bit 2=1 Mode 2
Bit 1=1 Mode 1
Bit 0=1 Mode 0
*10 Word 64: Advance PIO transfer mode support status
Bit 15-8: Reserved
Bit 7-0: Advance PIO transfer mode
Bit 1=1 Mode 4
Bit 0=1 Mode 3
*11 Word 80: Major version number
Bit 15-4: Reserved
Bit 3: ATA-3 Supported=1
Bit 2: ATA-2 Supported=1
Bit 1: ATA-1 Supported=1
Bit 0: Undefined
*12 Word 82: Support of command sets
Bit 15-4: Reserved
Bit 3: Power Management feature set supported=1
Bit 2: Removable feature set supported=0
Bit 1: Security feature set supported=0
Bit 0: SMART feature set supported=1
*13 Word 88: Ultra DMA modes
Bit 15-11: Reserved
Bit 10-8: Currently used Ultra DMA transfer modes
Bit 7-3: Reserved
Bit 2-0: Supportable Ultra DMA transfer mode
Bit 2=1 Mode 2
Bit 1=1 Mode 1
Bit 0=1 Mode 0
C141-E034-02EN5 - 32
(13) IDENTIFY DEVICE DMA (X'EE')
When this command is not used to transfer data to the host in DMA mode, this command functions
in the same way as the Identify Device command.
At command issuance (I/O registers setting contents)
1F7H(CM) 11101110
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
(14) SET FEATURES (X'EF')
The host system issues the SET FEATURES command to set parameters in the Features register
for the purpose of changing the device features to be executed. For the transfer mode (Feature
register = 03), detail setting can be done using the Sector Count register.
DV xx
xx
xx
xx
xx
xx
DV xx
xx
xx
xx
xx
Error information
Upon receipt of this command, the device sets the BSY bit of the Status register and saves the
parameters in the Features register. Then, the device clears the BSY bit, and generates an
interrupt.
If the value in the Features register is not supported or it is invalid, the device posts an ABORTED
COMMAND error.
Table 5.5 lists the available values and operational modes that may be set in the Features register.
C141-E034-02EN 5 - 33
Table 5.5 Features register values and settable modes
Features Register Drive operation mode
X‘02’ Enables the write cache function.
X‘03’ Specifies the transfer mode. Supports PIO mode 4, single word DMA mode 2,
and multiword DMA mode regardless of Sector Count register contents.
X‘55’ Disables read cache function.
X‘66’ Disables the reverting to power-on default settings after software reset.
X‘82’ Disables the write cache function.
X‘AA’ Enables the read cache function.
X‘BB’ Specifies the transfer of 4-byte ECC for READ LONG and WRITE LONG
commands.
X‘CC’ Enables the reverting to power-on default settings after software reset.
At power-on or after hardware reset, the default mode is the same as that is set with a value greater
than X‘AA’ (except for write cache). If X‘66’ is specified, it allows the setting value greater than
X‘AA’ which may have been modified to a new value since power-on, to remain the same even
after software reset.
At command issuance (I/O registers setting contents)
1F7H(CM) 11101111
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
×××
DV xx
xx
xx
xx
xx or transfer mode
[See Table 5.6]
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
×××
DV xx
xx
xx
xx
xx
Error information
C141-E034-02EN5 - 34
The host sets X'03' to the Features register. By issuing this command with setting a value to the
Sector Count register, the transfer mode can be selected. Upper 5 bits of the Sector Count register
defines the transfer type and lower 3 bits specifies the binary mode value.
However, the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2
regardless of reception of the SET FEATURES command for transfer mode setting.
The IDD supports following values in the Sector Count register value. If other value than below is
specified, an ABORTED COMMAND error is posted.
PIO default transfer mode 00000 000 (X‘00’)
PIO flow control transfer mode X 00001 000 (X‘08’: Mode 0)
00001 001 (X‘09’: Mode 1)
00001 010 (X‘0A’: Mode 2)
00001 011 (X‘0B’: Mode 3)
00001 100 (X‘0C’: Mode 4)
Single word DMA transfer mode X 00010 000 (X‘10’: Mode 0)
00010 001 (X‘11’: Mode 1)
00010 010 (X‘12’: Mode 2)
Multiword DMA transfer mode X 00100 000 (X‘20’: Mode 0)
00100 001 (X‘21’: Mode 1)
00100 010 (X‘22’: Mode 2)
Ultra DMA transfer mode X 01000 000 (X‘40’: Mode 0)
(15) SET MULTIPLE MODE (X'C6')
This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE
commands. The block count (number of sectors in a block) for these commands are also specified
by the SET MULTIPLE MODE command.
The number of sectors per block is written into the Sector Count register. The IDD supports 2, 4,
8, 16 and 32 (sectors) as the block counts.
Upon receipt of this command, the device sets the BSY bit of the Status register and checks the
contents of the Sector Count register. If the contents of the Sector Count register is valid and is a
supported block count, the value is stored for all subsequent READ MULTIPLE and WRITE
MULTIPLE commands. Execution of these commands is then enabled. If the value of the Sector
Count register is not a supported block count, an ABORTED COMMAND error is posted and the
READ MULTIPLE and WRITE MULTIPLE commands are disabled.
If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is
issued, the READ MULTIPLE and WRITE MULTIPLE commands are disabled.
When the SET MULTIPLE MODE command operation is completed, the device clears the BSY
bit and generates an interrupt.
01000 001 (X‘41’: Mode 1)
01000 010 (X‘42’: Mode 2)
C141-E034-02EN 5 - 35
At command issuance (I/O registers setting contents)
1F7H(CM) 11000110
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
×××
DV xx
xx
xx
xx
Sector count/block
xx
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
×××
DV xx
xx
xx
xx
Sector count/block
Error information
After power-on or after hardware reset, the READ MULTIPLE and WRITE MULTIPLE
command operation are disabled as the default mode.
Regarding software reset, the mode set prior to software reset is retained after software reset.
The parameters for the multiple commands which are posted to the host system when the
IDENTIFY DEVICE command is issued are listed below. See Subsection 5.3.2 for the
IDENTIFY DEVICE command.
Word 47 = 0020:
Maximum number of sectors that can be transferred per interrupt by the
READ MULTIPLE and WRITE MULTIPLE commands are 32 (fixed).
Word 59 = 0000:
= 01xx:
The READ MULTIPLE and WRITE MULTIPLE commands are disabled.
The READ MULTIPLE and WRITE MULTIPLE commands are enabled.
"xx" indicates the current setting for number of sectors that can be
transferred per interrupt by the READ MULTIPLE and WRITE
MULTIPLE commands.
e.g. 0110 = Block count of 16 has been set by the SET MULTIPLE MODE
command.
C141-E034-02EN5 - 36
(16) EXECUTE DEVICE DIAGNOSTIC (X'90')
This command performs an internal diagnostic test (self-diagnosis) of the device. This command
usually sets the DRV bit of the Drive/Head register is to 0 (however, the DV bit is not checked). If
two devices are present, both devices execute self-diagnosis.
If device 1 is present:
• Both devices shall execute self-diagnosis.
• The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG- signal.
• If the device 1 does not assert the PDIAG- signal but indicates an error, the device 0 shall
append X‘80’ to its own diagnostic status.
• T he device 0 clears the BSY bit of the Status register and generates an interrupt. (The device
1 does not generate an interrupt.)
• A diagnostic status of the device 1 is read by the host system. When a diagnostic failure of the
device 1 is detected, the host system can read a status of the device 1 by setting the DV bit
(selecting the device 1).
When device 1 is not present:
• The device 0 posts only the results of its own self-diagnosis.
• The device 0 clears the BSY bit of the Status register, and generates an interrupt.
Table 5.6 lists the diagnostic code written in the Error register which is 8-bit code.
If the device 1 fails the self-diagnosis, the device 0 "ORs" X‘80’ with its own status and sets that
code to the Error register.
Table 5.6 Diagnostic code
Code Result of diagnostic
X‘01’
X‘03’
X‘05’
X‘8x’
No error detected.
Data buffer compare error
ROM sum check error
Failure of device 1
C141-E034-02EN 5 - 37
At command issuance (I/O registers setting contents)
1F7H(CM) 10010000
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
×××
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
*1 This register indicates X‘00’ in the LBA mode.
(17) FORMAT TRACK (X'50')
Upon receipt of this command, the device sets the DRQ bit and waits the completion of 512-byte
format parameter transfer from the host system. After completion of transfer, the device clears the
DRQ bits, sets the BSY bit. However the device does not perform format operation, but the drive
clears the BYS bit and generates an interrupt soon. When the command execution completes, the
device clears the BSY bit and generates an interrupt.
DV xx
xx
xx
xx
xx
xx
DV xx
xx
xx
(*1)
01
H
01
H
Diagnostic code
The drive supports this command for keep the compatibility with previous drive only.
(18) READ LONG (X'22' or X'23')
This command operates similarly to the READ SECTOR(S) command except that the device
transfers the data in the requested sector and the ECC bytes to the host system. The ECC error
correction is not performed for this command. This command is used for checking ECC function
by combining with the WRITE LONG command.
Number of ECC bytes to be transferred is fixed to 4 bytes and cannot be changed by the SET
FEATURES command.
The READ LONG command supports only single sector operation.
C141-E034-02EN5 - 38
At command issuance (I/O registers setting contents)
1F7H(CM) 0010001R
1F6H(DH)
L
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(FR)
1F1
H
R = 0 →with Retry
R = 1 →without Retry
At command completion (I/O registers contents to be read)
1F7H(ST) Status information
1F6H(DH)
L
×
1F5H(CH)
(CL)
1F4
H
(SN)
1F3
H
(SC)
1F2
H
(ER)
1F1
H
*1 If the command is terminated due to an error, this reg ister in dicates 01.
(19) WRITE LONG (X'32' or X'33')
DV Head No. /LBA [MSB]
×
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
Number of sectors to be transferred
xx
DV Head No. /LBA [MSB]
×
Cylinder No. [MSB] / LBA
Cylinder No. [LSB] / LBA
Sector No. / LBA [LSB]
00 (*1)
Error information
This command operates similarly to the READ SECTOR(S) command except that the device
writes the data and the ECC bytes transferred from the host system to the disk medium. The device
does not generate ECC bytes by itself. The WRITE LONG command supports only single sector
operation.
The number of ECC bytes to be transferred is fixed to 4 bytes and can not be changed by the SET
FEATURES command.
This command is operated under the following conditions:
• T he command is issued in a sequence of the READ LONG or WRITE LONG (to the same
address) command issuance. (WRITE LONG command can be continuously issued after the
READ LONG command.)
If above condition is not satisfied, the command operation is not guaranteed.
C141-E034-02EN 5 - 39
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