Fujitsu MHV2060AH, MHV2040AH, MHV2080AH, MHV2100AH User Manual

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C141-E217-01EN

MHV2100AH, MHV2080AH MHV2060AH, MHV2040AH

DISK DRIVE

PRODUCT MANUAL

FOR SAFE OPERATION

Handling of This Ma nual

This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Us e th e product according t o t hi s m anual .

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT. INCORRECT USE OF THE PRODUCT MAY RES ULT IN INJURY OR DAMA GE TO USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought t o ens ure t h e accuracy of all i nform at i on i n t hi s m anual, FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual, its updates or supplements, whether such errors or omissions result from negligence, accident, or any o t h er cau s e. In ad dition, FUJITSU assumes no liability with respect to the application or use of any product or sy st em i n accordance wi t h t he des cript i ons or i n st ruct i ons contained herein; including any liability for incidental or consequential damages arising therefrom. FUJITSU DISCLAIM S ALL WAR R ANTIES R E GAR DING THE INF OR MATION CONTAINED HEREIN, WHETHER EXP R ES S E D, IM P LIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation.

This product is designed and manufactured for use in standard applications such as office work, personal devices and household appliances. This product is not intended for special uses (atomic controls , aeronautic o r s p ace s y s t em s , mass tran s p or t v ehicle operatin g co n t ro l s , medical dev i ces for life support, or weapons firing controls) where particularly high reliability requirements exist, where the pertinent levels of safety are not guaranteed, or where a failure or operational error could threaten a life or cause a physical injury (hereafter referred to as "mission-critical" use). Customers considering the use of these products for mission-critical applications must have safety-assurance measures in p l ace b efo rehan d . Moreover, they are request ed to consul t o ur s ales representat i v e before embarkin g o n s uch s p eci al ized use.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited.

Revision History

(1/1)

Edition Date

01 2004-11-15

Revised section (*1)

(Added/Deleted/Altered)

Details

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E217

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This manual describes MHV2100AH, MHV2080AH, MHV2060AH, MHV2040AH model of the MHV Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the ATA interface.

This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Device Overvie w

Preface

This chapter gives an overview of the disk drive and describes their features.

CHAPTER 2 Device Configuration

This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate.

CHAPTER 3 Installa tion Conditions

This chapter describes the external dimensions, installation conditions, and switch settings of the disk drive.

CHAPTER 4 Theory of Devi ce Operation

This chapter describes the operation theory of the disk drive.

CHAPTER 5 Interface

This chapt er d es cri b es t h e i n t erface s p eci fi cat i o n s o f t h e d i s k dr i v e.

CHAPTER 6 Operations

This chapter describes the operations of the disk drive.

Glossary

The glossary describes the technical terms that need to be understood to read this manual.

Acronyms and Abbreviations

This section gives the meanings of the definitions used in this manual.

C141-E217 i

Preface

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly.

This indicates information that could help the user use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:

(Example)

Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Operating Environment

This product is designed to be used in offices or computer rooms.

Conventions

An MHV series device is sometimes simply referred to as a "hard disk drive," "HDD," "drive," or "device" in this document.

Decimal numbers are represented normally.

Hexadecimal numbers are represented as shown in the following examples: X'17B9', 17B9h, 17B9

Binary numbers are represented as shown in the following examples: 010 or 010b.

ii C141-E217

, or 17B9H.

Preface

Attention

Please forward any comments you may have regarding this manual.

To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet.

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

C141-E217 iii

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Important Aler t Items

Important Alert Messages

The important alert messages in this manual are as follows:

A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the pro ced u re co rrect l y .

Task Alert message Page

Normal Operatio n

Data corruption: Avoid mounting the disk near strong magnetic sources such as loud speakers. Ensure that the disk drive is n o t affect ed b y ex t ern al m ag n et i c fi elds. Damage: Do not press the cover of the disk drive. Pressing it too hard, the cover and the spindle motor contact, which may cause damage to the disk drive.

Static: When handling the device, disconnect the body ground (500 kΩ or greater). Do not touch the printed circuit

board, but hold it by the edges.

3-7

C141-E217 v

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Manual Organization

MHV2100AH, MHV2080AH MHV2060AH, MHV2040AH

DISK DRIVE

PRODUCT MANUAL

(C141-E217)

MHV2100AH, MHV2080AH MHV2060AH, MHV2040AH

DISK DRIVE

MAINTENANCE MANUAL

(C141-F071)

• Device Overview

• Device Configuration

• Installation Conditions

• Theory of Devi ce Operation

• Interface

• Operations

• Maintenance and Diagnosis

• Removal an d R ep lacement Pro ced u re

C141-E217 vii

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CHAPTER 1 Device Overview....................................................................... 1-1

1.1 Features ......................................................................................................... 1-2

1.1.1 Functions and performance.................................................................. 1-2

1.1.2 Adaptability......................................................................................... 1-2

1.1.3 Interface..............................................................................................1-3

1.2 Device Specifications..................................................................................... 1-4

1.2.1 Specifications summary....................................................................... 1-4

1.2.2 Model and product number.................................................................. 1-5

1.3 Power Requirements ......................................................................................1-6

1.4 Environmental Specifications......................................................................... 1-8

1.5 Acoustic Noise............................................................................................... 1-9

1.6 Shock and Vibration....................................................................................... 1-9

1.7 Reliability.................................................................................................... 1-10

1.8 Error Rate.................................................................................................... 1-11

1.9 Media Defects.............................................................................................. 1-11

1.10 Load/Unload Function................................................................................ 1-11

1.11 Advanced Power Management ................................................................... 1-12

CHAPTER 2 Device Configuration................................................................ 2-1

2.1 Device Configuration..................................................................................... 2-2

2.2 System Configuration.....................................................................................2-3

2.2.1 ATA interface ...................................................................................... 2-3

2.2.2 1 drive connection ...............................................................................2-3

2.2.3 2 drives connection.............................................................................. 2-4

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Contents

CHAPTER 3 Installation Conditions .............................................................3-1

3.1 Dimensions .................................................................................................... 3-2

3.2 Mounting....................................................................................................... 3-3

3.3 Cable Connections......................................................................................... 3-9

3.3.1 Device connector ................................................................................. 3-9

3.3.2 Cable connector specifications........................................................... 3-10

3.3.3 Device connection............................................................................. 3-10

3.3.4 Power supply connector (CN1).......................................................... 3-11

3.4 Jumper Settings............................................................................................3-11

3.4.1 Location of setting jumpers ............................................................... 3-11

3.4.2 Factory default setting....................................................................... 3-12

3.4.3 Master drive-slave drive setting......................................................... 3-12

3.4.4 CSEL setting..................................................................................... 3-13

3.4.5 Power up in standby setting............................................................... 3-14

CHAPTER 4 Theory of Device Operation .....................................................4-1

4.1 Outline........................................................................................................... 4-2

4.2 Subassemblies................................................................................................ 4-2

4.2.1 Disk .................................................................................................... 4-2

4.2.2 Spindle................................................................................................ 4-2

4.2.3 Actuator .............................................................................................. 4-2

4.2.4 Air filter.............................................................................................. 4-3

4.3 Circuit Configuration..................................................................................... 4-3

4.4 Power-on Sequence........................................................................................ 4-6

4.5 Self-calibration .............................................................................................. 4-7

4.5.1 Self-calibration contents...................................................................... 4-7

4.5.2 Execution timing of self-calibration..................................................... 4-8

4.5.3 Command processing during self-calibration....................................... 4-8

4.6 Read/write Circuit .......................................................................................... 4-9

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Contents

4.6.1 Read/write preamplifier (PreAMP) ...................................................... 4-9

4.6.2 Write circuit ........................................................................................ 4-9

4.6.3 Read circuit....................................................................................... 4-10

4.6.4 Digital PLL circuit............................................................................. 4-11

4.7 Servo Control............................................................................................... 4-12

4.7.1 Servo control circuit.......................................................................... 4-12

4.7.2 Data-surface servo form at .................................................................. 4-15

4.7.3 Servo frame format ............................................................................ 4-17

4.7.4 Actuator motor control....................................................................... 4-18

4.7.5 Spindle motor control........................................................................ 4-19

CHAPTER 5 Interface..................................................................................... 5-1

5.1 Physical Interface ........................................................................................... 5-2

5.1.1 Interface signals................................................................................... 5-2

5.1.2 Signal assignment on the connector.....................................................5-3

5.2 Logical Interface............................................................................................ 5-6

5.2.1 I/O registers......................................................................................... 5-7

5.2.2 Command block registers.................................................................... 5-8

5.2.3 Control block registers....................................................................... 5-13

5.3 Host Commands........................................................................................... 5-14

5.3.1 Command code and parameters..........................................................5-14

5.3.2 Command descriptions ...................................................................... 5-18

(1) RECALIBRATE (X’10’ to X’1F’) ...............................................5-20

(2) READ SECTOR(S) (X’20’ or X’21’)...........................................5-21

(3) WRITE SECTOR(S) (X’30’ or X’31’) .........................................5-23

(4) WRITE VERIFY (X’3C’).............................................................5-25

(5) READ VERIFY SECTOR(S) (X’40’ or X’41’)............................5-26

(6) SEEK (X’70’ to X’7F’)................................................................5-27

(7) EXECUTE DEVICE DIAGNOSTIC (X’90’) ...............................5-28

(8) INITIALIZE DEVICE PARAMETERS (X’91’)...........................5-30

(9) DOWNLOAD MICROCODE (X’92’)..........................................5-31

(10) STANDBY IMMEDIATE (X’94’ or X’E0’) ...............................5-33

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Contents

(11) IDLE IMMEDIATE (X’95’ or X’E1’) / UNLOAD

IMMEDIATE (X’95’ or X’E1’)..................................................5-34

(12) STANDBY (X’96’ or X’E2’) ..................................................... 5-36

(13) IDLE (X’97’ or X’E3’)...............................................................5-37

(14) CHECK POWER MODE (X’98’ or X’E5’) ................................5-39

(15) SLEEP (X’99’ or X’E6’)............................................................ 5-40

(16) SMART (X’B0).........................................................................5-41

(17) DEVICE CONFIGURATION (X'B1')........................................5-58

(18) READ MULTIPLE (X’C4’)....................................................... 5-63

(19) WRITE MULTIPLE (X’C5’) .....................................................5-65

(20) SET MULTIPLE MODE (X’C6’) ..............................................5-67

(21) READ DMA (X’C8’ or X’C9’)..................................................5-69

(22) WRITE DMA (X’CA’ or X’CB’)...............................................5-71

(23) READ BUFFER (X’E4’)............................................................5-73

(24) FLUSH CACHE (X’E7’) ...........................................................5-74

(25) WRITE BUFFER (X’E8’) ..........................................................5-75

(26) IDENTIFY DEVICE (X’EC’) ....................................................5-76

(27) IDENTIFY DEVICE DMA (X’EE’)...........................................5-77

(28) SET FEATURES (X’EF’)..........................................................5-89

(29) SECURITY SET PASSWORD (X’F1’) .....................................5-93

(30) SECURITY UNLOCK(X’F2’)...................................................5-95

(31) SECURITY ERASE PREPARE (X’F3’)....................................5-97

(32) SECURITY ERASE UNIT (X’F4’)............................................5-98

(33) SECURITY FREEZE LOC K (X’F 5’).........................................5-99

(34) SECURITY DISABLE PASSWORD (X’F6’) ..........................5-101

(35) READ NATIVE MAX ADDRESS (X’F8’) ..............................5-103

(36) SET MAX (X’F9’)...................................................................5-104

(37) READ SECTOR(S) EXT (X’24’): Option (customizing).........5-110

(38) READ DMA EXT (X’25’): Option (customizing)...................5-111

(39) READ NATIVE MAX ADDRESS EXT (X’27’): Opti on

(customizing) ............................................................................5-112

(40) READ MULTIPLE EXT (X’29’): Option (customizing) .........5-113

(41) READ LOG EXT (X'2F') [Optional command

(Customize)].............................................................................5-114

(42) WRITE SECTOR(S) EXT (X’34’): Option (customizing).......5-116

(43) WRITE DMA EXT (X’35’): Option (customizing)..................5-117

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Contents

(44) SET MAX ADDRESS EXT (X’37’): Opti on

(customizing) ...........................................................................5-118

(45) WRITE MULTIPLE EXT (X’39’): Option (customizing)........5-120

(46) WRITE DMA FUA EXT (X’3D’): Option (customizing)........5-121

(47) WRITE LOG EXT (X’3F’) [Opti o nal com m and

(Customize)]............................................................................5-122

(48) READ VERIFY SECTOR (S) EXT (X’42): Option

(customizing) ...........................................................................5-124

(49) WRITE MULTIPLE FUA EXT (X’CE’): Opti on

(customizing) ...........................................................................5-125

(50) FLUSH CACHE EXT (X’EA’): Op t io n

(customizing)............................................................................5-126

5.3.3 Error posting.................................................................................... 5-127

5.4 Command Protocol.................................................................................... 5-129

5.4.1 PIO Data transferring commands from device to host ...................... 5-129

5.4.2 PIO Data transferring commands from host to device ...................... 5-132

5.4.3 Commands without data transfer...................................................... 5-134

5.4.4 Other commands.............................................................................. 5-135

5.4.5 DMA data transfer commands ......................................................... 5-135

5.5 Ultra DMA Feature Set.............................................................................. 5-137

5.5.1 Overview......................................................................................... 5-137

5.5.2 Phases of operation.......................................................................... 5-138

5.5.3 Ultra DMA data in commands ......................................................... 5-138

5.5.3.1 Initiating an Ultra DMA data in burst.................................... 5-138

5.5.3.2 The data in transfer............................................................... 5-139

5.5.3.3 Pausing an Ultra DMA data in burst ..................................... 5-139

5.5.3.4 Terminating an Ultra DMA data in burst............................... 5-140

5.5.4 Ultra DMA data out commands ....................................................... 5-143

5.5.4.1 Initiating an Ultra DMA data out burst.................................. 5-143

5.5.4.2 The data out transfer ............................................................. 5-144

5.5.4.3 Pausing an Ultra DMA data out burst.................................... 5-144

5.5.4.4 Terminating an Ultra DMA data out burst............................. 5-145

5.5.5 Ultra DMA CRC rules..................................................................... 5-147

5.5.6 Series termination required for Ultra DMA ...................................... 5-148

5.6 Timing....................................................................................................... 5-149

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Contents

5.6.1 PIO data transfer...............................................................................5-149

5.6.2 Multiword data transfer....................................................................5-150

5.6.3 Ultra DMA data transfer...................................................................5-151

5.6.3.1 Initiating an Ultra DMA data in burst ....................................5-151

5.6.3.2 Ultra DMA data burst timing requirements............................5-152

5.6.3.3 Sustained Ultra DMA data in burst........................................5-155

5.6.3.4 Host pausing an Ultra DMA data in burst ..............................5-156

5.6.3.5 Device terminating an Ultra DMA data in burst.....................5-157

5.6.3.6 Host terminating an Ultra DMA data in burst.........................5-158

5.6.3.7 Initiating an Ultra DMA data out burst ..................................5-159

5.6.3.8 Sustained Ultra DMA data out burst......................................5-160

5.6.3.9 Device pausing an Ultra DMA data out burst.........................5-161

5.6.3.10 Host terminating an Ultra DMA data out burst.....................5-162

5.6.3.11 Device terminating an Ultra DMA data out burst.................5-163

5.6.4 Power-on and reset...........................................................................5-164

CHAPTER 6 Operations .................................................................................6-1

6.1 Device Response to the Reset......................................................................... 6-2

6.1.1 Response to power-on ......................................................................... 6-2

6.1.2 Response to hardware reset.................................................................. 6-3

6.1.3 Response to software reset................................................................... 6-5

6.1.4 Response to diagnostic command........................................................ 6-6

6.2 Power Save.................................................................................................... 6-7

6.2.1 Power save mode................................................................................. 6-7

6.2.2 Power commands ................................................................................ 6-9

6.3 Defect Processing........................................................................................... 6-9

6.3.1 Spare area............................................................................................ 6-9

6.3.2 Alternating processing for defective sectors....................................... 6-10

6.4 Read-ahead Cache........................................................................................ 6-12

6.4.1 DATA buffer structure....................................................................... 6-12

6.4.2 Caching operation.............................................................................. 6-13

6.4.3 Using the read segment buffer........................................................... 6-15

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Contents

6.4.3.1 Miss-hit.................................................................................. 6-15

6.4.3.2 Sequential hit.......................................................................... 6-16

6.4.3.3 Full hit.................................................................................... 6-17

6.4.3.4 Partial hit................................................................................ 6-18

6.5 Write Cache................................................................................................. 6-19

6.5.1 Cache operation................................................................................. 6-19

Glossary........................................................................................................... GL-1

Acronyms and Abbreviations........................................................................ AB-1

Index ..................................................................................................................IN-1

C141-E217 xv

Contents

Illustrations

Figures

Figure 1.1 Negative voltage at +5 V when power is turned off........................... 1-6

Figure 1.2 Current fluctuation (Typ.) at +5 V when power is

turned on........................................................................................ 1-8

Figure 2.1 Disk drive outer view........................................................................ 2-2

Figure 2.2 1 drive system configuration............................................................. 2-3

Figure 2.3 2 drives configuration....................................................................... 2-4

Figure 3.1 Dimensions....................................................................................... 3-2

Figure 3.2 Orientation ....................................................................................... 3-3

Figure 3.3 Mounting frame structure..................................................................3-4

Figure 3.4 Location of breather.......................................................................... 3-5

Figure 3.5 Surface temperature meas ur em en t p oints .......................................... 3-6

Figure 3.6 Service area...................................................................................... 3-7

Figure 3.7 Handling cautions............................................................................. 3-8

Figure 3.8 Connector locations.......................................................................... 3-9

Figure 3.9 Cable connections........................................................................... 3-10

Figure 3.10 Power supply connector pins (CN1).............................................. 3-11

Figure 3.11 Jumper location............................................................................ 3-11

Figure 3.12 Factory default setting .................................................................. 3-12

Figure 3.13 Jumper setting of master or slave drive ......................................... 3-12

Figure 3.14 CSEL setting................................................................................ 3-13

Figure 3.15 Example (1) of cable select........................................................... 3-13

Figure 3.16 Example (2) of cable select........................................................... 3-14

Figure 4.1 Power supply configuration.............................................................. 4-4

Figure 4.2 Circuit configuration......................................................................... 4-5

Figure 4.3 Power-on operation sequence............................................................ 4-6

Figure 4.4 Read/write circuit block diagram ...................................................... 4-9

Figure 4.5 Frequency characteristic of programmable filter.............................. 4-10

Figure 4.6 Block diagram of servo control circuit............................................ 4-12

Figure 4.7 Physical sector servo configuration on disk surface......................... 4-16

Figure 4.8 Servo frame format......................................................................... 4-17

Figure 5.1 Interface sig n al s................................................................................ 5-2

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Figure 5.2 Execution example of READ MULTIPLE command...................... 5-63

Figure 5.3 READ S EC TOR (S ) C OMM AND prot ocol ................................... 5-130

Figure 5.4 Protocol for command abort.......................................................... 5-131

Figure 5.5 WRITE SECTOR(S) command protocol ....................................... 5-133

Figure 5.6 Protocol for the command execution without data

transfer ....................................................................................... 5-135

Figure 5.7 Normal DMA data transfer............................................................5-136

Figure 5.8 Ultra DMA termination with pull-up or pull-down........................ 5-148

Figure 5.9 PIO data transfer timing................................................................ 5-149

Figure 5.10 Multiword DMA data transfer timing (mode 2)........................... 5-150

Figure 5.11 Initiating an Ultra DMA data in burst.......................................... 5-151

Figure 5.12 Sustained Ultra DMA data in burst ............................................. 5-155

Figure 5.13 Host pausing an Ultra DMA data in burst.................................... 5-156

Figure 5.14 Device terminating an Ultra DMA data in burst.......................... 5-157

Figure 5.15 Host terminating an Ultra DMA data in burst.............................. 5-158

Figure 5.16 Initiating an Ultra DMA data out burst........................................ 5-159

Figure 5.17 Sustained Ultra DMA data out burst............................................ 5-160

Figure 5.18 Device pausing an Ultra DMA data out burst.............................. 5-161

Figure 5.19 Host terminating an Ultra DMA data out burst............................ 5-162

Figure 5.20 Device terminating an Ultra DMA data out burst ........................ 5-163

Figure 5.21 Power-on reset timing................................................................. 5-164

Figure 6.1 Response to power-on....................................................................... 6-3

Figure 6.2 Response to hardware reset ...............................................................6-4

Figure 6.3 Response to software reset ................................................................6-5

Figure 6.4 Response to diagnostic command...................................................... 6-6

Figure 6.5 Sector slip processing ..................................................................... 6-10

Figure 6.6 Automatic alternating processing.................................................... 6-11

Figure 6.7 Data buffer structure....................................................................... 6-12

C141-E217 xvii

Contents

Tables

Table 1.1 Specifications.....................................................................................1-4

Table 1.2 Examples of model names and product numbers ................................ 1-5

Table 1.3 Current and power dissipation............................................................ 1-7

Table 1.4 Environmental specifications ............................................................. 1-8

Table 1.5 Acoustic noise specification............................................................... 1-9

Table 1.6 Shock and vibration specification....................................................... 1-9

Table 1.7 Advanced Power Management......................................................... 1-13

Table 3.1 Surface temperatu re measurement p o i n t s an d s t an d ard

values................................................................................................ 3-6

Table 3.2 Cable connector specifications......................................................... 3-10

Table 5.1 Signal as si gnm ent on th e i nt erface connector ..................................... 5-3

Table 5.2 I/O registers....................................................................................... 5-7

Table 5.3 Command code and parameters........................................................ 5-15

Table 5.4 Diagnostic code ................................................................................ 5-28

Table 5.5 Operation of DOWNLOAD MICR OC ODE ..................................... 5-32

Table 5.6 Example of rewriting procedure of data 512 KBytes

(40000h Bytes) of microcode........................................................... 5-32

Table 5.7 Features register values (subcommands) and functions .................... 5-42

Table 5.8 Format of device attribute value data................................................ 5-46

Table 5.9 Format of insurance failure threshold value data............................... 5-46

Table 5.10 Off-line data collection status ......................................................... 5-49

Table 5.11 Self-test execution status................................................................ 5-49

Table 5.12 Off-line data collection capability................................................... 5-50

Table 5.13 Failure prediction capability flag.................................................... 5-50

Table 5.14 Error logging capability ................................................................. 5-51

Table 5.15 Log directory data format............................................................... 5-51

Table 5.16 Data format of SMART Summary Error Log................................. 5-53

Table 5.17 Data format of SMART Comprehensive Error Log ........................ 5-54

Table 5.18 SMART self-test log data format.................................................... 5-55

Table 5.19 Selective self-test log data structure................................................ 5-56

Table 5.20 Selective self-test feature flags ....................................................... 5-57

Table 5.21 DEVICE CONFIGURATION IDENTIFY data structure................ 5-61

Table 5.22 Information to be read by IDENTIFY DEVICE

command ....................................................................................... 5-78

Table 5.23 Features register values and settable modes.................................... 5-89

Table 5.24 Contents of SECURITY SET PASSWORD data............................ 5-93

Table 5.25 Relationship between combination of Identifier and

Security level, and operation of the lock function ........................... 5-93

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Contents

Table 5.26 Contents of security password...................................................... 5-101

Table 5.27 Command code and parameters ................................................... 5-127

Table 5.28 Recommended series termination for Ultra DMA......................... 5-148

Table 5.29 Ultra DMA data burst timing requirements ................................... 5-152

Table 5.30 Ultra DMA sender and recipient timing requirements................... 5-154

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CHAPTER 1 Device Overview

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

1.10 Load/Unload Function

1.11 Advanced Power Management

Overview and featu res are d es cri b ed i n t h i s ch ap t er, and specifi cat i o n s and p o wer requirement are described.

The disk drive is 2.5-inch hard disk drives with built-in disk controllers. These disk dri v es us e t h e AT -b us h ard d i s k i nterface protocol and are co m p act an d reliable.

C141-E217 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

The following features of the disk drive are described.

(1) Compact

The disk drive has up to 2 disks of 65 mm (2.5 inches) diameter, and its height is

9.5 mm (0.374 inch).

(2) Green product

The disk drive is lead (Pb)-free products and the European Parliament and Council Directive on the Res t ri cti on of t h e use of cert ai n Hazardous S ubs t ances i n electrical and electronic equipment (the RoHS Directive) compliant.

(3) Large capacity

The disk drive can record up to 50 GB (formatted) on one disk using the RLL recording method and 30 recording zone technology. The disk drive has a formatted capacity of 100 GB (MHV2100AH), 80 GB (MHV2080AH), 60 GB (MHV2060AH) and 40 GB (MHV2040AH) respectively.

(4) High-speed Transfer rate

The disk drive (the MHV Series) has an internal data rate up to 59.4 MB/s. The disk drive supports an external data rate up to 100 MB/s (U-DMA mode 5).

(5) Average positioning time

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 12 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The power save mode feature for Idle operation, Standby and Sleep modes and automatically power down by APM function makes the disk drive ideal for mobile use where power consumption is a factor.

(2) Wide temperature range

The disk drive can be used over a wide temperature range (5 °C to 55 °C).

(3) Low noise and vibration

In Ready status (while the device is waiting for any commands), the Sound Power level of the disk drives in idle mode is 2.2B [MHV2040AH]/2.6B [MHV2060AH,

1-2 C141-E217

1.1 Features

MHV2080AH, MHV2100AH]. The Sound Pressure level is 22dB [MHV2040AH]/28dB [MHV2060AH, MHV2080AH, MHV2100AH], as measured 0.3 m from the drive in Idle mode.

(4) High resistance against shock

The Load/Unload mechanism is highly resistant against non-operation shock up to 8820 m/s

(900G).

1.1.3 Interface

(1) Connection to ATA interface

The disk drive has built-in controllers compatible with the ATA interface.

(2) Data buffer

The disk drive uses 8MB data buffer to transfer data between the host and the disk media.

In combination with t h e read -ah ead cach e s y s t em d es cri b ed i n i t em (3 ) an d the write cache describ ed i n item (7), t he b u ffer co nt ributes to efficient I/O processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads the subsequent data block a nd wr ite s it to the da ta buff e r ( re a d a h e a d ope ra tion) . This cache system enables fast data access. The next disk read command would normally cause another disk access. But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.

(4) Master/slave

The disk d ri v e can b e con n ect ed t o ATA interface as dais y ch ai n con fi g u rat ion. Drive 0 is a m as t er d ev i ce, drive 1 i s a s l av e d evice.

(5) Error correction and retry by ECC

If a recoverable error occurs , the disk d ri ve itself att em pts error recovery. The ECC has im p ro ved b uffer erro r co rrect i o n fo r co rrect ab l e dat a erro rs .

(6) Self-diagnosis

The disk drive has a dia gnostic func tion to c h e c k ope ra tion of the c ontr olle r a nd disk drive. Executing a diagnostic f unc tion of the sma r t c omma nd invoke s se lf - dia gnosis.

(7) Write cache

When the di s k dr i v e recei v es a wri t e co m m an d , the dis k d rive posts t h e co m m an d completion at completion of transferring data to the data buffer completion of writing t o t h e d i s k m ed i a. This featu re red u ces t h e acces s time at writing.

C141-E217 1-3

Device Overview

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specifications of the disk drives.

Table 1.1 Specifications (1 of 2)

Format Capacity (*1) 100 GB 80GB 60GB 40GB Number of Sectors (User) 195,371,568 156,301,488 117,210,240 78,140,160 Bytes per Sector 512 bytes Rotational Speed 5,400 rpm ± 1% Average Latency 5.56 ms Positioning time (read and

seek)

• Minimum (Track-Track)

• Average

• Maximum (Full)

Start time 4.0 sec (typ.) Interface ATA-6 (Max. Cable length: 18inches (0.46 m))

Data Transfer Rate (*1)

• To/From Media

MHV2100AH MHV2080AH MHV2060AH MHV2040AH

1.5 ms (typ.)

Read: 12ms (typ.)

22 ms (typ.)

(equipped with expansion function)

59.4 MB/s Max.

• To/From Host Data Buffer Size (*2) 8MB (8,388,608 bytes) Physical Dimensions

(Height × Width × Depth) Weight 101 g (max) 96 g (max) *1: 1GB is equal to 1,000,000,000 bytes and 1MB is equal to 1,000,000 bytes. *2: 1MB is equal to 1,048,576 bytes.

1-4 C141-E217

100 MB/s Max (U-DMA mode5)

9.5 mm × 100.0 mm × 70.0 mm

1.2 Device Specifications

Table 1.1 lists the formatted capacity, number of logical cylinders, number

of heads, and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host.

Table 1.1 Specifications (2 of 2)

Model Capacity No. of Cylinder No. of Heads No. of Sectors

MHV2100AH 8.45 GB 16,383 16 63 MHV2080AH 8.45 GB 16,383 16 63 MHV2060AH 8.45 GB 16,383 16 63 MHV2040AH 8.45 GB 16,383 16 63

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers of the disk drive.

The model name does not necessarily correspond to the product number as listed in Table 1.2 since some models have been customized and have specifications that are different from t ho s e fo r t h e s t an dard m o del .

If a disk drive is ordered as a repl acem ent dri ve, the product number mus t be th e same as that of the dri ve b ei n g rep l aced .

Table 1.2 Examples of mode l names and product numbers

Model Name

MHV2100AH 100GB M3 Depth 3 CA06531-B040/B140 MHV2080AH 80GB M3 Depth 3 CA06531-B048/B148 MHV2060AH 60GB M3 Depth 3 CA06531-B036/B136 MHV2040AH 40GB M3 Depth 3 CA06531-B024/B124

Capacity

(user area)

Mounting screw Order No.

C141-E217 1-5

Device Overview

1.3 Power Requirements

(1) Input Voltage

• + 5 V ± 5 %

(2) Ripple

+5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz

(3) A negative voltage like the bottom figure isn't to occur at +5 V when power is turned

off and, a thing with no ringing.

Permissible level: −0.2 V

Voltage [V]

-1

0 100 200 300 400 500 600 700 800

Time [ms]

Figure 1.1 Negative voltage at +5 V when power is turned off

1-6 C141-E217

1.3 Power Requirements

(4) Current Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation (typical).

Table 1.3 Current and power diss ipation

Typical RMS Current Typical Power (*3)

Spin up (*1) Idle R/W (on track) (*2) Seek (*5) Standby Sleep Energy

Efficiency (*4 )

1.0 A 5.0 W

120 mA 0.60 W

380mA 1.9 W

420 mA 2.1 W

40 mA 0.20 W 20 mA 0.1 W

0.006 W/GB (rank E / MHV2100AH)

0.008 W/GB (rank E / MHV2080AH)

—

0.010 W/GB (rank E / MHV2060AH)

0.015 W/GB (rank D / MHV2040AH)

*1 Maximum current at starting spindle motor. *2 Curren t an d p ow er l ev el wh en t h e o p erat i o n (command) that acco m p an i es a

transfer of 63 sectors is executed 3 times in 100 ms *3 Power requirements reflect typical values for +5 V power. *4 Energy efficiency based on the Law concerning the Rational Use of Energy

indicates the value obtained by dividing power consumption by the storage

capacity. (J ap an o n l y ) *5 The seek average current is specified based on three operations per 100

msec.

C141-E217 1-7

Device Overview

(5) Current fluctuation (Typ.) at +5 V when power is turned on

Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on

(6) Power on/off sequence

The voltage detector circuits monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminate the need to be concerned with the power on/off sequence.

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4 Environmental specifications

Item Specification Temperature

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

5 °C to 55 °C (ambient) 5 °C to 60 °C (d i s k en cl o s ur e s urface) –40 °C to 65 °C 20 °C/h or less

8 % to 90 % RH (Non-condensing) 5 % to 95 % RH (Non-condensing) 29 °C (Operating)

40 °C (Non-operating)

–300 to 3,000 m –300 to 12,000 m

1-8 C141-E217

1.5 Acoustic Noise

Table 1.5 lists the acoustic noise specification.

Table 1.5 Acoustic noise specificati on

Item Specification (typical)

• Idle mode (DRIVE READY) Sound Power 2.8B [MHV2040AH]

2.6B [MHV2100AH/MHV2080AH/MHV2060AH]

Sound Pressure (at 0.3m) 22dB [MHV2040AH]

28dB [MHV2100AH/MHV2080AH/MHV2060AH]

Note: Measure the noise from the cover top surface.

1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6 Shock and vibration specificati on

Item Specification Vibration (Swept sine, 1/4 octave per minute)

• Operating

• Non-operating

5 to 500 Hz, 9.8m/s

0-peak (1G 0-peak)

(without non-recovered errors) 5 to 500 Hz, 49m/s

0-peak (5G 0-peak)

(no damage)

Shock (half-sine pulse)

• Operating

• Non-operating

2940 m/s

0-peak (300G 0-peak) 2ms duration (without non-recovered errors)

8820 m/s

0-peak (900G 0-peak)

1ms duration 1176 m/s

0-peak (120G 0-peak)

11ms duration (no damage)

C141-E217 1-9

Device Overview

1.7 Reliability

(1) Mean time between failures (MTBF)

Conditions of 300,000 h Power-on time 250H/month or less 3000H/years

or less Operating time 20 % or less of power-on time Environment 5 to 55 °C/8 to 90 %

But humidity bulb temperature

29 °C or less MTBF is defined as follows:

Total operation time in all fields MTBF= (H) number of device failure in all fields (*1)

*1 “Disk drive defects” refers to defects that involve repair, readjustment, or

replacement. Disk dri ve d efect s d o n ot include fai l u res cau s ed by ex t ern al fact o rs , such as damage caused by handling, inappropriate operating environments, defects in the power supply host s y st em , or i n terface cabl e.

(2) Mean time to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires no overhaul fo r fi v e y ears wh en t h e DE s u rface t em p erat u re i s l es s t h an 4 8 °C . When the DE su rface t em p erat u re ex ceed s 4 8 °C, the di s k d ri v es req uires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3 ) i n Subsectio n 3 .2 for the meas u rem en t p oint of the DE s u rface temperature. Also th e op erat ing conditions excep t t h e en vironment t em p erat u re are based on the MTBF conditions.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

1-10 C141-E217

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 10 recovery procedure, and include read retries accompanying head offset operations.

(2) Positioning error

bits. Read retries are executed according to the disk drive’s error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 10

seek operations.

1.9 Media Defects

Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory (low level format). Thus, the hosts see a defect-free device.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.

1.10 Load/Unload Function

The Load/Unload function is a mechanism that loads the head on the disk and unloads the head from the disk.

The product supports a minimum of 600,000 Load/Unload cycles. Unload is a normal head unloading operation and the commands listed below are executed.

• Hard Reset

• STANDBY

• STANDBY IMMEDIATE

• SLEEP

• IDLE

C141-E217 1-11

Device Overview

Emergency Unload other than Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Unload cannot be executed. Therefore, the number of Emergency other than Unload is specified.

Remark:

We recommend cutting the power supply of the HDD for this device after the Head Unload operation completes. The recommended power supply cutting sequence for this device is as follows:

1) Disk Flush

Flush Cache command execution.

2) Head Unload

Standby Immediate command execution.

3) Wait Status

Checking whether bit 7 of the status register was set to '0'. (wait to complete STANDBY IMMEDIATE command)

4) HDD power supply cutting

1.11 Advanced Power Management

The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition.

The APM mode can be chosen with a Sector Count register of the SET FEATURES (EF) command.

The disk drive complies with the three kinds of APM modes that a command from the host is required.

FR = 05h : Enable APM

SC = C0h - FEh : SC = 80h - BFh :

Mode-0 Active Idle → Low Power Idle Mode-1 Active Idle → Low Power Idle (Default)

SC = 01h - 7Fh :

FR = 85h : Disable APM (Set Mode-0)

Active Idle: The head is in a position of extreme inner in disk

Low Power Idle: The head is unloaded from disk.

1-12 C141-E217

Mode-2 Active Idle → Low Power Idle → Standby

medium. (VCM Lock)

The spindle motor rotates.

1.11 Advanced Power Management

Standby: The spindle motor stops.

In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle."

Table 1.7 Advanced Power Management

APM Mode

Mode-0 0.2-1.2 sec 15 min. N/A Mode-1 0.2-1.2 sec 10.0-40.0 sec N/A Mode-2 0.2-1.2 sec 10.0-40.0 sec 10.0-40.0 sec

When the maximum time that the HDD is waiting for commands has been exceeded:

Mode-0: Mode shifts from Active condition to Active Idle in 0.2-1.2, and to Low

Power Idle in 15 minutes.

Mode-1: Mode shifts from Active condition to Active Idle in 0.2-1.2 seconds and

to Low Power Idle in 10.0-40.0 seconds.

Mode-2: Mode shifts from Active condition to Active Idle in 0.2-1.2 seconds and

to Low Power Idle in 10.0-40.0 seconds. After 10.0-40.0 seconds in Low Power Idle, the mode shifts to standby.

Active Idle

(VCM Lock)

Low Power Idle

(Unload)

Standby

(Spin Off)

C141-E217 1-13

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CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.

C141-E217 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter.

Figure 2.1 Disk drive outer view

(1) Disk

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm.

(2) Head

The heads are of the load/unload (L/UL) type. The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts.

(3) Spindle motor

The disks are rotated by a direct drive Sensor-less DC motor.

(4) Actuator

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock.

(5) Air circulation syste m

The disk en cl o s u re (DE) is sealed to p rev en t d us t and dirt fro m en t eri n g . T h e d i s k enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.

2-2 C141-E217

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip to improve reliability. The highspeed microprocessor unit (MPU) achieves a high-performance AT controller.

2.2 System Configuration

2.2.1 ATA interface

Figures 2 .2 and 2.3 s h ow t h e ATA i n t erface s y s t em co n fi g u rat i o n . T h e drive has a 44pin PC AT interface connector and s upports P IO m ode 4 trans fer at 16.6 MB/s, Multiword DMA mode 2 transfer at 16.6 MB/s and also U-DMA mode 5 (100 MB/s).

2.2 System Configuration

2.2.2 1 drive connection

Figure 2.2 1 drive system configuration

MHV2100AH MHV2080AH MHV2060AH MHV2040AH

C141-E217 2-3

Device Configuration

2.2.3 2 drives connection

(Host ada pto r )

MHV2100AH MHV2080AH MHV2060AH MHV2040AH

Note: When the drive that is not conformed to ATA is connected to the disk drive above

configuration, the operation is not guaranteed.

Figure 2.3 2 drives configuration

HA (host adapt o r) co ns i s t s o f ad d res s deco d er, d ri v er, and receiver. ATA is an abbrev i at i o n of “AT at t ach m en t ”. The disk d ri v e i s conformed to t he AT A-6 i nterface.

At high-speed data transfer (PIO mode 4 or DMA mode 2 U-DMA mode 5), occurrence of ringing or crosstalk of the signal lines (AT bus) between the HA and the disk drive may be a great cause of the obstruction of system reliability. Thus, it is necess ary t h at t h e capacitance of the signal lines including the HA and cable does not exceed the ATA-6 s t and ard , and the cable l en g t h bet w een the HA and the disk drive should be as short as possible.

No need to push the top cover of the disk drive. If the over-power worked, the cover could be contacted with the spindle motor. Thus, that could be made it the cause of failure.

2-4 C141-E217

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.4 Jumper Settings

This chapt er g i v es t h e ex t ern al d i m en s i o n s , install at i o n con d i t ions, s urface temperature conditions, cable connections, and switch settings of the hard disk drives.

For information about handling this hard disk drive and the system installation procedure, refer to the following Integration Guide. C141-E144

C141-E217 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive and positions of the mounting screw holes. All dimensions are in mm.

Figure 3.1 Dime nsions

3-2 C141-E217

3.2 Mounting

For information on m ounti ng, see the "FUJITS U 2. 5-INC H HDD INTEGRATION GUIDANCE (C141-E144)."

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

3.2 Mounting

gravity

(a) Horizontal – 1

(b) Horizontal –1

(d) Vertical –2

gravity

(e) Vertical –3

Figure 3.2 Orientation

C141-E217 3-3

(f) Vertical –4

Installation Conditions

(2) Frame

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connect ed t o SG.

Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3.

The tightening torque must be 0.49N•m (5kgf•cm). When attaching the HDD to t h e sy s tem fram e, do not al l ow t h e

system frame to touch parts (cover and base) other than parts to which the HDD is attached.

(3) Limitation of mounting

Note) These dimensions are recommended values; if it is not possible to satisfy

them, co n t act u s .

Bottom surface m ount i ng

Frame of sy s t em cabinet

3.0 or less

2.5

Frame of sy s t em cabinet

Screw

3.0 or less

Details of A

Details of B

Figure 3.3 Mounting frame structure

Side surface mounting

PCA

Screw

2.5 2.5

3-4 C141-E217

3.2 Mounting

Because of breather hole mounted to the HDD, do not allow this to close during mounting.

Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around

φ 2.4 to block.

Figure 3.4 Location of breather

C141-E217 3-5

Installation Conditions

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a po int 3 cm from the disk d ri v e. The ambien t t emperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be co ns idered to preven t the DE surface tem perature from exceedi n g 6 0 °C.

Provide ai r circulation i n t h e cab i n et s u ch t h at t h e P CA side, i n p art i cu l ar, receives sufficient co o l i n g . To check the co o l i n g effi ci en cy , measure th e s urface temperatures o f t h e DE . Regardless o f t h e am b i en t t em p erat u re, this su rface temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the temperatur e m eas u rem en t p o i n t .

•

Figure 3.5 Surface temperature measurement points

Table 3.1 Surface temperature measurement points and standard values

No. Measurement point Temperature

1 DE cover 60 °C max

3-6 C141-E217

(5) Service area

Figure 3.6 shows h o w t h e d ri v e m u s t b e acces s ed (s ervice areas) during an d after installation.

3.2 Mounting

Mounting screw hole

Cable connection

Mounting screw hole

Figure 3.6 Service area

Data corruption: Avoid mounting the disk drive near strong

magnetic sources such as loud speakers. Ensure that the disk drive is not affect ed b y ex t ern al m ag n et i c fi elds. Damage: Do not press the cover of the disk drive. Pressing it too hard, the cover and the spindle motor contact, which may cause damage to the disk drive.

Static: When handling the device, disconnect the body ground (500 kΩ or greater). Do not touch the printed circuit board, but hold it by the edges.

(6) Handling cautions

Please keep the following cautions, and handle the HDD under the safety environment.

C141-E217 3-7

Installation Conditions

ying

- General notes

ESD mat

Wrist strap

Use the Wrist strap.

Do not hit HDD each other. Do not stack when carr

Do not place HDD verticall

to avoid falling

Shock absorbing mat

Place the shock absorbing mat on the operation table, and place ESD mat on it.

Do not dro

Figure 3.7 Ha ndling cautions

- Installation

(1) Please use the drive r of a low im pa ct when you use a n el e ct ri c dri ve r.

HDD is occasionally damaged by the impact of the driver.

(2) Please observe the t i ghte ni ng torque of t he scre w stric tl y.

M3 ······· 0.49N•m (5 kgf•cm).

- Recommende d e qui pm e nt s

Contents Model Maker

Wrist strap JX-1200-3056-8 SUMITOMO 3M ESD ESD mat SKY-8A (Color Seiden Mat) Achilles

Shock Low shock driver SS-6500 HIOS

3-8 C141-E217

3.3 Cable Connections

3.3.1 Device connector

The disk drive has the connectors and terminals listed below for connecting external devices. Fi gure 3.8 shows the locations of these connectors and terminals.

3.3 Cable Connections

Connector, setting pins

PCA

Figure 3.8 Connector locations

C141-E217 3-9

Installation Conditions

3.3.2 Cable connector specifications

Table 3.2 l i s t s the recommend ed s pecifications fo r t h e cab l e co n nectors.

Table 3.2 Cable connector specifications

Name Model Manufacturer

ATA interface and po wer supply cable (44-pin type)

For the host i nt erface cabl e, use a ri bbon cabl e. A t wi s t ed cable or a cable with wires that have become separated from the ribbon may cause crosst al k b et ween s i g n al lines. T his is becaus e t h e interface is designed for ribbon cables and not for cables carrying differential signals.

3.3.3 Device connection

Figure 3.9 shows how to connect the devices.

Host system

Cable sock et

(44-pin type)

ATA-cable

89361-144 FCI

Disk Drive #0

ATA-cable

DC Power supply

Power supply cable

Disk Drive #1

Figure 3.9 Cable connections

3-10 C141-E217

3.3.4 Power supply connector (CN1)

Figure 3.10 shows the pin assignment of the power supply connector (CN1).

3.4 Jumper Settings

Figure 3.10 Power supply connector pins (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

Figure 3.11 shows the location of the jumpers to select drive configuration and functions.

Figure 3.11 Jumper location

C141-E217 3-11

Installation Conditions

3.4.2 Factory default setting

Figure 3.12 shows the default setting position at the factory.

Open

Figure 3.12 Factory defaul t setting

3.4.3 Master drive-slave drive setting

Master drive (disk drive #0) or slave drive (disk drive #1) is selected.

Open

AC1

Short

BD2

(b) Slave drive(a) Master drive

Figure 3.13 Jumper setting of master or slave drive

Note: Pins A and C should be open.

3-12 C141-E217

3.4.4 CSEL setting

Figure 3.14 shows the cable select (CSEL) setting.

Open

AC1

BD2

Short

Note: The CSEL setting is not depended on setting between pins Band D.

3.4 Jumper Settings

Figure 3.14 CSEL setting

Figure 3 . 1 5 an d 3 . 1 6 s h o w ex am p l es o f cab l e s election us i n g u n i q u e i n t erface cables.

By connecting the CSEL of the master drive to the CSEL Line (conducer) of the cable and connecting it to ground further, the CSEL is set to low level. The drive is identified as a master drive. At this time, the CSEL of the slave drive does not have a conductor. Thus, since the slave drive is not connected to the CSEL conductor, the CSEL is set to high level. The drive is identified as a slave drive.

drive drive

Figure 3.15 Example (1) of cable select

C141-E217 3-13

Installation Conditions

drive drive

Figure 3.16 Example (2) of cable select

3.4.5 Power up in standby setting

When pin C is grounded, the drive does not spin up at power on.

3-14 C141-E217

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.6 Read/write Circuit

4.7 Servo Control

This chapt er ex p l ai n s b as i c d es i g n co n cep t s o f t h e d i s k drive. Also , this chap t er explains s u bas s emblies of t h e disk drive, each sequence, s erv o co n t ro l , and electrical ci rcu i t b l o ck s .

C141-E217 4-1

Theory of Devi ce Op er ation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.4.

The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details, see Sections 4.3.

4.2.1 Disk

The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm.

Servo data is recorded on each cylinder (tot al 134). Servo data written at factory is read out by the read head. For servo data, see Section 4.7.

4.2.2 Spindle

The spind l e co n s i s ts of a disk s tack assembl y an d s p i n d l e m o t o r. The disk s t ack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.

4.2.3 Actuator

The actuator co n s i s t s o f a v oi ce co i l motor (VCM ) an d a h ead carri age. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is d et ect ed an d repr od u ced from the servo i n formation read b y the read/writ e head.

4-2 C141-E217

4.2.4 Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk.

4.3 Circuit Configuration

Figure 4.1 shows the power supply configuration of the disk drive, and Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

4.3 Circuit Configuration

The read/write circuit consists of two circuits; read/write preamplifier (PreAMP) and read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the Modified Extended Partial Response (MEEPR), and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, data separator circuits, RLL (Run Length Limited) encoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by closed-loop servo using th e s erv o i nfo rm ation recorded o n t he d at a s u rface. The servo in formation is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor.

The MPU preci s el y s et s each head o n t h e t rack acco rding on the s erv o i n formation on the med i a s u rface.

(3) Spindle motor driver circuit

The circuit measures the interval of a PHASE signal generated by counterelectromotive voltage of a motor and controls the motor speed comparing target speed.

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Theory of Device Operation

(4) Controller circuit

Major functions are listed below.

• ATA interface control and data transfer control

• Data buffer management

• Sector format control

• Defect management

• ECC control

• Error recovery and self-diagnosis

Figure 4.1 Power supply configuration

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PCA

4.3 Circuit Configuration

ATA Interface

Data Buffe r

SDRAM

Serial

Flash ROM

SVC

TLS2291A

Shock

Sensor

Resonator

20MHz

MCU & HDC & RDC

88i6632

MCU

HDC

RDC

SP Motor

Media

VCM

HEAD

Thermisto

Figure 4.2 Circuit configuration

R/W Pre-Amp

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Theory of Devi ce Op er ation

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below.

a) After the power i s t u rn ed o n , the disk drive executes t he M PU bus test ,

internal register read/write test, and work RAM read/write test. When the self-diagnosis term i nat es s ucces s full y , t h e di s k dri ve s t art s t he s pi ndl e m o t or.

b) The disk drive executes self-diagnosis (data buffer read/write test) after

enabling response to the ATA bus.

c) After confirming that t h e s p i n dle motor has reach ed rated speed, t h e h ead

assembly is loaded on the disk.

d) The disk drive positions the heads onto the SA area and reads out the system

information. e) The drive beco m es read y . The host can i s s u e co m m an d s . f) The disk drive executes self -calibration. This collects data for VCM torque

and mechanical external forces applied to the actuator, and updates the

calibrating value.

Power-on

Start

Self-diagnosis 1

- MPU bus test

- Internal register write/read test

- Work RAM write/read test

The spindle motor starts.

Self-diagnosis 2

- Data buffer write/read test

Confirming spindle motor speed

Load the head assembl

Initial on-track and read out of system information

Drive ready state (command waiting state)

Execute self-calibration

End

Figure 4.3 Pow er-on operation seque nce

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4.5 Self-calibration

The disk d ri v e occas ionally perfo rm s s el f-cal ibration i n o rder t o s en s e an d calibrate mech an i cal ex t ern al fo rces on t h e act u at o r, and VCM to rq u e. T h i s enables preci s e s eek an d read / w ri t e o p erat i o n s .

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator s u ffers from torque due to the FPC forces an d wi n ds acco m p an yi n g disk revolution. The torque varies with the disk drive and the cylinder where the head is pos itioned. To execute stable fast seek o p erat i o n s , ex t ern al fo rces are occasional l y s en s ed .

The firmware of t h e drive measures an d s t o res t h e force (v al u e o f t h e act u at o r motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power am p l i fi er ci rcu i t an d DAC s y s t em .

The forces are comp en s at ed b y ad d i n g t h e m eas u red v al ue to the speci fi ed cu rren t value to the power amplifier. This makes the stable servo control.

4.5 Self-calibration

To compensate torque varying by the cylinder, the disk is divided into 13 areas from the innermost to the outermost circumference and the compensating value is measured at the measurin g cy l i n d er o n each area at factory cali b rat i o n . The measured val u es are s t o red i n t h e S A cylinder. In the self-cali bration, t h e compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque const an t v al u e of the VCM has d i s pers ion for each driv e, and varies depending on the cylinder that the head is positioned. To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and t he s table servo co ntrol is real i zed .

To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 13 partitions at calibration in the factory, and the compensation data is measured for representati v e cy l i n d er o f each par tition. This measured value is stored in the SA area. The comp en s at i o n v al u e at s el f-calibratio n is calculat ed u s ing the val u e i n the SA area.

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Theory of Devi ce Op er ation

4.5.2 Execution timing of self-calibration

Self-calibration is performed once when power is turned on. After that, the disk drive does not perform self-calibration until it detects an error.

That is, s el f-calibration i s p erformed each time one of the following events occur:

• When it passes from the power on for about 10 seconds except that the disk

drive shifts to Idle mode, Standby mode, and Sleep mode by execution of any

commands.

• The num ber o f ret r i es t o wri t e o r s eek d at a reaches the specified v al u e.

• The error rate of data reading, writing, or seeking becomes lower than the

specified v al u e.

4.5.3 Command processing during self-calibration

This enables the host to execute the command without waiting for a long time, even when the d i s k dr i v e i s p erform ing self-cali b rat i o n . The command ex ecu t i o n wait time is about maximum 72 ms.

When the error rate o f d at a read i n g, writing , or seeking beco m es l o wer t h an t h e specified value, self-calibration is performed to maintain disk drive stability.

If the disk drive receives a com m an d ex ecu t i o n req ues t fro m the host while performing self-calibration, it stops the self-calibration and starts to execute the command. In other words, i f a d i s k read o r wri t e s erv i ce i s n eces sary , the disk drive positions the head to the track requested by the host, reads or writes data, and then restarts calibration after about 3 seconds.

If the error rate recovers t o a v al u e ex ceedi n g t h e s p eci fi ed v al ue, self-calib rat i o n is not performed.

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4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

PreAMP equ i p s a read preamplifier and a wri te current switch, that s et s t h e b i as current to t h e M R d ev i ce an d t h e curren t in writin g. Each channel i s co n nected to each data head, an d PreAMP swi t ch es ch an n el b y s eri al I/O. In th e ev ent of any abnormalities, including a head short-circuit or head open circuit, the write unsafe signal is generated so that abnormal write does not occur.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) and sent to the RDC. The write data is sent to the PreAMP as differential signal, and the data is written onto the media.

4.6 Read/write Circuit

(1) Write precompensation

Write precompensation compensates, during a write process, for write nonlinearity generated at reading.

Figure 4.4 Read/write circuit block diagram

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Theory of Devi ce Op er ation

4.6.3 Read circuit

The head read si g nal from the P reAM P is regulated b y t h e automatic gai n co n t ro l (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This signal is converted into the read data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintai ned at a co n s t an t l ev el ev en wh en t h e head o u t p u t fl u ct u at es d u e t o t h e head characteris t i cs o r o u t er/ i n n er h ead p o s i t ions.

(2) Programmable filter circuit

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

-3 dB

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the register in read channel block. The MPU optimizes the cut-off frequency and boost-up gain according to the t rans fer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmable filter.

Figure 4.5 Frequency characteristic of programmable filter

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(3) FIR circuit

This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform.

(4) A/ D c onverter circuit

This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.

(5) Viterbi detection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection ci rcuit . The Viterbi detection ci rcui t demodul at es dat a according to the survivor path sequence.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cy l i n d er of each zo n e i s n earl y co nstant. T he d rive divid es d at a area i n t o 30 zones to set the data transfer rate.

4.6 Read/write Circuit

The MPU set the data transfer rate setup data (SD/SC) to the RDC that includes the Digital PLL circuit to change the data transfer rate.

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Theory of Devi ce Op er ation

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is con t ro l l ed acco rdi n g t o t h e s ervo d at a t hat is written on the data side beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following describes the functions of the blocks:

(1)

MPU/HDC/RDC

(2)

Head

Servo burst capture

Position Sense

CSR: Current Sense Resister VCM: Voice Coil Motor

Figure 4.6 Block diagram of servo control circuit

MPU core

(3)

(5)

DAC

Spindle motor control

SVC

(4)

Power Amp

(6)

Driver

(7)

VCM

CSR

VCM

Spindle motor

4-12 C141-E217

(1) Microproce ssor unit (MPU)

The MPU executes startup o f t h e s p i n dle motor, m o v em ent to the reference cylinder, seek to the specified cylinder, and calibration operations.

The main internal operations of the MPU are shown below.

a. Spindle motor start

Starts t h e s p i n dle motor and accel erat es i t to normal s p eed wh en p o wer i s applied.

b. Move head to reference cylinder

Drives the VC M to posit i o n t h e head at the any cyli nd er i n t h e d at a area. The logical initial cylinder is at the outermost circumference (cylinder 0).

c. Seek t o s pecified cylin d er

Drives the VC M t o p o s i t i o n t he h ead t o t h e s p eci fi ed cylinder.

d. Calibration

4.7 Servo Control

Senses and s t o res the thermal o ffs et b et w een head s an d t h e m ech an i cal fo rces on the actuator, and stores the calibration value.

(2) Servo burst capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate the head pos i t ion from th e s ervo d at a o n t h e data surface. Fro m the servo area on the data area surface, via the dat a head , the burst si g n al s of EVEN1 , ODD, EVEN2 are output as shown in Figure 4.8 in subsequent to the servo mark, gray code that indicates the cylinder position, and index information. The servo signals do A/D-convert by Fourier-demodulator in the servo burst capture circuit. At that time the AGC circuit is in hold mode. The A/D converted data is recognized by the MPU as position information.

(3) D/A c onverter (DAC)

The control program calculates the specified data value (digital value) of the VCM drive current, and the value is converted from digital-to-analog so that an analog output voltage is sent to the power amplifier.

(4) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.

(5) Spindle mo tor cont rol circuit

The spindle motor control circuit controls the sensor-less spindle motor. A spindle driver IC with a built-in PLL(FLL) circuit that is on a hardware unit controls the sensor-less spindle motor.

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Theory of Devi ce Op er ation

(6) Driver circuit

The driver circu i t is a power am plitude circu i t that receives s ignals from t h e spindle motor control circuit and feeds currents to the spindle motor.

(7) VCM c urrent sense resi s tor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.

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4.7.2 Data-surface servo format

Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below.

(1) Inner guard band

This area is l o cat ed i n s i d e t h e us er area, and the rot ational sp eed o f t h e VC M can be controlled on this cylinder area for head moving.

(2) Data area

This area is u s ed as the user dat a area SA area.

(3) Outer guard band

This area is l o cat ed at o u t er p o s i t i o n o f t h e u s er d at a area, and the rot at i o n al s p eed of the spindle can be controlled on this cylinder area for head moving.

4.7 Servo Control

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Theory of Devi ce Op er ation

area

Servo frame (134 servo frames per

IGB

Data area

expand

OGB

CYLn +

CYLn CYLn –1 (n: even number)

Diameter

W/R Recovery

Servo Mark Gray Code

W/R Recovery Servo Mark Gray Code

direction

EVEN1

ODD

Circumference

Direction

EVEN2

PAD

Erase: DC erase

Figure 4.7 Physical sector servo configuration on disk surface

4-16 C141-E217

4.7.3 Servo frame format

As the servo information, the IDD uses the phase signal servo generated from the gray code and servo EVEN and ODD. This servo informati on is used for positioning operation of radius direction and position detection of circumstance direction.

The servo frame consists of 5 blocks; write/read recovery, servo mark, gray code, Burst EVEN1, Burs t ODD, Burst EVEN2, and PAD. Figure 4.8 shows th e servo frame format.

4.7 Servo Control

Write/read recovery

(1) Write/read recovery

This area is us ed t o ab s o rb the write/read transient an d t o s t ab i l i ze t h e AGC.

(2) Servo mark

This area generates a timing for demodulating the gray code and positiondemodulating the burst signal by detecting the servo mark.

(3) Gray code (including sector address bits)

This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit

Servo

mark

Gray code Burst

Figure 4.8 Servo frame format

EVEN1

Burst ODD

Burst EVEN2

PAD

(4) Burst Even1, Burst Odd, Burst Even2

These areas are used as p os i tion sig n al s b et ween t rack s an d the IDD control s o that target phase signal is generated from Burst Even and Burst Odd.

(5) PAD

This area is used as a gap between servo and data.

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Theory of Devi ce Op er ation

4.7.4 Actuator motor control

The voice coi l m o t o r (VC M ) is control l ed by feed i n g back t h e s erv o dat a reco rd ed on the data s u rface. The MPU fetch es t h e po sition sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive cu rrent .

The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek op erat i o n t o m o v e t h e head t o t h e t arg et cy l i n d er t o read or write data, and the track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU mo ves the head to th e referen ce cy l i n d er when t h e p ow er i s t u rn ed. The reference cylinder is in the d at a area.

When power is applied the heads are moved from the outside of media to the normal servo data zone in the following sequence:

a) Micro current i s fed t o t h e VC M t o p res s t h e head ag ai n s t t h e o u t er d i rect i o n . b) T h e h ead i s l o ad ed o n the disk. c) When the servo m ark i s d et ect ed t h e h ead is moved s l ow l y t o ward t he inner

circumference at a co n s t an t s p eed . d) If the head is stopped at the reference cylinder from there. Track following

control starts.

(2) Seek operation

Upon a data read/write request from t h e host , the MPU confirms t he neces s i ty of access to th e d i s k. If a read/write instructi o n i s i s s u ed , the MPU seeks t h e d es i red track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head . The MPU cal culates the di fferen ce (s p eed erro r) b et ween t h e specified t arg et p os ition and t h e curren t p o s i t i o n fo r each s am p l ing timing during head movin g . The MPU th en feeds the VCM driv e cu rren t b y s et t ing the calculated result into the D/A converter. The calculation is digitally executed by the firmware. Wh en t h e head arri v es at t h e t arg et cy l i n d er, the track is fo l l o wed .

(3) Track following operation

Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed, the MPU does track following control. To positi o n t h e h ead at the center of a t rack , the DSP d ri v es t h e VC M b y feed i n g micro current . For each sampl i n g time, the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data. The filtering includes servo compensation. These are digitally controlled by the firmware.

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4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3phase full/half-wave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to t he SVC. There are t h ree m o d es for the spindl e co n t ro l ; s t art mode, acceleration m o d e, and stabl e ro t at ion mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge

the charge pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC to

the motor start mode. Then, a current (approx. 0.3 A) flows into the spindle motor.

c) A phase switching signal is generated and the phase of the current flowed in

the motor is changed in the order of (V-phase to U-phase), (W-phase to Uphase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that, repeating this order).

4.7 Servo Control

d) During phase switching, the spindle motor starts rotating in low speed, and

generates a counter electromotive force. The SVC detects this counter electromot i v e fo rce and rep orts to the M P U u s i n g a P HASE signal fo r s p eed detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a

specific period, the MPU resets the SVC and starts from the beginning. When a PHASE s i g n al i s s en t , the SVC en t ers t h e accel erat i o n m o d e.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rot at i o n o f t h e s pindle mot o r accel erat es . The MPU cal cu l at es a ro t at i o n al speed of the spindle motor based on the PHASE signal from the SVC, and waits till the rotational speed reaches 5,400 rpm. When t he rot at i onal sp eed reaches 5,400 rpm, the SVC enters the stable rotation mode.

(3) Stable rotation mode

The SVC builds the FLL/PLL circuit into, and to become the rotational speed of the target, controls a stable rotation with hardware.

The firmware calculates time of one rotation from PHASE signal. PHASE signal is outputted from the SVC. And the firmware observes an abnormal rotation.

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CHAPTER 5 Interface

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Ultra DMA Feature S et

5.6 Timing

This chapter gives detail s about t he i n terface, and t h e i nt erface comm ands and timings.

C141-E217 5-1

Interface

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows t h e i n t erface s i g n al s .

Host

DATA 0-15: DATA BUS

DMACK-: DMA ACKNOWLEDGE

DMARQ: DMA REQUEST INTRO: INTERRUPT RE

DIOW-: I/O WRITE STOP: STOP DURING ULTRA DMA DATA BURSTS

DIOR-:I/ O READ HDMARDY:DMA READY DURING ULTRA DMA DATA IN BURSTS HSTROBE:DATA STROBE D URING ULT RA DMA DATA OUT BURST

PDIAG-: PASSED DIAGNOSTICS CBLID-: CABLE TYPE IDENTIFIER DASP-: DEVICE ACTIVE/SLAVE PRESENT

IORDY:I/O READY DDMARDY:DMA READY DURING ULTRA DMA DATA OUT BURSTS DSTROBE: DATA STROBE DURING ULTRA DMA DATA IN BURSTS

DA 0-2: DEVICE ADDRESS CS0-: CHIP SELECT 0 CS1-: CHIP SELECT 1

RESET-: RESET CSEL: CABLE SELECT

MSTR: Master ENCSEL: ENABLE CSEL

+5V DC: +5 vol

GND: GROUND

UEST

IDD

Figure 5.1 Interface signals

5-2 C141-E217

5.1.2 Signal assignment on the connector

Table 5.1 shows the si gnal as si gnm ent on th e i nt erface connector.

Table 5.1 Signal assignment on the interface connector

Pin No. S ignal Pin No. Signal

5.1 Physical Interface

A C E

1 3 5 7

9 11 13 15 17 19 21 23 25

MSTR PUS(KEY) RESET– DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND DMARQ DIOW-, STOP DIOR-, HDMRDY,

HSTROBE

F 2 4 6

8 10 12 14 16 18 20 22 24 26

MSTR/ENCSEL ENCSEL (KEY) GND DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 (KEY) GND GND GND

29 31 33 35 37 39 41 43

C141-E217 5-3

IORDY, DDMARDY, DSTROBE

DMACK– INTRQ DA1 DA0 CS0– DASP– +5 VDC GND

30 32 34 36 38 40 42 44

CSEL

GND Reserved (IOCS 16 -) PDIAG–, CBLID– DA2 CS1– GND +5 VDC Unused

Interface

[Signal] [I/O] [Description]

ENCSEL I This signal is used to set master/sla ve using the CSEL signal (pin 28).

Pins B and D Open: Sets master/slave using the CSEL signal is

disabled.

Short: Sets master/slave using the CSEL signal is

enabled.

MSTR- I MSTR, I, Master/slave setting

Pin A, B, C, D open: Master setting

Pin A, B Short: Slave setting PUS- I When pin C is grounded, the drive does not spin up at power on. RESET- I Reset signal from the host. This signal is low active and is asserted

for a minimum of 25 µs during power on. DATA 0-15 I/O Sixteen-bit bi-directional data bus between the host and the device.

These sign al s are u s ed for d at a t r ans fer DIOW- I Signal asserted by the host to write to the device register or data port. STOP I DIOW- must be negated by the host before starting the Ultra DMA

transfer. The STOP signal must be negated by the host before data is

transferred during the Ultra DMA transfer. During data transfer in

Ultra DMA mode, the assertion of the STOP signal asserted by the

host lat er i n d i cates that t he transfer has been s u s pen d ed . DIOR- I Read strobe signal from the host to read the device register or data

port HDMARDY- I Flow control s i gn al for Ul t ra DM A d ata In t rans fer (R EAD DM A

command). This signal is asserted by the host to inform the device

that the h os t is ready to recei ve t h e Ul tra DMA data In tran sf er. T h e

host can negate the HDMARDY- signal to suspend the Ultra DMA

data In transfer. HSTROBE I Data Out Strobe signal from the host during Ultra DMA data Out

transfer (WRITE DMA command). Both the rising and falling edges

of the HSTROBE signal latch data from Data 15-0 into the device.

The host can suspend the inversion of the HSTROBE signal to

suspend the Ultra DMA data Out transfer. INTRQ O Interrupt signal to the host.

This signal is negated in the following cases:

− Assertion of RESET- signal

− Reset by SRST of the Device Control register

− Write to the command register by the host

− Read of the status register by the host

− Completion of sector data transfer

(without reading the Status register)

The signal output line has a high impedance when no devices are

selected or interruption is disabled.

5-4 C141-E217

5.1 Physical Interface

[Signal] [I/O] [Description] CS0- I C hip select signal decoded from the host address bus. This signal

is used by the host to select the command block registers.

CS1- I C hip select signal decoded from the host address bus. This signal

is used by the host to select the control block registers.

DA 0-2 I Bin ary d ecod ed add res s s i g n al s as s ert ed b y t he h o s t t o acces s t as k

file registers. KEY - Key pin for prevention of erroneous connector insertion PDIAG- I/O This signal is an input mode for the master device and an output

mode for the slave device in a daisy chain configuration. This

signal indicates that the s l av e dev ice has been com p l et ed s el f -

diagnostics.

This signal is pulled up to +5 V through 10 kΩ resistor at each device. CBLID- I/O This signal is used to detect the type of cable installed in the

system.

This signal is pulled up to +5 V through 10 kΩ resistor at each device. DASP- I/O This is a time-multiplexed signal that indicates that the device is

active and a s l av e d ev i ce i s p r es ent.

This signal is pulled up to +5 V through 10 kΩ resistor at each device. IORDY O This signal requests the host system to delay the transfer cycle

when the device is not ready to respond to a data transfer request

from the host system. DDMARDY- O Flow control s i gnal for Ul t ra DM A data Out t ransfer (WR ITE

DMA command). This signal is asserted by the device to inform

the host that the device is ready to recei v e t he Ultra DMA data

Out transfer. T he d evi ce can n egat e t h e DDM AR DY- s i g nal t o

suspend the Ultra DMA data Out transfer. DSTROBE O Data In Strobe signal from the device during Ultra DMA data In

transfer. Both the rising and falling edges of the DSTROBE

signal latch data from Data 15-0 into the host. The device can

suspend the inversion of the DSTROBE signal to suspend the

Ultra DMA data In transfer. CSEL I This si g n al t o co n fi g u re t h e d ev i ce as a m as t er o r a s lave device.

− When CSEL signal is grounded, the IDD is a master device.

− When C SEL signal i s o p en , the IDD is a slav e d ev i ce.

This signal is pulled up with 240 kΩ resistor at each d evice. DMACK- I The host system asserts this signal as a response that the host

system receives data or t o i n d i cate that dat a i s v al i d .

C141-E217 5-5

Interface

[Signal] [I/O] [Description]

DMARQ O This signal is used for DMA transfer between the host system and

the device. T h e d evice asserts t his signal wh en t h e dev i ce completes the preparation of DMA data transfer to the host system (at reading) or from the host system (at writing).

The direction of data transfer is controlled by the DIOR and DIOW signals. This signal hand shakes with the DMACK-signal. In other words, the device negates the DMARQ signal after the host sys t em as s ert s t h e DMACK signal. Wh en t h ere i s ot h er d at a to be transferred , the device as s ert s the DMARQ sig n al again.

When the DMA dat a t rans fer is performed, IOC S16-, CS 0 - an d CS1- si g nal s are n o t as s ert ed. The DMA data t ran sf er i s a 16 -b i t

data transfer. +5 VDC I +5 VDC power supplying to the device. GND - Grounded si gnal at each s i gnal wire.

Note:

“I” indicates input signal from the host to the device.

“O” indicates output signal from the device to the host.

“I/O” indicates common output or bi-directional signal between the host

and the device.

5.2 Logical Interface

The device can o perate for command execu t ion in eit h er ad d res s -s p eci fi ed m o d e; cylinder-head-sector (CHS) or Logical block address (LBA) mode. The IDENTIFY DEVICE information indicates whether the device supports the LBA mode. When the host system specifies the LBA mode by setting bit 6 in the Device/Head regi s t er t o 1, HS3 to HS 0 b i t s o f t h e Dev i ce/ Head register indi cat es the head No. under the LBA mode, and all bits of the Cylinder High, Cylinder Low, and S ect or Nu m b er reg i s t ers are LB A b i t s .

The sector No. under the LBA m ode proceeds i n t h e ascendi ng order wi t h th e s tart point of LBA0 (defined as follows).

LBA0 = [Cylinder 0, Head 0, Sector 1]

Even if th e h o s t s y s t em ch an g es t h e as s i g n m en t of the CHS mode by t h e INITIALIZE DEVICE PARAMETER command, th e sector LBA address is not changed.

LBA = [((Cylin der No.) × (Number of head ) + (Head No . )) × (Number of sector/track )] + (S ector No.) − 1

5-6 C141-E217

5.2.1 I/O registers

Communication between the host system and the device is done through inputoutput (I/O) registers of the device.

These I/O registers can be selected by the coded signals, CS0-, CS1-, and DA0 to DA2 from the host system. Table 5.2 shows the coding address and the function of I/O registers.

5.2 Logical Interface

Table 5.2 I/O registers

I/O registers

DA0 DA1 DA2 CS1– CS0–

Read operation Write operation

Command block registers

L H L L L Data Data X’1F0’ L H L L H Error Register Features X’1F1’ L H L H L Sector Count Sector Count X’1F2’ L H L H H Sector Number Sector Number X’1F3’ L H H L L Cylinder Low Cylinder Low X’1F4’ L H H L H Cylinder High Cylinder High X’1F5’ L H H H L Device/Head Device/Head X’1F6’ L H H H H Status Command X’1F7’ L L X X X (Invalid) (Invalid) —

Control block registers

H L H H L Alternate Status Device Control X’3F6’ H L H H H — — X’3F7’

Host I/O

address

Notes:

1. T he Data register for read or write operatio n can b e acces s ed b y 1 6 b i t d at a bus (DATA0 to DATA15).

2. The registers for read or write operation other than the Data registers can be accessed by 8 bit d ata b us (DATA0 t o DAT A7).

3. Wh en read i n g the Drive Addres s reg i s t er, bit 7 i s high-imped an ce s t at e.

4. H indicates signal level High and L indicates signal level Low.

There are two methods for specifying the LBA mode. One method is to

specify the LBA mode with 28-bit address information, and the other is to specify it with 48-bit address information (command of EXT system). If the LBA mode is specified with 28-bit address information, the Device/Head, Cylinder High, Cylinder Low, Sector Number registers

C141-E217 5-7

Interface

indicate LBA bits 27 to 24, bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively.

If the LBA mode is specified with 48-bit address information, the Cylinder

High, Cy l i n d er Lo w, Sector Number reg i s t ers are s et twice. In th e fi rs t time, the registers indicate LBA bits 47 to 40, bits 39 to 32, and bits 31 to 24, respectively. In the second time, the registers indicate LBA bits 23 to 16, bits 15 to 8, and bits 7 to 0, respectively.

5.2.2 Command block registers

(1) Data register (X’1F0’)

The Data register is a 16-bit register for data block transfer between the device and the host system. Data transfer mode is PIO or DMA mode.

(2) Error register (X’1 F1’)

The Error regis t er i n d i cat es t h e s t atus of the co m m an d ex ecuted by the dev i ce. The content s o f t h i s reg i s t er are v al i d wh en t h e ER R bit of t h e S t atus regist er i s 1 .

This register contains a diagnostic code after power is turned on, a reset, or the EXECUTIVE DEVICE DIAGNOSTIC comm and is executed.

[Status at the completion of command execution other than diagnostic command]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ICRC UNC X IDNF X ABRT TK0NF AMNF

X: Unused

- Bit 7: Interface CRC Error (ICRC). This bit indicates that a CRC error occurred during Ultra DMA transfer.

- Bit 6: Uncorrectable Data E rror (UNC). This b i t i n d i cat es t h at an uncorrectable data error has been encountered.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad sector, uncorrectable error and SB not found.

- Bit 3: Unused

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not R eady, Write Fault) or the command code was invalid.

5-8 C141-E217

5.2 Logical Interface

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred.

[Diagnostic code]

X’01’: No Error Detected. X’02’: HDC Diagnostic Error X’03’: Data Buffer Diagnostic Error. X’04’: Memory Diagnostic Error. X’05’: Reading the system area is abnormal. X’06’: Calibration is abnormal. X’80’: Device 1 (slave device) Failed.

Error register of the master device is valid under two devices (master and slave) con figuration . If the slave d ev i ce fai ls, the m as t er d ev i ce posts X’80’ OR (the diagnostic code) with its own status (X’01’ to X’06’).

However, when the host system selects the slave device, the diagnostic code of the slave device is posted.

(3) Features register (X’1F1’)

The Features reg i s t er p ro v i d es s p eci fi c feat u re to a command . For ins t an ce, it is used with SET FEATUR ES command t o enab l e o r d i s able caching.

(4) Sector Count register (X’1F2’)

The Sector Count register indicates the number of sectors of data to be transferred in a read or writ e o p erat i o n b et ween t h e h o s t s y s t em an d t h e d evice. When th e value in this register is X’00’, the sector count is 256. With the EXT system command, the sector count is 65536 when value of this register is X'00' in the first setting and X'00' in the second setting.

When this reg i s t er i n d i cat es X’0 0 ’ at the complet ion of the co m m an d execu tion, this indicates that the command is completed successfully. If the command is not completed successfully, this register indicates the number of sectors to be transferred to complete the request from the host system. That is, this register indicates the number of remaining sectors that the data has not been transferred due to the erro r.

The contents of this register have other definition for the following commands; INITIALIZE DEVICE PARAMETERS , S ET FEATURES, IDLE, S T ANDBY and SET MULTIPLE MODE.

C141-E217 5-9

Interface

(5) Sector Number register (X’1F3’)

The contents of this register indicate the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this register indicates LBA bits 7 to 0.

Under the LBA mode of the EXT system command, LBA bits 31 to 24 are set in the first setting, and LBA bits 7 to 0 are set in the second setting.

(6) Cylinder Low register (X’1F4’)

The contents of this register indicate low-order 8 bits of the starting cylinder address for any d i s k-acces s .

At the end of a command, the contents of this register are updated to the current cylinder number.

Under the LBA mode, this register indicates LBA bits 15 to 8.

Under the LBA mode of the EXT system command, LBA bits 39 to 32 are set in the first setting, and LBA bits 15 to 8 are set in the second setting.

(7) Cylinder High register (X’1F5’)

The content s o f t h i s reg i s t er indicate hi g h -o rd er 8 b i ts of the di s k -acces s s t art cylinder address.

At the end of a command, the contents of this register are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High register.

Under the LBA mode, this register indicates LBA bits 23 to 16.

Under the LBA mode of the EXT system command, LBA bits 47 to 40 are set in the first setting, and LBA bits 23 to 16 are set in the second setting.

5-10 C141-E217

(8) Device/Head register (X’1F6’)

The contents of this register indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, t he contents of this register defines “the number of heads minus 1” (a maximum head No.).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X L X DEV HS3 HS2 HS1 HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: DEV bit. 0 for the master device and 1 for the slave device.

- Bit 3: HS3 C HS mode head address 3 (2

under the LBA mode of the EXT command.

- Bit 2: HS2 C HS mode head address 2 (2

under the LBA mode of the EXT command.

- Bit 1: HS1 C HS mode head address 1 (2

under the LBA mode of the EXT command.

- Bit 0: HS0 C HS mode head address 0 (2

under the LBA mode of the EXT command.

5.2 Logical Interface

). bit 27 for LBA mode. Unused

). bit 26 for LBA mode. Unused

). bit 25 for LBA mode. Unused

). bit 24 for LBA mode. Unused

(9) Status register (X’1F7’)

The content s o f this regis ter indicat e t h e s t at u s o f t h e d ev i ce. The conten t s o f t h i s register are updated at the com pl eti on of each com m and. When t he B SY bit is cleared, other bits in this register should be validated within 400 ns. When the BSY bit is 1, other bits of this register are invalid. When the host system reads this register while an interrupt is pending, it is considered to be the Interrupt Acknowledge (the host system acknowledges the interrupt). Any pending interrupt is cleared (negating INTRQ s i gn al ) wh en ever this regis t er i s read .

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSY DRDY DF DSC DRQ 0 0 ERR

C141-E217 5-11

Interface

- Bit 7: Busy (BSY) bit. This bit is set whenever the Command register is accessed. Then this bit is cleared when the command is completed. However, even if a command is being executed, this bit is 0 while data transfer is being requested (DRQ bit = 1). When BSY bit is 1, the host system should not write the command block registers. If the host system reads any command block register when BSY bit is 1, the contents of the Status register are posted. This bit is set by the device under following conditions:

(a) Within 400 ns after RESET- is negated or SRST is set in the

Device Control register, the BSY bit is set. The BSY bit is cleared, when the reset process is completed.

The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

(b) Within 400 ns from the host system starts writing to the

Command register.

of the READ SECTOR(S), WRITE SECTOR(S), or WRITE BUFFER command.

- Bit 6: Device Ready (DRDY) bit. This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected (not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

- Bit 5: The Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

- Bit 3: Data Request (DRQ) bit. This bit indicates that the device is ready to transfer data of word unit or byte unit between the host system and the device.

- Bit 2: Always 0.

- Bit 1: Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was being executed. The Error register indicates the additional information of the cause for the error.

5-12 C141-E217

(10) Command register (X’1F7’)

The Command register contains a command code being sent to the device. After this register is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain registers before the Command register is written.

5.2.3 Control block registers

(1) Alternate Status register (X’3F6’)

The Alternate Status register contains the same information as the Status register of the command block register.

The only difference from the Status register is that a read of this register does not imply Interrupt Acknowledge and INTRQ signal is not reset.

5.2 Logical Interface

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSY DRDY DF DSC DRQ 0 0 ERR

C141-E217 5-13

Interface

(2) Devic e Control register (X’3F6’)

The Device Control register contains device interrupt and software reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HOB X X X X SRST nIEN 0

- Bit 7: High Order Byte (HOB) is the selector bit that selects higher-order information or lower-order information of the EXT system command.

If HOB = 1, LBA bits 47 to 24 and the higher-order 8 bits of the sector count are displayed in the task register.

If HOB = 0, LBA bits 23 to 0 and the lower-order 8 bits of the sector count are displayed in the task register.

- Bit 2: Software Reset (SRST) is the host software reset bit. When this bit is set, th e d ev i ce i s h el d res et s tate. When t w o dev i ces are d ai sy chained on the in t erface, s e tting this bit resets both devices simultaneously.

The slave device is not required to execute the DASP- handshake.

- Bit 1: nIEN bit enables an interrupt (INTRQ signal) from the device to the host. When this bit is 0 and the device is selected, an interruption (INTRQ signal) can be enabled through a tri-state buffer. When this bit is 1 or the device is not selected, the INTRQ signal is in the highimpedance s t ate.

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related registers in the command block and writing a command code in the Command register.

The device can accept the comman d wh en the BSY bi t i s 0 (t h e d evice is not i n the busy status).

The host system can h al t the uncom p l eted command ex ecu t i o n o n l y at ex ecu t i o n of hardware or software res et .

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the data transfer) and t h e h os t system wri tes to the co m m an d reg i s t er, the correct dev i ce operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.3 lists the supported commands, command code and the registers that needed parameters are written.

5-14 C141-E217

Table 5.3 Command code and parame ters (1 of 2)

5.3 Host Commands

COMMAND NAME

COMMAND CODE (Bit ) P AR AMETER US ED

7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y WRITE SECTOR(S) 0 0 1 1 0 0 0 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y READ VERIFY SECTOR(S) 0 1 0 0 0 0 0 R N Y Y Y Y SEEK 0 1 1 1 X X X X N N Y Y Y EXECUTE DEVICE

DIAGNOSTIC INITIALIZE DEVICE

PARAMETERS

1 0 0 1 0 0 0 0 N N N N

1 0 0 1 0 0 0 1 N Y N N

DOWNLOAD MICROCODE 1 0 0 1 0 0 1 0 Y Y Y N D

STANDBY IMMEDIATE

IDLE IMMEDIATE

11 01 01 10 00 10 00 0

11 01 01 10 00 10 00 1

N N N N D

UNLOAD IMMEDIATE

STANDBY

IDLE

CHECK POWER MODE

SLEEP

11 01 01 10 00 10 00 1

11 01 01 10 00 10 11 0

11 01 01 10 00 10 11 1

11 01 01 10 10 01 00 0

11 01 01 10 10 01 01 1

Y N Y Y

N Y N N D

N N N N D

SMART 1 0 1 1 0 0 0 0 Y Y Y Y D DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 Y N N N D READ MULTIPLE 1 1 0 0 0 1 0 0 N Y Y Y Y WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D READ DMA 1 1 0 0 1 0 0 R N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y READ BUFFER 1 1 1 0 0 1 0 0 N N N N D

C141-E217 5-15

Interface

Table 5.3 Command code and parame ters (2 of 2)

COMMAND NAME

COMMAND CODE (Bit ) P AR AMETER US ED

7 6 5 4 3 2 1 0 FR SC SN CY DH FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 0 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N* N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY DISABLE

PASSWORD READ NATIVE MAX

ADDRESS

1 1 1 1 0 1 1 0 N N N N

1 1 1 1 1 0 0 0 N N N N

SET MAX 1 1 1 1 1 0 0 1 Y Y Y Y Y READ SECTOR(S) EXT *O 0 0 1 0 0 1 0 0 N Y Y Y D READ DMA EXT *O 0 0 1 0 0 1 0 1 N Y Y Y D READ NATIVE MAX

ADDRESS EXT *O

1 1 1 1 1 0 0 0 N N N N

READ MULTIPLE EXT *O 0 0 1 0 1 0 0 1 N Y Y Y D READ LOG EXT *O 0 0 1 0 1 1 1 1 N Y Y Y D WRITE SECTOR(S) EXT *O 0 0 1 1 0 1 0 0 N Y Y Y D WRITE DMA EXT *O 0 0 1 1 0 1 0 1 N Y Y Y D SET MAX ADDRESS EXT *O 0 0 1 1 0 1 1 1 N Y Y Y Y WRITE MULTIPLE EXT *O 0 0 1 1 1 0 0 1 N Y Y Y D

WRITE DMA FUA EXT *O 0 0 1 1 1 1 0 1 N Y Y Y D

WRITE LOG EXT *O 0 0 1 1 1 1 1 1 N Y Y Y D READ VERIFY SEC T OR (S )

EXT *O

WRITE MULTIPLE FUA EXT *O

0 1 0 0 0 0 1 0 N Y Y Y

1 1 0 0 1 1 1 0 N Y Y Y D

FLUSH CACHE EXT *O 1 1 1 0 1 0 1 0 N N N N D

5-16 C141-E217

5.3 Host Commands

Note: READ LONG (0x22) command/WRITE LONG (0x33) com m and became a

unsupport from the MHV2xxxAH series. Notes: FR: Features Register CY: Cylinder Registers SC: Sector Count Register DH: Drive/Head Register SN: Sector Number R eg i s t er R: Retry at erro r 1 = Without retry 0 = With retry Y: Necessary to set parameters Y*: Necessary to set parameters under the LBA mode. N: Not necessary to set parameters (The parameter is ignored if it is set.) N*: May set parameters D: The device parameter is valid, and the head parameter is ignored. *O: Option (customizing) D*: The command is addressed to the master device, but both the master device

and the sl av e d ev i ce ex ecu t e i t . X: Do not care

C141-E217 5-17

Interface

5.3.2 Command descriptions

The contents of the I/O registers to be necessary for issuing a command and the example in d i cat i o n o f t h e I/ O reg i s t ers at co m mand compl et i o n are s h o wn as following in this subsection.

Example: READ SE C TOR (S)

At command i s s u an ce (I/ O reg i s t ers s et t i n g co n t ents)

Bit 7 6 5 4 3 2 1 0

1F7H(CM) 0 0 1 0 0 0 0 0

1F6H(DH) x L x DV Head No. / LBA [MS B ] 1F5H(CH) Start cyli n der ad dres s [M S B] / LBA

1F4H(CL) Start cylin der ad dres s [LS B ] / LB A 1F3H(SN) Start sector No. / LB A [LS B ] 1F2H(SC) Transfer sector count 1F1H(FR) xx

At command completion (I/O registers contents to be read)

Bit 7 6 5 4 3 2 1 0

1F7H(ST) Status information 1F6H(DH) x L x DV Head No. / LBA [MS B ] 1F5H(CH) End cylinder address [MSB] / LBA

1F4H(CL) End cylinder address [LSB] / LBA 1F3H(SN) End sector No. / LBA [LSB ] 1F2H(SC) X’00’ 1F1H(ER) Error information

CM: Command register FR: Features register

DH: Device/Head register ST: S t at u s reg i s t er

CH: Cyli n der Hi g h reg i s t er ER: Erro r regi s t er

CL: Cylinder Low register L: LBA (logical block address) setting bit

SN: Sect or Nu m b er reg i s t er DV: Dev i ce ad dres s . bit

5-18 C141-E217

5.3 Host Commands

SC: Sector C ount regis t er x, xx: Do not care (no necessary to set)

Note:

1. When the L bit is specified to 1, the lower 4 bits of the DH register and all bits of the CH, CL and SN registers indicate the LBA bits (bits of the DH register are th e M SB (most s i g n i fi can t b i t ) an d bits of the SN register are the LSB (least significant bit).

2. At error occur r e nc e , the SC re giste r indic a te s the r e ma ining se c tor c ount of da ta transfer.

3. In the table indica ting I /O re giste r s c onte nts in this subse c tion, bit indic a tion is omitted.

C141-E217 5-19

Interface

(1) RECALIBRATE (X’10’ to X’1F’)

This command performs the cal i brat i on. Upon recei pt of t hi s com m and, t he device sets B SY bit of th e Status regi s ter and performs a cal ibration. When the device completes the calibration, the device updates the Status register, clears the BSY bit, and generates an interrupt.

This command can be issued in the LBA mode.

At command i s s u an ce (I/ O reg i s t ers s et t i n g co n t ents)

1F7H(CM) 0 0 0 1 x x x x

1F6H(DH) x x x DV xx 1F5H(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(FR)

xx xx xx xx xx

At command completion (I/O registers contents to be read)

1F7H(ST) Status information 1F6H(DH) x x x DV xx 1F5H(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(ER)

xx xx xx xx Error informati o n

Note:

Also executab l e i n LB A m o d e.

5-20 C141-E217

(2) READ SECTOR(S) (X’20’ or X’21’)

This command reads data of sectors specified in the Sector Count register from the address specified in the Device/Head, Cylinder High, Cylinder Low and Sector Number registers. Number of sectors can be specified from 1 to 256 sectors. To specify 256 sectors reading, ‘00’ is specified. For the DRQ, INTRQ, and BS Y protocols related to data transfer, see Subsection 5.4.1.

If the head is no t o n t h e t rack s p eci fi ed b y t h e ho s t , the device p erfo rm s an impli ed s eek . After the head reach es t o t h e s p eci fi ed t r ack, the devi ce reads the target secto r.

If an error occurs, ret ry reads are attempted t o read t h e t arg et s ect o r befo re reporting an error, irrespective of the R bit setting.

The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition.

Upon the completion of the command execution, command block registers contain the cylinder, head, and sector addresses (in the CHS mode) or logical block address (in the LBA mode) of the last sector read.

5.3 Host Commands

If an unrecoverable error occurs in a sector, the read operation is terminated at the sector where the error occurred. Command block registers contain the cylinder, the head, and the sector addresses of the sector (in the CHS mode) or the logical block address (in the LBA mode) where the error occurred, and remaining number of sectors of which data was not transferred.

At command i s s u an ce (I/ O reg i s t ers s et t i n g co n t ents)

1F7H(CM) 0 0 1 0 0 0 0 R 1F6H(DH) x L x DV St a rt head N o . / LB A

[MSB] 1F5H(CH) 1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(FR)

Start cyli nd er No. [MSB] / LB A Start cyli nd er No. [LSB] / LBA Start secto r No . / L B A [L S B ] Transfer sector count xx

C141-E217 5-21

Interface

(R: Retry)

At command completion (I/O registers contents to be read)

1F7H(ST) Status information 1F6H(DH) x L x DV En d hea d N o . / LBA [ M S B ] 1F5H(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(ER)

End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error informati o n

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

5-22 C141-E217

(3) WRITE SECTOR(S) (X’30’ or X’31’)

This command writes data of sectors from the address specified in the Device/Head, Cylinder High, Cylinder Low, and Sector Number registers to the address specified in the Sector Count register. Number of sectors can be specified from 1 to 256 sectors. A sector count of 0 requests 256 sectors. Data transfer begins at t h e s ect o r s p eci fi ed i n t h e S ect o r Nu m b er reg i s t er. For the DR Q, INTRQ, and BSY protocols related to data transfer, see Subsection 5.4.2.

If the head is no t o n t h e t rack s p eci fi ed b y t h e ho s t , the device p erfo rm s an impli ed s eek . After the head reach es t o t h e s p eci fi ed t rack , the device writes the target secto r.

If an error occurs when wri ting to t he target sector, retries are att em pted irrespectively of the R bit setting.

The data stored in the buffer, and CRC code and ECC bytes are written to the data field of the corresponding sector(s). Upon the completion of the command execution, the command block registers contain the cylinder, head, and sector addresses of the last sector written.

5.3 Host Commands

If an error occurs during multiple sector write operation, the write operation is terminated at t h e s ect o r wh ere t h e erro r occu rred . Command b l o ck reg i s ters contain t h e cy l i n d er, the head, t he s ector addresses (i n t h e C H S mode) or the logical block address (in the LBA mode) of the sector where the error occurred.

At command issuance (I/O registers setting contents)

1F7H(CM) 0 0 1 1 0 0 0 R 1F6H(DH) x L x DV St a rt head N o . / LB A [ M S B ] 1F5H(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(FR)

Start cyli nd er No. [MSB] / LB A Start cyli nd er No. [LSB] / LBA Start secto r No . / L B A [L S B ] Transfer sector count xx

C141-E217 5-23

Interface

At command completion (I/O registers contents to be read)

1F7H(ST) Status information

1F6H(DH) x L x DV En d hea d N o . / LBA [ M S B ]

1F5H(CH)

1F4

(CL)

1F3

(SN)

1F2

(SC)

1F1

(ER)

End cylinder No. [MSB] / LBA End cylinder No. [LSB] / LBA End sector No. / LBA [LSB] 00 (*1) Error informati o n

*1 If the command is terminated due to an error, the remaining number of

sectors of which data was not transferred is set in this register.

5-24 C141-E217

Fujitsu MHV2060AH, MHV2040AH, MHV2080AH, MHV2100AH User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FOR SAFE OPERATION

Revision History

Preface

Important Alert Messages

Manual Organization

Contents

Illustrations

Figures

Tables

CHAPTER 1 Device Overview

1.1 Features

1.1.1 Functions and performance

1.1.2 Adaptability

1.1.3 Interface

1.2 Device Specifications

1.2.1 Specifications summary

1.2.2 Model and product number

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

1.10 Load/Unload Function

1.11 Advanced Power Management

CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

2.2.1 ATA interface

2.2.2 1 drive connection

2.2.3 2 drives connection

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

3.3.1 Device connector

3.3.2 Cable connector specifications

3.3.3 Device connection

3.3.4 Power supply connector (CN1)

3.4 Jumper Settings

3.4.1 Location of setting jumpers

3.4.2 Factory default setting

3.4.3 Master drive-slave drive setting

3.4.4 CSEL setting

3.4.5 Power up in standby setting

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.2.1 Disk

4.2.2 Spindle

4.2.3 Actuator

4.2.4 Air filter

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.5.1 Self-calibration contents

4.5.2 Execution timing of self-calibration

4.5.3 Command processing during self-calibration

4.6 Read/write Circuit

4.6.1 Read/write preamplifier (PreAMP)

4.6.2 Write circuit

4.6.3 Read circuit

4.6.4 Digital PLL circuit

4.7 Servo Control

4.7.1 Servo control circuit

4.7.2 Data-surface servo format

4.7.3 Servo frame format

4.7.4 Actuator motor control

4.7.5 Spindle motor control

CHAPTER 5 Interface

5.1 Physical Interface

5.1.1 Interface signals

5.1.2 Signal assignment on the connector

5.2 Logical Interface

5.2.1 I/O registers