Fujitsu MHT2080BH, MHT2040BH, MHT2060BH User Manual

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C141-E203-01EN

MHT2080BH, MHT2060BH, MHT2040BH

DISK DRIVES

PRODUCT MANUAL

FOR SAFE OPERATION

Handling of This Manual

This manual contains important information for using this product. Read thoroughly before using the product. Use this product only after thoroughly reading and understanding especially the section “Important Alert Items” in this manual. Keep this manual handy, and keep it carefully.

FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property. Use the product according to this manual.

IMPORTANT NOTE TO USERS

READ THE ENTIRE MANUAL CAREFULLY BEFORE USING THIS PRODUCT. INCORRECT USE OF THE PRODUCT MAY RESULT IN INJURY OR DAMAGE TO USERS, BYSTANDERS OR PROPERTY.

While FUJITSU has sought to ensure the accuracy of all information in this manual, FUJITSU assumes no liability to any party for any damage caused by any error or omission contained in this manual, its updates or supplements, whether such errors or omissions result from negligence, accident, or any other cause. In addition, FUJITSU assumes no liability with respect to the application or use of any product or system in accordance with the descriptions or instructions contained herein; including any liability for incidental or consequential damages arising therefrom. FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN, WHETHER EXPRESSED, IMPLIED, OR STATUTORY.

FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation.

This product is designed and manufactured for use in standard applications such as office work, personal devices and household appliances. This product is not intended for special uses (atomic controls, aeronautic or space systems, mass transport vehicle operating controls, medical devices for life support, or weapons firing controls) where particularly high reliability requirements exist, where the pertinent levels of safety are not guaranteed, or where a failure or operational error could threaten a life or cause a physical injury (hereafter referred to as "mission-critical" use). Customers considering the use of these products for mission-critical applications must have safety-assurance measures in place beforehand. Moreover, they are requested to consult our sales representative before embarking on such specialized use.

The contents of this manual may be revised without prior notice.

The contents of this manual shall not be disclosed in any way or reproduced in any media without the express written permission of Fujitsu Limited.

Revision History

(1/1)

Edition Date

01 2004-02-27

Revised section (*1)

(Added/Deleted/Altered)

Details

*1 Section(s) with asterisk (*) refer to the previous edition when those were deleted.

C141-E203-01EN

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This manual describes MHT2080BH/ MHT2060BH/ MHT2040BH models of the MHT Series, 2.5-inch hard disk drives. These drives have a built-in controller that is compatible with the Serial-ATA interface.

This manual describes the specifications and functions of the drives and explains in detail how to incorporate the drives into user systems. This manual assumes that the reader has a basic knowledge of hard disk drives and their implementations in computer systems.

This manual consists of seven chapters and sections explaining the special terminology and abbreviations used in this manual:

Overview of Manual

CHAPTER 1 Device Overview

Preface

This chapter gives an overview of the disk drive and describes their features.

CHAPTER 2 Device Configuration

This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate.

CHAPTER 3 Installation Conditions

This chapter describes the external dimensions, installation conditions, and switch settings of the disk drive.

CHAPTER 4 Theory of Device Operation

This chapter describes the operation theory of the disk drive.

CHAPTER 5 Interface

This chapter describes the interface specifications of the disk drive.

CHAPTER 6 Operations

This chapter describes the operations of the disk drive.

Glossary

The glossary describes the technical terms that need to be understood to read this manual.

Acronyms and Abbreviations

This section gives the meanings of the definitions used in this manual.

C141-E203-01EN i

Preface

Conventions for Alert Messages

This manual uses the following conventions to show the alert messages. An alert message consists of an alert signal and alert statements. The alert signal consists of an alert symbol and a signal word or just a signal word.

The following are the alert signals and their meanings:

This indicates a hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly.

This indicates information that could help the user use the product more efficiently.

In the text, the alert signal is centered, followed below by the indented message. A wider line space precedes and follows the alert message to show where the alert message begins and ends. The following is an example:

(Example)

Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

The main alert messages in the text are also listed in the “Important Alert Items.”

Operating Environment

This product is designed to be used in offices or computer rooms.

Conventions

An MHT series device is sometimes simply referred to as a "hard disk drive," "HDD," "drive," or "device" in this document.

Decimal numbers are represented normally.

Hexadecimal numbers are represented as shown in the following examples: X'17B9', 17B9h, 17B9H, or 17B9H.

Binary numbers are represented as shown in the following examples: 010 or 010b.

Serial-ATA may be referred to as "SATA."

ii C141-E203-01EN

Preface

Attention

Please forward any comments you may have regarding this manual.

To make this manual easier for users to understand, opinions from readers are needed. Please write your opinions or requests on the Comment at the back of this manual and forward it to the address described in the sheet.

Liability Exception

“Disk drive defects” refers to defects that involve adjustment, repair, or replacement.

Fujitsu is not liable for any other disk drive defects, such as those caused by user misoperation or mishandling, inappropriate operating environments, defects in the power supply or cable, problems of the host system, or other causes outside the disk drive.

C141-E203-01EN iii

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Important Alert Items

Important Alert Messages

The important alert messages in this manual are as follows:

A hazardous situation could result in minor or moderate personal injury if the user does not perform the procedure correctly. Also, damage to the product or other property, may occur if the user does not perform the procedure correctly.

Task Alert message Page

Normal Operation

Data corruption: Avoid mounting the disk drive near strong magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

Damage: Do not press the cover of the disk drive. Pressing it too hard, the cover and the spindle motor contact, which may cause damage to the disk drive.

Static: When handling the device, disconnect the body ground (500 kΩ or greater). Do not touch the printed circuit

board, but hold it by the edges.

3-7

C141-E203-01EN v

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Manual Organization

MHT2080BH, MHT2060BH,

MHT2040BH

DISK DRIVES

PRODUCT MANUAL

(C141-E203)

MHT2080BH, MHT2060BH,

MHT2040BH

DISK DRIVES

MAINTENANCE MANUAL

(C141-F068)

• Device Overview

• Device Configuration

• Installation Conditions

• Theory of Device Operation

• Interface

• Operations

• Maintenance and Diagnosis

• Removal and Replacement Procedure

C141-E203-01EN vii

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CHAPTER 1 Device Overview........................................................................1-1

1.1 Features .....................................................................................................1-2

1.1.1 Functions and performance...................................................................1-2

Adaptability...........................................................................................1-2

1.1.2

1.1.3 Interface ................................................................................................1-3

1.2 Device Specifications................................................................................1-4

1.2.1 Specifications summary........................................................................1-4

1.2.2 Model and product number...................................................................1-5

1.3 Power Requirements..................................................................................1-6

1.4 Environmental Specifications ...................................................................1-8

1.5 Acoustic Noise ..........................................................................................1-9

1.6 Shock and Vibration..................................................................................1-9

1.7 Reliability................................................................................................1-10

1.8 Error Rate ................................................................................................1-11

1.9 Media Defects..........................................................................................1-11

1.10 Load/Unload Function...........................................................................1-11

1.11 Advanced Power Management..............................................................1-12

1.12 Interface Power Management (IPM).....................................................1-14

1.12.1 Host-initiated Interface Power Management (HIPM)........................1-14

1.12.2 Device-initiated Interface Power Management (DIPM)....................1-14

CHAPTER 2 Device Configuration ................................................................2-1

2.1 Device Configuration................................................................................2-2

2.2 System Configuration................................................................................2-3

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Contents

2.2.1 SATA interface..................................................................................... 2-3

2.2.2 Drive connection.................................................................................. 2-3

CHAPTER 3 Installation Conditions ............................................................. 3-1

3.1 Dimensions............................................................................................... 3-2

3.2 Mounting................................................................................................... 3-3

3.3 Connections with Host System................................................................. 3-9

3.3.1 Device connector.................................................................................. 3-9

3.3.2 Signal segment and power supply segment........................................ 3-10

3.3.3 Connector specifications for host system........................................... 3-10

3.3.4 SATA interface cable connection ...................................................... 3-11

3.3.5 Note about SATA interface cable connection.................................... 3-11

CHAPTER 4 Theory of Device Operation..................................................... 4-1

4.1 Outline ...................................................................................................... 4-2

4.2 Subassemblies........................................................................................... 4-2

4.2.1 Disk ...................................................................................................... 4-2

4.2.2 Spindle.................................................................................................. 4-2

4.2.3 Actuator................................................................................................ 4-2

4.2.4 Air filter................................................................................................ 4-3

4.3 Circuit Configuration................................................................................ 4-3

4.4 Power-on Sequence .................................................................................. 4-6

4.5 Self-calibration ......................................................................................... 4-7

4.5.1 Self-calibration contents....................................................................... 4-7

4.5.2 Execution timing of self-calibration..................................................... 4-8

4.5.3 Command processing during self-calibration...................................... 4-8

4.6 Read/write Circuit..................................................................................... 4-9

4.6.1 Read/write preamplifier (PreAMP)...................................................... 4-9

4.6.2 Write circuit.......................................................................................... 4-9

4.6.3 Read circuit......................................................................................... 4-10

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Contents

4.6.4 Digital PLL circuit..............................................................................4-11

4.7 Servo Control ..........................................................................................4-12

4.7.1 Servo control circuit............................................................................4-12

4.7.2 Data-surface servo format...................................................................4-14

4.7.3 Servo frame format.............................................................................4-16

4.7.4 Actuator motor control........................................................................4-17

4.7.5 Spindle motor control..........................................................................4-18

CHAPTER 5 Interface .....................................................................................5-1

5.1 Physical Interface......................................................................................5-2

5.1.1 Interface signals....................................................................................5-2

5.1.2 Signal interface regulation....................................................................5-4

5.1.2.1 Out of band signaling..........................................................................5-4

5.1.2.2 Primitives descriptions......................................................................5-5

5.1.3 Electrical specifications........................................................................5-6

5.1.4 Connector pinouts.................................................................................5-8

5.2 Logical Interface........................................................................................5-9

5.2.1 Communication layers........................................................................5-10

5.2.2 Outline of the Shadow Block Register................................................5-11

5.2.3 Outline of the frame information structure (FIS)................................5-12

5.2.3.1 FIS types ...........................................................................................5-12

5.2.3.2 Register - Host to Device..................................................................5-12

5.2.3.3 Register - Device to Host..................................................................5-13

5.2.3.4 DMA Active - Device to Host ..........................................................5-13

5.2.3.5 DMA Setup - Device to Host or Host to Device (Bidirectional)......5-14

5.2.3.6 BIST Active - Bidirectional..............................................................5-15

5.2.3.7 Data - Host to Device or Device to Host (Bidirectional)..................5-16

5.2.4 Shadow block registers .......................................................................5-17

5.3 Host Commands ......................................................................................5-22

5.3.1 Command code and parameters..........................................................5-22

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Contents

5.3.2 Command descriptions....................................................................... 5-25

(1) RECALIBRATE (X’10’ to X’1F’)...........................................5-26

(2) READ SECTOR(S) (X’20’ or X’21’)....................................5-27

(3) READ LONG (X’22’ or X’23’) .............................................5-29

(4) WRITE SECTOR(S) (X’30’ or X’31’) ...................................5-30

(5) WRITE LONG (X’32’ or X’33’) .............................................5-32

(6) WRITE VERIFY (X’3C’) .......................................................5-34

(7) READ VERIFY SECTOR(S) (X’40’ or X’41’)......................5-36

(8) SEEK (X’70’ to X’7F’)............................................................5-38

(9) EXECUTE DEVICE DIAGNOSTIC (X’90’)..........................5-39

(10) INITIALIZE DEVICE PARAMETERS (X’91’).....................5-40

(11) DOWNLOAD MICROCODE (X’92’).....................................5-41

(12) STANDBY IMMEDIATE (X’94’ or X’E0’)...........................5-43

(13) IDLE IMMEDIATE (X’95’ or X’E1’).....................................5-44

(14) STANDBY (X’96’ or X’E2’)...................................................5-45

(15) IDLE (X’97’ or X’E3’).............................................................5-46

(16) CHECK POWER MODE (X’98’ or X’E5’) ............................5-48

(17) SLEEP (X’99’ or X’E6’).........................................................5-49

(18) SMART (X’B0’).......................................................................5-50

(19) DEVICE CONFIGURATION (X'B1') .....................................5-67

(20) READ MULTIPLE (X’C4’).....................................................5-71

(21) WRITE MULTIPLE (X’C5’)...................................................5-74

(22) SET MULTIPLE MODE (X’C6’)............................................5-76

(23) READ DMA (X’C8’ or X’C9’)................................................5-78

(24) WRITE DMA (X’CA’ or X’CB’) ............................................5-80

(25) READ BUFFER (X’E4’)..........................................................5-82

(26) FLUSH CACHE (X’E7’) ........................................................5-83

(27) WRITE BUFFER (X’E8’)........................................................5-84

(28) IDENTIFY DEVICE (X’EC’)..................................................5-85

(29) IDENTIFY DEVICE DMA (X’EE’).......................................5-86

(30) SET FEATURES (X’EF’) ........................................................5-97

(31) SECURITY SET PASSWORD (X’F1’).................................5-102

(32) SECURITY UNLOCK(X’F2’)...............................................5-104

(33) SECURITY ERASE PREPARE (X’F3’) ...............................5-106

(34) SECURITY ERASE UNIT (X’F4’) .......................................5-107

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(35) SECURITY FREEZE LOCK (X’F5’) ................................... 5-108

(36) SECURITY DISABLE PASSWORD (X’F6’) ...................... 5-110

(37) READ NATIVE MAX ADDRESS (X’F8’)..........................5-112

(38) SET MAX (X’F9’)................................................................. 5-113

(39) READ SECTOR (S) EXT (X’24’)......................................... 5-119

(40) READ DMA EXT (X’25’)..................................................... 5-120

(41) READ NATIVE MAX ADDRESS EXT (X’27’).................. 5-121

(42) READ MULTIPLE EXT (X’29’) .......................................... 5-122

(43) READ LOG EXT (X'2F')....................................................... 5-123

(44) WRITE SECTOR (S) EXT (X’34’).......................................5-126

(45) WRITE DMA EXT (X’35’)................................................... 5-127

(46) SET MAX ADDRESS EXT (X’37’) ..................................... 5-128

(47) WRITE MULTIPLE EXT (X’39’) ........................................ 5-130

(48) WRITE LOG EXT (X'3F').....................................................5-131

(49) READ VERIFY SECTOR (S) EXT (X’42’) ........................ 5-133

(50) FLUSH CACHE EXT (X’EA’) ............................................ 5-134

(51) WRITE MULTIPLE FUA EXT (X'CE') ............................... 5-135

(52) WRITE DMA FUA EXT (X'3D') .......................................... 5-136

(53) READ FP DMA QUEUED (X'60')........................................ 5-137

(54) WRITE FP DMA QUEUED (X'61')......................................5-138

5.3.3 Error posting.....................................................................................5-139

5.4 Command Protocol ............................................................................... 5-141

5.4.1 Non-data command protocol............................................................5-141

5.4.2 PIO data-in command protocol.........................................................5-143

5.4.3 PIO data-out command protocol.......................................................5-144

5.4.4 DMA data-in command protocol......................................................5-146

5.4.5 DMA data-out command protocol....................................................5-147

5.4.6 Native Command Queuing protocol.................................................5-148

5.5 Power-on and COMRESET..................................................................5-151

CHAPTER 6 Operations................................................................................. 6-1

6.1 Reset and Diagnosis.................................................................................. 6-2

6.1.1 Response to power-on...........................................................................6-2

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Contents

6.1.2 Response to COMRESET.................................................................... 6-4

6.1.3 Response to a software reset ................................................................ 6-5

6.2 Power Save ............................................................................................... 6-6

6.2.1 Power save mode.................................................................................. 6-6

6.2.2 Power commands ................................................................................. 6-8

6.3 Interface Power Save................................................................................ 6-9

6.3.1 Power save mode of the interface ........................................................ 6-9

6.4 Read-ahead Cache .................................................................................. 6-11

6.4.1 Data buffer structure........................................................................... 6-11

6.4.2 Caching operation............................................................................... 6-12

6.4.3 Using the read segment buffer ........................................................... 6-14

6.4.3.1 Miss-hit............................................................................................. 6-14

6.4.3.2 Sequential hit.................................................................................... 6-15

6.4.3.3 Full hit.............................................................................................. 6-15

6.4.3.4 Partial hit.......................................................................................... 6-17

6.5 Write Cache............................................................................................ 6-18

6.5.1 Cache operation.................................................................................. 6-18

Glossary ....................................................................................................... GL-1

Acronyms and Abbreviations ........................................................................ AB-1

Index .................................................................................................................. IN-1

xiv C141-E203-01EN

Contents

Illustrations

Figures

Figure 1.1 Negative voltage at +5 V when power is turned off ............................1-6

Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on...............1-8

Figure 2.1 Disk drive outerview............................................................................2-2

Figure 2.2 Drive system configuration..................................................................2-3

Figure 3.1 Dimensions...........................................................................................3-2

Figure 3.2 Orientation............................................................................................3-3

Figure 3.3 Mounting frame structure.....................................................................3-4

Figure 3.4 Location of breather .............................................................................3-5

Figure 3.5 Surface cover temperature measurement points ..................................3-6

Figure 3.6 Service area ..........................................................................................3-7

Figure 3.7 Handling cautions.................................................................................3-8

Figure 3.8 Connector locations..............................................................................3-9

Figure 3.9 Power supply pins (CN1) ...................................................................3-10

Figure 4.1 Power Supply Configuration................................................................4-4

Figure 4.2 Circuit Configuration ...........................................................................4-5

Figure 4.3 Power-on operation sequence...............................................................4-6

Figure 4.4 Read/write circuit block diagram.........................................................4-9

Figure 4.5 Frequency characteristic of programmable filter...............................4-10

Figure 4.6 Block diagram of servo control circuit...............................................4-12

Figure 4.7 Physical sector servo configuration ( on disk surface........................4-15

Figure 4.8 Servo frame format.............................................................................4-16

Figure 5.1 Interface signals....................................................................................5-2

Figure 5.2 Conceptual diagram of communication layers.....................................5-9

Figure 5.3 Register - Host to Device FIS layout .................................................5-12

Figure 5.4 Register - Device to Host FIS layout .................................................5-13

Figure 5.5 DMA Active - Device to Host FIS layout..........................................5-13

Figure 5.6 DMA Setup - Device to Host or Host to Device FIS layout..............5-14

Figure 5.7 BIST Active - Bidirectional FIS layout..............................................5-15

Figure 5.8 Data FIS (Bidirectional) layout..........................................................5-16

Figure 5.9 Execution example of READ MULTIPLE command .......................5-72

Figure 5.10 Non-data command protocol..........................................................5-142

C141-E203-01EN xv

Contents

Figure 5.11 PIO data-in command protocol...................................................... 5-144

Figure 5.12 PIO data-out command protocol.................................................... 5-145

Figure 5.13 DMA data-in command protocol................................................... 5-146

Figure 5.14 DMA data-out command protocol................................................. 5-147

Figure 5.15 READ FP DMA QUEUED command protocol............................ 5-149

Figure 5.16 WRITE FP DMA QUEUED command protocol .......................... 5-150

Figure 5.17 Power-on sequence........................................................................ 5-151

Figure 5.18 COMRESET sequence .................................................................. 5-152

Figure 6.1 Response to power-on (when the host is powered

on earlier than the device)................................................................. 6-2

Figure 6.2 Response to power-on (when the device is powered

on earlier than the host).................................................................... 6-3

Figure 6.3 Response to COMRESET.................................................................... 6-4

Figure 6.4 Response to a software reset................................................................ 6-5

Figure 6.5 Data buffer structure.......................................................................... 6-11

xvi C141-E203-01EN

Contents

Tables

Table 1.1 Specifications ........................................................................................1-4

Table 1.2 Examples of model names and product numbers..................................1-5

Table 1.3 Current and power dissipation...............................................................1-7

Table 1.4 Environmental specifications ................................................................1-8

Table 1.5 Acoustic noise specification..................................................................1-9

Table 1.6 Shock and vibration specification..........................................................1-9

Table 1.7 Advanced power management.............................................................1-13

Table 1.8 Interface power management...............................................................1-15

Table 3.1 Surface temperature measurement points and standard values.............3-6

Table 3.2 The recommended connector specifications for the host system........3-10

Table 5.1 Physical Layer Electrical Requirements................................................5-6

Table 5.2 Connector pinouts..................................................................................5-8

Table 5.3 Shadow Block Register........................................................................5-11

Table 5.4 BIST combinations..............................................................................5-15

Table 5.5 Command code and parameters ..........................................................5-22

Table 5.6 Diagnostic code ...................................................................................5-39

Table 5.7 Operation of DOWNLOAD MICROCODE........................................5-41

Table 5.8 Example of rewriting procedure of data 384K Bytes

(30000h Bytes) of microcode.............................................................5-42

Table 5.9 Features Field values (subcommands) and functions..........................5-51

Table 5.10 Format of device attribute value data................................................5-55

Table 5.11 Format of guarantee failure threshold value data..............................5-55

Table 5.12 Off-line data collection status.............................................................5-58

Table 5.13 Self-test execution status...................................................................5-58

Table 5.14 Off-line data collection capability.....................................................5-59

Table 5.15 Failure prediction capability flag.......................................................5-59

Table 5.16 Drive error logging capability ...........................................................5-59

Table 5.17 Log Directory Data Format ...............................................................5-60

Table 5.18 Data format of SMART Summary Error Log....................................5-61

Table 5.19 Data format of SMART Comprehensive Error Log..........................5-63

Table 5.20 SMART self-test log data format ......................................................5-64

Table 5.21 Selective self-test log data structure..................................................5-65

Table 5.22 Selective self-test feature flags..........................................................5-66

Table 5.23 DEVICE CONFIGURATION IDENTIFY data structure.................5-70

Table 5.24 Information to be read by IDENTIFY DEVICE command ..............5-87

Table 5.25 Features field values and settable modes ..........................................5-97

Table 5.26 Contents of SECURITY SET PASSWORD data............................5-102

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Contents

Table 5.27 Relationship between combination of Identifier and Security

level, and operation of the lock function........................................ 5-102

Table 5.28 Contents of security password........................................................ 5-110

Table 5.29 Data format of Read Log Ext log page 10h.................................... 5-125

Table 5.30 Tag field information...................................................................... 5-125

Table 5.31 Command code and parameters ..................................................... 5-139

xviii C141-E203-01EN

CHAPTER 1 Device Overview

1.1 Features

1.2 Device Specifications

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

1.10 Load/Unload Function

1.11 Advanced Power Management

1.12 Interface Power Management (IPM)

Overview and features are described in this chapter, and specifications and power requirement are described.

The disk drive is 2.5-inch hard disk drives with built-in disk controllers. These disk drives use the SATA interface protocol which has a high-speed interface data transfer rate.

C141-E203-01EN 1-1

Device Overview

1.1 Features

1.1.1 Functions and performance

The following features of the disk drive is described.

(1) Compact

The disk drive has 1 disk or 2 disks of 65 mm (2.5 inches) diameter, and its height is 9.5 mm (0.374 inch).

(2) Large capacity

The disk drive can record up to 40 GB (formatted) on one disk using the RLL recording method and 30 recording zone technology. The disk drive has a formatted capacity of 80 GB (MHT2080BH), 60 GB (MHT2060BH), 40 GB (MHT2040BH) respectively.

(3) High-speed Transfer rate

The disk drive (the MHT Series) has an internal data rate up to 53.9 MB/s. The disk drive supports an external data rate up to 1.5Gbps (Serial-ATA Generation-1).

(4) Aver age posit ioning t im e

Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed. The average positioning time is 12 ms (at read).

1.1.2 Adaptability

(1) Power save mode

The disk drive is ideal for applications since it supports the power save mode function that works in each of the Idle, Standby and Sleep modes and has the Partial and Slumber interface power management functions.

(2) Wide tem perature range

The disk drive can be used over a wide temperature range (5 °C to 55 °C).

(3) Low noise and vibration

In Ready status (while the device is waiting for any commands), the Sound Power level of the disk drives in idle mode is 2.2 Bels [MHT2040BH]/2.8 Bels [MHT2080BH, MHT2060BH]. The Sound Pressure level is 25.0 dB [MHT2040BH]/34.0 dB [MHT2080BH, MHT2060BH] as measured 0.3 m from the drive in Idle mode.

(4) High resist ance against shock

The Load/Unload mechanism is highly resistant against non-operation shock up to 8820 m/s

(900G).

1-2 C141-E203-01EN

1.1 Features

1.1.3 Interface

(1) Connect ion t o SATA int e r f ace

The disk drive has built-in controllers compatible with the SATA interface.

(2) Data buffer

The disk drive use a 2MB or 8MB data buffer to transfer data between the host and the disk media.

In combination with the read-ahead cache system described in item (3) and the write cache described in item (6), the buffer contributes to efficient I/O processing.

(3) Read-ahead cache system

After the execution of a disk read command, the disk drive automatically reads the subsequent data block and writes it to the data buffer (read ahead operation). This cache system enables fast data access. The next disk read command would normally cause another disk access. But, if the read ahead data corresponds to the data requested by the next read command, the data in the buffer can be transferred instead.

(4) Error correction and retry by ECC

If a recoverable read error occurs, the disk drive itself attempt error recovery. The ECC has improved buffer error correction for correctable data errors.

(5) Self-diagnosis

The disk drive has a diagnostic function to check operation of the controller and disk drive. Executing a diagnostic function of the smart command invokes selfdiagnosis.

(6) Write cache

When the disk drive receives a write command, the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media. This feature reduces the access time at writing.

C141-E203-01EN 1-3

Device Overview

1.2 Device Specifications

1.2.1 Specifications summary

Table 1.1 shows the specifications of the disk drives.

Table 1.1 Specifications (1/2)

MHT2080BH MHT2060BH MHT2040BH

Format Capacity (*1, *2) 80 GB 60 GB 40 GB Number of Sectors (User) 156,301,488 sectors 117,210,240 sectors 78,140,160 sectors Bytes per Sector 512 bytes Rotational Speed 5,400 rpm ± 1% Average Latency 5.56 ms Positioning time

(read and seek)

• Minimum (Track-Track)

• Average

• Maximum (Full)

Start time 4.0 sec (typ.) Interface Compliant with ATA/ATAPI-7, SATA1.0a, and SATA II 1.0

Data Transfer Rate (*2)

• To/From Media

• To/From Host

Data Buffer Size (*3) 8MB Physical Dimensions

(Height × Depth × Width) Weight 99 g (max) *1: Capacity under the LBA mode.

1.5 ms (typ.)

Read: 12ms (typ.)

22 ms (typ.)

[Cable length: less than 1.0m (39.37 inchs)]

53.9 MB/s Max.

1.5Gbps Max (Serial-ATA Generation-1)

9.5 mm × 100.0 mm × 70.0 mm (*4)

*2: 1GB = 1,000,000,000 bytes, and 1 MB = 1,000,000 bytes. *3: 1MB = 1,048,576 bytes. *4: The value of Depth (=100.0 mm) does not include PCBA

(Printed Circuit Board Assembly). Refer to Section 3.1.

1-4 C141-E203-01EN

1.2 Device Specifications

Table 1.1 lists the formatted capacity, number of logical cylinders, number

of heads, and number of sectors of every model for which the CHS mode has been selected using the BIOS setup utility on the host.

Table 1.1 Specifications (2/2)

Model Capacity (*1) No. of Cylinder No. of Heads No. of Sectors

MHT2080BH 8.45 GB 16,383 16 63 MHT2060BH 8.45 GB 16,383 16 63 MHT2040BH 8.45 GB 16,383 16 63 *1 Indicates the storage capacity when the numbers of logical cylinders, heads, and sectors are

specified as shown in this table.

1.2.2 Model and product number

Table 1.2 lists the model names and product numbers of the disk drive.

The model name does not necessarily correspond to the product number as listed in Table 1.2 since some models have been customized and have specifications that are different from those for the standard model.

If a disk drive is ordered as a replacement drive, the product number must be the same as that of the drive being replaced.

Table 1.2 Examples of model names and product numbers

Model Name

MHT2080BH 80 GB M3 depth 3 CA06500-B048 MHT2060BH 60 GB M3 depth 3 CA06500-B046 MHT2040BH 40 GB M3 depth 3 CA06500-B024

Capacity

(user area)

Mounting screw Order No.

C141-E203-01EN 1-5

Device Overview

1.3 Power Requirements

(1) Input Voltage

• + 5 V ± 5 %

• It is unnecessary for this drive to supply +3.3V and +12V power supplies.

(2) Ripple

+5 V Maximum 100 mV (peak to peak) Frequency DC to 1 MHz

(3) A negative voltagelike the bottom figure isn't to occur at +5 V when power is turned off

and, a thing with no ringing.

Permissible level: −0.2 V

Voltage [V]

-1

0 100 200 300 400 500 600 700 800

Time [ms]

Figure 1.1 Negative voltage at +5 V when power i s t urned of f

1-6 C141-E203-01EN

1.3 Power Requirements

(4) Cur r ent Requirements and Power Dissipation

Table 1.3 lists the current and power dissipation (typical).

Table 1.3 Current and power dissipation

Typical RMS Current Typical Power (*3)

MHT2080BH, MHT2060BH,

MHT2040BH

MHT2080BH, MHT2060BH,

MHT2040BH Spin up (*1) 1.0 A 5.0 W Idle (*6) 170 mA 0.85 W R/W (on track) (*2) Read 460 mA / Write 460mA Read 2.3 W / Write 2.3 W Seek (*5) 500 mA 2.5 W Standby (*6) 50 mA 0.25 W Sleep (*6) 20 mA 0.1 W Energy

Efficiency (*4)

— 0.011 W/GB

(rank E / MHT2080BH)

0.014 W/GB

(rank E / MHT2060BH)

0.021 W/GB

(rank D / MHT2040BH)

*1 Maximum current and power at starting spindle motor. *2 Current and power level when the operation (command) that accompanies a

transfer of 63 sectors is executed 3 times in 100 ms. *3 Power requirements reflect nominal values for +5 V power. *4 Energy efficiency based on the Law concerning the Rational Use of Energy

indicates the value obtained by dividing power consumption by the storage

capacity. (Japan only) *5 The seek average current is specified based on three operations per

100 msec. *6 IPM mode: Slumber mode.

C141-E203-01EN 1-7

Device Overview

(5) Current fluctuation (Typ.) at +5 V when power is tur n ed on

Figure 1.2 Current fluctuation (Typ.) at +5 V when power is turned on

(6) Power on/off sequence

The voltage detector circuits monitor +5 V. The circuits do not allow a write signal if either voltage is abnormal. These prevent data from being destroyed and eliminates the need to be concerned with the power on/off sequence.

1.4 Environmental Specifications

Table 1.4 lists the environmental specifications.

Table 1.4 Environmental specificati ons

Item Specification Temperature

• Operating

• Non-operating

• Thermal Gradient

Humidity

• Operating

• Non-operating

• Maximum Wet Bulb

Altitude (relative to sea level)

• Operating

• Non-operating

5 °C to 55 °C (ambient) 5 °C to 60 °C (disk cover surface) –40 °C to 65 °C 20 °C/h or less

8 % to 90 % RH (Non-condensing) 5 % to 95 % RH (Non-condensing) 29 °C (Operating)

40 °C (Non-operating)

–300 to 3,000 m –300 to 12,000 m

1-8 C141-E203-01EN

1.5 Acoustic Noise

Table 1.5 lists the acoustic noise specification.

Table 1.5 Acoustic noise specificati on

Item Specification (typical)

• Idle mode (DRIVE READY)

Sound Power 2.2 Bels [MHT2040BH]

2.8 Bels [MHT2080BH/MHT2060BH]

Sound Pressure (at 0.3m) 25.0 dB [MHT2040BH]

34.0 dB [MHT2080BH/MHT2060BH]

1.6 Shock and Vibration

Table 1.6 lists the shock and vibration specification.

Table 1.6 Shock and vibration specificati on

Item Specification Vibration (Swept sine, 1/4 octave per minute)

• Operating

• Non-operating

5 to 500 Hz, 9.8m/s

0-peak (1G 0-peak)

(without non-recovered errors) 5 to 500 Hz, 49m/s

0-peak (5G 0-peak)

(no damage)

Shock (half-sine pulse)

• Operating

• Non-operating

2205 m/s

0-peak (225G 0-peak) 2ms duration (without non-recovered errors)

8820 m/s

0-peak (900G 0-peak)

1ms duration 1176 m/s

0-peak (120G 0-peak)

11ms duration (no damage)

C141-E203-01EN 1-9

Device Overview

1.7 Reliability

(1) Mean time between failures (MTBF)

Conditions of 300,000 h Power-on time 250H/month or less 3000H/years

or less Operating time 20 % or less of power-on time Environment 5 to 55 °C/8 to 90 %

But humidity bulb temperature

29 °C or less MTBF is defined as follows:

Total operation time in all fields MTBF= (H) number of device failure in all fields (*1)

*1 “Disk drive defects” refers to defects that involve repair, readjustment, or

replacement. Disk drive defects do not include failures caused by external factors, such as damage caused by handling, inappropriate operating environments, defects in the power supply host system, or interface cable.

(2) M ean t im e to repair (MTTR)

The mean time to repair (MTTR) is 30 minutes or less, if repaired by a specialist maintenance staff member.

(3) Service life

In situations where management and handling are correct, the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 °C. When the DE surface temperature exceeds 48 °C, the disk drives requires no overhaul for five years or 20,000 hours of operation, whichever occurs first. Refer to item (3) in Subsection 3.2 for the measurement point of the DE surface temperature. Also the operating conditions except the environment temperature are based on the MTBF conditions.

(4) Data assurance in the event of power failure

Except for the data block being written to, the data on the disk media is assured in the event of any power supply abnormalities. This does not include power supply abnormalities during disk media initialization (formatting) or processing of defects (alternative block assignment).

1-10 C141-E203-01EN

1.8 Error Rate

Known defects, for which alternative blocks can be assigned, are not included in the error rate count below. It is assumed that the data blocks to be accessed are evenly distributed on the disk media.

(1) Unrecoverable read error

Read errors that cannot be recovered by maximum read retries of drive without user’s retry and ECC corrections shall occur no more than 10 times when reading data of 10 recovery procedure, and include read retries accompanying head offset operations.

(2) Positioning error

bits. Read retries are executed according to the disk drive’s error

Positioning (seek) errors that can be recovered by one retry shall occur no more than 10 times in 10

seek operations.

1.9 Media Defects

Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory (low level format). Thus, the hosts see a defect-free devices.

Alternate sectors are automatically accessed by the disk drive. The user need not be concerned with access to alternate sectors.

1.10 Load/Unload Function

The Load/Unload function is a mechanism that loads the head on the disk and unloads the head from the disk.

The product supports a minimum of 300,000 normal Load/Unload cycles. Normal Unload is a normal head unloading operation and the commands listed below are executed.

• COMRESET signal asserted

• STANDBY command issued

• STANDBY IMMEDIATE command issued

• SLEEP command issued

• IDLE command issued

• SLUMBER signal transferred

(PMREQ_S signal is transferred from the host or the drive, and the host responds with PMACK signal.)

C141-E203-01EN 1-11

Device Overview

Emergency Unload other than Normal Unload is performed when the power is shut down while the heads are still loaded on the disk. The product supports the Emergency Unload a minimum of 20,000 times. When the power is shut down, the controlled Normal Unload cannot be executed. Therefore, the number of Emergency other than Normal Unload is specified.

Remark:

We recommend cutting the power supply of the HDD for this device after the Head Unload operation completes. The recommended power supply cutting sequence for this device is as follows:

1) Disk Flush

Flush Cache command execution.

2) Head Unload

Standby Immediate command execution.

3) Wait Status

Checking whether bit 7 of the status register was set to '0'. (wait to complete STANDBY IMMEDIATE command)

4) HDD power supply cutting

1.11 Advanced Power Management

The disk drive shifts to the three kinds of APM modes automatically under the Idle condition.

The APM mode can be chosen with a Sector Count register of the SET FEATURES(EF) command.

In APM Mode-1, which is the APM default mode, the operation status shifts till it finally reaches "Low Power Idle."

The disk drive complies with the three kinds of APM modes that a command from the host is required.

FR = 05h : Enable APM

SC = C0h - FEh : SC = 80h - BFh : SC = 01h - 7Fh :

FR = 85h : Disable APM (Set Mode-0)

1-12 C141-E203-01EN

Mode-0 Active Idle → Low Power Idle Mode-1 Active Idle → Low Power Idle (Default) Mode-2 Active Idle → Low Power Idle → Standby

1.11 Advanced Power Management

Active Idle: The head is in a position of extreme inner in disk medium. Low Power Idle: The head is unloaded from disk.

The spindle motor rotates.

Standby: The spindle motor stops.

Table 1.7 Advanced power management

APM Mode Active Idle

Mode-0 0.2-1.2 sec 15 min. N/A Mode-1 0.2-1.2 sec 10.0-40.0 sec N/A Mode-2 0.2-1.2 sec 10.0-40.0 sec 10.0-40.0 sec

When the maximum time that the HDD is waiting for commands has been exceeded:

Mode-0: Mode shifts from Active condition to Active Idle in 0.2-1.2, and to Low

Power Idle in 15 minutes.

Mode-1: Mode shifts from Active condition to Active Idle in 0.2-1.2 seconds and

to Low Power Idle in 10.0-40.0 seconds.

Mode-2: Mode shifts from Active condition to Active Idle in 0.2-1.2 seconds and

to Low Power Idle in 10.0-40.0 seconds. After 10.0-40.0 seconds in Low Power Idle, the mode shifts to standby.

* The default values of these settings are reflected in the WORD 91 values of

the IDENTIFY DEVICE command. Also, the APM mode is initialized to Mode-1 (default value) by a hardware reset and at power-off.

Low Power Idle

(Unload)

Standby

(Spin Off)

C141-E203-01EN 1-13

Device Overview

1.12 Interface Power Management (IPM)

1.12.1 Host-initiated Interface Power Management (HIPM)

When the disk drive is waiting for commands, it can enter one of three IPM modes as requested by the host. The three IPM modes are:

1) Partial mode: PMREQ_P is sent when the host requests the Partial mode.

2) Slumber mode: PMREQ_S is sent when the host requests the Slumber mode.

3) Active mode: When the serial ATA interface is in active state. There are three interface (I/F) power states: Active, Partial, and Slumber. As

requested by the host, the disk drive switches its I/F power state from the Active state to the Partial state, or from the Active state to the Slumber state.

1.12.2 Device-initiated Interface Power Management (DIPM)

If this function is enabled by Set Features command, the disk drive shifts to two kinds of IPM modes automatically under the Idle condition.

1) Partial mode: PMREQ_P is sent when the disk drive requests the Partial

mode.

2) Slumber mode: PMREQ_S is sent when the disk drive requests the Slumber

mode.

I/F power states

1) Active state

The SATA interface is active, and data can be sent and received.

2) Partial state

The SATA interface is in the Power Down state. In this state, the interface is switched to the Partial state when a PMREQ_P signal is received from or sent to host. Because the return time to the Active state from the Partial state is specified as within 10 µs, the degree of the I/F Power Save mode is shallow so that this recovery time is satisfied.

3) Slumber state

The SATA interface is in the Power Down state. In this state, the interface is switched to the Slumber state when a PMREQ_S signal is received from or sent to host. Because the return time to the Active state from the Slumber state is specified as within 10 ms, the degree of the I/F Power Save mode is deep so that this recovery time is satisfied.

1-14 C141-E203-01EN

1.12 Interface Power Management (IPM)

Table 1.8 Interface power management

IPM Mode I/F power state Return time to active I/F condition

Active Active State Partial Partial State

Slumber Slumber State 5 to 10 ms maximum Power Down

5 to 10 µs maximum

−

Active

Power Down

C141-E203-01EN 1-15

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CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate.

C141-E203-01EN 2-1

Device Configuration

2.1 Device Configuration

Figure 2.1 shows the disk drive. The disk drive consists of a disk enclosure (DE), read/write preamplifier, and controller PCA. The disk enclosure contains the disk media, heads, spindle motors, actuators, and a circulating air filter.

Figure 2.1 Disk drive outerview

(1) Disk

The outer diameter of the disk is 65 mm. The inner diameter is 20 mm.

(2) Head

The heads are of the load/unload (L/UL) type. The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts.

(3) Spindle motor

The disks are rotated by a direct drive Sensor-less DC motor.

(4) Actuator

The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays on the ramp out of the disk and is fixed by a mechanical lock.

(5) Air circulation system

The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure.

2-2 C141-E203-01EN

2.2 System Configuration

(6) Read/write circuit

The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise.

(7) Controller circuit

The controller circuit consists of an LSI chip which includes Serial-ATA core to achieve a high-performance native Serial-ATA controller.

2.2 System Configuration

2.2.1 SATA interface

Figure 2.2 shows the SATA interface system configuration. The disk drive complies with ATA/ATAPI-7, SATA 1.0a and SATA II 1.0 standards.

2.2.2 Drive connection

Operating System

Application 1

Application 2

Application 3

Figure 2.2 Drive system configuration

Driver

Serial ATA Adapter

Disk Drive

C141-E203-01EN 2-3

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CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Cable Connections

This chapter gives the external dimensions, installation conditions, surface temperature conditions, cable connections, and switch settings of the hard disk drives.

C141-E203-01EN 3-1

Installation Conditions

3.1 Dimensions

Figure 3.1 illustrates the dimensions of the disk drive. All dimensions are in mm.

*1 The PCA and connectors are not included in these dimensions. *2 Dimension from the center of the user tap to the base of the connector pins *3 Length of the connector pins *4 Dimension from the outer edge of the user tap to the center of the connector

pins

*5 Dimension from the outer edge of the user tap to the innermost edge of the

connector pins

Figure 3.1 Dimensions

3-2 C141-E203-01EN

3.2 Mounting

For information on mounting, see the "FUJITSU 2.5-INCH HDD INTEGRATION GUIDANCE (C141-E144)."

(1) Orientation

Figure 3.2 illustrates the allowable orientations for the disk drive.

gravity

(a) Horizontal –1

(b) Horizontal –1

(e) Vertical –3

Figure 3.2 Orientation

gravity

(d) Vertical –2

gravity

(f) Vertical –4

C141-E203-01EN 3-3

Installation Conditions

(2) Frame

The MR head bias of the HDD disk enclosure (DE) is zero. The mounting frame is connected to Signal Ground (SG).

IMPORTANT

Use M3 screw for the mounting screw and the screw length should satisfy the specification in Figure 3.3.

The tightening torque must be 0.49N•m (5kgf•cm).m (5kgf•cm). When attaching the HDD to the system frame, do not allow the

system frame to touch parts (cover and base) other than parts to which the HDD is attached.

(3) Limit ation of mounting

Note) These dimensions are recommended values; if it is not possible to satisfy

them, contact us.

Bottom surface mounting

Frame of system cabinet

3.0 or less

Details of A

2.5

PCA

Frame of system cabinet

Screw

3.0 or less

Figure 3.3 Mounting frame structure

Side surface mounting

Screw

2.5 2.5

3-4 C141-E203-01EN

3.2 Mounting

IMPORTANT

Because of breather hole mounted to the HDD, do not allow this to close during mounting.

Locating of breather hole is shown as Figure 3.4. For breather hole of Figure 3.4, at least, do not allow its around

φ 2.4 to block.

Figure 3.4 Location of breather

C141-E203-01EN 3-5

Installation Conditions

(4) Ambient temperature

The temperature conditions for a disk drive mounted in a cabinet refer to the ambient temperature at a point 3 cm from the disk drive. The ambient temperature must satisfy the temperature conditions described in Section 1.4, and the airflow must be considered to prevent the DE surface cover temperature from exceeding 60

Provide air circulation in the cabinet such that the PCA side, in particular, receives sufficient cooling. To check the cooling efficiency, measure the surface cover temperatures of the DE. Regardless of the ambient temperature, this surface cover temperature must meet the standards listed in Table 3.1. Figure 3.5 shows the temperature measurement point.

°C.

•

Figure 3.5 Surface cover temperature measurement points

Table 3.1 Surface temperature measurement points and standard values

No. Measurement point Temperature

1 DE cover 60 °C max

3-6 C141-E203-01EN

3.2 Mounting

(5) Service area

Figure 3.6 shows how the drive must be accessed (service areas) during and after installation.

Mounting screw hole

Cable connection

Figure 3.6 Service area

Mounting screw hole

Data corruption: Avoid mounting the disk drive near strong

magnetic sources such as loud speakers. Ensure that the disk drive is not affected by external magnetic fields.

Damage: Do not press the cover of the disk drive. Pressing it too

hard, the cover and the spindle motor contact, which may cause damage to the disk drive.

Static: When handling the device, disconnect the body ground

(500 k

Ω or greater). Do not touch the printed circuit board, but

hold it by the edges.

(6) Handling cautions

Please keep the following cautions, and handle the HDD under the safety environment.

C141-E203-01EN 3-7

Installation Conditions

ying

- General notes

ESD mat

Wrist strap

Use the Wrist stra

Do not hit HDD each other.

Do not to avoid fallin

lace HDD vertically

down.

Shock absorbing mat

Place the shock absorbing mat on the operation table, and place ESD mat on it.

Do not stack when carr

Do not dro

Figure 3.7 Handling cautions

- Installation

(1) Please use the driver of a low impact when you use an electric driver.

HDD is occasionally damaged by the impact of the driver.

(2) Please observe the tightening torque of the screw strictly.

M3 ······· 0.49N

Recommended equipments

•m (5 kgf•cm).m (5 kgf•cm).

Contents Model Maker

Wrist strap JX-1200-3056-8 SUMITOMO 3M ESD

ESD mat SKY-8A (Color Seiden Mat) Achilles

Shock Low shock driver SS-6500 HIOS

3-8 C141-E203-01EN

3.3 Connections with Host System

3.3.1 Device connector

The disk drive has the SATA interface connectors listed below for connecting external devices. Figure 3.8 shows the locations of these connectors and terminals.

ATA interface and power connectors

Figure 3.8 Connector locations

PCA

C141-E203-01EN 3-9

Installation Conditions

3.3.2 Signal segment and power supply segment

Figure 3.9 shows each segment of the SATA interface connector and pin numbers.

View from the

Power supply

segment

connector side

Signal segment

View from the

P1 pins in the power

supply segment

S1 pins in the signal

segment

PCA side

Figure 3.9 Power supply pins (CN1)

3.3.3 Connector specifications for host system

Table 3.2 lists the recommended specifications for the host interface connectors.

Table 3.2 The recommended connector specifications for the host syst em

Segment Name Model (Manufacturer)

SATA interface and power supply

Host receptacle 67492-0220 (Molex) or compatibles

3-10 C141-E203-01EN

3.3 Connections with Host System

3.3.4 SATA interface cable connection

The cable that connects the disk drive to the host system must be compliant with the Serial ATA 1.0a specification.

3.3.5 Note about SATA interface cable connection

Take note of the following precaution about plugging a SATA interface cable into the SATA interface connector of the disk drive and plugging the connector into a host receptacle:

• When plugging together the disk drive SATA interface connector and the

host receptacle or SATA interface cable connector, do not apply more than 10 kgf of force in the connection direction once they are snugly and securely in position.

Note: Hot Plug

These drives support the serial ATA interface and Hot Plug (hot-pluggable). However, the disk drive installation and removal procedures and notes on safety precautions with regard to hot-plugging vary depending on the specific requirements and environment-related conditions of the system to which the drive is connected by hot-plugging.

When using the drive under general conditions of use (i.e., without hot-plugging), observe the important alert messages and notes on safety precautions given in this manual.

For the conditions of use and notes on using the drive with a system that supports hot-plugging, contact our sales representative at one of our offices.

C141-E203-01EN 3-11

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CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.6 Read/write Circuit

4.7 Servo Control

This chapter explains basic design concepts of the disk drive. Also, this chapter explains subassemblies of the disk drive, each sequence, servo control, and electrical circuit blocks.

C141-E203-01EN 4-1

Theory of Device Operation

4.1 Outline

This chapter consists of two parts. First part (Section 4.2) explains mechanical assemblies of the disk drive. Second part (Sections 4.3 through 4.7) explains a servo information recorded in the disk drive and drive control method.

4.2 Subassemblies

The disk drive consists of a disk enclosure (DE) and printed circuit assembly (PCA).

The DE contains all movable parts in the disk drive, including the disk, spindle, actuator, read/write head, and air filter. For details, see Subsections 4.2.1 to 4.2.4.

The PCA contains the control circuits for the disk drive. The disk drive has one PCA. For details, see Sections 4.3.

4.2.1 Disk

The DE contains disks with an outer diameter of 65 mm and an inner diameter of 20 mm.

Servo data is recorded on each cylinder (total 124). Servo data written at factory is read out by the read head. For servo data, see Section 4.7.

4.2.2 Spindle

The spindle consists of a disk stack assembly and spindle motor. The disk stack assembly is activated by the direct drive sensor-less DC spindle motor, which has a speed of 5,400 rpm ±1%. The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting.

4.2.3 Actuator

The actuator consists of a voice coil motor (VCM) and a head carriage. The VCM moves the head carriage along the inner or outer edge of the disk. The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read/write head.

4-2 C141-E203-01EN

4.3 Circuit Configuration

4.2.4 Air filter

There are two types of air filters: a breather filter and a circulation filter.

The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the disk starts or stops rotating. When disk drives are transported under conditions where the air pressure changes a lot, filtered air is circulated in the DE.

The circulation filter cleans out dust and dirt from inside the DE. The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating disk.

4.3 Circuit Configuration

Figure 4.1 shows the power supply configuration of the disk drive, and Figure 4.2 shows the disk drive circuit configuration.

(1) Read/write circuit

The read/write circuit consists of two circuits; read/write preamplifier (PreAMP) and read channel (RDC).

The PreAMP consists of the write current switch circuit, that flows the write current to the head coil, and the voltage amplifier circuit, that amplitudes the read output from the head.

The RDC is the read demodulation circuit using the Modified Extended Partial Response (MEEPR), and contains the Viterbi detector, programmable filter, adaptable transversal filter, times base generator, data separator circuits, RLL (Run Length Limited) encoder and servo demodulation circuit.

(2) Servo circuit

The position and speed of the voice coil motor are controlled by 2 closed-loop servo using the servo information recorded on the data surface. The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voice coil motor.

The MPU precisely sets each head on the track according on the servo information on the media surface.

(3) Spindle m ot o r dr iver circuit

The circuit measures the interval of a PHASE signal generated by counterelectromotive voltage of a motor and controls the motor speed comparing target speed.

C141-E203-01EN 4-3

Theory of Device Operation

(4) Controller circuit

Major functions are listed below.

• Serial-ATA interface control and data transfer control

• Data buffer management

• Sector format control

• Defect management

• ECC control

• Error recovery and self-diagnosis

Figure 4.1 Power Supply Configuration

4-4 C141-E203-01EN

4.3 Circuit Configuration

PCA

Data Buffer

SDRAM

Flash ROM

FROM

SVC

TLS2255

Shoc

Sensor

Console

Serial ATA Interface

MPU & HDC & RDC

(88i6535; Marvell)

MPU

HDC

RDC

SP Motor

Media

Crystal

40MHz

ThermistorVCM

HEAD

Figure 4.2 Circuit Configuration

R/W Pre-Amp

TLS26B624

C141-E203-01EN 4-5

Theory of Device Operation

4.4 Power-on Sequence

Figure 4.3 describes the operation sequence of the disk drive at power-on. The outline is described below.

a) After the power is turned on, the disk drive executes the MPU bus test,

internal register read/write test, and work RAM read/write test. When the self-diagnosis terminates successfully, the disk drive starts the spindle motor.

b) The disk drive executes self-diagnosis (data buffer read/write test) after

enabling response to the SATA interface.

c) After confirming that the spindle motor has reached rated speed, the head

assembly is loaded on the disk.

d) The disk drive positions the heads onto the SA area and reads out the system

information.

e) The disk drive sets up a requirement for execution of self -calibration. This

collects data for VCM torque and mechanical external forces applied to the actuator, and updates the calibrating value.

Power-on

f) The drive becomes ready. The host can issue commands.

Start

Self-diagnosis 1

- MPU bus test

- Internal reg i ste r write/read test

- Work RAM write/read test

The spindle mot or starts.

Self-diagnosis 2

- Data buffer write/read test

Confirming spindle motor speed

Load the head assembl

Initial on-track and read out of system information

Execute self-calibration

Drive ready state (command waiting state)

End

Figure 4.3 Power-on operation sequence

4-6 C141-E203-01EN

4.5 Self-calibration

The disk drive occasionally performs self-calibration in order to sense and calibrate mechanical external forces on the actuator, and VCM torque. This enables precise seek and read/write operations.

4.5.1 Self-calibration contents

(1) Sensing and compensating for external forces

The actuator suffers from torque due to the FPC forces and winds accompanying disk revolution. The torque vary with the disk drive and the cylinder where the head is positioned. To execute stable fast seek operations, external forces are occasionally sensed.

The firmware of the drive measures and stores the force (value of the actuator motor drive current) that balances the torque for stopping head stably. This includes the current offset in the power amplifier circuit and DAC system.

The forces are compensated by adding the measured value to the specified current value to the power amplifier. This makes the stable servo control.

To compensate torque varying by the cylinder, the disk is divided into 13 areas from the innermost to the outermost circumference and the compensating value is measured at the measuring cylinder on each area at factory calibration. The measured values are stored in the SA cylinder. In the self-calibration, the compensating value is updated using the value in the SA cylinder.

(2) Compensating open loop gain

Torque constant value of the VCM has a dispersion for each drive, and varies depending on the cylinder that the head is positioned. To realize the high speed seek operation, the value that compensates torque constant value change and loop gain change of the whole servo system due to temperature change is measured and stored.

For sensing, the firmware mixes the disturbance signal to the position signal at the state that the head is positioned to any cylinder. The firmware calculates the loop gain from the position signal and stores the compensation value against to the target gain as ratio.

For compensating, the direction current value to the power amplifier is multiplied by the compensation value. By this compensation, loop gain becomes constant value and the stable servo control is realized.

To compensate torque constant value change depending on cylinder, whole cylinders from most inner to most outer cylinder are divided into 13 partitions at calibration in the factory, and the compensation data is measured for representative cylinder of each partition. This measured value is stored in the SA area. The compensation value at self-calibration is calculated using the value in the SA area.

C141-E203-01EN 4-7

Theory of Device Operation

4.5.2 Execution timing of self-calibration

Self-calibration is performed once when power is turned on. After that, the disk drive does not perform self-calibration until it detects an error.

That is, self-calibration is performed each time one of the following events occur:

• When it passes from the power on for about 7 or 8 seconds except that the

disk drive shifts to Low Power Idle mode, Standby mode and Sleep mode by execution of any commands.

• The number of retries to write or seek data reaches the specified value.

• The error rate of data reading, writing, or seeking becomes lower than the

specified value.

4.5.3 Command processing during self-calibration

This enables the host to execute the command without waiting for a long time, even when the disk drive is performing self-calibration. The command execution wait time is about maximum 72 ms.

When the error rate of data reading, writing, or seeking becomes lower than the specified value, self-calibration is performed to maintain disk drive stability.

If the disk drive receives a command execution request from the host while performing self-calibration, it stops the self-calibration and starts to execute the command. In other words, if a disk read or write service is necessary, the disk drive positions the head to the track requested by the host, reads or writes data, and then restarts calibration after about 3 seconds.

If the error rate recovers to a value exceeding the specified value, self-calibration is not performed.

4-8 C141-E203-01EN

4.6 Read/write Circuit

The read/write circuit consists of the read/write preamplifier (PreAMP), the write circuit, the read circuit, and the time base generator in the read channel (RDC). Figure 4.4 is a block diagram of the read/write circuit.

4.6.1 Read/write preamplifier (PreAMP)

PreAMP equips a read preamplifier and a write current switch, that sets the bias current to the MR device and the current in writing. Each channel is connected to each data head, and PreAMP switches channel by serial I/O. In the event of any abnormalities, including a head short-circuit or head open circuit, the write unsafe signal is generated so that abnormal write does not occur.

4.6.2 Write circuit

The write data is output from the hard disk controller (HDC) with the NRZ data format, and sent to the encoder circuit in the RDC. The NRZ write data is converted to RLL (Run Length Limited) code data by the encoder circuit then sent to the PreAMP, and the data is written onto the media.

(1) RLL code M EEPRM L

This device converts data using the RLL (Run Length Limited) algorithm.

(2) Write precompensation

Write precompensation compensates, during a write process, for write nonlinearity generated at reading.

Figure 4.4 Read/write circuit bl ock di agram

C141-E203-01EN 4-9

Theory of Device Operation

4.6.3 Read circuit

The head read signal from the PreAMP is regulated by the automatic gain control (AGC) circuit. Then the output is converted into the sampled read data pulse by the programmable filter circuit and the flash digitizer circuit. This clock signal is converted into the NRZ data by the ENDEC circuit based on the read data maximum-likelihood-detected by the Viterbi detection circuit, then is sent to the HDC.

(1) AGC circuit

The AGC circuit automatically regulates the output amplitude to a constant value even when the input amplitude level fluctuates. The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer/inner head positions.

(2) Pr ogr ammable filter circuit

The programmable filter circuit has a low-pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost-up function that equalizes the waveform of the read signal.

-3 dB

Cut-off frequency of the low-pass filter and boost-up gain are controlled from the register in read channel by an instruction of the serial data signal from MPU (M5). The MPU optimizes the cut-off frequency and boost-up gain according to the transfer frequency of each zone.

Figure 4.5 shows the frequency characteristic sample of the programmable filter.

Figure 4.5 Frequency characteristic of programmable filter

4-10 C141-E203-01EN

4.6 Read/write Circuit

(3) FIR circuit

This circuit is 10-tap sampled analog transversal filter circuit that equalizes the head read signal to the Modified Extended Partial Response (MEEPR) waveform.

(4) A/D converter circuit

This circuit changes Sampled Read Data Pulse from the FIR circuit into Digital Read Data.

(5) Vit er b i det ection circuit

The sample hold waveform output from the flash digitizer circuit is sent to the Viterbi detection circuit. The Viterbi detection circuit demodulates data according to the survivor path sequence.

(6) ENDEC

This circuit converts the read data into the NRZ data.

4.6.4 Digital PLL circuit

The drive uses constant density recording to increase total capacity. This is different from the conventional method of recording data with a fixed data transfer rate at all data area. In the constant density recording method, data area is divided into zones by radius and the data transfer rate is set so that the recording density of the inner cylinder of each zone is nearly constant. The drive divides data area into 30 zones to set the data transfer rate.

The MPU transfers the data transfer rate setup data (SD/SC) to the RDC that includes the Digital PLL circuit to change the data transfer rate.

C141-E203-01EN 4-11

Theory of Device Operation

4.7 Servo Control

The actuator motor and the spindle motor are submitted to servo control. The actuator motor is controlled for moving and positioning the head to the track containing the desired data. To turn the disk at a constant velocity, the actuator motor is controlled according to the servo data that is written on the data side beforehand.

4.7.1 Servo control circuit

Figure 4.6 is the block diagram of the servo control circuit. The following describes the functions of the blocks:

(2)

Head

CSR: Current Sense Resister VCM: Voice Coil Motor

Servo burst capture

Position Sense

(1)

MPU

MPU core

(3)

(5)

DAC

Spindle motor control

SVC

(4)

Power Amp

(6)

Driver

(7)

VCM current

CSR

VCM

Spindle motor

Figure 4.6 Block diagram of servo control circuit

(1) Microprocessor unit (MPU)

The MPU executes startup of the spindle motor, movement to the reference cylinder, seek to the specified cylinder, and calibration operations. Main internal operation of the MPU are shown below.

The major internal operations are listed below.

a. Spindle motor start

4-12 C141-E203-01EN

4.7 Servo Control

Starts the spindle motor and accelerates it to normal speed when power is applied.

b. Move head to reference cylinder

Drives the VCM to position the head at the any cylinder in the data area. The logical initial cylinder is at the outermost circumference (cylinder 0).

c. Seek to specified cylinder

Drives the VCM to position the head to the specified cylinder.

d. Calibration

Senses and stores the thermal offset between heads and the mechanical forces on the actuator, and stores the calibration value.

(2) Serv o bur st capture circuit

The servo burst capture circuit reproduces signals (position signals) that indicate the head position from the servo data on the data surface. From the servo area on the data area surface, via the data head, the burst signal of SERVO A, SERVO B, SERVO C, and SERVO D is output as shown in Figure 4.9 in subsequent to the servo mark, gray code that indicates the cylinder position, and index information. The servo signals do A/D-convert by Fourier-demodulator in the servo burst capture circuit. At that time the AGC circuit is in hold mode. The A/D converted data is recognized by the MPU as position information with A-B and C-D processed.

(3) D/A converter (DAC)

The control program calculates the specified data value (digital value) of the VCM drive current, and the value is converted from digital-to-analog so that an analog output voltage is sent to the power amplifier.

(4) Power amplifier

The power amplifier feeds currents, corresponding to the DAC output signal voltage to the VCM.

(5) Spindle motor control circuit

The spindle motor control circuit controls the sensor-less spindle motor. A spindle driver IC with a built-in PLL(FLL) circuit that is on a hardware unit controls the sensor-less spindle motor.

(6) Driver circuit

The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor.

(7) VCM current sense resistor (CSR)

This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back.

C141-E203-01EN 4-13

Theory of Device Operation

4.7.2 Data-surface servo format

Figure 4.7 describes the physical layout of the servo frame. The three areas indicated by (1) to (3) in Figure 4.7 are described below.

(1) Inner guard band (IGB)

This area is located inside the user area, and the rotational speed of the VCM can be controlled on this cylinder area for head moving.

(2) Data area

This area is used as the user data area and the SA cylinder.

(3) Outer guard band (OGB)

This area is located at outer position of the user data area, and the rotational speed of the spindle can be controlled on this cylinder area for head moving.

4-14 C141-E203-01EN

4.7 Servo Control

IGB

Data are

expand

CYLn + 1

W/R Recovery Servo Mark Gray Code

Erase Servo A Erase Servo A

Servo B Erase Servo B Erase

Servo C Erase Servo C

Erase Servo D Erase

CYLn CYLn –1 (n: even number)

W/R Recovery Servo Mark Gray Code

PAD

OGB

Servo frame (124 servo frames per revolution)

Diameter

direction

# #

Circumference

Direction

Erase: DC erase

area

Figure 4.7 Physical sector servo configuration on disk surf ace

C141-E203-01EN 4-15

Theory of Device Operation

4.7.3 Servo frame format

As the servo information, the IDD uses the two-phase servo generated from the gray code and servo A to D. This servo information is used for positioning operation of radius direction and position detection of circumstance direction.

The servo frame consists of 6 blocks; write/read recovery, servo mark, gray code, servo A to D, and PAD. Figure 4.8 shows the servo frame format.

Figure 4.8 Servo frame format

(1) Write/read recovery

This area is used to absorb the write/read transient and to stabilize the AGC.

(2) Servo mark

This area generates a timing for demodulating the gray code and positiondemodulating the servo A to D by detecting the servo mark.

(3) Gr ay code ( including sect or addr ess bits)

This area is used as cylinder address. The data in this area is converted into the binary data by the gray code demodulation circuit

(4) Servo A, servo B, servo C, servo D,

This area is used as position signals between tracks and the IDD control at ontrack so that servo A level equals to servo B level.

(5) PAD

This area is used as a gap between servo and data.

4-16 C141-E203-01EN

4.7 Servo Control

4.7.4 Actuator motor control

The voice coil motor (VCM) is controlled by feeding back the servo data recorded on the data surface. The MPU fetches the position sense data on the servo frame at a constant interval of sampling time, executes calculation, and updates the VCM drive current.

The servo control of the actuator includes the operation to move the head to the reference cylinder, the seek operation to move the head to the target cylinder to read or write data, and the track-following operation to position the head onto the target track.

(1) Operation to move the head to the reference cylinder

The MPU moves the head to the reference cylinder when the power is turned. The reference cylinder is in the data area.

When power is applied the heads are moved from the outside of media to the normal servo data zone in the following sequence:

a) Micro current is fed to the VCM to press the head against the outer direction. b) The head is loaded on the disk. c) When the servo mark is detected the head is moved slowly toward the inner

circumference at a constant speed.

d) If the head is stopped at the reference cylinder from there. Track following

control starts.

(2) Seek operation

Upon a data read/write request from the host, the MPU confirms the necessity of access to the disk. If a read/write instruction is issued, the MPU seeks the desired track.

The MPU feeds the VCM current via the D/A converter and power amplifier to move the head. The MPU calculates the difference (speed error) between the specified target position and the current position for each sampling timing during head moving. The MPU then feeds the VCM drive current by setting the calculated result into the D/A converter. The calculation is digitally executed by the firmware. When the head arrives at the target cylinder, the track is followed.

(3) Track-following operation

Except during head movement to the reference cylinder and seek operation under the spindle rotates in steady speed, the MPU does track following control. To position the head at the center of a track, the DSP drives the VCM by feeding micro current. For each sampling time, the VCM drive current is determined by filtering the position difference between the target position and the position clarified by the detected position sense data. The filtering includes servo compensation. These are digitally controlled by the firmware.

C141-E203-01EN 4-17

Theory of Device Operation

4.7.5 Spindle motor control

Hall-less three-phase twelve-pole motor is used for the spindle motor, and the 3phase full/half-wave analog current control circuit is used as the spindle motor driver (called SVC hereafter). The firmware operates on the MPU manufactured by Fujitsu. The spindle motor is controlled by sending several signals from the MPU to the SVC. There are three modes for the spindle control; start mode, acceleration mode, and stable rotation mode.

(1) Start mode

When power is supplied, the spindle motor is started in the following sequence:

a) After the power is turned on, the MPU sends a signal to the SVC to charge

the charge pump capacitor of the SVC. The charged amount defines the current that flows in the spindle motor.

b) When the charge pump capacitor is charged enough, the MPU sets the SVC

to the motor start mode. Then, a current (approx. 0.3 A) flows into the spindle motor.

c) A phase switching signal is generated and the phase of the current flowed in

the motor is changed in the order of (V-phase to U-phase), (W-phase to Uphase), (W-phase to V-phase), (U-phase to V-phase), (U-phase to W-phase), and (V-phase to W-phase) (after that, repeating this order).

d) During phase switching, the spindle motor starts rotating in low speed, and

generates a counter electromotive force. The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection.

e) The MPU is waiting for a PHASE signal. When no phase signal is sent for a

specific period, the MPU resets the SVC and starts from the beginning. When a PHASE signal is sent, the SVC enters the acceleration mode.

(2) Acceleration mode

In this mode, the MPU stops to send the phase switching signal to the SVC. The SVC starts a phase switching by itself based on the counter electromotive force. Then, rotation of the spindle motor accelerates. The MPU calculates a rotational speed of the spindle motor based on the PHASE signal from the SVC, and waits till the rotational speed reaches 5,400 rpm. When the rotational speed reaches 5,400 rpm, the SVC enters the stable rotation mode.

4-18 C141-E203-01EN

4.7 Servo Control

(3) St able r otation mode

The SVC calculates a time for one revolution of the spindle motor based on the PHASE signal. The MPU takes a difference between the current time and a time for one revolution at 4,200 rpm that the MPU already recognized. Then, the MPU keeps the rotational speed to 4,200 rpm by charging or discharging the charge pump for the different time. For example, when the actual rotational speed is 4,000 rpm, the time for one revolution is 15.000 ms. And the time for one revolution at 4,200 rpm is 14.286 ms. Therefore, the MPU charges the charge pump for 0.714 ms × k (k: constant value). This makes the flowed current into the motor higher and the rotational speed up. When the actual rotational speed is faster than 4,200 rpm, the MPU discharges the pump the other way. This control (charging/discharging) is performed every 1 revolution.

C141-E203-01EN 4-19

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left blank.

CHAPTER 5 Interface

5.1 Physical Interface

5.2 Logical Interface

5.3 Host Commands

5.4 Command Protocol

5.5 Power-on and COMRESET

This chapter gives details about the interface, and the interface commands and timings.

C141-E203-01EN 5-1

Interface

GND

5.1 Physical Interface

5.1.1 Interface signals

Figure 5.1 shows the interface signals.

TX data

RX data

ComWake

ComInit

Host analog front end

TX+

TX−

RX+

RX−

5VDC

Figure 5.1 Interface signals

TX+

TX−

RX+

RX−

Device analog front end

TX data

RX data

ComWake

ComReset

An explanation of each signal is provided below.

TX + / TX -

These signals are the outbound high speed differential signals that are connected to the serial ATA cable.

RX + / RX -

These signals are the inbound high speed differential signals that are connected to the serial ATA cable.

TxData

Serially encoded 10b data attached to the high speed serial differential line driver

5-2 C141-E203-01EN

5.1 Physical Interface

RxData

Serially encoded 10b data attached to the high speed serial differential line receiver

COMWAKE

Signal from the out of band detector that indicates the COMWAKE out of band signal is being detected.

COMRESET / COMINIT

Host: Signal from the out of band detector that indicates the COMINIT out

of band signal is being detected.

Device: Signal from the out of band detector that indicates the COMRESET

out of band signal is being detected.

5VDC/GND

5VDC: +5 V power supply to the disk drive

GND: Ground signal for each signal

C141-E203-01EN 5-3

Interface

5.1.2 Signal interface regulation

5.1.2.1 Out of band signaling

During OOB signaling transmissions, the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in-band data transmission, specified as follows.

COMRESET/COMINIT

COMWAKE

106.7 ns 106.7 ns

106.7 ns

320 ns

5-4 C141-E203-01EN

5.1 Physical Interface

5.1.2.2 Primitives descriptions

The following table contains the primitive mnemonics and a brief description of each.

Primitive Name Description

ALIGN Physical layer control Upon receipt of an ALIGN, the physical layer

readjusts internal operations as necessary to

perform its functions correctly. EOF End of frame EOF marks the end of a frame. PMACK Power management

acknowledge

Sent in response to a PMREQ_S or

PMREQ_P when a receiving node is prepared

to enter a power mode state. PMNAK Power management

denial

Sent in response to a PMREQ_S or

PMREQ_P when a receiving node is not

prepared to enter a power mode state or when

power management is not supported. PMREQ_P Power management

request to partial

This primitive is sent continuously until

PMACK or PMNAK is received. When

PMACK is received, current node (host or

device) will stop PMREQ_P and enters the

Partial power management state.

PMREQ_S Power management

request to Slumber

This primitive is sent continuously until

PMACK or PMNAK is received. When

PMACK is received, current node (host or

device) will stop PMREQ_S and enters the

Slumber power management state. R_ERR Reception error Current node (host or device) detected error in

received payload. R_OK Reception with no error Current node (host or device) detected no

error in received payload. R_RDY Receiver ready Current node (host or device) is ready to

receive payload. SOF Start of frame Start of a frame. Payload and CRC follow to

EOF. SYNC Synchronization Synchronizing primitive - always idle. X_RDY Transmission data ready Current node (host or device) has payload

ready for transmission.

C141-E203-01EN 5-5

Interface

5.1.3 Electrical specifications

Table 5.1 Physical Layer Electrical Requirements (1/2)

Nom Min Max Units Comments

T,UI 666.43 670.12 ps Operating data period (nominal value

architecture specific)

rise

fall

cm,dc

cm,ac coupled TX

cm,ac coupled RX

FCM

settle,CM

diff,tx

diff,rx

0.3 0.15 0.41 UI 20%-80% at transmitter

0.3 0.15 0.41 UI 80%-20% at transmitter

250 200 450 mV Common mode DC level measured at

receiver connector

0 2.0 V Transmitter common mode DC level

measured at TX pins

0 2.0 V Receiver common mode DC level

measured at RX pins

2 200 MHz Sinusoidal common-mode noise

components inside this frequency range with an amplitude of Vcm,ac.

10 ns Maximum time for common-mode

transients to and from the idle bus condition

500 400 600

+/- 250 mV differential nominal.

p-p

Measured at Serial ATA connector on transmit side

400 325 600

+/- 200 mV differential nominal.

p-p

Measured at Serial ATA connector on receive side

Tx pair differential impedance

100 85 115 Ohm As seen by a differential TDR with 100 ps

(max) edge looking into connector (20%-80%). Measured with TDR in differential mode.

Rx pair differential impedance

100 85 115 Ohm As seen by a differential TDR with 100 ps

(max) edge looking into connector (20%-80%). Measured with TDR in differential mode.

Tx single-ended impedance

40 Ohm As seen by TDR with 100 ps (max) edge

looking into connector (20%-80%). TDR set to produce simultaneous positive

pulses on both signals of the Tx pair.

5-6 C141-E203-01EN

5.1 Physical Interface

Table 5.1 Physical Layer Electrical Requirement s ( 2/ 2)

Nom Min Max Units Comments

Rx single-ended impedance

ACcoupling

TX DC clock frequency skew

TX AC clock frequency skew

TX differential skew

Squelch detector threshold

COMRESET/C OMINIT detector off threshold

40 Ohm As seen by TDR with 100 ps (max) edge

looking into connector (20%-80%). TDR set to produce simultaneous positive

pulses on both signals of the Rx pair.

12 nF Coupling capacitance value for AC

coupled TX and RX pairs

-350 +350 ppm Specifies the allowed ppm tolerance for TX DC frequency variations around the nominal 1.5GHz

-5000 +0 ppm Specifies the allowed ppm tolerance for TX AC frequency variations around the nominal 1.5GHz

20 ps Nominal value architecture specific

100 50 200 mV

Minimum differential signal amplitude

p-p

175 525 ns Detector shall reject all bursts with

spacings outside this spec

COMRESET/C OMINIT detector on threshold

COMRESET/C OMINIT transmit spacing

COMWAKE detector off threshold

COMWAKE detector on threshold

COMWAKE transmit spacing

646.67 686.67 ps Operating data period during OOB burst

OOB

320 304 336 ns Detector shall detect all bursts with

spacings meeting this period

320.0 310.4 329.6 ns Differential crosspoints of last and first edges of bursts

55 175 ns Detector shall reject all bursts with

spacings outside this spec

106.7 101.3 112 ns Detector shall detect all burst spacings meeting this period

106.7 103.5 109.9 ns Differential crosspoints from last to first edges of bursts

transmission

C141-E203-01EN 5-7

Interface

5.1.4 Connector pinouts

The pin definitions are shown in Table 5.2.

Table 5.2 Connector pinouts

Signal segment key S1 Gnd 2nd mate S2 A+ S3 AS4 Gnd 2nd mate

Signal

segment

S5 B- Differential signal pair B from Phy S6 B+ S7 Gnd 2nd mate

P1 V33 3.3 V power *1 P2 V33 3.3 V power *1 P3 V33 3.3 V power, pre-charge, 2nd mate *1 P4 Gnd 1st mate P5 Gnd 2nd mate P6 Gnd 2nd mate P7 V5 5 V power, pre-charge, 2nd mate P8 V5 5 V power P9 V5 5 V power

Power

Power segment key Notes:

P10 Gnd 2nd mate

segment

P11 Reserved The pin corresponding to P11 in the backplane

P12 Gnd 1st mate P13 V12 12 V power, pre-charge, 2nd mate *1 P14 V12 12 V power *1 P15 V12 12 V power *1

Central connector polarizer

Differential signal pair A from Phy

Signal segment “L”

Power segment “L”

receptacle connector is also reserved The corresponding pin to be mated with P11

in the power cable receptacle connector shall be grounded

*1 Since applying a single external supply voltage of 5V enables this

drive to operate it is unnecessary to supply +3.3V and +12V power supplies.

5-8 C141-E203-01EN

5.2 Logical Interface

The host system and the device communicate with each other by sending and receiving serial data.

The host and the device have several dedicated communication layers between them. These layers have different functions, enabling communication between the different levels of layers within the host or device and between layers at the same level that link the host and device.

Figure 5.2 is a conceptual diagram of the communication layers.

Host: Software control Buffer Memory DMA engine(s)

Shadow Block Register

Transport Layer

Link Layer

Physical Layer

Host located layers

pplication

layer 4

ransport

layer 3

ink

layer 2

hysical

layer 1

evice: Software control Buffer memory DMA e n gi n e (s )

Block Register

Transport Layer

Link Layer

Physical Layer

Device located layers

Figure 5.2 Conceptual diagram of communication layers

C141-E203-01EN 5-9

Interface

5.2.1 Communication layers

Each of the layers is outlined below.

Physical layer

• Detects, sends, and receives band signals.

• Sends serial data to and receives it from the link layer.

Link layer

• Negotiates against mutual transfer requests between the host system and

device.

• Encodes serial data as 10- or 8-bit data, then converts it into DWORD data.

• Inserts auxiliary signals (SOF, CRC, and EOF), deletes auxiliary signals, and

communicates with the transport and physical layers.

Transport layer

• Exchanges data in communication with the link layer, and builds the frame

information structure (FIS).

• Contains a (Shadow) Block Register.

• Reflects the FIS contents to the Block Register.

5-10 C141-E203-01EN

5.2 Logical Interface

5.2.2 Outline of the Shadow Block Register

Each transport layer in the host system and device has a block register, which is called a Shadow Block Register in the host system, and a Block Register in the device.

These registers are used when the host system issues a command to the device.

Table 5.3 Shadow Block Register

Command Block registers

Read Write

Data Port

Error Features

Sector Count (exp) Sector Count Sector Count (exp) Sector Count

Sector Number (exp) Sector Number Sector Number (exp) Sector Number

Cylinder Low (exp) Cylinder Low Cylinder Low (exp) Cylinder Low Cylinder High (exp) Cylinder High Cylinder High (exp) Cylinder High

Device / Head

Status Command

Control Block registers

Alternate Status Device Control

Note: Each of the Sector Count, Sector Number, Cylinder Low, and Cylinder

High fields has a higher-order field used for issuing the Ext command. The fields are called Sector Count exp, Sector Number exp, Cylinder Low exp, and Cylinder High exp, respectively. For information on writing data to these fields, see "Device Control Field."

C141-E203-01EN 5-11

Interface

9 8 7

5.2.3 Outline of the frame information structure (FIS)

The transport layer converts data written in a Block Register into the FIS, and sends it to the upper layer.

The FIS, which is generated in the transport layer, is explained below.

5.2.3.1 FIS types

The types of FIS are as follows:

• Register- Host to Device

• Register- Device to Host

• DMA Active – Device to Host

• DMA Setup – Device to Host or Host to Device (Bidirectional)

• Set Device Bits – Device to Host

• BIST Active – Bidirectional

• PIO Setup – Device to Host

• Data – Host to Device or Device to Host (Bidirectional)

5.2.3.2 Register - Host to Devi ce

The Register - Host to Device FIS has the following layout:

31 30 29 28 27 26 2

Features Command C R R Reserved (0)

24 23 22 21 20 1

6 5 4 3 2 1 0

FIS Type (27h)

Device LBA High LBA Mid LBA Low

Features (exp) LBA High (exp) LBA Mid (exp) LBA Low (exp)

Control Reserved (0) Sector Count (exp) Sector Count

Reserved (0) Reserved (0) Reserved (0) Reserved (0)

Figure 5.3 Register - Host to Device FIS l ayout

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5.2 Logical Interface

The host system uses the Register - Host to Device FIS when information in the Register Block is transferred from the host system to the device. This is the mechanism for issuing the ATA command from the host system to the device.

C - To update the Command field, "1" would be set in this field; and to update the Device Control field, "0" would be set in the field.

If both C = 1 and SRST = 1 are set, operation is not guaranteed.

5.2.3.3 Register - Device to Host

The Register - Device to Host FIS has the following layout:

31 30 29 28 2

26 25 24 23 22 2

Error Status R I R Reserved (0) FIS Type (34h)

8 7 6 5 4 3 2 1 0

Device LBA High LBA Mid LBA Low

Reserved (0) LBA High (exp) LBA Mid (exp) LBA Low (exp) (0)

Reserved (0) Reserved (0) Sector Count (exp) Sector Count

Reserved (0) Reserved (0) Reserved (0) Reserved (0)

Figure 5.4 Register - Device to Host FIS l ayout

The Register - Device to Host FIS is used when information concerning the Shadow Register Block in the host adapter is updated. This FIS indicates that the device has completed a command operation. Furthermore, this is a mechanism for changing information concerning the Shadow Register Block of the host adapter.

I - If this bit is set, an interrupt request is issued to the host system.

5.2.3.4 DMA Active - Devi ce to Host

The DMA Active - Device to Host FIS has the following layout:

31 30 29 28 2

26 25 24 23 22 2

Reserved (0) Reserved (0) R R R Reserved (0) FIS Type (39h)

9 8 7 6 5 4 3 2 1 0

Figure 5.5 DMA Active - Device to Host FIS layout

C141-E203-01EN 5-13

Interface

9 8 7

The host uses the DMA Active - Device to Host FIS layout. This FIS instructs the host to continue transferring DMA data from the host to the device.

5.2.3.5 DMA Setup - Device t o Host or Host to Device (Bidirectional)

The DMA Setup - Device to Host or Host to Device FIS has the following layout:

31 30 29 28 27 26 2

Reserved (0) Reserved (0) A I D Reserved (0)

24 23 22 21 20 1

6 5 4 3 2 1 0

FIS Type (41h)

0 TAG

Reserved (0)

DMA Buffer Offset

DMA Transfer Count

Reserved (0)

Figure 5.6 DMA Setup - Device to Host or Host t o Device FIS layout

The DMA Setup - Device to Host or Host to Device FIS communicates the start of a first-party DMA access to the host system. This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer.

A - Auto Active bit. If this bit is cleared ("0" is set for the bit), it indicates that a DMA Active FIS transfer is required before a Data FIS transfer.

D - Direction bit. If this bit is set ("1" is set for the bit), it indicates that the data transfer direction is from the device to the host system.

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5.2 Logical Interface

L F P R V

5.2.3.6 BIST Active - Bi directional

The BIST Active - Bidirectional FIS has the following layout:

31 30 29 28 2

Reserved (0) Pattern definition R R R Reserved (0) FIS Type (58h)

26 25 24 23 22 2

T A S

Data [31:24] Data [23:16] Data [23:16] Data [7:0]

8 7 6 5 4 3 2 1 0

Data [31:24] Data [23:16] Data [23:16] Data [7:0]

Figure 5.7 BIST Active - Bidirectional FIS layout

The BIST Active - Bidirectional FIS is used to set the receiver to Loop Back mode. This FIS can be sent by either the host system or device.

The following combinations of pattern definitions are supported:

Table 5.4 BIST combinations

T A S L F P V

Reg

Contents

- - - 1 - - 1 09h SATA Phy Analog Loopback Mode

- - - 1 - - - 10h Far End Retimed Loopback Mode

1 1 - - - - -

C0h No ALIGN Transmit_only Mode (Scramble ON)

(*1)

1 1 1 - - - - E0h No ALIGN Transmit_only Mode (Scramble OFF) 1 1 - - - 1 -

1 1 1 - - 1 -

C4h No ALIGN Transmit_only with primitive Mode

(Scramble ON) (*1)

E4h No ALIGN Transmit_only with primitive Mode

(Scramble OFF) 1 - - - - - - 80h ALIGN Transmit_only Mode (Scramble ON) (*1) 1 - 1 - - - - A0h ALIGN Transmit_only Mode (Scramble OFF)

1 - - - - 1 -

1 - 1 - - 1 -

84h ALIGN Transmit_only with primitive Mode

(Scramble ON) (*1)

A4h ALIGN Transmit_only with primitive Mode

(Scramble OFF)

C141-E203-01EN 5-15

Interface

9 8 7

5.2.3.7 Data - Host to Device or Device to Host (Bidirectional)

This Data FIS has the following layout:

31 30 29 28 27 26 2

Reserved (0) Reserved (0) R R R Reserved (0)

24 23 22 21 20 1

6 5 4 3 2 1 0

FIS Type (46h)

…

N Dwords of data

…

(1 to 2048 Dwords)

Figure 5.8 Data FIS (Bidirecti onal ) layout

The Data FIS is used for data transfers between the host system and device.

5-16 C141-E203-01EN

5.2 Logical Interface

5.2.4 Shadow block registers

(1) Error Field

The Error Field indicates the status of the command executed by the device. The fields are valid when the ERR bit of the Status field is 1.

This register contains a diagnostic code after power is turned on, the Com Reset, or the EXECUTIVE DEVICE DIAGNOSTIC command is executed.

• [Stat us at the completion of command execution other than diagnostic command]

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X UNC X IDNF/ SFRW SFRR ABRT TK0NF AMNF

X: Unused

- Bit 7: Unused

- Bit 6: Uncorrectable Data Error (UNC). This bit indicates that an uncorrectable data error has been encountered.

SATA Frame Error Write (SF RW). This bit indicates that a SATA communication error has been encountered during the write process.

- Bit 5: Unused

- Bit 4: ID Not Found (IDNF). This bit indicates an error except for bad sector, uncorrectable error and SB not found.

Or, SATA Frame Error Write (SFRW) This bit indicates that a SATA communication error has been encountered during the write process. In this case, bit4 and bit2 are set both.

- Bit 3: SATA Frame Error Read (SF RR). This bit indicates that a SATA communication error has been encountered during the read process. In this case, bit3 and bit2 are set both.

- Bit 2: Aborted Command (ABRT). This bit indicates that the requested command was aborted due to a device status error (e.g. Not Ready, Write Fault) or the command code was invalid.

- Bit 1: Track 0 Not Found (TK0NF). This bit indicates that track 0 was not found during RECALIBRATE command execution.

- Bit 0: Address Mark Not Found (AMNF). This bit indicates that the SB Not Found error occurred.

[Diagnostic code]

- X’00’: Format Unit is not completed.

- X’01’: No Error Detected.

- X’02’: HDC Diagnostic Error

C141-E203-01EN 5-17

Interface

- X’03’: Data Buffer Diagnostic Error.

- X’04’: Memory Diagnostic Error.

- X’05’: Reading the system area is abnormal.

- X’06’: Calibration is abnormal.

(2) Features Field (exp)

The Features Field provides specific feature to a command. For instance, it is used with SET FEATURES command to enable or disable caching.

(3) Sector Count Field (exp)

The Sector Count Field indicates the number of sectors of data to be transferred in a read or write operation between the host system and the device. When the value in this field is X’00’, the sector count is 256. With the EXT system command, the sector count is 65536 when value of the Sector Count Field is X'00' and that of the Sector Count Field (exp) is X’00’.

When this field indicates 0 at the completion of the command execution, this indicates that the command is completed successfully. If the command is not completed successfully, this field indicates the number of sectors to be transferred to complete the request from the host system. That is, this field indicates the number of remaining sectors that the data has not been transferred due to the error. However, as of the last sector of PIO transfer, SC=1 indicates the normal completion.

The contents of this field also have other definitions (Refer to 5.4)

(4) Sector Number Field (exp)

The contents of this field indicates the starting sector number for the subsequent command. The sector number should be between X’01’ and [the number of sectors per track defined by INITIALIZE DEVICE PARAMETERS command.

Under the LBA mode, this field indicates LBA bits 7 to 0. Under the LBA mode of the EXT system command, LBA bits 31 to 24 are set in the Sector Number Field, and LBA bits 7 to 0 are set in the Sector Number Field (exp).

(5) Cylinder Low Field (exp)

The contents of this field indicates low-order 8 bits of the starting cylinder address for any disk-access.

At the end of a command, the contents of this field are updated to the current cylinder number.

Under the LBA mode, this field indicates LBA bits 15 to 8. Under the LBA mode of the EXT system command, LBA bits 39 to 32 are set in the Cylinder Low Field, and LBA bits 15 to 8 are set in the Cylinder Low Field (exp).

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5.2 Logical Interface

(6) Cylinder High Field (exp)

The contents of this field indicates high-order 8 bits of the disk-access start cylinder address.

At the end of a command, the contents of this field are updated to the current cylinder number. The high-order 8 bits of the cylinder address are set to the Cylinder High Register.

Under the LBA mode, this field indicates LBA bits 23 to 16. Under the LBA mode of the EXT system command, LBA bits 47 to 40 are set in the Cylinder High Field, and LBA bits 23 to 16 are set in the Cylinder High Field (exp).

(7) Device/Head Field

The contents of this field indicate the device and the head number.

When executing INITIALIZE DEVICE PARAMETERS command, the contents of this field defines “the number of heads minus 1” (a maximum head No.).

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X L X X HS3 HS2 HS1 HS0

- Bit 7: Unused

- Bit 6: L. 0 for CHS mode and 1 for LBA mode.

- Bit 5: Unused

- Bit 4: Unused

- Bit 3: HS3 CHS mode head address 3 (2

). bit 27 for LBA mode.

Unused under the LBA mode of the EXT command.

- Bit 2: HS2 CHS mode head address 2 (2

). bit 26 for LBA mode.

Unused under the LBA mode of the EXT command.

- Bit 1: HS1 CHS mode head address 1 (2

). bit 25 for LBA mode.

Unused under the LBA mode of the EXT command.

- Bit 0: HS0 CHS mode head address 0 (2

). bit 24 for LBA mode.

Unused under the LBA mode of the EXT command.

C141-E203-01EN 5-19

Interface

(8) Status field

The contents of this field indicate the status of the device. The contents of this field are updated at the completion of each command. When the BSY bit is 1, other bits of this field, are invalid.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BSY DRDY DF DSC DRQ 0 0 ERR

- Bit 7: Busy (BSY) bit . This bit is set whenever the Command filed of the shadow block registers for the

host system is accessed. Then this bit is cleared when the command is completed. However, even if a

command is being executed, this bit is cleared during the PIO data transfer request. When BSY bit is 1, the host system should not write the shadow block registers.

This bit is set by the device under following conditions: (a) After COMRESET or SRST is set in the Device Control Field, the BSY bit is

set, then the BSY bit is cleared, when the COMRESET process is completed. The BSY bit is set for no longer than 15 seconds after the IDD accepts reset.

- Bit 6: Device Ready (DRDY) bit . This bit indicates that the device is capable to respond to a command.

The IDD checks its status when it receives a command. If an error is detected (not ready state), the IDD clears this bit to 0. This is cleared to 0 at power-on and it is cleared until the rotational speed of the spindle motor reaches the steady speed.

- Bit 5: Device Write Fault (DF) bit. This bit indicates that a device fault (write fault) condition has been detected.

If a write fault is detected during command execution, this bit is latched and retained until the device accepts the next command or reset.

- Bit 4: Device Seek Complete (DSC) bit. This bit indicates that the device heads are positioned over a track.

In the IDD, this bit is always set to 1 after the spin-up control is completed.

- Bit 3: Data Request (DRQ) bit.

This bit indicates that the device is ready to transfer PIO data of word unit or byte

unit between the host system and the device.

- Bit 2:

Always 0.

- Bit 1:

Always 0.

- Bit 0: Error (ERR) bit. This bit indicates that an error was detected while the previous command was

being executed. The Error field indicates the additional information of the cause for the error.

5-20 C141-E203-01EN

5.2 Logical Interface

(9) Command Field

The Command Field contains a command code being sent to the device. After this field is written, the command execution starts immediately.

Table 5.3 lists the executable commands and their command codes. This table also lists the necessary parameters for each command which are written to certain fields before the Command register is written.

(10) Device Control Field

The Device Control Field contains software reset.

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

X X X X X SRST X 0

- Bit 2: Software Reset (SRST)

This is the host software reset bit. When this bit is set, the device is held reset state.

The slave device is not required to execute the DASP- handshake.

(11) E_Status Field

This field is in the PIO Setup FIS. The field contents are the same as those described in (8), "Status Field." However, the values in the Status field are those before a PIO data transfer, and the values in the E_Status field are those when a PIO data transfer is completed.

(12) DMA Buffer Offset Field

This field is in the DMA Setup FIS, representing byte offset. Since this device does not support byte offset, 0 is always set for the field.

(13) DMA Transfer Count Field

This field is in the DMA Setup FIS, representing the number of bytes to be transferred.

(14) Active Field

This field is in the Set Device Bits FIS. Each bit number corresponds to the tag number of one of 32 commands that can be placed in a queue, and the bit setting of "1" indicates that the corresponding command is completed.

C141-E203-01EN 5-21

Interface

5.3 Host Commands

The host system issues a command to the device by writing necessary parameters in related fileds in the shadow block registers and writing a command code in the Command field of the shadow block registers.

The device can accept the command when the BSY bit is 0 (the device is not in the busy status).

The host system can halt the uncompleted command execution only at execution of hardware or software reset.

When the BSY bit is 1 or the DRQ bit is 1 (the device is requesting the PIO data transfer) and the host system writes to the command field of the shadow block register, the correct device operation is not guaranteed.

5.3.1 Command code and parameters

Table 5.5 lists the supported commands, command code and the related fields to be written necessary parameters at command execution.

Table 5.5 Command code and parameters (1/3)

COMMAND NAME

RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR(S) 0 0 1 0 0 0 0 R N Y Y Y Y READ LONG 0 0 1 0 0 0 1 R N Y Y Y Y WRITE SECTOR(S) 0 0 1 1 0 0 0 R N Y Y Y Y WRITE LONG 0 0 1 1 0 0 1 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0 0 N Y Y Y Y READ VERIFY SECTOR(S) 0 1 0 0 0 0 0 R N Y Y Y Y SEEK 0 1 1 1 X X X X N N Y Y Y EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N N INITIALIZE DEVICE PARAMETERS 1 0 0 1 0 0 0 1 N Y N N Y DOWNLOAD MICROCODE 1 0 0 1 0 0 1 0 Y Y Y N D

STANDBY IMMEDIATE

COMMAND CODE (Bit) PARAMETER USED

7 6 5 4 3 2 1 0 FR SC SN CY DH

1 1 0

N N N N D

IDLE IMMEDIATE

STANDBY

1 1 0

Y N Y Y D

1 0

N Y N N D

5-22 C141-E203-01EN

5.3 Host Commands

Table 5.5 Command code and parameters (2/3)

COMMAND NAME

IDLE

CHECK POWER MODE

SLEEP

SMART 1 0 1 1 0 0 0 0 Y Y Y Y D DEVICE CONFIGURATION 1 0 1 1 0 0 0 1 Y N N N D READ MULTIPLE 1 1 0 0 0 1 0 0 N Y Y Y Y

WRITE MULTIPLE 1 1 0 0 0 1 0 1 N Y Y Y Y SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D READ DMA 1 1 0 0 1 0 0 R N Y Y Y Y WRITE DMA 1 1 0 0 1 0 1 R N Y Y Y Y READ BUFFER 1 1 1 0 0 1 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D

COMMAND CODE (Bit) PARAMETER USED 7 6 5 4 3 2 1 0 FR SC SN CY 1

N Y N N D

1 0

N N N N D

1 1

N N N N D

WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N* N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N N D SECURITY FREEZE LOCK 1 1 1 1 0 1 0 1 N N N N D SECURITY DISABLE

PASSWORD READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D SET MAX 1 1 1 1 1 0 0 1 N Y Y Y Y READ SECTOR(S) EXT 0 0 1 0 0 1 0 0 N Y Y Y D READ DMA EXT 0 0 1 0 0 1 0 1 N Y Y Y D READ NATIVE MAX ADDRESS

EXT

1 1 1 1 0 1 1 0 N N N N D

0 0 1 0 0 1 1 1 N N N N D

READ MULTIPLE EXT 0 0 1 0 1 0 0 1 N Y Y Y D

C141-E203-01EN 5-23

Interface

Table 5.5 Command code and parameters (3/3)

COMMAND NAME

READ LOG EXT 0 0 1 0 1 1 1 1 N Y Y Y D WRITE SECTOR(S) EXT 0 0 1 1 0 1 0 0 N Y Y Y D WRITE DMA EXT 0 0 1 1 0 1 0 1 N Y Y Y D SET MAX ADDRESS EXT 0 0 1 1 0 1 1 1 N Y Y Y Y WRITE MULTIPLE EXT 0 0 1 1 1 0 0 1 N Y Y Y D WRITE LOG EXT 0 0 1 1 1 1 1 1 N Y Y Y D READ VERIFY SECTOR(S) EXT 0 1 0 0 0 0 1 0 N Y Y Y D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D WRITE DMA FUA EXT 0 0 1 1 1 1 0 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D

COMMAND CODE (Bit) PARAMETER USED

7 6 5 4 3 2 1 0 FR SC SN CY DH

CY: cylinder field DH: device/head field FR: features field SC: sector count field SN: sector number field R: Retry at error

1 = Without retry

0 = With retry Y: Necessary to set parameters Y*: Necessary to set parameters under the LBA mode. N: Not necessary to set parameters (The parameter is ignored if it is

set.) N*: May set parameters D: The device parameter is valid, and the head parameter is ignored. X: Do not care

5-24 C141-E203-01EN

5.3 Host Commands

5.3.2 Command descriptions

The contents of the shadow block registers to be necessary for issuing a command and the example indication of the shadow block registers at command completion are shown as following in this subsection.

Example: READ SECTOR (S)

At command issuance

(Shadow Block Registers setting contents)

Bit 7 6 5 4 3 2 1 0 Bit 7 6 5 4 3 2 1 0 CM 0 0 1 0 0 0 0 0 ST Status information DH x L x x HD No./LBA DH x L x x HD No./LBA

CH EXP LBA(47-40) CH EXP LBA(47-40)

CL EXP LBA(39-32) CL EXP LBA(39-32)

SN EXP LBA(31-24) SN EXP LBA(31-24)

SN Start sector No. / LBA (7-0) SN End sector No. / LBA (7-0)

SC EXP Transfer sector count (15-8) SC EXP X ' 00 '

SC Transfer sector count (7-0) SC X ' 00 '

FR EXP xx

FR xx

CH (EXP): Cylinder High Field (EXP) CL (EXP): Cylinder Low Field (EXP) CM: Command Field DH: Device/Head Field ER: Error Field FR (EXP): Features Field (EXP) L: LBA (Logical Block Address) setting bit SN (EXP): Sector Number Field (EXP) SC (EXP): Sector Count Field (EXP) ST: Status Field x, xx: Don't care (setting is not necessary)

Note:

Start cylinder address [MSB] / LBA(23-16)

Start cylinder address

[LSB] / LBA(15-8)

1. When the L bit is specified to 1, the lower 4 bits of the DH field and all bits of the CH field, CL and SN fields indicate the LBA bits (bits of the DH filed are the MSB (mo st significant bit) and bits of the SN field are the LSB (least significant bit).

2. At error occurrence, the SC field indicates the remaining sector count of data transfer.

3. Bit indication is omitted in each command description.

ER Error information

At command completion

(Shadow Block Registers to be read)

End cylinder address

[MSB] / LBA(23-16)

End cylinder address

[LSB] / LBA(15-8)

C141-E203-01EN 5-25

Interface

(1) RECALIBRATE (X’10’ to X’1F’)

This command performs the calibration. When the device completes the calibration, the device reports the status to the host system.

This command can be issued in the LBA mode.

• Error reporting conditions

(1) An error was detected during head positioning (ST = 51h, ER = 02h). (2) A SATA communication error occurred (ST = 51h, ER = 14h).

At command issuance (Shadow Block Registers setting contents)

CM 0 0 0 1 x x x x

DH x x x x xx CH

CL SN SC FR

xx xx xx xx xx

At command completion (Shadow Block Registers contents to be read)

ST Status information DH x x x x xx CH

Error information

xx xx xx xx

Note: Also executable in LBA mode.

5-26 C141-E203-01EN

Fujitsu MHT2080BH, MHT2040BH, MHT2060BH User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FOR SAFE OPERATION

Revision History

Preface

Important Alert Items

Manual Organization

Contents

Illustrations

Figures

Tables

CHAPTER 1 Device Overview

1.1 Features

1.1.1 Functions and performance

1.1.2 Adaptability

1.1.3 Interface

1.2 Device Specifications

1.2.1 Specifications summary

1.2.2 Model and product number

1.3 Power Requirements

1.4 Environmental Specifications

1.5 Acoustic Noise

1.6 Shock and Vibration

1.7 Reliability

1.8 Error Rate

1.9 Media Defects

1.10 Load/Unload Function

1.11 Advanced Power Management

1.12 Interface Power Management (IPM)

1.12.1 Host-initiated Interface Power Management (HIPM)

1.12.2 Device-initiated Interface Power Management (DIPM)

CHAPTER 2 Device Configuration

2.1 Device Configuration

2.2 System Configuration

2.2.1 SATA interface

2.2.2 Drive connection

CHAPTER 3 Installation Conditions

3.1 Dimensions

3.2 Mounting

3.3 Connections with Host System

3.3.1 Device connector

3.3.2 Signal segment and power supply segment

3.3.3 Connector specifications for host system

3.3.4 SATA interface cable connection

3.3.5 Note about SATA interface cable connection

CHAPTER 4 Theory of Device Operation

4.1 Outline

4.2 Subassemblies

4.2.1 Disk

4.2.2 Spindle

4.2.3 Actuator

4.2.4 Air filter

4.3 Circuit Configuration

4.4 Power-on Sequence

4.5 Self-calibration

4.5.1 Self-calibration contents

4.5.2 Execution timing of self-calibration

4.5.3 Command processing during self-calibration

4.6 Read/write Circuit

4.6.1 Read/write preamplifier (PreAMP)

4.6.2 Write circuit

4.6.3 Read circuit

4.6.4 Digital PLL circuit

4.7 Servo Control

4.7.1 Servo control circuit

4.7.2 Data-surface servo format

4.7.3 Servo frame format

4.7.4 Actuator motor control

4.7.5 Spindle motor control

CHAPTER 5 Interface

5.1 Physical Interface

5.1.1 Interface signals

5.1.2 Signal interface regulation

5.1.3 Electrical specifications

5.1.4 Connector pinouts

5.2 Logical Interface

5.2.1 Communication layers

5.2.2 Outline of the Shadow Block Register