FUJITSU MBM29PL3200TE, MBM29PL3200BE70, MBM29PL3200BE90 DATA SHEET

FUJITSU SEMICONDUCTOR

DATA SHEET

PAGE MODE FLASH MEMORY

CMOS

DS05-20890-1E

32 M (2 M

MBM29PL3200TE/BE

DESCRIPTION

■■■■

The MBM29PL3200TE/BE is 32 M-bit, 3.0 V-only Page mode Flash memory organized as 2 M words of 16 bits
each or 1 M words of 32 bits each. The device is off ered in 90-pin SSOP and 84-ball FBGA packages . This device
is designed to be programmed in-system with the standard system 3.0 V V
are not required for write or erase operations. The device can also be reprogrammed in standard EPROM pro­grammers.

PRODUCT LINE-UP

■■■■

Part No. MBM29PL3200TE/BE

V

Ordering Part No.

Max. Random Address Access Time (ns) 70 90

CC = 3.3 V 70 

V

CC = 3.0 V  90

16/1 M

××××

+

0.3 V

−

0.3 V

+

0.6 V

−

0.3 V

32) BIT

××××

70/90

CC supply. 12.0 V VPP and 5.0 V VCC

(Continued)

Max. Page Address Access Time (ns) 25 35
Max. CE
Max. OE Access Time (ns) 25 35

■■■■

Access Time (ns) 70 90

PACKAGES

90-pin plastic SSOP 84-ball plastic FBGA

(FPT-90P-M01) (BGA-84P-M01)

MBM29PL3200TE/BE70/90

(Continued)

The device provides truly high perfor mance non-volatile Flash memory solution. The device offers fast page
access times of 25 ns and 35 ns with random access times of 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE
write enable (WE

The device is command set compatible with JEDEC standard E
register using standard microprocessor write timings. Register contents serve as input to an internal state­machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and
data needed for the programming and erase operations. Reading data out of the device is similar to reading
from 5.0 V and 12.0 V Flash or EPROM devices.

) and output enable (OE) controls. The page size is 8 words or 4 double words.

2

PROMs. Commands are written to the command

),

The device is programmed by executing the program command sequence. This will invoke the Embedded
Program

TM

* Algorithm, which is an internal algorithm that automatically times the program pulse widths and
verifies proper cell margins. Typically, each sector can be programmed and v erified in about 2.2 seconds. Erase
is accomplished by ex ecuting the erase command sequence. This will inv oke the Embedded Erase

TM

* Algorithm,
which is an internal algorithm that automatically preprograms the array if it is not already programmed before
ex ecuting the erase oper ation. During erase, the device automatically times the erase pulse widths and verifies
proper cell margins.

Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.)
The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The device is erased when shipped from the factory.
The device f eatures single 3.0 V po w er supply operation for both read and write functions. Internally generated

and regulated voltages are provided for the program and erase operations. A low V
inhibits write operations on the loss of power. The end of program or erase is detected by Data
by the Toggle Bit feature on DQ

6, output pin. Once the end of a program or erase cycle has been completed,

CC detector automatically

Polling of DQ7,

the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest

levels of quality, reliability, and cost effectiveness. The device memory electrically erases all bits within a sector
simultaneously via Fo wler-Nordhiem tunneling. The words/double words are programmed one word/doub le word
at a time using the EPROM programming mechanism of hot electron injection.

*: Embedded Erase

FEATURES

■■■■

•

•

µµµµ

0.23

m Process Technology

Single 3.0 V read, program and erase

TM

and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

Minimized system level power requirements

•

High Performance Page Mode

25 ns maximum page access time (70 ns random access time)

•

8 words Page (

•

Compatible with JEDEC-standard commands

Uses same software commands as E

•

Compatible with JEDEC-standard world-wide pinouts

××××

16) /4 double words (

××××

32) size

2

PROMs

90-pin SSOP (Package suffix : PFV)
84-ball FBGA (Package suffix : PBT)

•

Minimum 100,000 program/erase cycles

•

Sector erase architecture

One 16 K word, two 8 K words, one 96 K word, and fifteen 128 K words sectors in word mode ( × 16)
One 8 K double word, two 4 K doub le w ords, one 48 K doub le w ord, and fifteen 64 K doub le w ords sectors in
double word mode ( × 32)
Any combination of sectors can be concurrently erased. Also supports full chip erase

2

MBM29PL3200TE/BE70/90

•

Boot Code Sector Architecture

T = Top sector
B = Bottom sector

•

Embedded Erase

Automatically pre-programs and erases the chip or any sector

•

Embedded Program

Automatically programs and verifies data at specified address

•Data

•

Polling and Toggle Bit feature for detection of program or erase cycle completion

Automatic sleep mode

When addresses remain stable, automatically switches themselves to low power mode

•

•

CC

Low V

write inhibit

Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

•

Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Fast Programming Function by Extended command

•

Temporary sector unprotection

Temporary sector unprotection with the software command

• In accordance with CFI (C

TM

Algorithms

TM

Algorithms

≤≤≤≤

2.5 V

ommon Flash Memory Interface)

3

MBM29PL3200TE/BE70/90

PIN ASSIGNMENTS

■■■■

(TOP VIEW)

SSOP

N.C.
N.C.
N.C.
N.C.
N.C.

A
A1
A2
A3
A4
A5

VCC

DQ0

DQ16

DQ1

DQ17

VSS
VCC

DQ2

DQ18

DQ3

DQ19

DQ4

DQ20

DQ5

DQ21

VSS
VCC

DQ6

DQ22

DQ7

DQ23

VSS

A6
A7
A8

A9
A10
A11
A12

N.C.
N.C.
N.C.
N.C.
N.C.

1
2
3
4
5
6

0

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46

N.C.
N.C.
ACC
WP
WE
N.C.
N.C.
N.C.
DW/W
OE
CE
V

SS

DQ31/A-1
DQ15
DQ30
DQ14
VSS
VCC
DQ29
DQ13
DQ28
DQ12
DQ27
DQ11
DQ26
DQ10
VSS
VCC
DQ25
DQ9
DQ24
DQ8
VCC
A19
A18
A17
A16
A15
A14
A13
N.C.
N.C.
N.C.
N.C.
N.C.

FPT-90P-M01

(Continued)

4

(Continued)

A8

CE

A7

N.C.

A6

WE

A5

N.C.

A4
A1

A3
A4

B9

DQ

30

B8

VSS

B7

DW/W

B6

N.C.

B5

ACC

B4
A2

B3
A5

B2

VCC

V

C9

CC

(TOP VIEW)

Marking Side

D9

DQ

DQ

13

MBM29PL3200TE/BE70/90

FBGA

E9

F9

G9

H9

J9

DQ

12

DQ

27

V

CC

DQ

N.C.N.C.N.C.N.C.N.C.N.C.WP

DQ23DQ7DQ6DQ4DQ19VSSDQ1

DQ22VCCVSSDQ20DQ3VCCDQ17

9

K8

J8H8G8F8E8D8C8

VCCDQ24VSSDQ11DQ28DQ29DQ15

A19

K7

J7H7G7F7E7D7C7

A16

A17A18DQ25DQ10VSSDQ14OE

K6

J6H6G6F6E6D6C6

A13

A14A15DQ8N.C.N.C.DQ31/A-1N.C.

K5

J5H5G5F5E5D5C5

N.C.

K4

J4H4G4F4E4D4C4

A10

A9A11A12N.C.DQ2A0A3

K3

J3H3G3F3E3D3C3

A7

A6A8DQ21DQ5DQ18DQ16DQ0

K2

J2H2G2F2E2D2C2

VSS

J1H1G1F1E1D1C1

26

BGA-84P-M01

5

MBM29PL3200TE/BE70/90

PIN DESCRIPTIONS

■■■■

Table 1 MBM29PL3200TE/BE Pin Configuration

Pin Name Function

A

19 to A0, A-1 Address Input

DQ

31 to DQ0 Data Input/Output

CE Chip Enable
OE

WE

DW/W Selects 32-bit or 16-bit mode

WP
ACC Program Acceleration
N.C. Pin Not Connected Internally

V

SS Device Ground

V

CC Device Power Supply

BLOCK DIAGRAM

■■■■

VCC
VSS

WE

DW/W

WP

ACC

CE
OE

State

Control

Circuit

(Command

Register)

Output Enable
Write Enable

Hardware Write Protection

Erase Voltage

Generator

Program Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ31 to DQ0

Input/Output

Buffers

Data Latch

A

19 to A29

A1, A0
(A−1)

Low V

CC Detector

Timer for

Program/Erase

STB

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

33,554,432

Cell Matrix

6

LOGIC SYMBOL

■■■■

20

A-1

A

19 to A0

CE
OE
WE
DW/W

MBM29PL3200TE/BE70/90

32 or 16

DQ31 to DQ0

7

MBM29PL3200TE/BE70/90

DEVICE BUS OPERATION

■■■■

Table 2 MBM29PL3200TE/BE User Bus Operations (DW/W

=

IH)

V

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *

1

1

Extended Auto-Select Device Code *
Read *

3

1

OE WE A0A1A2A3A6A9DQ31 to DQ0WP

LLHLLLLLVID Code X
LLHHLLLLVID Code X
LLHHHHHLVID Code X

LLHA0 A1 A2 A3 A6 A9 DOUT X
Standby H X X XXXXXX HIGH-Z X
Output Disable LHHXXXXXX HIGH-Z X
Write (Program/Erase) L H L A
Enable Sector Protection *
Verify Sector Protection *
Boot Block Sector Write Protection *

Legend : L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.

2, *4

2, *4

LVID LHLLLVID XX

LLHLHLLLVID Code X

5

XXXXXXXXX X L

0 A1 A2 A3 A6 A9 DIN X

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4.
*2:Refer to section on Sector Protection.
*3:WE

can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4:VCC = 3.3 V ± 10%
*5:Protect “outermost” 16 K words (8 K double words) of the boot block sectors.

=

Table 3 MBM29PL3200TE/BE User Bus Operations (DW/W

Operation CE

Auto-Select Manufacturer Code *
Auto-Select Device Code *

1

1

Extended Auto-Select Device Code *
Read *

3

OE WE DQ31/A-1A0A1A2A3A6A9DQ15 to DQ0WP

LLH L LLLLLVID Code X
LLH L HLLLLVID Code X

1

LL H L HHHHLVID Code X
LLH A-1 A0 A1 A2 A3 A6 A9 DOUT X

IL)

V

Standby H X X X XXXXXX HIGH-Z X
Output Disable LHH X XXXXXX HIGH-Z X
Write (Program/Erase) L H L A­Enable Sector Protection *
Verify Sector Protection *
Boot Block Sector Write Protection *

Legend : L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.

2, *4

2, *4

LVID L LHLLLVID XX
LLH L LHLLLVID Code X

5

XXX X XXXXXX X L

1 A0 A1 A2 A3 A6 A9 DIN X

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See Table 4.
*2:Refer to section on Sector Protection.
*3:WE

can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4:VCC = 3.3 V ± 10%
*5:Protect “outermost” 16 K words (8 K double words) of the boot block sectors.

8

Command

Sequence

Read/Reset

DW

W

MBM29PL3200TE/BE70/90

Table 4 MBM29PL3200TE/BE Command Definitions

Bus

Write

First Bus

Write Cycle

Second Bus

Write Cycle

Third Bus

Write Cycle

Cycles

Req’d

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

1XXXhF0h

Fourth Bus
Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Read/Reset

DW

555h

3

AAh

2AAh

55h

555h

F0h RA RD 

W AAAh 555h AAAh

Autoselect

DW

555h

3

AAh

2AAh

55h

555h

90h 

W AAAh 555h AAAh

Program

DW

555h

4

AAh

2AAh

55h

555h

A0h PA PD 

W AAAh 555h AAAh

Chip Erase

DW

555h

6

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h

555h

10h

W AAAh 555h AAAh AAAh 555h AAAh

Sector Erase

DW

555h

6

AAh

2AAh

55h

555h

80h

555h

AAh

2AAh

55h SA 30h

W AAAh 555h AAAh AAAh 555h
Erase Suspend 1 XXXh B0h 
Erase Resume 1 XXXh 30h 

Set to
Fast Mode

Fast
Program *

1

Reset from
Fast Mode *

Temporary
Unprotection
Enable

DW

W AAAh 555h AAAh

DW

WXXXh

DW

1

W XXXh XXXh

DW

W AAAh 555h AAAh

555h

3

AAh

2AAh

55h

555h

20h 

XXXh

2

XXXh

2

555h

4

A0h PA PD 

XXXh

90h

2AAh

AAh

*

F0h

55h

4



555h

E0h XXXh 01h 

Temporary
Unprotection
Disable

Query *

2

Hi-ROM
Entry

Hi-ROM
Program *

3

Hi-ROM

3

Exit *

DW

555h

4

AAh

2AAh

555h

55h

W AAAh 555h AAAh

DW

1

55h

98h





WAAh

DW

555h

3

AAh

2AAh

555h

55h

W AAAh 555h AAAh

DW

555h

4

AAh

2AAh

555h

55h

W AAAh 555h AAAh

DW

555h

4

AAh

2AAh

555h

55h

W AAAh 555h AAAh

E0h XXXh 00h 

88h 

(HRA)

A0h

PA

PD 

90h XXXh 00h 

(Continued)

9

MBM29PL3200TE/BE70/90

(Continued)

DW : Double Word
W : Word

*1:This command is valid while Fast Mode.
*2:The valid addresses are A

6 to A0.

*3:This command is valid while Hi-ROM mode.
*4:The data “00h” is also acceptable.

Notes : 1.Address bits A

19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA), and

Sector Address (SA).

2.Bus operations are defined in Tables 2 and 3.

3.RA = Address of the memory location to be read
PA = Address of the memory location to be programmed

Addresses are latched on the falling edge of the write pulse.

SA = Address of the sector to be erased. The combination of A

will uniquely select any sector.

4.RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5.HRA = Address of the Hi-ROM area Word Mode : 000000h to 000100h

6.The system should generate the following address patterns :
DW (Double Word) Mode : 555h or 2AAh to addresses A
W (Word) Mode : AAAh or 555h to addresses A10 to A0, and A-1

7.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

19, A18, A17, A16, A15, A14, A13 and A12

Double Word Mode : 000000h to 000080h

10 to A0

10

Table 5.1 MBM29PL3200TE Sector Protection Verify Autoselect Codes

Type A

19

to A

MBM29PL3200TE/BE70/90

12

6

A

3

A

2

A

1

A

0

A

A-1 *

1

Code (HEX)

Manufacture’s Code X V

Word

Device Code

Double

XV

Word
Word

XV

XV

Extended Device
Code

Double

Word
Word

Double

Word
Sector Protection
Temporary Sector

Unprotection

*1 : A-

1 is for W ord mode. In double word mode, DQ15 to DQ30 become “High-Z” and DQ31 becomes the lo wer address

“A-

1”.

Sector

Addresses

XVIL VIL VIL VIH VIH VIL 01h *

IL VIL VIL VIL VIL VIL 04h

VIL 227Eh

IL VIL VIL VIL VIH

X 2222227Eh

VIL 2203h

IL VIH VIH VIH VIL

X 22222203h

VIL 2201h

IL VIH VIH VIH VIH

X 22222201h

V

IL VIL VIL VIH VIL VIL 01h *

*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
*3 : Outputs 01h at Temporary Sector Unprotection and outputs 00h at Non Temporary Sector Unprotection.

2

3

11

MBM29PL3200TE/BE70/90

Table 5.2 Expanded Autoselect Code

Type Code

DQ31DQ30DQ29DQ28DQ27DQ26DQ25DQ24DQ23DQ22DQ21DQ20DQ19DQ18DQ17DQ

16

Manufacturer’s
Code

(W)

227Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

04h

A-1/0

000000000000000

Device
Code

Extended
Device
Code

Sector
Protection

2222

(DW)

227Eh

(W)

2203h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

2222

(DW)

2203h

(W)

2201h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

2222

(DW)

2201h

0010001000100010

0010001000100010

0010001000100010

A-1/0

01h

000000000000000

Temporary
Sector

01h

A-1/0

000000000000000

Unprotection

Type

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

0

Manufacturer’s Code0000000000000100

(W)0010001001111110

Device Code

(DW)0010001001111110

(W)0010001000000011

Extended
Device Code

(DW)0010001000000011

(W)0010001000000001

(DW)0010001000000001
Sector Protection 0000000000000001
Temporary Sector

Unprotection

0000000000000001

(W) : Word mode
(DW) : Double Word mode

12

Table 5.3 MBM29PL3200BE Sector Protection Verify Autoselect Codes

Type A

19

to A

MBM29PL3200TE/BE70/90

12

6

A

3

A

2

A

1

A

0

A

A-1 *

1

Code (HEX)

Manufacture’s Code X V

Word

Device Code

Double

XV

Word
Word

XV

XV

Extended Device
Code

Double

Word
Word

Double

Word
Sector Protection
Temporary Sector

Unprotection

*1 : A-

1 is for W ord mode. In double word mode, DQ15 to DQ30 become “High-Z” and DQ31 becomes the lo wer address

“A-

1”.

Sector

Addresses

XVIL VIL VIL VIH VIH VIL 01h *

IL VIL VIL VIL VIL VIL 04h

VIL 227Eh

IL VIL VIL VIL VIH

X 2222227Eh

VIL 2203h

IL VIH VIH VIH VIL

X 22222203h

VIL 2200h

IL VIH VIH VIH VIH

X 22222200h

V

IL VIL VIL VIH VIL VIL 01h *

*2 : Outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses.
*3 : Outputs 01h at Temporary Sector Unprotection and outputs 00h at Non Temporary Sector Unprotection.

2

3

13

MBM29PL3200TE/BE70/90

Table 5.4 Expanded Autoselect Code

Type Code

DQ31DQ30DQ29DQ28DQ27DQ26DQ25DQ24DQ23DQ22DQ21DQ20DQ19DQ18DQ17DQ

16

Manufacturer’s
Code

(W)

227Eh A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

04h

A-1/0

000000000000000

Device
Code

Extended
Device
Code

Sector
Protection

2222

(DW)

227Eh

(W)

2203h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

2222

(DW)

(DW)

2203h

(W)

2200h A-1 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z

2222

2200h

01h

0010001000100010

0010001000100010

0010001000100010

A-1/0

000000000000000

Temporary
Sector

01h

A-1/0

000000000000000

Unprotection

Type

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

0

Manufacturer’s Code 0000000000000100

(W)0010001001111110

Device Code

(DW)0010001001111110

(W)0010001000000011

Extended
Device Code

(DW)0010001000000011

(W)0010001000000000

(DW)0010001000000000
Sector Protection 0000000000000001
Temporary Sector

Unprotection

0000000000000001

(W) : Word mode
(DW) : Double Word mode

14

MBM29PL3200TE/BE70/90

Table 7 Sector Address (MBM29PL3200TE)

Sector Address Sector

Size

Sector

19A18A17A16A15A14A13A12

A

(Kwords/

Double

××××

(

16) Address Range (

kwords)

SA0 0 0 0 0 X X X X 128/64 000000h to 01FFFFh 00000h to 0FFFFh
SA1 0 0 0 1 X X X X 128/64 020000h to 03FFFFh 10000h to 1FFFFh
SA2 0 0 1 0 X X X X 128/64 040000h to 05FFFFh 20000h to 2FFFFh
SA3 0 0 1 1 X X X X 128/64 060000h to 07FFFFh 30000h to 3FFFFh
SA4 0 1 0 0 X X X X 128/64 080000h to 09FFFFh 40000h to 4FFFFh
SA5 0 1 0 1 X X X X 128/64 0A0000h to 0BFFFFh 50000h to 5FFFFh
SA6 0 1 1 0 X X X X 128/64 0C0000h to 0DFFFFh 60000h to 6FFFFh
SA7 0 1 1 1 X X X X 128/64 0E0000h to 0FFFFFh 70000h to 7FFFFh
SA8 1 0 0 0 X X X X 128/64 100000h to 11FFFFh 80000h to 8FFFFh
SA9 1 0 0 1 X X X X 128/64 120000h to 13FFFFh 90000h to 9FFFFh

SA10 1 0 1 0 X X X X 128/64 140000h to 15FFFFh A0000h to AFFFFh

××××

32) Address Range

SA11 1 0 1 1 X X X X 128/64 160000h to 17FFFFh B0000h to BFFFFh
SA12 1 1 0 0 X X X X 128/64 180000h to 19FFFFh C0000h to CFFFFh
SA13 1 1 0 1 X X X X 128/64 1A0000h to 1BFFFFh D0000h to DFFFFh
SA14 1 1 1 0 X X X X 128/64 1C0000h to 1DFFFFh E0000h to EFFFFh
SA15 1 1 1 1 0000 to 1011 96/48 1E0000h to 1F7FFFh F0000h to FBFFFh
SA1611111100 8/4 1F8000h to 1F9FFFh FC000h to FEFFFh
SA1711111101 8/4 1FA000h to 1FBFFFhFD000h to FDFFFh
SA181111111X 16/8 1FC000h to 1FFFFFh FE000h to FFFFFh

Note : The address range is A

The address range is A

19 to A-1 if in word mode (DW/W = VIL).
19 to A0 if in double word mode (DW/W = VIH).

15

MBM29PL3200TE/BE70/90

Table 8 Sector Address (MBM29PL3200BE)

Sector Address Sector

Size

Sector

19A18A17A16A15A14A13A12

A

(Kwords/

Double

××××

(

16) Address Range (

kwords)

SA00000000X 16/8 000000h to 003FFFh 00000h to 01FFFh
SA100000010 8/4 004000h to 005FFFh 02000h to 02FFFh
SA200000011 8/4 006000h to 007FFFh 03000h to 03FFFh
SA3 0 0 0 0 0100 to 1111 96/48 008000h to 01FFFFh 04000h to 0FFFFh
SA4 0001XXXX 128/64 020000h to 03FFFFh 10000h to 1FFFFh
SA5 0010XXXX 128/64 040000h to 05FFFFh 20000h to 2FFFFh
SA6 0011XXXX 128/64 060000h to 07FFFFh 30000h to 3FFFFh
SA7 0100XXXX 128/64 080000h to 09FFFFh 40000h to 4FFFFh
SA8 0101XXXX 128/640A0000h to 0BFFFFh 50000h to 5FFFFh
SA9 0110XXXX 128/640C0000h to 0DFFFFh 60000h to 6FFFFh

SA100111XXXX 128/64 0E0000h to 0FFFFFh 70000h to 7FFFFh

××××

32) Address Range

SA111000XXXX 128/64 100000h to 11FFFFh 80000h to 8FFFFh
SA121001XXXX 128/64 120000h to 13FFFFh 90000h to 9FFFFh
SA131010XXXX 128/64 140000h to 15FFFFh A0000h to AFFFFh
SA141011XXXX 128/64 160000h to 17FFFFh B0000h to BFFFFh
SA151100XXXX 128/64 180000h to 19FFFFh C0000h to CFFFFh
SA161101XXXX 128/641A0000h to 1BFFFFh D0000h to DFFFFh
SA171110XXXX 128/641C0000h to 1DFFFFh E0000h to EFFFFh
SA181111XXXX 128/64 1E0000h to 1FFFFFh F0000h to FFFFFh

Note : The address range is A

The address range is A

19 to A-1 if in word mode (DW/W = VIL).
19 to A0 if in double word mode (DW/W = VIH).

16

MBM29PL3200TE/BE70/90

Table 9 Common Flash Memory Interface Code

A6 to A0DQ15 to DQ

10h
11h
12h

13h
14h

15h
16h

17h
18h

19h
1Ah

0051h
0052h
0059h

0002h
0000h

0040h
0000h

0000h
0000h

0000h
0000h

1Bh 0027h

1Ch 0036h

0

Description

Query-unique ASCII string
“QRY”

Primary OEM Command Set
2h : AMD/FJ standard type

Address for Primary
Extended Table

Alternate OEM Command Set
(00h = not applicable)

Address for Alternate OEM
Extended Table

V

CC Min. (write/erase)

D7-4 : 1 V, D3-0 : 100 mV
V

CC Max. (write/erase)

D7-4 : 1 V, D3-0 : 100 mV
1Dh 0000h VPP Min. voltage
1Eh 0000h V

1Fh 0004h

20h 0000h

21h 000Ah

22h 0000h

23h 0005h

24h 0000h

25h 0006h

26h 0000h

PP Max. voltage

Typical timeout per single

byte/word write (2

Typical timeout for Min. size

buffer write (2

Typical timeout per individual

block erase (2

Typical timeout for full chip

erase (2

N

ms)

Max. timeout for byte/word write

N

(2

× typical time)

Max. timeout for buffer write

N

(2

× typical time)

Max. timeout per individual

block erase (2

Max. timeout for full chip erase

N

(2

× typical time)
27h 0016h Device Size = 2
28h

29h

2Ah
2Bh

2Ch 0004h

0005h
0000h

0000h
0000h

Flash Device Interface
description

Max. number of bytes in
multi-byte write = 2

Number of Erase Block
Regions within device

N

µs)

N

µs)

N

ms)

N

× typical time)

N

byte

N

A6 to A0DQ15 to DQ

2Dh
2Eh
2Fh
30h

31h
32h
33h
34h

35h
36h
37h
38h

40h
41h
42h

0000h
0000h
0080h
0000h

0001h
0000h
0040h
0000h

0000h
0000h
0000h
0003h

0050h
0052h
0049h

0

Description

Erase Block Region 1
Information

Bit0 to 15: y = Number of sectors
Bit16 to 31: z = Size
(Z × 256 Byte)

Erase Block Region 2
Information

Bit0 to 15: y = Number of sectors
Bit16 to 31: z = Size
(Z × 256 Byte)

Erase Block Region 3
Information

Bit0 to 15: y = Number of sectors
Bit16 to 31: z = Size
(Z × 256 Byte)

Query-unique ASCII string
“PRI”

43h 0031h Major version number, ASCII
44h 0033h Minor version number, ASCII

Address Sensitive Unlock

45h 0000h

0h = Required
1h = Not Required

Erase Suspend

46h 0002h

0h = Not Supported
1h = To Read Only
2h = To Read & Write

Sector Protection

47h 0001h

0h = Not Supported
X = Number of sectors per
group

Sector Temporary

48h 0001h

Unprotection
00h = Not Supported
01h = Supported

49h 0003h Sector Protection Algorithm

00h = Not Supported,

4Ah 0000h

X = Total number of sectors in
all Banks except Bank 1

4Bh 0000h

4Ch 0002h

Burst Mode Type
00h = Not Supported

Page Mode Type
00h = Not Supported

(Continued)

17

MBM29PL3200TE/BE70/90

(Continued)

6

to A0DQ15 to DQ

A

4Dh 00B5h

4Eh 00C5h

4Fh 00XXh

Note : DQ31 to DQ16 = “0000h”

0

ACC (Acceleration) Supply
Minimum
00h = Not Supported,
D7-4 : 1 V, D3-0 : 100 mV

ACC (Acceleration) Supply
Maximum
00h = Not Supported,
D7-4 : 1 V, D3-0 : 100 mV

Boot Type
02h = MBM29PL3200BE
03h = MBM29PL3200TE

Description

18

MBM29PL3200TE/BE70/90

FUNCTIONAL DESCRIPTION

■■■■

Read Mode

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE
power control and should be used for de vice selection. OE
to the output pins when a device is selected.

is the output control and should be used to gate data

is the

Address access time (t
access time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE
addresses have been stable pr ior to t
power-up, it is necessary to input hardware reset or to change CE

ACC) is equal to the delay from stable addresses to valid output data. The chip enable

to valid data at the output pins (assuming the

ACC − tOE time). When reading out data without changing addresses after

pin from “H” to “L”.

Page Mode Read

The device is capable of f ast P age mode read and is compatible with the P age mode Mask ROM read oper ation.
This mode provides faster read access speed for random locations within a page. The Page size of the device
is 8 words, or 4 double words, within the appropriate Page being selected by the higher address bits A
and the LSB bits A1 to A0 (in double word mode) and A1 to A-1 (in word mode) determining the specific double
word/word within that page. This is an asynchronous operation with the microprocessor supplying the specific
double word or word location.

The random or initial page access is equal to t
specified by the microprocessor fall within that Page) is equivalent to t
and OE

is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A
double word, or changing A

1 to A-1 to select the specific word within that page. See Figure 5.2 for timing speci-

ACC and subsequent Page read access (as long as the locations

PAC C. Here again, CE selects the device

19 to A2 constant and changing A1 and A0 to select the specific

fications.

Standby Mode

The device has CMOS standby mode (CE
50 µA. In the standby mode, the output pins are in a high impedance state, independent of OE

input held at VCC ± 0.3 V.), when the current consumed is less than

input.

During Embedded Algorithm operation, VCC Active current (ICC2) is required ev en if CE = “H”. The device can be
read with standard access time (tCE) from either of these standby modes.

19 to A2

In the standby mode, the output pins are in the high impedance state, independent of OE

input.

Automatic Sleep Mode

Automatic sleep mode lower consumption during read-out of the device data. This mode can be useful for
applications such as a handy terminal that requires low power consumption.

To activate this mode, the device automatically s witches itself to low pow er mode when addresses remain stable
during access time of 150 ns. It is not necessary to control CE

, WE and OE in this mode. In this mode, the

current consumed is typically 50 µA (CMOS Level).
Since the data are latched during this mode, they are read out continuously. If the addresses are changed, this

mode is canceled automatically, and the device reads the data for changed addresses.

Output Disable

With the OE

input is at a logic high level (VIH), output from the device is disabled. This will put the output pins in

a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the device.

19

MBM29PL3200TE/BE70/90

To activate this mode, the progr amming equipment must f orce V
then be sequenced from the device outputs by toggling address A
DON’T CAREs except A

6, A3, A2, A1, and A0 (A-1). (See Tables 2 and 3.)

ID on address pin A9. Three identifier words may

0 and A1 from VIL to VIH. All addresses are

The manufacturer and device codes may also be read via the command register, for instance when the device
is erased or programmed in a system without access to high voltage on the A

9 pin. The command sequence is

illustrated in Table 11. (Refer to Autoselect Command section.)
A read cycle from address 00h returns the manufacturer’ s code (Fujitsu = 04h). A read cycle from address 01h,

0Eh to 0Fh returns the device code. (See Tables 5.1 to 5.4.)
In order to determine which sectors are write protected, A

addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ

1 must be at VIH while running through the sector

0 (DQ0 = 1).

Write

The device erasure and progr amming are accomplished via the command register. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com­mand register is written by bringing WE
falling edge of WE

or CE, whichever happens later, while data is latched on the rising edge of WE or CE,

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the

whichever happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

Sector Protection

The device f eatures hardware sector protection. This feature will disable both program and erase operations in
any number of sectors (0 through 18). The sector protection feature is enabled using programming equipment
at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V
V

IL, A6 = A3 = A2 = A0 = VIL, A1 = VIH. The sector address pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be

ID on address pin A9 and control pin OE, CE =

set to the sector to be protected. T ab les 7 and 8 define the sector address for each of the nineteen (19) individual
sectors. Programming of the protection circuitry begins on the falling edge of the WE
with the rising edge of the same. Sector addresses must be held constant during the WE

pulse and is terminated

pulse. See Figures 15

and 21 for sector protection waveforms and algorithms.
To verify programming of the protection circuitry, the programming equipment must f orce VID on address pin A9

with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)
while (A

6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector.

Otherwise the device will read 00h for an unprotected sector. In this mode, the lower order address, except for
A

0, A1 and A6 are DON’T CAREs. Address locations with A1 = VIL are reserved for A utoselect man ufacturer and

device codes. A

-1 requires to VIL in word mode.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming
a read operation at the address location XX02h, where the higher order address pins (A
A

13 and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See Tables

19, A18, A17, A16, A15, A14,

5.1 to 5.4 for Autoselect codes.

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the de vice in order to change data.
The Sector Unprotection mode is activated by the command register. In this mode, formerly protected sectors
can be programmed or erased by selecting the sector addresses. Once the mode is taken away using the
command register, all previously protected sectors will be protected again. (See Figure 22.)

20

MBM29PL3200TE/BE70/90

Boot Block Sector Protection

The Write Protection function provides a hardware method of protecting certain “outermost” 16 K word ( × 16
mode) sector without using V

ID.

If the system asserts V

IL on the WP pin, the device disables program and erase functions in the “outermost”

16 K word sector independently of whether this sector was protected or unprotected using the method described
in “Sector Protection/Unprotection”. The outermost 16 K word sector is the highest addresses in
MBM29PL3200TE, or the lowest addresses in MBM29PL3200BE.

(MBM29PL3200TE : SA18, MBM29PL3200BE : SA0)

If the system asserts V

IL on the WP pin, the device re verts to whether the outermost 16 K word sector was last

set to be protected or unprotected. That is, sector protection or unprotection for this sector depends on whether
this was last protected or unprotected using the method described in “Sector protection/unprotection”.

Accelerated Program Operation

The device off ers accelerated program operation which enab les high-speed programming. If the system asserts

ACC

V

to the ACC pin, the device automatically enters the acceleration mode and the time required for program
operation will reduce to about 60%. This function is primarily intended to allow high-speed programming, so
caution is needed as the sector group will temporarily be unprotected.

The system would use a fast program command sequence when programming during acceleration mode.
Set command to fast mode and reset command from f ast mode are not necessary. When the device enters the
acceleration mode, the device is automatically set to f ast mode. Theref ore, the present sequence could be used
for programming and detection of completion in acceleration mode.

Removing V

ACC

from the ACC pin returns the device to normal operation. Do not remove V

ACC

from the ACC pin

while programming. See Figure 16.

21

MBM29PL3200TE/BE70/90

COMMAND DEFINITIONS

■■■■

The device operations are selected b y writing specific address and data sequences into the command register .
Writing incorrect address and data values or writing them in an improper sequence will reset the device to the
read mode. Table 4 defines the valid register command sequences. Note that the Erase Suspend (B0h) and
Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Moreover both
Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that
commands are always written at DQ

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ
Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro­processor read cycles retrieve array data from the memor y. The device remains enabled for reads until the
command register contents are altered.

The device will automatically power-up in the Read/Reset state . In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character­istics and Waveforms for specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
both manufacture and device codes must be accessible while the device resides in the target system. PROM
programmers typically access the signature codes by raising A
voltage onto the address lines is not generally desired system design practice.

15 to DQ0 and DQ31 to DQ16 bits are ignored.

5 = 1) to Read/Reset mode, the Read/

9 to a high voltage. However, multiplexing high

The device contains an A utoselect command operation to supplement tr aditional PR OM programming method­ology. The operation is initiated by writing the Autoselect command sequence into the command register. Fol­lowing the last command write, a read cycle from address XX00h retrieves the manuf acture code of 04h. A read
cycle at address XX01h (XX02h for ×8) returns 7Eh indicating that this device uses an extended device code.
The successive read cycle from XX0Eh to XX0Fh returns this extended de vice code for this de vice . (See Tab les

5.1 to 5.4.)
The sector state (protection or unprotection) will be indicated by address XX02h for × 32 (XX04h for × 16).

Scanning the sector addresses (A
will produce a logical “1” at device output DQ

19, A18, A17, A16, A15, A14, A13 and A12) while (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0)

0 for a protected sector . The programming verification should perform

margin mode verification on the protected sector. (See Tables 2 and 3.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and to

write the Autoselect command during the operation by executing it after writing the Read/Reset command
sequence.

Word/Double Word Programming

The device is programmed on a word-by-word (or double word-by-double word) basis. Programming is a four
bus cycle operation. There are two “unlock” wr ite cycles. These are followed by the program set-up command
and data write cycles. Addresses are latched on the falling edge of CE
data is latched on the rising edge of CE

or WE, whicheve r happens first. The rising edge of the last CE or WE

or WE, whichever happens later, and the

(whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command
sequence, the system is not required to provide further controls or timings. The device will automatically provide
adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The system can determine the status of the program operation by using DQ
The Data

Polling and Toggle Bit must be performed at the memory location which is being programmed.

7 (Data Polling), or DQ6 (Toggle Bit).

The automatic programming operation is completed when the data on DQ

7 is equivalent to data written to this

bit. Then, the device return to the read mode and addresses are no longer latched. (See Table 10, Hardware
Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time.
Hence, Data

Polling must be performed at the memory location which is being programmed.

22

MBM29PL3200TE/BE70/90

Any commands written to the chip during this period will be ignored.
Programming is allowed in any sequence and across sector boundar ies. Beware that a data “0” cannot be

programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.

TM

Figure 17 illustrates the Embedded Program

Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” wr ite cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase
Algorithm command sequence, the device will automatically program and verify the entire memor y for an all­zero data pattern prior to electrical erase (Preprogram Function). The system is not required to provide any
controls or timings during these operations.

Algorithm using typical command strings and bus operations.

The system can determine the status of the erase operation by using DQ
The chip erase begins on the rising edge of the last CE
and terminates when the data on DQ

7 is “1” (See Write Operation Status section), at which time the device

or WE, whichever happens first in the command sequence

7 (Data Polling), or DQ6 (Toggle Bit).

returns to the read mode.
Chip Erase Time = Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
Figure 18 illustrates the Embedded Erase

TM

Algorithm using typical command strings and bus operations.

Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then follo wed b y the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of CE
happens later, while the command (Data = 30h) is latched on the rising edge of CE
After time-out of “t

TOW” from the rising edge of the last sector erase command, the sector erase operation will begin.

or WE, which happens first.

or WE, whichever

Multiple sectors may be erased concurrently by writing the six bus cycle operations on Table 4. This sequence
is followed with writes of the Sector Erase command (30h) to addresses in other sectors desired to be concurrently
erased. The time between writes must be less than “t

TOW”, or that command will not be accepted and erasure

will not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of “t
rising edge of last CE
(s). If another falling edge of CE
timer is reset. (Monitor DQ

or WE, whichever happens first, will initiate the execution of the Sector Erase command

or WE, whichever happens first, occurs within the “tTOW” time-out window, the

3 to determine if the sector erase timer window is still open; see section DQ3, Sector

TOW” from the

Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset
the device to the read mode, ignoring the previous command string. In that case, restart the erase on those
sectors and allow them to complete. (Ref er to Write Operation Status section for Sector Erase Timer oper ation.)
Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 19).

Sector erase does not require the user to program the de vice prior to erase. The de vice automatically progr ams
all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors, the remaining unselected sectors are not affected. The system is not required to provide
any controls or timings during these operations.

The system can determine the status of the erase operation by using DQ
The sector erase begins after the “t

TOW” time out from the rising edge of CE or WE, whichever happens first ,for

the last sector erase command pulse and terminates when the data on DQ
section), at which time the device returns to the read mode. Data

polling and Toggle Bit must be performed at

7 (Data Polling) or DQ6 (Toggle Bit).

7 is “1” (See Write Operation Status

an address within any of the sectors being erased.
Multiple Sector Erase Time = [Sector Erase Time + Sector Program Time (Preprogramming)] × Number of

Sector Erase.

23

MBM29PL3200TE/BE70/90

Erase Suspend/Resume

The Erase Suspend/Resume command allows the user to interrupt a Sector Erase operation and then perf orm
data reads from or programs to a sector not being erased. Erase suspend command is applicab le ONLY during
the Sector Erase operation, which includes the time-out period for sector erase . The Erase Suspend command
will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writing the Erase
Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out
period and suspension of the erase operation.

Writing the Erase Resume command (30h) resumes the erase operation. The addresses are “DON’T CAREs”
when writing the Erase Suspend or Erase Resume command.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximu m
of “t

SPD” to suspend the erase operation. When the device has entered the er ase-suspended mode , the DQ 7 bit

will be at logic “1” and DQ
DQ

6 and DQ7 to determine if the erase operation has been suspended. Further wr ites of the Erase Suspend

command are ignored.
When the erase operation has been suspended, the device def aults to the er ase-suspend-read mode. Reading

data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successiv ely reading from the er ase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ

6 will stop toggling. The user must use the address of the erasing sector for reading

2 to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device b y writing the appropriate com­mand sequence for Program. This program mode will become the erase-suspend-program mode. Again, pro­gramming in this mode is the same as programming in the regular Progr am mode except that the data must be
programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the device is in the erase-suspend-progr am mode will cause DQ
Program operation is detected by the Data
regular Program operation. Note that DQ

polling of DQ7 or by the Toggle Bit I (DQ6), which is the same as the

7 must be read from the Program address while DQ6 can be read from

2 to toggle. The end of the erase-suspended

any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of

the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.

24

MBM29PL3200TE/BE70/90

Extended Command

(1) Fast Mode

The device has a Fast Mode function. This mode dispenses with the initial two unlock cycles required in the
standard program command sequence by writing a Fast Mode command into the command register. In this
mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program
command. (Do not write erase command in this mode.) The read operation is also executed after exiting this
mode. To exit this mode, it is necessary to write a Fast Mode Reset command into the command register. (Refer
to Figure 23.) The V

(2) Fast Programming

In Fast Mode, the prog ramming can be executed with two b us cycle operation. The Embedded Program Algorithm
is executed by writing a program set-up command (A0h) and data write cycles (PA/PD). (Refer to Figure 23.)

(3) CFI (Common Flash Memory Interface)

The CFI (Common Flash Memory Interface) specification outlines the device and host system software interro­gation handshake which allows specific vendor-specified software algorithms to be used for entire families of
the device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible
software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98h) into the command register. F ollowing the command
write, a read cycle from specific address retrieves device inf ormation. Please note that output data of upper byte
(DQ

15 to DQ8) is “0” in word mode (16 bit) read. Refer to the CFI code table . T o terminate operation, it is necessary

to write the Read/Reset command sequence into the register.

CC active current is required even if CE = VIH during Fast Mode.

25

MBM29PL3200TE/BE70/90

Hidden ROM (Hi-ROM) Region

The Hi-ROM feature provides a Flash memor y region that the system may access through a new command
sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the
device with the ESN protected against modification. Once the Hi-ROM region is protected, any further modifi­cation of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.

The Hi-ROM region is 512 words in length. After the system has written the Enter Hi-ROM command sequence,
it may read the Hidden ROM region by using device addresses A
care). That is, the device sends only program command that would normally be sent to the address to the Hi­ROM region. This mode of operation continues until the system issues the Exit Hi-ROM command sequence,
or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to
sending commands to the address.

Hidden ROM (Hi-ROM) Entry Command

The device has a Hidden ROM area with One Time Protect function. This area is to enter the security code and
to unable the change of the code once set. Program/erase is possib le in this area until it is protected. Ho w e ver,
once it is protected, it is impossible to unprotect, so please use this with caution.

Hidden ROM area is 512 words. This area is normally the “outermost” 16 K word boot block area. Therefore,
write the Hidden ROM entry command sequence to enter the Hidden ROM area. It is called Hidden ROM mode
when the Hidden ROM area appears.

7 to A0 (A11 to A8 are “00”, A19 to A12 are don’t

Hidden ROM (Hi-ROM) Program Command

T o program the data to the Hidden R OM area, write the Hidden ROM program command sequence during Hidden
ROM mode. This command is the same as the program command in usual e xcept to write the command during
Hidden ROM mode. Therefore the detection of completion method is the same as in the past, using the DQ
data polling, and DQ6 toggle bit. Need to pay attention to the address to be programmed. If the address other
than the Hidden ROM area is selected to program, data of the address will be changed.

Hidden ROM (Hi-ROM) Protect Command

The method to protect the Hidden ROM is to apply high voltage (V
the Hidden ROM area and (A
mode. To verify the protect circuit, apply high voltage (V

6, A3, A2, A1, A0) = (0, 0, 0, 1, 0), and apply the write pulse during the Hidden ROM

ID

) to A9, specify (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0) and
the sector address in the Hidden ROM area, and read. When “1” appears on DQ
“0” will appear on DQ

0 if it is not protected. Please apply write pulse agian. The same command sequence could

ID

) to A9 and OE, set the sector address in

0, the protect setting is completed.

be used for the above method because other than the Hidden ROM mode, it is the same as the sector protect
in the past. Please refer to “Function Explanation Secor Protection” for details of the sector protect setting.

Other sector will be effected if the address other than those for Hidden ROM area is selected for the sector
address, so please be carefull. Once it is protected, protection can not be cancelled, so please pay the closest
attention.

7

26

MBM29PL3200TE/BE70/90

Write Operation Status

Detailed in Table 10 are all the status flags that can be used to check the status of the device for current mode
operation. During sector erase, the part provides the status flags automatically to the I/O ports. The information
on DQ

2 is address sensitive. This means that if an address from an erasing sector is consecutively read, then

the DQ
read. This allows users to determine which sectors are in erase and which are not.

Once erase suspend is entered, address sensitivity still applies. If the address of a non-erasing sector (that is,
one available for read) is provided, then stored data can be read from the device. If the address of an erasing
sector (that is, one unavailable for read) is applied, the device will output its status bits.

2 bit will toggle. However, DQ2 will not toggle if an address from a non-erasing sector is consecutively

Table 10 Hardware Sequence Flags

7

Status DQ

Embedded Program Algorithm DQ

DQ

7 Toggle 0 0 1

Embedded Erase Algorithm 0 Toggle 0 1 Toggle *

In Progress

Erase
Suspended
Mode

Erase Suspend Read
(Erase Suspended Sector)

Erase Suspend Read
(Non-Erase Suspended Sector)

Erase Suspend Program
(Non-Erase Suspended Sector)

1100Toggle

Data Data Data Data Data

DQ

7 Toggle 0 0 1 *

Embedded Program Algorithm DQ7 Toggle 1 0 1

Exceeded
Time Limits

Embedded Erase Algorithm 0 Toggle 1 1 N/A
Erase Suspend Program

(Non-Erase Suspended Sector)

DQ

7 Toggle 1 0 N/A

*: Successive reads from the erasing or erase-suspend sector will cause DQ

suspend sector address will indicate logic “1” at the DQ

Notes : 1.DQ

0 and DQ1 are reserve pins for future use.

2.DQ

4 is Fujitsu internal use only.

2 bit.

6

2 to toggle. Reading from non-erase

DQ

5

DQ

3

DQ

2

27

MBM29PL3200TE/BE70/90

7

DQ

Data Polling

The device features Data

Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a
complement of data last written to DQ
read the device will produce true data last written to DQ
read the device will produce a “0” at the DQ
attempt to read the device will produce a “1” on DQ

For programming, the Data

Polling is valid after the rising edge of the four th wr ite pulse in the four write pulse

7. Upon completion of the Embedded Program Algorithm, an attempt to

7. During the Embedded Erase Algorithm, an attempt to

7 output. Upon completion of the Embedded Erase Algorithm an

7. The flowchart for Data Polling (DQ7) is sho wn in Figure 19.

sequence.
For chip erase and sector erase, the Data

write pulse sequence. Data

Polling must be performed at the sector address of sectors being erased, not

Polling is valid after the rising edge of the sixth write pulse in the six

protected sectors. Otherwise, the status may be invalid.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ7) may change

asynchronously while the output enable (OE
information on DQ
the system samples the DQ

7 at one instant and then that byte’ s v alid data at the next instant of time . Depending on when

7 output, it may read the status or valid data. Even if the device has completed the

Embedded Algorithm operation and DQ
valid data on DQ

The Data

Polling f eature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm

7 to DQ0 will be read on successive read attempts.

) is asserted low. This means that the device is dr iving status

7 has valid data, data outputs on DQ6 to DQ0 may be still invalid. The

or sector erase time-out. (See Table 10.)
See Figure 9 for the Data

6

DQ

Polling timing specifications and diagrams.

Toggle Bit I

The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.

During the Embedded Program or Erase Algorithm cycle, successive attempts to read (OE
the device will result in DQ
cycle is completed, DQ

6 toggling between one and zero. Once the Embedded Program or Erase Algorithm

6 will stop toggling and valid data will be read on the next successive attempts. During

toggling) data from

programming, the T oggle Bit I is v alid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.

In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop
toggling with data unchanged. In erase, device will erase all selected sectors e xcept f or ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data unchanged.

Either CE
DQ

or OE toggling will cause DQ6 to toggle. In addition, an Erase Suspend/Resume command will cause

6 to toggle.

See Figure 10 and Figure 20 for the Toggle Bit I timing specifications and diagrams.

28

MBM29PL3200TE/BE70/90

5

DQ

Exceeded Timing Limits

DQ

5 will indicate if the program or erase time has exceeded the specified limits (inter nal pulse count). Under

these conditions DQ
cycle was not successfully completed. Data
CE

circuit will partially power down the device under these conditions (to approximately 2 mA). The OE and WE

pins will control the output disable functions as described in Tables 2 and 3.

5 will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is only oper ating function of device under this condition. The

The DQ

5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. In

this case the device locks out and ne ver completes the Embedded Algorithm operation. Hence, the system ne ver
reads valid data on DQ

7 bit and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device f ailure condition since the device w as incorrectly used.
If this occurs, reset the device with the command sequence.

3

DQ

Sector Erase Timer

After completion of the initial sector erase command sequence, sector erase time-out will begin. DQ3 will remain
low until the time-out is completed. Data

Polling and Toggle Bit are valid after the initial sector erase command

sequence.
If Data

Polling or the Toggle Bit I indicates that the device has been written with a valid erase command, DQ3
may be used to determine whether the sector erase timer window is still open. If DQ3 is high (“1”), the internally
controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until
the erase operation is completed as indicated by Data

Polling or Toggle Bit I. If DQ 3 is low (“0”), the device will
accept additional sector erase commands. To insure the command has been accepted, the system software
should check the status of DQ

3 prior to and following each subsequent Sector Erase command. If DQ3 is high

on the second status check, the command may not have been accepted.
See Table 10 : Hardware Sequence Flags.

2

DQ

Toggle Bit II

This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase
Algorithm or in Erase Suspend.

Successive reads from the erasing sector will cause DQ

2 to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ

2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte

address of the non-erase suspended sector will indicate a logic “1” at the DQ
DQ

6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. The behavior of these two status bits, along with that of DQ

2 bit.

7, is summarized

as follows :
For example, DQ2 and DQ6 can be used together to deter mine whether the erase-suspend-read mode is in

progress. (DQ
Furthermore, DQ

mode, DQ

2 toggles while DQ6 does not.) See also Table 11 and Figure 11.

2 can also be used to determine which sector is being erased. When the device is in the erase

2 toggles if this bit is read from an erasing sector.

29

MBM29PL3200TE/BE70/90

6

2

Reading Toggle Bits DQ

Whenever the system initially begins reading toggle bit status , it m ust read DQ7 to DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit
after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the program or er ase oper ation. The system can
read array data on DQ

Howev er, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system
also should note whether the value of DQ
determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ
went high. If the toggle bit is no longer toggling, the device has successfully completed the progra m or erase
operation. If it is still toggling, the device did not complete the operation successfully, and the system must write
the reset command to return to reading array data.

/DQ

7 to DQ0 on the following read cycle.

5 is high (see the section on DQ5). If it is the system should then

5

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ
gone high. The system may continue to monitor the toggle bit and DQ

5 through successive read cycles, deter-

5 has not

mining the status as described in the previous paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status
of the operation. (Refer to Figure 20.)

Table 11 Toggle Bit Status

Mode DQ

7

DQ

6

DQ

2

Program DQ7 Toggle 1
Erase 0 Toggle Toggle (Note)
Erase-Suspend Read

(Erase-Suspended Sector)
Erase-Suspend Program DQ

Note : Successive reads from the erasing or erase-suspend sector will cause DQ

erase suspend sector address will indicate logic “1” at the DQ

11Toggle

7 Toggle 1 (Note)

2 to toggle. Reading from non-

2 bit.

Double Word/Word Configuration

DW/W

pin selects double word (32-bit) mode or word (16-bit) mode f or the device. When this pin is driven high,
the device operates in the doub le word (32-bit) mode . Data is read and progr ammed at DQ
pin is driven low, the device oper ates in word (16-bit) mode. In this mode, the DQ
address bit, and DQ
and hence commands are written at DQ

30 to DQ16 bits are tri-stated. Howev er, the command bus cycle is alw a ys an 16-bit operation

31 to DQ16 and DQ15 to DQ0 bits are ignored. Refer to Figures 12, 13 and

31/A-1 pin becomes the lowest

31 to DQ0. When this

14 for the timing diagram.

Data Protection

The device is designed to off er protection against accidental erasure or programming caused by spurious system
level signals that ma y exist during power transitions . During power-up, the device automatically resets the internal
state machine to Read mode. Also, with its control register architecture, alteration of memory contents only
occurs after successful completion of the specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadver tent wr ite cycles resulting from V
and power-down transitions or system noise.

30

CC power-up

Low V

CC

Write Inhibit

MBM29PL3200TE/BE70/90

To avoid initiation of a write cycle during V
than V

LKO (Min.). If VCC < VLKO, the command register is disabled and all inter nal program/erase circuits are

CC power-up and power-do wn, a write cycle is loc ked out for VCC less

disabled. Under this condition, the device will reset to the read mode. Subsequent wr ites will be ignored until
the V

CC level is g reater than VLK O . It is the user’s responsibility to ensure that the control pins are logically correct

to prevent unintentional writes when V

CC is above VLKO (Min.).

If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector (s) can not be used.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE

, CE, or WE will not initiate a write cycle.

Logical Inhibit

Writing is inhibited by holding any one of OE

= VIL, CE = VIH, or WE = VIH. To initiate a write cycle, CE and WE

must be “L” while OE is a logical one.

Power-up Write Inhibit

Power-up of the device with WE

= CE = VIL and OE = VIH will not accept commands on the rising edge of WE.

The internal state machine is automatically reset to read mode on power-up.

31

MBM29PL3200TE/BE70/90

ABSOLUTE MAXIMUM RATINGS

■■■■

Parameter Symbol

Unit

Min. Max.

Storage Temperature Tstg −55 +125 °C
Ambient Temperature with Power Applied Ta −40 +85 °C

Rating

Voltage with Respect to Ground All pins except A
OE

, and ACC *
Power Supply Voltage *
A

9, OE, and ACC *

1

1

2

9,

VIN, VOUT −0.5 VCC + 0.5 V

VCC −0.5 +4.0 V

VIN −0.5 +13.0 V

*1:Minimum DC voltage on input or l/O pins is −0.5 V. During vo ltage transitions, input or I/O pins ma y undershoot

V

SS to −2.0 V for periods of up to 20 ns. Maximum DC v oltage on input or l/O pins is VCC +0.5 V. During voltage

transitions, input or I/O pins may overshoot to V

CC +2.0 V for periods of up to 20 ns.

*2:Minimum DC input voltage on A9, OE and A CC pins is −0.5 V. During voltage tr ansitions, A9, OE and ACC pins

may undershoot V
(V

IN − VCC) does not exceed 9.0 V. Maximum DC input voltage on A9, OE and ACC pins is +13.0 V which may

SS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage

overshoot to 14.0 V for periods of up to 20 ns.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

RECOMMENDED OPERATING CONDITIONS

■■■■

Value

Parameter Symbol Part No.

Unit

Min. Max.

Ambient Temperature Ta

°C

MBM29PL3200TE/BE 90 −40 +85
MBM29PL3200TE/BE 70 +3.0 +3.6

MBM29PL3200TE/BE 70 −20 +70

Power Supply Voltage V

CC

V

MBM29PL3200TE/BE 90 +2.7 +3.6
Operating ranges define those limits between which the functionality of the device is quaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

32

MAXIMUM OVERSHOOT/UNDERSHOOT

■■■■

MBM29PL3200TE/BE70/90

+0.6 V

−0.5 V

−2.0 V

CC + 2.0 V

V
VCC + 0.5 V

+2.0 V

20 ns

20 ns

20 ns

Figure 1 Maximum Undershoot Waveform

20 ns

20 ns20 ns

Figure 2 Maximum Overshoot Waveform 1

+14.0 V
+13.0 V

V

CC + 0.5 V

Note : This waveform is applied for A9, OE and ACC.

Figure 3 Maximum Overshoot Waveform 2

20 ns

20 ns20 ns

33

MBM29PL3200TE/BE70/90

ELECTRICAL CHARACTERISTICS

■■■■

1. DC Characteristics

Parameter Symbol Conditions

Value

Unit

Min. Max.

Input Leakage Current
(except WP

, ACC)

Output Leakage Current
(except WP

, ACC)

Input Leakage Current
(WP

, ACC)

Output Leakage Current
(WP

, ACC)

A

9, OE, ACC Inputs Leakage

Current

CC Active Current (Read) *

V

V

CC Active Current

(Program/Erase) *
V

CC Current (Standby) ICC3 VCC = VCC Max., CE = VCC ± 0.3 V  5 µA

V

CC Current

2

(Automatic Sleep Mode) *

CC Active Current

V

1

3

(Page Read Mode)

ILI VIN = VSS to VCC, VCC = VCC Max. −1.0 +1.0 µA

ILO VOUT = VSS to VCC, VCC = VCC Max. −1.0 +1.0 µA

ILI VIN = VSS to VCC, VCC = VCC Max. −2.0 +2.0 µA

ILO VOUT = VSS to VCC, VCC = VCC Max. −2.0 +2.0 µA

ILIT

VCC = VCC Max.,
A

9, OE, ACC = 12.5 V

CE = VIL, OE = VIH
f = 10 MHz

 35 µA

Word

80



Double Word 80

ICC1

CE

= VIL, OE = VIH

f = 5 MHz

Word



Double Word 50

50

ICC2 CE = VIL, OE = VIH  80 mA

ICC4

VCC = VCC Max., CE = VSS ± 0.3 V,
V

IN = VCC ± 0.3 V or VSS ± 0.3 V

 5 µA

30 MHz  12

ICC5 CE = VIL, OE = VIH

40 MHz  15

mA

mA

mA

ACC Accelerated Program
Current

I

ACC VCC = VCC Max., ACC = VACC Max.  20 mA

Input Low Level VIL −0.5 0.8 V
Input High Level V
Voltage for Program Acceleration

4

*
Voltage for Autoselect and Sector

Protection (A

9, OE) *

4

Output Low Voltage Level V

IH  2.0 VCC + 0.3 V

VACC  11.5 12.5 V

VID  11.5 12.5 V

OL IOL = 4.0 mA, VCC = VCC Min.  0.45 V

OH1 IOH = −2.0 mA, VCC = VCC Min. 2.4  V

V

Output High Voltage Level

VOH2 IOH = −100 µAVCC − 0.4  V

Low V

CC Lock-Out Voltage VLKO  2.3 2.5 V

*1:The lCC current listed includes both the DC operating current and the frequency dependent component.
*2:l

CC active while Embedded Erase or Embedded Program is in progress.

*3:Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4:(V

ID − VCC) do not exceed 9 V.

34

2. AC Characteristics

(1) Read Only Operations Characteristics

Parameter

JEDEC Standard Min. Max. Min. Max.

Symbol

MBM29PL3200TE/BE70/90

Value

Condition

70 *

1

90 *

2

Unit

Read Cycle Time t
Address to Output Delay t

AVAV tRC  70  90  ns

AVQV tACC

CE = VIL
OE = VIL

 70  90 ns
Page Read Cycle Time  tPRC  25 35 ns
Page Address to Output Delay  t
Chip Enable to Output Delay t

ELQV tCE OE = VIL  70  90 ns

PACC

CE = VIL
OE = VIL

 25  35 ns

Output Enable to Output Delay tGLQV tOE 25  35 ns
Chip Enable to Output HIGH-Z t
Output Enable to Output HIGH-Z t
Output Hold Time From Address,

CE

or OE, Whichever Occurs First

CE or DW/W Switching Low or High 

*1:Test Conditions :

Output Load : 1 TTL gate and 50 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level

Input : 1.5 V
Output : 1.5 V

EHQZ tDF 25  30 ns
GHQZ tDF 25  30 ns

tAXQX tOH  4  5  ns

tELFL

tELFH

5  5ns

*2 Test Conditions :

Output Load : 1 TTL gate and 100 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level

Input : 1.5 V
Output : 1.5 V

Device

Under

Test

IN3064
or Equivalent

6.2 kΩ

CL

Figure 4 Test Conditions

3.3 V

2.7 kΩ

Diodes = IN3064
or Equivalent

35

MBM29PL3200TE/BE70/90

(2) Write (Erase/Program) Operations

Symbol

Parameter

JEDEC Standard

70 *

Min. Typ. Max. Min. Typ. Max.

tAVAV tWC Write Cycle Time 70 90  ns
t

AVWL tAS Address Setup Time 0 0  ns

tWLAX tAH Address Hold Time 45 45  ns

t

DVWH tDS Data Setup Time 35 45  ns

t

WHDX tDH Data Hold Time 0  0  ns

 tOES Output Enable Setup Time 0 0  ns

Value

1

90 *

2

Unit

 t

OEH

Output Enable
Hold Time

Read 0 0  ns
Toggle and Data

Polling 10 10  ns

tGHWL tGHWL Read Recover Time Before Write 0 0  ns

t

GHEL tGHEL

t

ELWL tCS CE Setup Time 0 0  ns

t

WLEL tWS WE Setup Time 0 0  ns

Read Recover Time Before Write
(OE

High to CE Low)

0 0  ns

tWHEH tCH CE Hold Time 0 0  ns
t

EHWH tWH WE Hold Time 0  0  ns

t

WLWH tWP Write Pulse Width 35 35  ns

tELEH tCP CE Pulse Width 35 35  ns

t

WHWL tWPH Write Pulse Width High Level 30 30  ns

t

EHEL tCPH CE Pulse Width High Level 30 30  ns

Double Word  18.3 18.3 

WHWH1 tWHWH1 Programming Operation

t

Word  14.3 14.3 

t

WHWH2 tWHWH2 Sector Erase Operation *

3

 4 4  s
 tVCS VCC Setup Time 50 50  µs
 t
 t
 t

VIDR Rise Time to VID *

VACCR Rise Time to VACC *

VLHT Voltage Transition Time *

 tWPP Write Pulse Width *
 t
 t

OESP OE Setup Time to WE Active *

CSP CE Setup Time to WE Active *

4

5

4

4

4

4

500 500  ns
500 500  ns

4 4  µs

100 100  µs

4 4  µs
4 4  µs

 tEOE Delay Time from Embedded Output Enable 70 90 ns

µs

36

 t
 t

FLQZ DW/W Switching Low to Output HIGH-Z 30 30 ns
FHQV DW/W Switching High to Output Active 35 30  ns

 tTOW Erase Time-out Time 50 50  µs
 t

SPD Erase Suspend Transition Time 20 20 µs

MBM29PL3200TE/BE70/90

*1:Test Conditions :

Output Load : 1 TTL gate and 50 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level

Input : 1.5 V
Output : 1.5 V

*3:This does not include the preprogramming time.
*4:This timing is for Sector Protection operation.
*5:This timing is for Accelerated Program operation.

*2 Test Conditions :

Output Load : 1 TTL gate and 100 pF
Input rise and fall times : 5 ns
Input pulse levels : 0.0 V to 3.0 V
Timing measurement reference level

Input : 1.5 V
Output : 1.5 V

37

MBM29PL3200TE/BE70/90

ERASE AND PROGRAMMING PERFORMANCE

■■■■

Parameter

Sector Erase Time  440s
Word Programming Time  14.3 360

Double Word Programming Time  18.3 480
Chip Programming Time  20 280 s
Erase/Program Cycle 100,000 cycle 

PIN CAPACITANCE

■■■■

Parameter Symbol Condition

Input Capacitance C
Output Capacitance C
Control Pin Capacitance CIN2 VIN = 0 8 10.0 pF

Note : Test conditions Ta = 25 °C, f = 1.0 MHz

Min. Typ. Max.

IN VIN = 067.5pF

OUT VOUT = 0 8 10.0 pF

Value

Unit Comments

Excludes programming time
prior to erasure

Excludes system-level

µs

overhead
Excludes system-level

overhead

Value

Typ. Max.

Unit

FBGA PIN CAPACITANCE

■■■■

Parameter Symbol Condition

Input Capacitance C
Output Capacitance COUT VOUT = 0TBDTBDpF
Control Pin Capacitance C

Note : Test conditions Ta = 25 °C, f = 1.0 MHz

IN VIN = 0TBDTBDpF

IN2 VIN = 0TBDTBDpF

Value

Unit

Typ. Max.

38

SWITCHING WAVEFORMS

■■■■

•

Key to Switching Waveforms

MBM29PL3200TE/BE70/90

WAVEFORM INPUTS OUTPUTS

Address

Must Be
Steady

May
Change
from H to L

May
Change
from L to H

"H" or "L":
Any Change
Permitted

Does Not
Apply

RC

t

Address Stable

Will Be
Steady

Will Be
Change
from H to L

Will Be
Change
from L to H

Changing,
State
Unknown

Center Line is
High­Impedance
"Off" State

CE

OE

WE

Outputs

tACC

tOE tDF

tOEH

tCE

HIGH-Z HIGH-Z

Output Valid

tOH

Figure 5.1 Read Operation Timing Diagram

39

MBM29PL3200TE/BE70/90

19 to A2

A

1 to A0

A

(A-1)

Aa Ab Ac

t

tACC

Same page Address

RC

tPRC

CE

OE

WE

Output

tCE

tOEH

High-Z

tOE

tPACC tPACC

tOH tOH tOH

Da Db Dc

Figure 5.2 Page Read Operation Timing Diagram

tDF

40

MBM29PL3200TE/BE70/90

3rd Bus Cycle Data Polling

Address

555h PA

tWC

tAS tAH

PA

CE

tCS

tCH

OE

tGHWL

tWPHtWP

tWHWH1

WE

tDF

DOUT DOUT

7

Data

tDH

tDS

A0h PD

DQ

Notes : 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at word address.

3.DQ

7 is the output of the complement of the data written to the device.

4.D

OUT is the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

6.These waveforms are for the × 32 mode. (The addresses differ from × 16 mode.)

tRC

tCE

tOE

tOH

Figure 6 Alternate WE

Controlled Program Operation Timing Diagram

41

MBM29PL3200TE/BE70/90

3rd Bus Cycle Data Polling

Address

555h PA

tWC

tAS tAH

WE

tWS

tWH

OE

tGHEL

tCP

tWHWH1

tCPH

CE

Data

tDS

A0h

tDH

PD

Notes : 1.PA is address of the memory location to be programmed.

2.PD is data to be programmed at word address.

3.DQ

7 is the output of the complement of the data written to the device.

4.D

OUT is the output of the data written to the device.

5.Figure indicates last two bus cycles out of four bus cycle sequence.

6.These waveforms are for the × 32 mode. (The addresses differ from × 16 mode.)

DQ

PA

DOUT

7

42

Figure 7 Alternate CE Controlled Program Operation Timing Diagram

MBM29PL3200TE/BE70/90

Address

CE

OE

WE

Data

V

CC

tCS

tGHWL

tVCS

555h 2AAh 555h 555h 2AAh SA*

t

WC

tWP

tDS

tAS

tAH

tCH

tWPH

tDH

AAh 55h 80h AAh 55h 10h

30h for Sector Erase

Note : 1.SA is the sector address f or Sector Erase. Addresses = 555h (Double Word), AAAh (W ord)

for Chip Erase.

2.These wav e forms are for the × 32 mode. (The addresses differ from × 16 mode.)

Figure 8 Chip/Sector Erase Operation Timing Diagram

43

MBM29PL3200TE/BE70/90

CE

tCH

tOE

OE

tOEH

WE

tCE

*

DQ

7

DQ6 to DQ0

Data

Data

tWHWH1 or 2

DQ7

DQ

6 to DQ0 =

Output Flag

DQ7 =
Valid Data

tEOE

DQ
Valid Data

* : DQ7 = Valid Data (The device has completed the Embedded operation)

tDF

6 to DQ0

High-Z

High-Z

Figure 9 Data Polling during Embedded Algorithm Operation Timing Diagram

44

CE

WE

OE

MBM29PL3200TE/BE70/90

tOEH

tOES

DQ

Data (DQ0 to DQ7)

6

tDH

6 = Toggle

DQ

DQ6 = Toggle

*

DQ6 =

Stop Toggling

tOE

* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)

Figure 10 Toggle Bit I during Embedded Algorithm Operation Timing Diagram

Enter

Embedded

Erasing

WE

DQ6

DQ2

DQ2 and DQ6

Erase

Toggle

with OE

Erase

Suspend

Suspend Program

Erase Suspend

Read

Enter Erase

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase

DQ0 to DQ7

Data Valid

Erase

Complete

Note : DQ2 is read from the erase-suspended sector.

Figure 11 DQ2 vs. DQ

6

45

MBM29PL3200TE/BE70/90

CE

tCE

DW/W

DQ

30 to DQ0

DQ31/A-1

CE

DW/W

DQ

30 to DQ0

DQ31/A-1

tELFH

Data Output

(DQ15 to DQ0)

tFHQV

A-1

Data Output

(DQ30 to DQ0)

DQ

31

Figure 12 Double Word Mode Configuration Timing Diagram

tELFL

Data Output

(DQ30 to DQ0)

DQ31

tFLQZ

Data Output

(DQ15 to DQ0)

tACC

A-1

46

Figure 13 Word Mode Configuration Timing Diagram

The falling edge of the last write signal

CE or WE

DW/W

tAS

Input
Valid

tAH

Figure 14 DW/W Timing Diagram for Write Operations

A19, A18, A17
A16, A15, A14

A13, A12

A0

A1

A6

ID

V
3 V

A9

tVLHT

SAX

MBM29PL3200TE/BE70/90

SAY

V

ID

3 V

OE

tVLHT

WE

tOESP

CE

tCSP

Data

tVCS

VCC

SAX : Sector Address for initial sector
SAY : Sector Address for next sector

Note : A

-1 is VIL on word mode.

Figure 15 Sector Protection Timing Diagram

tWPP

tVLHT

tVLHT

01h

tOE

47

MBM29PL3200TE/BE70/90

VCC

VACC
VIH
ACC

CE

WE

tVACCR

tVCS

tVLHT

Program or Erase Command Sequence

Acceleration period

Figure 16 Accelerated Program Timing Diagram

tVLHT

tVLHT

48

EMBEDDED ALGORITHM

Start

Write Program

Command Sequence

(See Below)

Data Polling Device

No

Verify Byte

MBM29PL3200TE/BE70/90

Embedded
Program
Algorithm
in progress

?

Yes

Increment Address

Program Command Sequence* (Address/Command):

No

Programming Completed

Program Address/Program Data

* : The sequence is applied for × 32 mode.

The addresses differ from × 16 mode.

Last Address

?

Yes

555h/AAh

2AAh/55h

555h/A0h

Figure 17 Embedded ProgramTM Algorithm

49

MBM29PL3200TE/BE70/90

EMBEDDED ALGORITHM

Start

Write Erase

Command Sequence

(See Below)

Data Polling or Toggle Bit

from Device

No

Data = FFh

?

Erasure Completed

Embedded
Erase
Algorithm
in progress

Yes

Chip Erase Command Sequence*

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

555h/10h

Individual Sector/Multiple Sector*

Erase Command Sequence

(Address/Command):

555h/AAh

2AAh/55h

555h/80h

555h/AAh

2AAh/55h

Sector Address

/30h

Sector Address

/30h

Sector Address

/30h

Additional sector
erase commands
are optional.

50

* : The sequence is applied for × 32 mode.

The addresses differ from × 16 mode.

Figure 18 Embedded EraseTM Algorithm

MBM29PL3200TE/BE70/90

No

Start

Read Byte

7 to DQ0)

(DQ

Addr. = VA

DQ7 = Data?

DQ5 = 1?

Read Byte

(DQ

7 to DQ0)

Addr. = VA

DQ7 = Data?

*

Fail Pass

Yes

No

Yes

Yes

No

VA = Address for programming

= Any of the sector addresses

within the sector being erased
during sector erase or multiple
erases operation.

= Any of the sector addresses

within the sector not being
protected during sector erase or
multiple sector erases
operation.

* : DQ

7 should be rechecked e v en if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 19 Data Polling Algorithm

51

MBM29PL3200TE/BE70/90

Start

Read

7 to DQ0)

(DQ

Addr. = "H" or "L"

Read

(DQ

7 to DQ0)

Addr. = "H" or "L"

(Note 1)

Yes

Yes

Yes

No

(Notes 1, 2)

No

Program/Erase

Operation
Complete

Toggle Bit

= Toggle?

No

DQ5 = 1?

Read (DQ7 to DQ0)

Twice

Addr. = "H" or "L"

Toggle Bit
= Toggle?

Program/Erase

Operation Not

Complete.Write

Reset Command

Notes : 1.Read toggle bit twice to determine whether or not it is toggling.

2.Recheck toggle bit because it may stop toggling as DQ

5 changes to “1”.

52

Figure 20 Toggle Bit Algorithm

MBM29PL3200TE/BE70/90

Start

Setup Sector Group Addr.

A

19, A18, A17,A16,

()

A15, A14, A13, A12

PLSCNT = 1

OE = VID, A9 = VID, CE = VIL,

A

6 = A3 = A2 = A0 = VIL, A1 = VIH

Activate WE Pulse

Increment PLSCNT

No

PLSCNT = 25?

Yes Yes

Remove V

Write Reset Command

ID from A9

Device Failed

Time out 100 µs

WE = V

IH, CE = OE = VIL

(A9 should remain VID)

Read from Sector

Addr. = SA, A

()

A6 = A3 = A2 = A0 = VIL

No

Data = 01h?

Protect Another Sector

Remove V

Write Reset Command

Sector Protection

Completed

1 = VIH

?

No

ID from A9

*

Yes

* : A

-1 is V IL on word mode.

Figure 21 Sector Protection Algorithm

53

MBM29PL3200TE/BE70/90

Temporary Unprotect Enable

Command Write (Note 1)

Perform Erase or

Program Operations

Temporary Unprotect

Disable Command Write

Start

Temporary Sector

Unprotection Completed

(Note 2)

Notes : 1.All protected sectors are unprotected.

2.All previously protected sectors are protected once again.

Figure 22 Temporary Sector Unprotection Algorithm

54

FAST MODE ALGORITHM

MBM29PL3200TE/BE70/90

Start

555h/AAh

Increment Address

2AAh/55h

555h/20h

XXXh/A0h

Program Address/Program Data

Data Polling Device

Verify Data?

Yes

No

Last Address?

Yes

Programming Completed

XXXXh/90h

XXXXh/F0h

No

Set Fast Mode

In Fast Program

Reset Fast Mode

Notes 1 : The sequence is applied for × 32 mode.

2 : The addresses differ from × 16 mode.

Figure 23 Embedded Programming Algorithm for Fast Mode

55

MBM29PL3200TE/BE70/90

ORDERING INFORMATION

■■■■

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29PL3200 T E 70 PFV

PACKAGE TYPE
PFV = 90-Pin Shrink Outline L-leaded

Package (SSOP)

PBT = 84-Ball Fine Pitch Ball Grid Array

Package (FBGA)

DEVICE NUMBER/DESCRIPTION
MBM29PL3200
32 Mega-bit (2 M × 16-Bit or 1 M × 32-Bit) CMOS Page Mode Flash Memory

3.0 V-only Read, Write, and Erase

Valid Combinations

MBM29PL3200TE/BE

70
90

PFV
PBT

SPEED OPTION
See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector

Valid Combinations

Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Fujitsu sales office to confirm availability
of specific valid combinations and to check on
newly released combinations.

56

PACKAGE DIMENSIONS

■■■■

90-pin plastic SSOP

(FPT-90P-M01)

MBM29PL3200TE/BE70/90

23.70±0.30(.933±.012)

90

INDEX

1 45

C

2000 FUJITSU LIMITED F90001S-1c-1

0.50(.020)

0.08(.003)

0.22±0.05

(.009±.002)

46

13.30±0.20
(.524±.008)

0.08(.003)

16.00±0.30
(.630±.012)

M

+0.05
–0.03

0.17

+.002

.007 –.001

1.80±0.10

(.071±.004)

0.55±0.10

(.022±.004)

"A"

(Mounting height)

(Stand off)

Details of "A" part

0°~8°

0.73/1.00

(.029/.039)

0.25(.010)

Dimensions in mm (inches)

(Continued)

57

MBM29PL3200TE/BE70/90

(Continued)

84-ball plastic FBGA

(BGA-84P-M01)

11.00±0.10(.433±.004)

8.00±0.10

(.315±.004)

+0.15
–0.10

1.05

+.006

.041 –.004

0.38±0.10

(.015±.004)

(Mounting height)

(Stand off)

6.40(.252)
REF

7.20(.283)REF

0.80(.031)
TYP

9
8
7
6
5
4
3
2
1

INDEX-MARK AREA

0.10(.004)

C

2000 FUJITSU LIMITED B84001S-1c-1

84-Ø0.45±0.05

(84-Ø.018Ø.002)

ABCDEFGHJK

INDEX SIDE

0.08(.003)

M

Dimensions in mm (inches)

58

MBM29PL3200TE/BE70/90

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: [phone]
Fax: [phone]

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: [phone]
Fax: [phone]

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: [phone]
Fax: [phone]

http://www.fujitsumicro.com/

Europe

FUJITSU MICROELECTRONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: [phone]
Fax: [phone]

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: [phone]
Fax: [phone]

http://www.fmap.com.sg/

Korea

FUJITSU MICROELECTRONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: [phone]
Fax: [phone]

All Rights Reserved.

The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.

The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.

The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.

FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.

Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.

F0101

 FUJITSU LIMITED Printed in Japan