FUJITSU MBM29PL160TD-75, MBM29PL160TD-90, MBM29PL160BD-90, MBM29PL160BD-75 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

PAGE MODE FLASH MEMORY

CMOS

16M (2M × 8/1M × 16) BIT

DS05-20872-1E

MBM29PL160TD

FEATURES

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• Single 3.0 V read, program and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Uses same software commands as E

• Compatible with MASK ROM pinouts

48-pin TSOP (I) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 44-pin SOP (Package suffix: PF)

• Minimum 100,000 program/erase cycles

• High performance

25 ns maximum page access time (75ns maximum random access time)

• An 8 words page read mode function

• Sector erase architecture

One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector B = Bottom sector

• Embedded Erase

Automatically pre-programs and erases the chip or any sector

• Embedded program

Automatically programs and verifies data at specified address

•Data

• Ready/Busy output (RY/BY)

• Automatic sleep mode

•Low V

Polling and Toggle Bit feature for detection of program or erase cycle completion

Hardware method for detection of program or erase cycle completion

When addresses remain stable, automatically switches themselves to low power mode

write inhibit ≤ 2.5 V

Algorithms

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PROMs

/MBM29PL160BD

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(Continued)

Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.

MBM29PL160TD

(Continued)

• Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device

• Sector protection

Hardware method disables any combination of sectors from program or erase operations

• Temporary sector unprotection

Temporary sector unprotection with the software command

• 5V tolerant (Data, Address, and Control Signals)

• In accordance with CFI (C

PACKAGE

■

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ommon Flash Memory Interface)

Marking Side

/MBM29PL160BD

48-pin plastic TSOP (I)

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44-pin plastic SOP

(FPT-44P-M16)

Marking Side

(FPT-48P-M20)(FPT-48P-M19)

MBM29PL160TD

GENERAL DESCRIPTION

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The MBM29PL160TD/BD is a 16M-bit, 3.0 V-only Flash memory organized as 2M bytes of 8 bits each or 1M words of 16 bits each. The MBM29PL160TD/BD is offered in a 48-pin TSOP (I), and 44-pin SOP pac kages. The device is designed to be programmed in-system with the standard system 3.0 V V V V

are not required for write or erase operations. The de vice can also be reprogr ammed in standard EPROM

programmers. The standard MBM29PL160TD/BD offers access times of 75 ns and 90 ns, allowing operation of high-speed

microprocessors without wait states. To eliminate bus contention the de vice has separate chip enable (CE enable (WE

The MBM29PL160TD/BD is pin and command set compatible with JEDEC standard E written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations . Reading data out of the de vice is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The MBM29PL160TD/BD is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. Typically, each sector can be programmed and verified in about 2.0 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before e xecuting the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margins.

), and output enable (OE) controls.

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/MBM29PL160BD

supply. 12.0 V VPP and 5.0

PROMs. Commands are

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), write

Any individual sector is typically erased and verified in 4.8 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and

reprogrammed without affecting other sectors. The MBM29PL160TD/BD is erased when shipped from the factory .

The device f eatures single 3.0 V power supply oper ation f or both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V inhibits write operations on the loss of power. The end of program or erase is detected by Data or by the Toggle Bit feature on DQ the device internally resets to the read mode.

Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiv eness . The MBM29PL160TD/BD memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The b ytes/words are programmed one b yte/word at a time using the EPROM programming mechanism of hot electron injection.

output pin. Once the end of a program or erase cycle has been comleted,

detector automatically

Polling of DQ7

MBM29PL160TD

FLEXIBLE SECTOR-ERASE ARCHITECTURE

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• One 8K word, two 4K words, one 112K word, and seven 128K words sectors in word mode.

• One 16K byte, two 8K bytes, one 224K byte, and seven 256K bytes sectors in byte mode.

• Individual-sector, multiple-sector, or bulk-erase capability.

• Individual or multiple-sector protection is user definable.

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 256 Kbytes or 128 Kwords 000000H to 03FFFFH 00000H to 1FFFFH SA1 256 Kbytes or 128 Kwords 040000H to 07FFFFH 20000H to 3FFFFH SA2 256 Kbytes or 128 Kwords 080000H to 0BFFFFH 40000H to 5FFFFH SA3 256 Kbytes or 128 Kwords 0C0000H to 0FFFFFH 60000H to 7FFFFH SA4 256 Kbytes or 128 Kwords 100000H to 13FFFFH 80000H to 9FFFFH SA5 256 Kbytes or 128 Kwords 140000H to 16FFFFH A0000H to BFFFFH SA6 256 Kbytes or 128 Kwords 180000H to 1BFFFFH C0000H to DFFFFH SA7 224 Kbytes or 112 Kwords 1C0000H to 1F7FFFH E0000H to FBFFFH SA8 8 Kbytes or 4 Kwords 1F8000H to 1F9FFFH FC000H to FCFFFH SA9 8 Kbytes or 4 Kwords 1FA000H to 1FBFFFH FD000H to FDFFFH

SA10 16 Kbytes or 8 Kwords 1FC000H to 1FFFFFH FE000H to FFFFFH

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MBM29PL160TD Top Boot Sector Architecture

Sector Sector Size (× 8) Address Range (× 16) Address Range

SA0 16 Kbytes or 8 Kwords 000000H to 003FFFH 00000H to 01FFFH SA1 8 Kbytes or 4 Kwords 004000H to 005FFFH 02000H to 02FFFH SA2 8 Kbytes or 4 Kwords 006000H to 007FFFH 03000H to 03FFFH SA3 224 Kbytes or 112 Kwords 008000H to 03FFFFH 04000H to 1FFFFH SA4 256 Kbytes or 128 Kwords 040000H to 07FFFFH 20000H to 3FFFFH SA5 256 Kbytes or 128 Kwords 080000H to 0BFFFFH 40000H to 5FFFFH SA6 256 Kbytes or 128 Kwords 0C0000H to 0FFFFFH 60000H to 7FFFFH SA7 256 Kbytes or 128 Kwords 100000H to 13FFFFH 80000H to 9FFFFH SA8 256 Kbytes or 128 Kwords 140000H to 17FFFFH A0000H to BFFFFH SA9 256 Kbytes or 128 Kwords 180000H to 1BFFFFH C0000H to DFFFFH

SA10 256 Kbytes or 128 Kwords 1C0000H to 1FFFFFH E0000H to FFFFFH

MBM29PL160BD Bottom Boot Sector Architecture

MBM29PL160TD

PRODUCT LINE UP

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Part No. MBM29PL160TD/160BD

Ordering Part No.

= 3.0 V

+0.6 V –0.3 V

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Max. Address Access Time (ns) 75 90 Max. Page Address Access Time (ns) 25 35 Max. CE

Access Time (ns) 75 90

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Max. OE

■

Access Time (ns) 25 35

BLOCK DIAGRAM

BYTE

CE OE

State

Control

Command

Program Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

DQ0 to DQ

Input/Output

Buffers

Data Latch

A0 to A

STB

Low V

Detector

-1

Timer for

Program/Erase

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

MBM29PL160TD

CONNECTION DIAGRAMS

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/MBM29PL160BD

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SOP

(Marking Side)

144

243

342 441

540

639 738

837

936

10 35 11 34

12 33

13 32

14 31

15 30 16 29

17 28

18 27 19 26

20 25 21 24

22 23

FPT-44P-M16

N.C. A

BYTE V

DQ15/A DQ

TSOP(I)

BYTE

A A A A A A A

N.C.

A A

11 12 13

23 24

(Marking Side)

Standard Pinout

N.C.

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

DQ15/A DQ

OE V

N.C.

-1

FPT-48P-M19

-1

A A

N.C.

A A A A A A A

BYTE

14 13 12

2 1

(Marking Side)

Reverse Pinout

N.C.

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

OE DQ

DQ15/A V

N.C.

-1

FPT-48P-M20

MBM29PL160TD

LOGIC SYMBOL

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Table 1 MBM29PL160TD/BD Pin Configuration

Pin Function

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-1

A0 to A

CE OE WE BYTE

DQ0 to DQ

16 or 8

-1

, A0 to A

DQ0 to DQ

BYTE

N.C.

Address Inputs Data Inputs/Outputs Chip Enable Output Enable Write Enable Selects 8-bit or 16-bit mode Pin Not Connected Internally Device Ground

Device Power Supply

MBM29PL160TD

DEVICE BUS OPERATIONS

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Table 2 MBM29PL160TD/BD User Bus Operation (BYTE = VIH)

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Operation CE

OE WE A

Auto-Select Manufacture Code (1) L L H L L L V Auto-Select Device Code (1) L L H H L L V Read (3) L L H A

DQ0 to DQ

Code Code

OUT

Standby H X X X X X X HIGH-Z Output Disable LHHXXXXHIGH-Z Write (Program/Erase) L H L A Enable Sector Protection (2), (4) L V

LHLVIDX

Verify Sector Protection (2), (4) L L H L H L V

Table 3 MBM29PL160TD/BD User Bus Operation (BYTE

Operation CE

OE WE

DQ15/

-1

Auto-Select Manufacture Code (1) L L H L L L L V Auto-Select Device Code (1) L L H L H L L V Read (3) L L H A

-1

Code

= VIL)

DQ0 to DQ

Code Code

OUT

Standby H X X X X X X X HIGH-Z Output Disable L H H X X X X X HIGH-Z Write (Program/Erase) L H L A Enable Sector Protection (2), (4) L V

-1

LLHLV

Verify Sector Protection (2), (4) L L H L L H L V

Legend: Notes:

L = V

1. Manufacturer and device codes may also be accessed via a command register write sequence. See

, H = VIH, X = VIL or VIH. = pulse input. See DC Characteristics for voltage levels.

Code

Table 7.

2. Refer to the section on Sector Protection.

3. WE

4. V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

= 3.3 V ±10%

MBM29PL160TD

FUNCTIONAL DESCRIPTION

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/MBM29PL160BD

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Random Read Mode

The MBM29PL160TD/BD has two control functions which must be satisfied in order to obtain data at the outputs. CE

is the power control and should be used for a de vice selection. OE is the output control and should be used

to gate data to the output pins if a device is selected. Address access time (t

access time (t enable access time is the delay from the falling edge of OE addresses have been stable for at least t out a data without changing addresses after powe-up, it is necessary to input hardware reset or to change CE pin from "H" to "L".

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

) is equal to the delay from stable addresses to valid output data. The chip enable

ACC

to valid data at the output pins. (Assuming the

- tOE time.) See Figure 5.1 for timing specifications. When reading

ACC

Page Read Mode

The MBM29PL160TD/BD is capable of fast P age read mode and is compatible with the P age mode MASK ROM read operation. This mode provides faster read access speed f or random locations within a page. The P age size of the MBM29PL160TD/BD device is 8 words, or 16 bytes, within the appropriate Page being selected by the higheraddress bits A bytewithin that page. This is an asynchronous oper ation with the microprocessor supplying the specific word or byte location.

The rondom or initial page access is equal to t specified by the microprocessor fall within that Page) is equivalent to t and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast Page mode accesses are obtained by keeping A word, or changing A

to A2 (in the word mode) and A-1 to A2 (in the byte mode) determining the specific word/

and subsequent Page read access (as long as the locations

ACC

. Here again, CE selects the device

PAC C

to A19 constant and changing A0 to A2 to select the specific

to A2 to select the specific byte, within that page. See Figure 5.2 for timing specifications.

-1

Standby Mode

The MBM29PL160TD/BD has a standby mode, a CMOS standby mode (CE input hel at VCC ±0.3 V.), when the current consumed is less than 50 µA. During Embedded Algorithm operation, V even CE

= “H”. The device can be read with standard access time (tCE) from standby modes.

Active current (I

) is required

CC2

In the standby mode, the outputs are in the high-impedance state, independent of the OE is deselected during erasure or programming, the device will dr aw active current until the operation is completed.

input. If the device

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of MBM29PL160TD/BD data. This mode can be used effectively with an application requesting low power consumption such as handy terminals.

To activate this mode, MBM29PL160TD/BD automatically switches itself to low power mode when addresses remain stable for 150 ns. It is not necessary to control CE current consumed is typically 50 µA (CMOS Lev e l).

Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system.

, WE, and OE in this mode. During such mode, the

Output Disable

If the OE input is at a logic high lev el (VIH), output from the device is disabled. This will cause the output pins to be in a high-impedance state.

MBM29PL160TD

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/MBM29PL160BD

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Autoselect

The Autoselect mode allows the reading out of a binary code from the device and will identify its manu facturer and type. The intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. The Autoselect command ma y also be used to check the status of write-protected sectors. (See Tables 4.1 and 4.2.) This mode is functional ov er the entire temper ature range of the device.

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the devices outputs by toggling address A addresses are DON’T CARES except A

, A1, and A6 (A-1). (See Table 2 or Table 3.) (Recomend to set VIL for

(11.5 V to 12.5 V) on address pin A9. Two

from VIL to VIH. All

the other addresses pins.) The manufacturer and device codes may also be read via the command register, for instances when the

MBM29PL160TD/BD is erased or programmed in a system without access to high voltage on the A

pin. The

command sequence is illustrated in Table 7, Command Definitions. Word 0 (A

= VIL) represents the manufacture’ s code and w ord 1 (A0 = VIH) represents the device identifier code.

For the MBM29PL160TD/BD these two bytes are given in the Table 4.2. All identifiers for manufactures and device will exhibit odd parity with DQ executing the Autoselect, A

If BYTE = V

= VIL (for byte mode), the de vice code is 27H (f or top boot bloc k) or 45H (for bottom boot b lock). If BYTE

(for word mode), the device code is 2227H (for top boot block) or 2245H (for bottom boot block).

must be VIL. (See Tables 2 or 3.)

In order to determine which sectors are write protected, A addresses; if the selected sector is protected, a logical ‘1’ will be output on DQ

defined as the parity bit. In order to read the proper device codes when

must be at VIH while running through the sector

(DQ0 =1).

MBM29PL160TD

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/MBM29PL160BD

Table 4.1 MBM29PL160TD/BD Sector Protection Verify Autoselect Code

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Type A

to A

Manufacture’s Code X V

Byte

MBM29PL160TD

A-1*

V V

Code

(HEX)

04H 27H

Word X 2227H

Device Code

MBM29PL160BD

Byte

45H

Word X 2245H

Sector Protection

Sector

Addresses

Temporary Sector Unprotection X V

01H*

*1: A-1 is for Byte mode. *2: Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses. *3: Outputs 01H at Temporary Sector Unprotect and outputs 00H at Non Temporary Sector Unprotect.

Table 4.2 Expanded Autoselect Code Table

Type

Code DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

Manufacture’s Code 04H A-1/0000000000000100

(B)

MBM29PL160TD

Device Code

MBM29PL160BD

27H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z10100111

(W) 2227H

(B)

45H A-1HI-ZHI-ZHI-ZHI-ZHI-ZHI-ZHI-Z01000101

(W)

2245H

Sector Protection 01H A Temporary Sector

Unprotection

01H A

(B): Byte mode (W): Word mode

0010001010100111

0010001001000101

/0000000000000001

-1

/0000000000000001

-1

MBM29PL160TD

Table 5 Sector Address Tables (MBM29PL160TD)

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/MBM29PL160BD

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Sector

Address

(× 8) Address Range (× 16) Address Range

SA0 000XXXXX000000H to 03FFFFH 00000H to 1FFFFH SA1 001XXXXX040000H to 07FFFFH 20000H to 3FFFFH SA2 010XXXXX080000H to 0BFFFFH 40000H to 5FFFFH SA3 011XXXXX0C0000H to 0FFFFFH60000H to 7FFFFH SA4 100XXXXX100000H to 13FFFFH 80000H to 9FFFFH SA5 101XXXXX140000H to 17FFFFH A0000H to BFFFFH SA6 110XXXXX180000H to 1BFFFFH C0000H to DFFFFH SA7 1 1 1 00000 - 11011 1C0000H to 1F7FFFH E0000H to FBFFFH SA8 111111001F8000H to 1F9FFFHFC000H to FCFFFH SA9 111111011FA000H to 1FBFFFHFD000H to FDFFFH

SA101111111X1FC000H to 1FFFFFH FE000H to FFFFFH

Table 6 Sector Address Tables (MBM29PL160BD)

Sector

Address

(× 8) Address Range (× 16) Address Range

SA0 0000000X000000H to 003FFFH 00000H to 01FFFH SA1 00000010004000H to 005FFFH 02000H to 02FFFH SA2 00000011006000H to 007FFFH 03000H to 03FFFH SA3 0 0 0 00100 - 11111 008000H to 03FFFFH 04000H to 1FFFFH SA4 001XXXXX040000H to 07FFFFH 20000H to 3FFFFH SA5 010XXXXX080000H to 0BFFFFH 40000H to 5FFFFH SA6 011XXXXX0C0000H to 0FFFFFH60000H to 7FFFFH SA7 100XXXXX100000H to 13FFFFH 80000H to 9FFFFH SA8 101XXXXX140000H to 17FFFFH A0000H to BFFFFH SA9 110XXXXX180000H to 1BFFFFH C0000H to DFFFFH

SA10 111XXXXX1C0000H to 1FFFFFHE0000H to FFFFFH

MBM29PL160TD

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Write

Device erasure and progr amming are accomplished via the command register . The command register is written by bringing WE WE

, whichever occurs later, while data is latched on the rising edge of CE or WE pulse, whichever occurs first.

Standard microprocessor write timings are used. See Figures 6 to 8. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of CE or

Sector Protection

The MBM29PL160TD/BD features hardware sector protection. This f eature will disable both progr am and erase operations in any number of sectors (0 through 10). The sector protection f eature is enabled using programming equipment at the user’s site. The device is shipped with all sectors unprotected.

To activate this mode, the programming equipment must force V V

, A0 = A6 = VIL, A1 = VIH. The sector addresses pins (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to

the sector to be protected. T ab les 5 and 6 define the sector address for each of the ele ven (11) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE rising edge of the same. Sector addresses must be held constant during the WE for sector protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V with CE while (A device will read 00H for an unprotected sector. In this mode, the lower order addresses, except for A A codes. A

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming a read operation at the address location XX02H, where the higher order addresses pins (A A Tables 4.1 and 4.2 for Autoselect codes.

and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, A13, and A12)

, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector . Otherwise the

are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device

requires to VIL in byte mode.

-1

, A13, and A12) represents the sector address will produce a logical “1” at DQ0 for a protected sector. See

on address pin A9 and control pin OE, CE =

pulse and is terminated with the

pulse. See figures 14 and 20

on address pin A9

, A1, and

, A18, A17, A16, A15,

Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29PL160TD/BD de vices in order to change data. The Temporary Sector Unprotection mode is activated by command register. During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the mode is taken away using command register, all the previously protected sectors will be protected again. (See Figures 20.)

MBM29PL160TD

Table 7 MBM29PL160TD/BD Standard Command Definitions

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Command Sequence

(Notes 1, 2, 3, 5)

Read/Reset (Note 6)

Word

/Byte

Word

Byte AAAH 555H AAAH

Word

Autoselect

Byte AAAH 555H AAAH

Byte/Word Program (Notes 3, 4)

Word

Byte AAAH 555H AAAH

Word

Chip Erase

Byte AAAH 555H AAAH AAAH 555H AAAH

Sector Erase (Note 3)

Sector Erase Suspend

Sector Erase Resume

Temporary Unprotect Enable

Temporary Unprotect Disable

Word

Byte AAAH 555H AAAH AAAH 555H

Word

/Byte

Word

/Byte

Word

Byte AAAH 555H AAAH

Word

Byte AAAH 555H AAAH

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Second

Bus

Write Cycle

Third Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Fourth Bus

Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

1XXXHF0H——————————

555H

AAH

2AAH

55H

555H

F0H RA RD — — — —

90H——————

A0H PA PD — — — —

555H

80H

555H

80H

AAH

2AAH

555H

55H

10H

55H SA 30H

1XXXHB0H——————————

1XXXH30H——————————

555H

AAH

2AAH

55H

555H

E0H XXXH 01H — — — —

555H

E0H XXXH 00H — — — —

Notes:

1. Address bits A

to A19 = X = “H” or “L” for all address commands e xcept or Prog r am Address (PA) and

Sector Address (SA).

2. Bus operations are defined in Tables 2 and 3.

3. RA =Address of the memory location to be read. PA =Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE

SA =Address of the sector to be erased. The combination of A

pulse.

, A18, A17, A16, A15, A14, A13, and A12 will

uniquely select any sector.

4. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. Data is latched on the rising edge of WE

5. The system should generate the following address patterns:

Word Mode: 555H or 2AAH to addresses A Byte Mode: AAAH or 555H to addresses A-1 to A

to A

10 10

6. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

MBM29PL160TD

Table 8 MBM29PL160TD/BD Extended Command Definitions

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/MBM29PL160BD

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Command

Sequence

Set to Fast Mode

Fast Program *1

Reset from Fast Mode *1

Query Command *2

SPA : Sector Address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector

addresses.

. This command is valid while fast mode.

. Addresses from system set to A

. The data" 00H" is also acceptable.

Word

Byte AAAH 555H AAAH

Word

Byte XXXH

Word

Byte XXXH XXXH

Word

Byte AAH

Bus

Write

Cycles

Req'd

First Bus

Write Cycle

Addr Data Addr Data Addr Data Addr Data

555H

XXXH

55H

to A6. The other addresses are “Don’t care”.

AAH

A0H PA PD — — — —

90H

98H — — — — — —

Second Bus

Write Cycle

2AAH

XXXH

F0H *3 — — — —

55H

Third Bus

Write Cycle

555H

Fourth Bus Read Cycle

20H — —

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in an improper sequence will reset the device to the read mode. Table 7 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in prog ress . Moreo v er both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ

to DQ7 and DQ8 to DQ15 bits are ignored.

Read/Reset Command

In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read mode, the read/reset operation is initiated by writing the Read/Reset command sequence into the command register . Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered.

The device will automatically power-up in the Read/Reset state . In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory contents occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. (See Figure 5.1 and 5.2.)

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufactures and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A voltage onto the address lines is not generally desired system design practice.

The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register . Following the last command write, a read cycle from address XX00H retrie v es the manufacture code of 04H. A read cycle from address XX01H for ×16 (XX02H for ×8) retrieves the de vice code (MBM29PL160TD = 27H and

to a high voltage. However, multiplexing high

MBM29PL160TD

MBM29PL160BD = 45H for ×8 mode; MBM29PL160TD = 2227H and MBM29PL160BD = 2245H for ×16 mode). (See Tables 4.1 and 4.2.)

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All manufactures and device codes will exhibit odd parity with DQ The sector state (protection or unprotection) will be indicated by address XX02H for ×16 (XX04H for ×8). Scanning the sector addresses (A a logical “1” at device output DQ mode verification on the protected sector. (See Tables 2 and 3.)

To terminate the operation, it is necessary to write the Read/Reset command sequence into the register and, also to write the Autoselect command during the operation, by e xecuting it after writing the Read/Reset command sequence.

, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce

for a protected sector . The programming v erification should be perform margin

defined as the parity bit.

Word/Byte Programming

The device is programmed on a b yte-by-byte (or word-by-word) basis . Programming is a four bus cycle operation. There are two “unlock” write cycles. These are f ollowed b y the program set-up command and data write cycles . Addresses are latched on the falling edge of CE rising edge of CE first) begins programming. Upon ex ecuting the Embedded Progr am Algorithm command sequence, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. (See Figures 6 and 7.)

The automatic programming operation is completed when the data on DQ bit at which time the device return to the read mode and addresses are no longer latched. (See T ab le 9, Hardware Sequence Flags.) Therefore, the device requires that a valid address be supplied by the system at this time. Hence, Data

Any commands written to the chip during this period will be ignored. If hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not.

or WE, whichever happens first. The rising edge of the last CE or WE (whichever happens

Polling must be performed at the memory location which is being programmed.

or WE, whichev er happens later and the data is latched on the

is equivalent to data written to this

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so ma y either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded Program

Algorithm using typical command strings and bus operations.

Chip Erase

Chip erase is a six-bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does not require the user to program the de vice prior to erase. Upon ex ecuting the Embedded Erase Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero data pattern prior to electrical erase . (Preprogram Function.) The system is not required to provide an y controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE when the data on DQ (See Figure 8.)

Figure 17 illustrates the Embedded Erase

is “1” (See Write Operation Status section.) at which time the device returns to read mode.

Algorithm using typical command strings and bus operations.

pulse in the command sequence and terminates

Sector Erase

Sector erase is a six-bus cycle operation. There are two “unlock” write cycles, followed by writing the “set-up” command. Two more “unlock” write cycles are then follo wed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE = 30H) is latched on the rising edge of WE command, the sector erase operation will begin.

. After a time-out of 50 µs from the rising edge of the last sector erase

, while the command (Data

MBM29PL160TD

Multiple sectors may be erased concurrently b y writing six-bus cycle operations on Table 7. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE edge of the WE erase timer window is still open. (See section DQ or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once excution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section f or Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 10).

Sector erase does not require the user to program the de vice prior to erase. The device automatically prog rams all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram Function). When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide an y controls or timings during these operations. (See Figure 8.)

occurs within the 50 µs time-out window the timer is reset. Monitor DQ3 to determine if the sector

will initiate the ex ecution of the Sector Erase command(s). If another falling

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, Sector Erase Timer .) Any command other than Sector Erase

/MBM29PL160BD

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The automatic sector erase begins after the 50 µs time out from the rising edge of the WE sector erase command pulse and terminates when the data on DQ at which time the device returns to the read mode. Data the sectors being erased. Multiple Sector Erase Time; [Sector Program Time (Preprogr amming) + Sector Erase Time] × Number of Sector Erase.

Figure 17 illustrates the Embedded Erase

Algorithm using typical command strings and bus operations.

polling must be performed at an address within any of

is “1” (See Write Operation Status section)

pulse for the last

Erase Suspend/Resume

The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perf orm data reads from or program to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Er ase Suspend command will be ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation.

Writing the Erase Resume command resumes the erase operation. The addresses are “DON’T CARES” when writing the Erase Suspend or Erase Resume commands.

When the Erase Suspend command is written during the Sector Erase operation, the device will take a maxim um of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/ BY

output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ writes of the Erase Suspend command are ignored.

When the erase operation has been suspended, the device def aults to the erase-suspend-read mode . Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successiv ely reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ

and DQ7 to determine if the erase operation has been suspended. Further

to toggle. (See the section on DQ2.)

After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This Program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Progr am mode e xcept that the data must be programmed to sectors that are not erase-suspended. Successively reading from the er ase-suspended sector while the devices are in the erase-suspend-program mode will cause DQ suspended Program operation is detected by Data as the regular Program operation. Note that DQ from any address.

polling of DQ7 and the Toggle Bit (DQ6) which is the same

must be read from the Program address while DQ6 can be read

to toggle. The end of the erase-

MBM29PL160TD

To resume the operation of Sector Erase, the Resume command (30H) should be written. Any further writes of the Resume command at this point will be ignored. Another Erase Suspend command can be written after the chip has resumed erasing.

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Extended Command

(1) Fast Mode

MBM29PL160TD/BD has Fast Mode function. This mode dispenses with the initial tw o unlock cycles required in the standard program command sequence writing Fast Mode command into the command register . In this mode, the required bus cycle f or progr amming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also ex ecuted after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. (Refer to the Figure 22 Extended algorithm.) The V Mode.

(2) Fast Programming

During Fast Mode, the prog ramming can be executed with two b us cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0H) and data write cycles (PA/PD). (Refer to the Figure 22 Extended algorithm.)

(3) CFI (Common Flash Memory Interface)

active current is required even CE = VIH during Fast

The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward-and backwardcompatible software support for the specified flash device families. Refer to CFI specification in detail.

The operation is initiated by writing the query command (98H) into the command register. Following the command write, a read cycle from specific address retrives device inf ormation. Please note that output data of upper byte (DQ operation, it is necessary to write the read/reset command sequence into the register.

to DQ15) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate

MBM29PL160TD

Write Operation Status

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Table 9 Hardware Sequence Flags

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In Progress

Exceeded Time Limits

Notes:

Status DQ

Embedded Program Algorithm DQ

Toggle 0 0 1

Embedded/Erase Algorithm 0 Toggle 0 1 Toggle

Erase Suspend Read

(Erase Suspended Sector) Erase Suspend Mode

Erase Suspend Read

(Non-Erase Suspended Sector)

Erase Suspend Program

(Non-Erase Suspended Sector) Embedded Program Algorithm DQ

1 1 0 0 Toggle

Data Data Data Data Data

Toggle

(Note 1)

Toggle 1 0 1

(Note 2)

Embedded/Erase Algorithm 0 Toggle 1 1 N/A Erase Suspend Program

(Non-Erase Suspended Sector)

1. Performing successive read operations from any address will cause DQ

Toggle 1 0 N/A

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ2 bit. Howev er, successive reads from the erase-suspended sector will cause DQ

toggle.

3. DQ

4. DQ

and DQ1 are reserve pins for future use.

is Fujitsu internal use only.

Data Polling

The MBM29PL160TD/BD device features Data

Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the devices will produce the complement of the data last written to DQ Algorithm, an attempt to read the device will produce the true data last written to DQ Erase Algorithm, an attempt to read the device will produce a “0” at the DQ Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ for Data

For chip erase and sector erase , Data pulse sequence. Data

Polling (DQ7) is shown in Figure 18.

Polling is v alid after the rising edge of the sixth WE pulse in the six-write

Polling m ust be performed at a sector address within any of the sectors being erased and

. Upon completion of the Embedded Program

. During the Embedded

output. Upon completion of the

output. The flowchart

not at a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to being completed, the MBM29PL160TD/BD data pins (DQ enable (OE

) is asserted low. This means that the device is driving status information on DQ7 at one instant of

) may change asynchronously while the output

time and then that byte’ s v alid data at the next instant of time . Depending on when the system samples the DQ output, it may read the status or valid data. Ev en if the de vice has completed the Embedded Program Algorithm operation and DQ to DQ

will be read on successive read attempts.

The Data

Polling f eature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm

has a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0

or sector erase time-out. See Figure 9 for the Data

Polling timing specifications and diagrams.

MBM29PL160TD

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Toggle Bit I

The MBM29PL160TD/BD also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed.

During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE the device will result in DQ cycle is completed, DQ programming, the T oggle Bit I is v alid after the rising edge of the fourth WE

toggling between one and zero . Once the Embedded Program or Erase Algorithm

will stop toggling and valid data can be read on the next successive attempts. During

pulse in the four write pulse sequence.

For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth WE

toggling) data from

pulse in the six-

write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written to is protected, the toggle bit will toggle for about 1 µs and then stop

toggling without the data having changed. In erase, the device will erase all the selected sectors except for the ones that are protected. If all selected sectors are protected, the chip will toggle the Toggle Bit I for about 100 µs and then drop back into read mode, having changed none of the data.

Either CE cause the DQ

or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will

to toggle.

See Figure 10 and Figure 19 for the Toggle Bit I timing specifications and diagrams.

Exceeded Timing Limits

will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under

these conditions DQ cycle was not successfully completed. Data condition. The CE

will produce a “1”. This is a failure condition which indicates that the program or erase

Polling is the only operating function of the device under this

circuit will partially power down the device under these conditions. The OE and WE pins will

control the output disable functions as described in Tables 2 and 3. The DQ

failure condition ma y also appear if a user tries to program a non blank location without erasing. In this

case the device locks out and never completes the Embedded Algorithm operation. Hence, the system never reads a valid data on DQ

and DQ6 never stops toggling. Once the device has exceeded timing limits, the DQ5

bit will indicate a “1.” Please note that this is not a device f ailure condition since the device was incorrectly used. If this occurs, reset the device with command sequence.

Sector Erase Timer

After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ remain low until the time-out is complete. Data

Polling and Toggle Bit I are valid after the initial sector erase

command sequence. If Data

Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may

be used to determine if the sector erase timer window is still open. If DQ

is high (“1”) the internally controlled

erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data

Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ

prior to and following each subsequent sector erase command. If DQ3 is high on the

second status check, the command may not have been accepted. See Table 9: Hardware Sequence Flags.

will

Toggle Bit II

MBM29PL160TD

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This Toggle Bit II, along with DQ

, can be used to determine whether the device is in the Embedded Erase

Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ

to toggle during the Embedded Erase Algorithm. If the

device is in the erase-suspended-read mode, successiv e reads from the erase-suspended sector will cause DQ to toggle. When the device is in the erase-suspended-prog r am mode , successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at DQ

is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend

Program operation is in progress. For example, DQ

(DQ

toggles while DQ6 does not.) See also Table 10 and Figure 15.

Furthermore, DQ mode, DQ

toggles if this bit is read from an erasing sector.

and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.

can also be used to determine which sector is being erased. When the device is in the erase

Table 10 Toggle Bit Status

Mode DQ

Program DQ

Toggle 1

Erase 0 Toggle Toggle Erase Suspend Read

(Erase Suspended Sector)

11Toggle

(Note 1) Erase-Suspend Program DQ

Toggle (Note 1) 1 (Note 2)

Notes:

1. Performing successive read operations from any address will cause DQ

to toggle.

2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1” at the DQ

bit. However, successive reads from the erase-suspended sector will cause DQ2 to

toggle.

Word/Byte Configuration

The BYTE pin selects the byte (8-bit) mode or word (16-bit) mode for the MBM29PL160TD/BD device. When this pin is driven high, the device operates in the w ord (16-bit) mode. The data is read and prog rammed at DQ to DQ becomes the lowest address bit and DQ an 8-bit operation and hence commands are written at DQ

. When this pin is driven low, the device operates in byte (8-bit) mode. Under this mode, DQ15/A-1 pin

to DQ14 bits are tri-stated. Howev er , the command b us cycle is alwa ys

to DQ7 and DQ8 to DQ15 bits are ignored. Refer to

Figures 11 to 13 for the timing diagrams.

Data Protection

The MBM29PL160TD/BD is designed to offer protection against accidental erasure or progr amming caused by spurious system level signals that ma y e xist during power transitions . During power up the de vice automatically resets the internal state machine to the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequence.

The device also incorporates several features to prevent inadvertent write cycles resulting form V and power-down transitions or system noise.

power-up

MBM29PL160TD

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Low VCC Write Inhibit

To avoid initiation of a write cycle during VCC power-up and power-do wn, a write cycle is locked out for VCC less than 2.3 V (typically 2.4 V). If V are disabled. Under this condition, the device will reset to the read mode . Subsequent writes will be ignored until the V to prevent unintentional writes when V

If the Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming.

level is g reater than V

< V

LKO

, the command register is disabled and all internal program/erase circuits

LKO

. It is the users responsibility to ensure that the control pins are logically correct

is above 2.3 V.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not change the command registers.

Logical Inhibit

Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write, CE and WE must be a logical zero while OE

is a logical one.

Power-up Write Inhibit

Po wer-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to read mode on power-up.

MBM29PL160TD

Table 11 Common Flash Memory Interface Code

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Description A0 to A

Query-unique ASCII string “QRY”

10h 11h

DQ0 to DQ

12h

Primary OEM Command Set 2h: AMD/FJ standard type

Address for Primary Extended Table

Alternate OEM Command Set (00h = not applicable)

Address for Alternate OEM Extended Table

Min. (write/erase)

13h 14h

15h 16h

17h 18h

19h 1Ah

1Bh 0027h

D7-4: volt, D3-0: 100 mvolt V

Max. (write/erase)

1Ch 0036h

D7-4: volt, D3-0: 100 mvolt V

Min. voltage 1Dh 0000h

Max. voltage 1Eh 0000h

Typical timeout per single byte/word write 2

µs

Typical timeout for Min. size buffer write 2

µs

T y pical timeout per individual block erase 2

Typical timeout for full chip erase 2

Max. timeout for byte/word

write 2

times typical

Max. timeout for buffer write

times typical

Max. timeout per individual block erase 2

times typical

Max. timeout for full chip erase 2

Device Size = 2

times typical

byte

Flash Device Interface description

Max. number of byte in multi-byte write = 2

Number of Erase Block

1Fh 0004h

20h 0000h

21h 000Ah

22h 0000h

23h 0005h

24h 0000h

25h 0004h

26h 0000h

27h 0015h 28h

29h 2Ah

2Bh 2Ch 0004h

Regions within device Erase Block Region 1

Information

2Dh 2Eh 2Fh 30h

0051h 0052h 0059h

0002h 0000h

0040h 0000h

0000h 0000h

0002h 0000h

0000h 0000h

0000h 0000h 0040h 0000h

Erase Block Region 2 Information

Description A

to A

31h 32h

33h 34h

Erase Block Region 3 Information

35h 36h 37h 38h

Erase Block Region 4 Information

39h 3Ah 3Bh 3Ch

Query-unique ASCII string “PRI”

40h

41h

42h

Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0030h Address Sensitive Unlock

45h 0000h

0 = Required 1 = Not Required

Erase Suspend

46h 0002h

0 = Not Supported 1 = To Read Only 2 = To Read & Write

Sector Protect

47h 0001h

0 = Not Supported X = Number of sectors in per group

Sector Temporary Unprotect

48h 0001h

00 = Not Supported 01 = Supported

Sector Protection Algorithm 49h 0004h Number of Sector for Bank2 4Ah 00h Burst Mode Type

4Bh 00h

00 = Not supported Page Mode Type

4Ch 02h

00 = Not supported 01 = 4 word Page 02 = 8 word Page

DQ0 to DQ

0001h 0000h 0020h 0000h

0000h 0000h 0080h 0003h

0006h 0000h 0000h 0004h

0050h 0052h 0049h

MBM29PL160TD

ABSOLUTE MAXIMUM RATINGS

■

Storage Temperature ..................................................................................................–55°C to +125°C

Ambient Temperature with Power Applied ..................................................................–40°C to +85°C

Voltage with respect to Ground All pins except A V

(Note 1) ................................................................................................................–0.5 V to +4.0 V

, OE, and RESET (Note 2)......................................................................................–0.5 V to +13.0 V

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/MBM29PL160BD

, OE, and RESET (Note 1)............–0.5 V to +5.5 V

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Notes:

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

■

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

1. Minimum DC voltage on input or l/O pins are –0.5 V. During vo ltage transitions, inputs may negative overshoot V During voltage transitions,outputs may positive overshoot to V

2. Minimum DC input voltage on A and RESET voltage on A up to 20 ns. Voltage difference between input voltage and supply voltage (V

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

to –2.0 V for periods of up to 20 ns. Maximum DC v oltage on output and l/O pins are 6.0V.

+2.0 V for periods of up to 20 ns.

, OE, and RESET pins are –0.5 V. During voltage transitions, A9, OE,

pins may negative overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC input

, OE, and RESET pins are +13.0 V which may positive overshoot to 13.5 V for periods of

– VCC) do not exceed 9 V.

RECOMMENDED OPERATING RANGES

Ambient Temperature (TA)

MBM29PL160TD/BD-75 ...........................................................................–20°C to +70°C

MBM29PL160TD/BD-90 ...........................................................................–40°C to +85°C

Supply Voltages

MBM29PL160TD/BD-75/90 ......................................................................+2.7 V to +3.6 V

Operating ranges define those limits between which the functionality of the device is quaranteed.

semiconductor device. All the device’s electrical characteristics are warranted when the device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

MBM29PL160TD

MAXIMUM OVERSHOOT

■

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/MBM29PL160BD

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+0.6 V –0.5 V –2.0 V

6.0 V

+0.5 V

+2.0 V

20 ns

Figure 1 Maximum Negative Overshoot Waveform

20 ns

Figure 2 Maximum Positive Overshoot Waveform 1

+13.5 V

+13.0 V

VCC +0.5 V

Note : This waveform is applied for A9, OE, and RESET.

Figure 3 Maximum Positive Overshoot Waveform 2

20 ns

MBM29PL160TD

DC CHARACTERISTICS

■

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Parameter

Symbol

LIT

CC1

CC2

CC3

CC4

CC5

Parameter Description Test Conditions Min. Max. Unit

Input Leakage Current VIN = VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA Output Leakage Current V A9, OE, RESET Inputs Leakage

Current

= VSS to VCC, VCC = VCC Max. –1.0 +1.0 µA

OUT

VCC = VCC Max., A

, OE = 12.5 V

= VIL, OE = V

f = 10 MHz

—35µA

—70mA

VCC Active Current (Note 1)

= VIL, OE = V

f = 5 MHz VCC Active Current (Note 2) CE = VIL, OE = V VCC Current (Standby) VCC = VCC Max., CE = V VCC Current

(Automatic Sleep Mode) (Note 3) VCC Active Current

(Page Read Mode)

VCC = VCC Max., CE = V

= V

= VIL, OE = V

0.3 V or V

—40mA —35mA

0.3 V, — 5 µA

0.3 V,

0.3 V

—5µA

30MHz — 12 mA

40MHz — 15 mA Input Low Level — –0.5 0.8 V Input High Leve l (Note 5) — 2.0 5.5 V

V V V V

Notes:

OH1

Voltage for Autoselect,Sector Protection (A

, OE) (Note 4, 5)

Output Low Voltage Level IOL = 4.0 mA, VCC = VCC Min. — 0.45 V

= –2.0 mA, VCC = VCC Min. 2.4 — V

— 11.5 12.5 V

Output High Voltage Level

OH2

LKO

1. The l

2. l

IOH = –100 µA V

Low VCC Lock-Out Voltage — 2.3 2.5 V

current listed includes both the DC operating current and the frequency dependent component.

active while Embedded Erase or Embedded Progr a m is in progress.

– 0.4 — V

3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns.

4. Applicable for only sector protection.

5. The input voltage must be input after Vcc is valid.

MBM29PL160TD

AC CHARACTERISTICS

■

• Read Only Operations Characteristics

Parameter

Symbols

JEDEC Standard

Description Test Setup

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/MBM29PL160BD

-75

(Note)

-90

(Note)

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Unit

AVAV

AVQV

—t

ELQV

GLQV

EHQZ

GHQZ

AXQX

—

Note:

Test Conditions: Output Load: 1 TTL gate and 30 pF (MBM29PL160TD/BD-75)

ACC

PRC

PACC

ELFL

ELFH

Read Cycle Time — Min. 75 90 ns

Address to Output Delay

CE OE = V

Max. 75 90 ns

= V

Page Read Cycle Time — Min. 25 35 ns

= V

Page Address to Output Delay

CE OE = V

Chip Enable to Output Delay OE = V

Max. 25 35 ns

Max. 75 90 ns

Output Enable to Output Delay — Max. 25 35 ns Chip Enable to Output HIGH-Z — Max. 20 30 ns Output Enable to Output HIGH-Z — Max. 20 30 ns Output Hold Time From Address, CE

or OE

, Whichever Occurs First

—Min.4 5 ns

CE or BYTE Switching Low or High — Max. 4 5 ns

1 TTL gate and 100 pF (MBM29PL160TD/BD-90) Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level

Input: 1.5 V Output: 1.5 V

Notes:

Device

Under

Test

= 30 pF including jig capacitance (MBM29PL160TD/BD-75)

= 100 pF including jig capacitance (MBM29PL160TD/BD-90)

Figure 4 Test Conditions

IN3064 or Equivalent

Ω

6.2 k

3.3 V

2.7 k

Ω

Diodes = IN3064 or Equivalent

MBM29PL160TD

• Write (Erase/Program) Operations

-75/-90

/MBM29PL160BD

-75/-90

Parameter Symbols

MBM29PL160TD/BD

Description

JEDEC Standard -75 -90

AVAV

AVWL

WLAX

DVWH

WHDX

—t

GHWL

GHEL

ELWL

WLEL

WHEH

EHWH

t t t

OES

OEH

GHWL

GHEL

t t t t

Write Cycle Time Min. 75 90 ns Address Setup Time Min. 0 0 ns Address Hold Time Min. 45 45 ns Data Setup Time Min. 35 45 ns Data Hold Time Min. 0 0 ns Output Enable Setup Time Min. 0 0 ns

Output Enable Hold Time

Read Min. 0 0 ns Toggle and Data

Polling Min. 10 10 ns Read Recover Time Before Wr ite Min. 0 0 ns Read Recover Time Before Wr ite

(OE

High to CE Low)

Min. 0 0 ns

CE Setup Time Min. 0 0 ns WE Setup Time Min. 0 0 ns CE Hold Time Min. 0 0 ns WE Hold Time Min. 0 0 ns

Unit

WLWH

ELEH

WHWL

EHEL

WHWH1

WHWH2

—t —t —t —t —t —t —t —t —t

WPH

CPH

WHWH1

WHWH2

EOE

VCS

VLHT

WPP

OESP

CSP

FLQZ

FHQV

Write Pulse Width Min. 35 35 ns CE Pulse Width Min. 35 35 ns Write Pulse Width High Min. 20 30 ns CE Pulse Width High Min. 20 30 ns

Programming Operation

Byte

Typ.

8.6 8.6 µs

Word 12.6 12.6 Sector Erase Operation (Note 1) Typ. 4.8 4.8 sec Delay Time from Embedded Output Enable Max. 75 90 ns VCC Setup Time Min. 50 50 µs Voltage Transition Time (Note 2) Min. 4 4 µs Write Pulse Width (Note 2) Min. 100 100 µs OE Setup Time to WE Active (Note 2) Min. 4 4 µs CE Setup Time to WE Active (Note 2) Min. 4 4 µs Recover Time From RY/BY Min. 0 0 ns BYTE Switching Low to Output HIGH-Z Max. 30 30 ns BYTE Switching High to Output Active Min. 40 30 ns

Notes:

1. This does not include the preprogramming time.

2. This timing is for Sector Protection operation.

MBM29PL160TD

SWITCHING WAVEFORMS

■

• Key to Switching Waveforms

-75/-90

WAVEFORM INPUTS OUTPUTS

/MBM29PL160BD

-75/-90

Addresses

Must Be Steady

May Change from H to L

May Change

from L to H

“H” or “L”: Any Change Permitted

Does Not Apply

Addresses Stable

Will Be Steady

Will Be Change from H to L

Will Be Change

from L to H

Changing, State Unknown

Center Line is High-

Impedance “Off” State

Outputs

ACC

OEH

HIGH-Z

Output Valid

Figure 5.1 AC Waveforms for Read Operations

HIGH-Z

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

A13 to A

A0 to A

(A-1)

Outputs

ACC

OEH

Addresses Valid

Aa Ab Ac

PACC

PRC

PACC

HIGH-Z

Db Dc

Figure 5.2 AC Waveforms for Page Read Mode Operations

MBM29PL160TD

-75/-90

Data Polling3rd Bus Cycle

/MBM29PL160BD

-75/-90

Addresses

Data

Notes:

555H PA PA

GHWL

A0H

WPH

WHWH1

OUT

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 6 AC Waveforms for Alternate WE

Controlled Program Operations

MBM29PL160TD

-75/-90

/MBM29PL160BD

Data Polling3rd Bus Cycle

-75/-90

Notes:

Addresses

555H

PA PA

GHEL

WHWH1

CPH

Data

A0H

OUT

1. PA is address of the memory location to be programmed.

2. PD is data to be programmed at word address.

3. DQ

4. D

is the output of the complement of the data written to the device.

is the output of the data written to the device.

OUT

5. Figure indicates last two bus cycles out of four bus cycle sequence.

6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 7 AC Waveforms for Alternate CE Controlled Program Operations

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

Addresses

Data

GHWL

VCS

AStAH

WPH

2AAH

55H 80H

555H

AAH

555H

AAH

2AAH

SA*

30H for Sector Erase

55H

10H

* : 1. SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAAH (Byte) f or Chip

Erase.

2. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)

Figure 8 AC Waveforms for Chip/Sector Erase Operations

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

OEH

DQ0 to DQ

Data

WHWH1 or 2

DQ0 to DQ6 = Output Flag

EOE

*:DQ7 = Valid Data (The device has completed the Embedded operation.)

Figure 9 AC Waveforms for Data Polling during Embedded Algorithm Operations

DQ7 =

Valid Data

DQ0 to DQ6

Valid Data

)

High-Z

OEH

OES

Stop Toggling

Data Valid

Data

= Toggle

DQ6 = Toggle

* : DQ6 = Stops toggling. (The device has completed the Embedded operation.)

Figure 10 AC Waveforms for Taggle Bit I during Embedded Algorithm Operations

to DQ

MBM29PL160TD

BYTE

-75/-90

/MBM29PL160BD

-75/-90

DQ0 to DQ

DQ15/A

BYTE

DQ0 to DQ

ELFH

-1

FHQV

-1

DQ0 to DQ

Figure 11 Timing Diagram for Word Mode Configuration

ELFL

DQ0 to DQ

DQ15/

A-1

DQ0 to DQ

FLQZ

DQ0 to DQ

-1

Figure 12 Timing Diagram for Byte Mode Configuration

MBM29PL160TD

-75/-90

/MBM29PL160BD

The falling edge of the last WE signal

-75/-90

BYTE

SET

(tAS)

Figure 13 BYTE Timing Diagram for Write Operations

Input Valid

HOLD

(tAH)

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

A19, A18, A A16, A15, A

A13, A

3 V

17 14 12

SAX SAY

VLHT

OESP

WPP

VLHT

CSP

Data

VCS

SAX = Sector Address for initial sector SAY = Sector Address for next sector

Note:

is VIL on byte mode.

-1

Figure 14 AC Waveforms for Sector Protection Timing Diagram

01H

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

Enter

Embedded

Erasing

Note:

Erase

Suspend

Erase

Toggle

and DQ6

with OE

is read from the erase-suspended sector.

Erase Suspend

Read

Enter Erase

Suspend Program

Figure 15 DQ2 vs. DQ

Erase

Suspend

Program

Erase Suspend

Read

Erase

Resume

Erase Erase

Complete

FLOW CHART

■

MBM29PL160TD

-75/-90

Write Program Command

/MBM29PL160BD

Start

Sequence

(See Below)

Data

Polling Device

-75/-90

Increment Address

Program Command Sequence* (Address/Command):

Verify Byte

Yes

Last Address

Yes

Programming Completed

555H/AAH

2AAH/55H

555H/A0H

Program Address/Program Data

* :The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Figure 16 Embedded ProgramTM Algorithm

MBM29PL160TD

-75/-90

Data

/MBM29PL160BD

Write Erase Command

Sequece

(See Below)

Polling or Toggle Bit

from Device

-75/-90

Start

Data = FFH

Erasure Completed

Chip Erase Command Sequence*

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

555H/10H

Yes

Individual Sector/Multiple Sector*

Erase Command Sequence

(Address/Command):

555H/AAH

2AAH/55H

555H/80H

555H/AAH

2AAH/55H

Sector Address/30H

* :The sequence is applied for ×16 mode.

The addresses differ from ×8 mode.

Figure 17 Embedded EraseTM Algorithm

Sector Address/30H

Additional sector erase commands are optional.

MBM29PL160TD

Read Byte

(DQ

Addr. = VA

DQ7 = Data?

-75/-90

Start

to DQ7)

/MBM29PL160BD

VA =Address for programming

=Any of the sector addresses

within the sector being erased during sector erase or multiple erases operation.

=Any of the sector addresses

within the sector not being protected during sector erase or

Yes

multiple sector erases operation.

-75/-90

DQ5 = 1?

Yes

Read Byte

(DQ

to DQ7)

Addr. = VA

DQ7 = Data?

Fail

Yes

Pass

* : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.

Figure 18 Data Polling Algorithm

MBM29PL160TD

-75/-90

/MBM29PL160BD

Start

Read

(DQ

to DQ7)

Addr. = “H” or “L”

-75/-90

DQ6 = Toggle

DQ5 = 1?

Read Byte

(DQ

Addr. = “H” or “L”

DQ6 = Toggle

to DQ7)

? *

Fail

Yes

Pass

* : DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as

changing to “1”.

Figure 19 Toggle Bit Algorithm

MBM29PL160TD

-75/-90

/MBM29PL160BD

Start

Setup Sector Addr.

19, A18

(

A15, A14, A13, A

PLSCNT = 1

, A17, A

16,

)

-75/-90

Increment PLSCNT

Yes

Remove VID from A

Write Reset Command

Device Failed

= VIL)*

Yes

VID from A

= VID, A9 = V

A6 = CE = V

A0 = VIL, A1 = V

Activate WE Pulse

Time out 100 µs

WE = VIH, CE = OE = V

(A9 should remain VID)

Read from Sector

= VIH, A0 = VIL,

( A

Addr. = SA, A

Data = 01H?PLSCNT = 25?

Protect Another Sector?

Remove

Write Reset Command

* :A-1 is VIL on byte mode.

Sector Protection

Completed

Figure 20 Sector Protection Algorithm

MBM29PL160TD

-75/-90

/MBM29PL160BD

Temporary Unprotect Enable

Command Write (Note 1)

Perform Erase or

Program Operations

Temporary Unprotect Disable

Command Write

-75/-90

Start

Notes:

Temporary Sector

Unprotection Completed

(Note 2)

1. All protected sectors are unprotected.

2. All previously protected sectors are protected once again.

Figure 21 Te mporary Sector Unprotection Algorithm

MBM29PL160TD

-75/-90

Start

/MBM29PL160BD

-75/-90

Increment Address

555H/AAH

2AAH/55H

555H/20H

XXXXH/A0H

Program Address/Program Data

Data Polling Device

Verify Byte?

Last Address

Programming Completed

Yes

Set Fast Mode

In Fast Program

* :The sequence is applied for ×16 mode. * :The addresses differ from ×8 mode.

Figure 22 Embedded Programming Algorithm for Fast Mode

XXXH/90H

XXXH/F0H

Reset Fast Mode

MBM29PL160TD

ERASE AND PROGRAMMING PERFORMANCE

■

-75/-90

/MBM29PL160BD

-75/-90

Parameter

Sector Erase Time — 4.8 60 sec

Byte Programming Time — 8.6 300 Word Programming Time — 12.6 360

Chip Programming Time — 18 140 sec

Erase/Program Cycle 100,000 — — cycles —

PIN CAPACITANCE

■

Parameter

Symbol

OUT

IN2

Test conditions T

Note:

Parameter Description Test Setup Typ. Max. Unit

Input Capacitance VIN = 0 6.0 7.5 pF Output Capacitance V Control Pin Capacitance VIN = 0 8.0 11.5 pF

= 25°C, f = 1.0 MHz

Min. Typ. Max.

Limits

= 0 8.5 12.0 pF

OUT

Unit Comments

Excludes programming time prior to erasure

µs

Excludes system-level overhead

MBM29PL160TD

ORDERING INFORMATION

■

Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29PL160 T D -80 PFTN

-75/-90

/MBM29PL160BD

PACKAGE TYPE PFTN = 48-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 48-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PF =44-Pin Small Outline Package (SOP)

-75/-90

SPEED OPTION See Product Selector Guide

DEVICE REVISION

BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION MBM29PL160 16 Mega-bit (2M × 8-Bit or 1M × 16-Bit) CMOS Page Mode Flash Memory

3.0 V-only Read, Write, and Erase

MBM29PL160TD

PACKAGE DIMENSIONS

■

-75/-90

/MBM29PL160BD

-75/-90

48-pin plastic TSOP (I)

(FPT-48P-M19)

LEAD No.

INDEX

"A"

24 25

20.00±0.20 (.787±.008)

18.40±0.20

(.724±.008)

0.10(.004)

19.00±0.20 (.748±.008)

0.15±0.05

(.006±.002)

0.50±0.10

(.020±.004)

*: Resin protruction. (Each side: 0.15(.006) Max)

Details of "A" part

0.15(.006) 0.25(.010)

12.00±0.20

(.472±.008)

11.50REF (.460)

0.50(.0197) TYP

0.20±0.10

(.008±.004)

0.15(.006) MAX

0.35(.014) MAX

0.10(.004)

1.10 .043 –.002

(Mounting height)

0.05(0.02)MIN (STAND OFF)

+0.10 –0.05

+.004

1996 FUJITSU LIMITED F48029S-2C-2

Dimensions in mm (inches)

(Continued)

MBM29PL160TD

-75/-90

/MBM29PL160BD

-75/-90

48-pin plastic TSOP (I)

(FPT-48P-M20)

LEAD No.

INDEX

"A"

24 25

19.00±0.20

(.748±.008)

0.10(.004)

18.40±0.20

(.724±.008)

20.00±0.20

(.787±.008)

0.50±0.10

(.020±.004)

0.15±0.10

(.006±.002)

*: Resin protrusion. (Each side: 0.15(.006) Max)

Details of "A" part

0.15(.006) 0.25(.010)

0.50(.0197) TYP

11.50(.460)REF

12.00±0.20(.472±.008)

0.15(.006)

0.20±0.10

(.008±.004)

MAX

0.35(.014) MAX

0.10(.004)

0.05(0.02)MIN (STAND OFF)

(Mounting height)

+0.10 –0.05

1.10

+.004

.043 –.002

1996 FUJITSU LIMITED F48030S-2C-2

Dimensions in mm (inches)

(Continued)

MBM29PL160TD

44-pin plastic SOP

(FPT-44P-M16)

-75/-90

/MBM29PL160BD

-75/-90

+0.25 –0.20

28.45

INDEX

LEAD No.

1 22

1.27(.050)TYP

0.10(.004)

1998 FUJITSU LIMITED F44023S-4C-4

1.120

0.40 .016

26.67(1.050)REF

+.010 –.008

+0.10 –0.05

+.004 –.002

Ø0.13(.005)

2.35±0.15(.093±.006) (Mounting height)

2344

13.00±0.10 16.00±0.20 (.512±.004) (.630±.008)

+.004

+0.10

.008 –.006

–0.15

0.20 (Stand off)

0.80±0.20

(.031±.008)

14.40±0.20 (.567±.008)

0.15±0.05

(.006±.002)

Dimensions in mm (inches)

MBM29PL160TD

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kaw a saki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329

-75/-90

The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering.

/MBM29PL160BD

-75/-90

http://www.fujitsu.co.jp/

North and South America

FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: (800) 866-8608 Fax: (408) 922-9179

http://www.fujitsumicro.com/

Europe

FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122

http://www.fujitsu-ede.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220

http://www.fmap.com.sg/

The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams.

FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval.

Any semiconductor devices have an inhereut chance inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.

F9907



FUJITSU LIMITED Printed in Japan

FUJITSU MBM29PL160TD-75, MBM29PL160TD-90, MBM29PL160BD-90, MBM29PL160BD-75 DATA SHEET

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

PACKAGE

GENERAL DESCRIPTION

FLEXIBLE SECTOR-ERASE ARCHITECTURE

PRODUCT LINE UP

BLOCK DIAGRAM

CONNECTION DIAGRAMS

LOGIC SYMBOL

DEVICE BUS OPERATIONS

FUNCTIONAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING RANGES

MAXIMUM OVERSHOOT

DC CHARACTERISTICS

AC CHARACTERISTICS

SWITCHING WAVEFORMS

FLOW CHART

ERASE AND PROGRAMMING PERFORMANCE

PIN CAPACITANCE

ORDERING INFORMATION

PACKAGE DIMENSIONS