FUJITSU MBM29PDS322TE, MBM29PDS322BE DATA SHEET

查询MBM29PDS322BE供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

32M (2M × 16) BIT

Page Dual Operation

MBM29PDS322TE/BE

DESCRIPTION

■■■■

The MBM29PDS322TE/BE is 32M-bit, 1.8 V-only Flash memor y organized as 2M words of 16 bits each. The device is offered in 63-ball FBGA package. This device is designed to be programmed in system with standard system 1.8 V V also be reprogrammed in standard EPROM programmers.

CC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The de vice can

DS05-20889-1E

10/11

The device is organized into tw o banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as f ar as certain operations are concerned. This device is the same as Fujitsu’ s standard 1.8 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) oper ation is simultaneously taking place on the other bank.

(Continued)

PRODUCT LINE-UP

■■■■

Part No. MBM29PDS322TE/BE

Ordering Part No. V Max. Random Address Access Time (ns) 100 115

Max. Page Address Access Time (ns) 45 45 Max. CE Max. OE

■■■■

Access Time (ns) 100 115 Access Time (ns) 35 45

PACKAGE

CC = 2.0 V

+0.2 V –0.2 V

10 11

63-ball plastic FBGA

(BGA-63P-M01)

MBM29PDS322TE/BE

10/11

(Continued)

The device provides truly high perfor mance non-volatile Flash memory solution. The device offers fast page access times of 45 ns with random access times of 100 ns and 115 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the de vice has separate chip enable (CE enable (WE

The device is pin and command set compatible with JEDEC standard E

), and output enable (OE) controls. The page size is 4 words.

PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations. Reading data out of the de vice is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.

The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by ex ecuting the erase command sequence. This will inv oke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed bef ore ex ecuting the erase operation. During erase, the device automatically time the erase pulse widths and verify proper cell margin.

A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)

), write

The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory.

The device f eatures single 1.8 V po w er supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low V inhibits write operations on the loss of power. The end of program or erase is detected by Data by the Toggle Bit feature on DQ

6, or the RY/BY output pin. Once the end of a program or erase cycle has been

CC detector automatically

Polling of DQ7,

completed, the device internally resets to the read mode. The device also has a hardware RESET

pin. When this pin is driven low, execution of any Embedded Progr am Algorithm or Embedded Erase Algorithm is terminated. The inter nal state machine is then reset to the read mode. The RESET

pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu’s Flash technology combines years of EPROM and E

PROM experience to produce the highest levels of quality , reliability, and cost eff ectiveness . The device memory electrically erase the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection.

MBM29PDS322TE/BE

FEATURES

■■■■

•

0.23 µm Process Technology

•

Simultaneous Read/Write operations (Dual Bank)

Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations. Read-while-erase Read-while-program

•

High performance Page Mode

45 ns maximum page access time (100 ns random access time) 4 words Page Size

•

Single 1.8 V read, program, and erase

Minimized system level power requirements

•

Compatible with JEDEC-standard commands

Use the same software commands as E

•

Compatible with JEDEC-standard world-wide pinouts

63-ball FBGA (Package suffix: PBT)

• Minimum 100,000 program/erase cycles

•

Sector erase architecture

Eight 4 Kword and sixty-three 32 Kword sectors in word mode Any combination of sectors can be concurrently erased. Also supports full chip erase.

•

Boot Code Sector Architecture

T = Top sector B = Bottom sector

•

Hidden ROM (Hi-ROM) region

64 Kbyte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN)

•

/ACC input pin

At V

IL, allows protection of boot sectors, regardless of sector protection/unprotection status.

At VIH, allows removal of boot sector protection. At V

ACC, increases program performance.

•

Embedded Erase

Algorithms

Automatically pre-programs and erases the chip or any sector.

•

Embedded Program

Algorithms

Automatically writes and verifies data at specified address.

•Data

•

Polling and Toggle Bit feature for detection of program or erase cycle completion

Ready/Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

•

Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

•

Erase Suspend/Resume

Suspends the erase operation to allow a read data and/or program in another sector within the same device.

•

Sector group protection

Hardware method disables any combination of sector groups from program or erase operations.

• Sector Group Protection Set function by Extended sector group protection command

• Fast Programming Function by Extended Command

•

Temporary sector group unprotection

Temporary sector group unprotection via the RESET

PROMs.

pin.

10/11

MBM29PDS322TE/BE

Table 1: MBM29PDS322TE/BE Device Bank Division

Device

Part Number

Organization

Megabits Sector Sizes Megabits Sector Sizes

10/11

Bank 1 Bank 2

MBM29PDS322TE/BE × 16 4 Mbit

Eight 4 Kword,

seven 32 Kword

28 Mbit Fifty-six 32 Kword

PIN ASSIGNMENT

■■■■

MBM29PDS322TE/BE

(TOP VIEW)

10/11

A8 B8

N.C.

A7 B7 C7 D7 E7 F7 G7 H7 J7 K7

N.C.

13 A12 A14 A15 A16 DQ15 VSS N.C.

C6 D6 E6 F6 G6 H6 J6 K6

9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6

C5 D5 E5 F5 G5 H5 J5 K5

WE RESET N.C. A19 DQ5 DQ12 VCC DQ4

C4 D4 E4 F4 G4 H4 J4 K4

RY/BY WP/ACC A

C3 D3 E3 F3 G3 H3 J3 K3

7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1

C2 D2 E2 F2 G2 H2 J2 K2 L2 M2

4 A2 A1 A0 CE OE VSS

(Marking Side)

N.C.

18 A20 DQ2 DQ10 DQ11 DQ3

N.C.

(BGA-63P-M01)

*: Peripheral balls on each corner are shorted together via the substrate but not connected to the die.

MBM29PDS322TE/BE

PIN DESCRIPTION

■■■■

Table 2: MBM29PDS322TE/BE Pin Configuration

Pin name Function

20 to A0 Address Inputs

15 to DQ0 Data Inputs/Outputs

10/11

CE OE

WE Write Enable

RY/BY

RESET

WP/ACC Hardware Write Protection/Program Acceleration

N.C. No Internal Connection

SS Device Ground

VCC Device Power Supply

Chip Enable Output Enable

Ready/Busy Output Hardware Reset Pin/Temporary Sector Group Unprotection

BLOCK DIAGRAM

■■■■

A20 to A0

VCC VSS

Bank 2

address

MBM29PDS322TE/BE

Cell Matrix

(Bank 2)

Y-Gating

X-Decoder

10/11

LOGIC SYMBOL

■■■■

RESET

CE OE

WP/ACC

15 to DQ0

State

Control

Command

Status Control

Bank 1

address

CE OE WE RESET WA/ACC

20 to A0

RY/BY

DQ15 to DQ0

X-Decoder

Cell Matrix

(Bank 1)

Y-Gating

DQ15 to DQ0

RY/BY

MBM29PDS322TE/BE

DEVICE BUS OPERATION

■■■■

Table 3: MBM29PDS322TE/BE User Bus Operations

Operation CE

OE WE A0A1A2A3A6A

10/11

DQ15 to

RESET

WP/

ACC

Auto-Select Manufacturer Code *

Auto-Select Device Code * Extended Auto-Select Device

Code * Read *

LLHLLLLLVID Code H X

LLHHLLLLVID Code H X LLHL/HHHHLVID Code H X

LLHA0 A1 A2 A3 A6 A9 DOUT HX Standby H X XXXXXXX High-Z H X Output Disable LHHXXXXXX High-Z H X Write (Program/Erase) L H L A Enable Sector Group

Protection *

2, *4

Verify Sector Group Protection

2, *4

* Temporary Sector Group

Unprotection *

LVID LHLLLVID XHX

LLHLHLLLVID Code H X

XXXXXXXXX X VID X

0 A1 A2 A3 A6 A9 DIN HX

Reset (Hardware) / Standby XXXXXXXXX High-Z L X Boot Block Sector Write

Protection *

Legend: L = V

IL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels.

XXXXXXXXX X X L

*1:Manufacturer and device codes may also be accessed via a command register write sequence. See Table 3. *2:Refer to section on Sector Group Protection. *3:WE *4:V

can be VIL if OE is VIL, OE at VIH initiates the write operations.

CC must be between the minimum and maximum of the operation range.

*5:It is also used for the extended sector group protection. *6:Protect “outermost” 2 × 4 Kwords of the boot block sectors.

MBM29PDS322TE/BE

10/11

Table 4: MBM29PDS322TE/BE Command Definitions

Fourth Bus Read/Write

Cycle

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Command

Sequence

Bus

Write

Cycles

Req’d

First Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

Second Bus

Write Cycle

Third Bus

Write Cycle

Read/Reset Word 1 XXXh F0h — — — — — — — — — — Read/Reset Word 3 555h AAh 2AAh 55h 555h F0h RA RD — — — — Auto

select

Word 3 555h AAh 2AAh 55h

(BA)

555h

90h——————

Program Word 4 555h AAh 2AAh 55h 555h A0h PA PD — — — — Chip Erase Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h Sector

Erase

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h

Erase Suspend 1 BA B0h — — — — — — — — — — Erase Resume 1 BA30h—————————— Set to

Fast Mode Fast

Program * Reset from

Fast Mode *

Extended Sector Group Protection *

Query Word 1 Hi-ROM

Entry Hi-ROM

Program *

Word 3 555h AAh 2AAh 55h 555h 20h — — — — — —

Word 2 XXXh A0h PA PD — — — — — — — —

Word 2 BA 90h XXXh

F0h

————————

Word 4 XXXh 60h SPA 60h SPA 40h SPA SD — — — —

(BA)

55h

98h——————————

Word 3 555h AAh 2AAh 55h 555h 88h — — — — — —

Word 4 555h AAh 2AAh 55h 555h A0h

(HRA)

PD————

Hi-ROM Erase *

Hi-ROM

Exit *

Word 6 555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h HRA 30h

Word 4 555h AAh 2AAh 55h

*1:This command is valid while Fast Mode. *2:This command is valid while RESET

= VID. *3:This command is valid while Hi-ROM mode. *4:The data “00h” is also acceptable. Note 1.Address bits A

20 to A12 = X = “H” or “L” for all address commands e xcept or Program Address (PA), Sector

Address (SA), and Bank Address (BA).

2.Bus operations are defined in Table 8.

3.RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse.

(HRBA)

555h

90h XXXh 00h — — — —

MBM29PDS322TE/BE

10/11

SA = Address of the sector to be erased. The combination of A A BA = Bank Address (A

12 will uniquely select any sector.

20 to A15)

20, A19, A18, A17, A16, A15, A14, A13, and

4.RD = Data read from location RA during the read operation. PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.

5.SPA = Sector group address to be protected. Set sector group address (SGA) and (A

6, A1, A0) = (0, 1, 0).

SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses.

6.HRA = Address of the Hi-ROM area 29PDS322TE (Top Boot Type)Word Mode:1F8000h to 1FFFFFh 29PDS322BE (Bottom Boot Type)Word Mode:000000h to 007FFFh

7.HRBA =Bank Address of the Hi-ROM area 29PDS322TE (Top Boot Type):A 29PDS322BE (Bottom Boot Type):A

= A

= A16 = A

= A

= A16 = A

= 1

= 0

8.The system should generate the following address patterns: Word Mode: 555h or 2AAh to addresses A

10 to A0

9.Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

Table 5.1 MBM29PDS322TE Sector Group Protection Verify Autoselect Codes

Type A

to A

Manufacture’s Code BA Device Code Word BA

Extended Device Code *

Word BA Word BA

MBM29PDS322TE/BE

VIL VIL VIL VIL VIL 04h VIL VIL VIL VIL VIH 227Eh VIL VIH VIH VIH VIL 2206h VIL VIH VIH VIH VIH 2201h

10/11

Code (HEX)

Sector Group Protection

Sector Group

Addresses

IL VIL VIL VIH VIL 01h

*1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2:When V

ID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous oper ation

unable to be ex ecuted. Consequently , specifying the bank address is not demanded. How ever , the bank address needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to activate simultaneous operation.

*3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Table 5.2 Expanded Autoselect Code Table

Type Code

Manufacturer’s Code

Device Code (W) Extended

Device Code

(W) (W)

Sector Group Protection

227Eh 2206h 2201h

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

04h0 0 0 0 0 00000000100

0 0 1 0 0 01001111110 0 0 1 0 0 01000000110 0 0 1 0 0 01000000001

01h0 0 0 0 0 00000000001

(W): Word mode

MBM29PDS322TE/BE

10/11

Table 5.3 MBM29PDS322BE Sector Group Protection Verify Autoselect Codes

Type A

to A

Manufacture’s Code BA Device Code Word BA

Extended Device Code *

Sector Group Protection

Word BA Word BA

Sector Group

Addresses

Code (HEX)

VIL VIL VIL VIL VIL 04h VIL VIL VIL VIL VIH 227Eh VIL VIH VIH VIH VIL 2206h VIL VIH VIH VIH VIH 2200h

VIL VIL VIL VIH VIL 01h

*1:Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.

*2:When V

ID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous oper ation

* 3:A read cycle at address (BA)01h outputs device code. When 227Eh was output, this indicates that there will

require two additional codes, called Extended Device Codes. Therefore, the system may continue reading out these Extended Device Codes at the address of (BA)0Eh, as well as at (BA)0Fh.

Table 5.4 Expanded Autoselect Code Table

Type Code

Manufacturer’s Code

Device Code (W) Extended

Device Code

(W) (W)

Sector Group Protection

227Eh 2206h 2200h

DQ15DQ14DQ13DQ12DQ11DQ10DQ9DQ8DQ7DQ6DQ5DQ4DQ3DQ2DQ1DQ

04h0000000000000100

0010001001111110 0010001000000110 0010001000000000

01h0000000000000001

(W): Word mode

FLEXIBLE SECTOR-ERASE ARCHITECTURE

■■■■

Table 6.1 Sector Address Tables (MBM29PDS322TE)

Sector Address

Bank Sector

20A19

Bank Address

A18A17A

SA0 0 0 0 0 0 0 X X X 32 000000h to 007FFFh SA1 0 0 0 0 0 1 X X X 32 008000h to 00FFFFh SA2 0 0 0 0 1 0 X X X 32 010000h to 017FFFh SA3 0 0 0 0 1 1 X X X 32 018000h to 01FFFFh SA4 0 0 0 1 0 0 X X X 32 020000h to 027FFFh SA5 0 0 0 1 0 1 X X X 32 028000h to 02FFFFh SA6 0 0 0 1 1 0 X X X 32 030000h to 037FFFh SA7 0 0 0 1 1 1 X X X 32 038000h to 03FFFFh SA8 0 0 1 0 0 0 X X X 32 040000h to 047FFFh

SA9 0 0 1 0 0 1 X X X 32 048000h to 04FFFFh SA10 0 0 1 0 1 0 X X X 32 050000h to 057FFFh SA11 0 0 1 0 1 1 X X X 32 058000h to 05FFFFh SA12 0 0 1 1 0 0 X X X 32 060000h to 067FFFh SA13 0 0 1 1 0 1 X X X 32 068000h to 06FFFFh SA14 0 0 1 1 1 0 X X X 32 070000h to 077FFFh SA15 0 0 1 1 1 1 X X X 32 078000h to 07FFFFh SA16 0 1 0 0 0 0 X X X 32 080000h to 087FFFh

Bank 2

SA17 0 1 0 0 0 1 X X X 32 088000h to 08FFFFh SA18 0 1 0 0 1 0 X X X 32 090000h to 097FFFh SA19 0 1 0 0 1 1 X X X 32 098000h to 09FFFFh SA20 0 1 0 1 0 0 X X X 32 0A0000h to 0A7FFFh SA21 0 1 0 1 0 1 X X X 32 0A8000h to 0AFFFFh SA22 0 1 0 1 1 0 X X X 32 0B0000h to 0B7FFFh SA23 0 1 0 1 1 1 X X X 32 0B8000h to 0BFFFFh SA24 0 1 1 0 0 0 X X X 32 0C0000h to 0C7FFFh SA25 0 1 1 0 0 1 X X X 32 0C8000h to 0CFFFFh SA26 0 1 1 0 1 0 X X X 32 0D0000h to 0D7FFFh SA27 0 1 1 0 1 1 X X X 32 0D8000h to 0DFFFFh SA28 0 1 1 1 0 0 X X X 32 0E0000h to 0E7FFFh SA29 0 1 1 1 0 1 X X X 32 0E8000h to 0EFFFFh SA30 0 1 1 1 1 0 X X X 32 0F0000h to 0F7FFFh SA31 0 1 1 1 1 1 X X X 32 0F8000h to 0FFFFFh SA32 1 0 0 0 0 0 X X X 32 100000h to 107FFFh SA33 1 0 0 0 0 1 X X X 32 108000h to 10FFFFh SA34 1 0 0 0 1 0 X X X 32 110000h to 117FFFh

MBM29PDS322TE/BE

Sector

Size

(Kwords)

(

Address Range

××××

16)

(Continued)

10/11

MBM29PDS322TE/BE

(Continued)

Sector Address

Bank Sector

SA35 1 0 0 0 1 1 X X X 32 118000h to 11FFFFh SA36 1 0 0 1 0 0 X X X 32 120000h to 127FFFh SA37 1 0 0 1 0 1 X X X 32 128000h to 12FFFFh SA38 1 0 0 1 1 0 X X X 32 130000h to 137FFFh SA39 1 0 0 1 1 1 X X X 32 138000h to 13FFFFh SA40 1 0 1 0 0 0 X X X 32 140000h to 147FFFh SA41 1 0 1 0 0 1 X X X 32 148000h to 14FFFFh SA42 1 0 1 0 1 0 X X X 32 150000h to 157FFFh SA43 1 0 1 0 1 1 X X X 32 158000h to 15FFFFh SA44 1 0 1 1 0 0 X X X 32 160000h to 167FFFh

Bank 2

SA45 1 0 1 1 0 1 X X X 32 168000h to 16FFFFh SA46 1 0 1 1 1 0 X X X 32 170000h to 177FFFh SA47 1 0 1 1 1 1 X X X 32 178000h to 17FFFFh SA48 1 1 0 0 0 0 X X X 32 180000h to 187FFFh SA49 1 1 0 0 0 1 X X X 32 188000h to 18FFFFh SA50 1 1 0 0 1 0 X X X 32 190000h to 197FFFh SA51 1 1 0 0 1 1 X X X 32 198000h to 19FFFFh SA52 1 1 0 1 0 0 X X X 32 1A0000h to 1A7FFFh SA53 1 1 0 1 0 1 X X X 32 1A8000h to 1AFFFFh SA54 1 1 0 1 1 0 X X X 32 1B0000h to 1B7FFFh SA55 1 1 0 1 1 1 X X X 32 1B8000h to 1BFFFFh SA56 1 1 1 0 0 0 X X X 32 1C0000h to 1C7FFFh SA57 1 1 1 0 0 1 X X X 32 1C8000h to 1CFFFFh SA58 1 1 1 0 1 0 X X X 32 1D0000h to 1D7FFFh SA59 1 1 1 0 1 1 X X X 32 1D8000h to 1DFFFFh SA60 1 1 1 1 0 0 X X X 32 1E0000h to 1E7FFFh SA61 1 1 1 1 0 1 X X X 32 1E8000h to 1EFFFFh SA62 1 1 1 1 1 0 X X X 32 1F0000h to 1F7FFFh

Bank 1

SA63 1 1 1 1 1 1 0 0 0 4 1F8000h to 1F8FFFh SA64 1 1 1 1 1 1 0 0 1 4 1F9000h to 1F9FFFh SA65111111010 4 1FA000h to 1FAFFFh SA66111111011 4 1FB000h to 1FBFFFh SA67111111100 4 1FC000h to 1FCFFFh SA68111111101 4 1FD000h to 1FDFFFh SA69111111110 4 1FE000h to 1FEFFFh SA70111111111 4 1FF000h to 1FFFFFh

20A19

Bank Address

A18A17A

10/11

Sector

Size

(Kwords)

××××

(

16)

Address Range

MBM29PDS322TE Top Boot Sector Architecture

Bank Sector

SA70 1 1 1 1 1 1 X X X 32 1F8000h to 1FFFFFh SA69 1 1 1 1 1 0 X X X 32 1F0000h to 1F7FFFh SA68 1 1 1 1 0 1 X X X 32 1E8000h to 1EFFFFh SA67 1 1 1 1 0 0 X X X 32 1E0000h to 1E7FFFh SA66 1 1 1 0 1 1 X X X 32 1D8000h to 1DFFFFh SA65 1 1 1 0 1 0 X X X 32 1D0000h to 1D7FFFh SA64 1 1 1 0 0 1 X X X 32 1C8000h to 1CFFFFh SA63 1 1 1 0 0 0 X X X 32 1C0000h to 1C7FFFh SA62 1 1 0 1 1 1 X X X 32 1B8000h to 1BFFFFh SA61 1 1 0 1 1 0 X X X 32 1B0000h to 1B7FFFh SA60 1 1 0 1 0 1 X X X 32 1A8000h to 1AFFFFh SA59 1 1 0 1 0 0 X X X 32 1A0000h to 1A7FFFh SA58 1 1 0 0 1 1 X X X 32 198000h to 19FFFFh SA57 1 1 0 0 1 0 X X X 32 190000h to 197FFFh SA56 1 1 0 0 0 1 X X X 32 188000h to 18FFFFh SA55 1 1 0 0 0 0 X X X 32 180000h to 187FFFh SA54 1 0 1 1 1 1 X X X 32 178000h to 17FFFFh

Bank 2

SA53 1 0 1 1 1 0 X X X 32 170000h to 177FFFh SA52 1 0 1 1 0 1 X X X 32 168000h to 16FFFFh SA51 1 0 1 1 0 0 X X X 32 160000h to 167FFFh SA50 1 0 1 0 1 1 X X X 32 158000h to 15FFFFh SA49 1 0 1 0 1 0 X X X 32 150000h to 157FFFh SA48 1 0 1 0 0 1 X X X 32 148000h to 14FFFFh SA47 1 0 1 0 0 0 X X X 32 140000h to 147FFFh SA46 1 0 0 1 1 1 X X X 32 138000h to 13FFFFh SA45 1 0 0 1 1 0 X X X 32 130000h to 137FFFh SA44 1 0 0 1 0 1 X X X 32 128000h to 12FFFFh SA43 1 0 0 1 0 0 X X X 32 120000h to 127FFFh SA42 1 0 0 0 1 1 X X X 32 118000h to 11FFFFh SA41 1 0 0 0 1 0 X X X 32 110000h to 117FFFh SA40 1 0 0 0 0 1 X X X 32 108000h to 10FFFFh SA39 1 0 0 0 0 0 X X X 32 100000h to 107FFFh SA38 0 1 1 1 1 1 X X X 32 0F8000h to 0FFFFFh SA37 0 1 1 1 1 0 X X X 32 0F0000h to 0F7FFFh SA36 0 1 1 1 0 1 X X X 32 0E8000h to 0EFFFFh SA35 0 1 1 1 0 0 X X X 32 0E0000h to 0E7FFFh

20A19

MBM29PDS322TE/BE

Table 6.2 Sector Address Tables (MBM29PDS322BE)

Sector Address

Bank Address

A18A17A

Sector

Size

(Kwords)

10/11

××××

(

16)

Address Range

(Continued)

MBM29PDS322TE/BE

(Continued)

Sector Address

Bank Sector

SA34 0 1 1 0 1 1 X X X 32 0D8000h to 0DFFFFh SA33 0 1 1 0 1 0 X X X 32 0D0000h to 0D7FFFh SA32 0 1 1 0 0 1 X X X 32 0C8000h to 0CFFFFh SA31 0 1 1 0 0 0 X X X 32 0C0000h to 0C7FFFh SA30 0 1 0 1 1 1 X X X 32 0B8000h to 0BFFFFh SA29 0 1 0 1 1 0 X X X 32 0B0000h to 0B7FFFh SA28 0 1 0 1 0 1 X X X 32 0A8000h to 0AFFFFh SA27 0 1 0 1 0 0 X X X 32 0A0000h to 0A7FFFh SA26 0 1 0 0 1 1 X X X 32 098000h to 09FFFFh

Bank 2

SA25 0 1 0 0 1 0 X X X 32 090000h to 097FFFh SA24 0 1 0 0 0 1 X X X 32 088000h to 08FFFFh SA23 0 1 0 0 0 0 X X X 32 080000h to 087FFFh SA22 0 0 1 1 1 1 X X X 32 078000h to 07FFFFh SA21 0 0 1 1 1 0 X X X 32 070000h to 077FFFh SA20 0 0 1 1 0 1 X X X 32 068000h to 06FFFFh SA19 0 0 1 1 0 0 X X X 32 060000h to 067FFFh SA18 0 0 1 0 1 1 X X X 32 058000h to 05FFFFh SA17 0 0 1 0 1 0 X X X 32 050000h to 057FFFh SA16 0 0 1 0 0 1 X X X 32 048000h to 04FFFFh SA15 0 0 1 0 0 0 X X X 32 040000h to 047FFFh SA14 0 0 0 1 1 1 X X X 32 038000h to 03FFFFh SA13 0 0 0 1 1 0 X X X 32 030000h to 037FFFh SA12 0 0 0 1 0 1 X X X 32 028000h to 02FFFFh SA11 0 0 0 1 0 0 X X X 32 020000h to 027FFFh SA10 0 0 0 0 1 1 X X X 32 018000h to 01FFFFh

SA9 0 0 0 0 1 0 X X X 32 010000h to 017FFFh

SA8 0 0 0 0 0 1 X X X 32 008000h to 00FFFFh

Bank 1

SA7 0 0 0 0 0 0 1 1 1 4 007000h to 007FFFh

SA6 0 0 0 0 0 0 1 1 0 4 006000h to 006FFFh

SA5 0 0 0 0 0 0 1 0 1 4 005000h to 005FFFh

SA4 0 0 0 0 0 0 1 0 0 4 004000h to 004FFFh

SA3 0 0 0 0 0 0 0 1 1 4 003000h to 003FFFh

SA2 0 0 0 0 0 0 0 1 0 4 002000h to 002FFFh

SA1 0 0 0 0 0 0 0 0 1 4 001000h to 001FFFh

SA0 0 0 0 0 0 0 0 0 0 4 000000h to 000FFFh

20A19

Bank Address

A18A17A

10/11

Sector

Size

(Kwords)

××××

(

16)

Address Range

MBM29PDS322BE Bottom Boot Sector Architecture

MBM29PDS322TE/BE

10/11

Table 7.1 Sector Group Address Table (MBM29PDS322TE) (Top Boot Block)

Sector Group A

Sectors

SGA0 000000XXX SA0

SGA1 0000

XXXSA1 to SA310

11 SGA2 0001XXXXXSA4 to SA7 SGA3 0010XXXXXSA8 to SA11 SGA4 0011XXXXXSA12 to SA15 SGA5 0100XXXXXSA16 to SA19 SGA6 0101XXXXXSA20 to SA23 SGA7 0110XXXXXSA24 to SA27 SGA8 0111XXXXXSA28 to SA31 SGA9 1000XXXXXSA32 to SA35

SGA10 1001XXXXXSA36 to SA39 SGA11 1010XXXXXSA40 to SA43 SGA12 1011XXXXXSA44 to SA47 SGA13 1100XXXXXSA48 to SA51 SGA14 1101XXXXXSA52 to SA55 SGA15 1110XXXXXSA56 to SA59

SGA16 1 1 1 1

X X X SA60 to SA6201

SGA17 111111000 SA63 SGA18 111111001 SA64 SGA19 111111010 SA65 SGA20 111111011 SA66 SGA21 111111100 SA67 SGA22 111111101 SA68 SGA23 111111110 SA69 SGA24 111111111 SA70

MBM29PDS322TE/BE

10/11

Table 7.2 Sector Group Address Table (MBM29PDS322BE) (Bottom Boot Block)

Sector Group A

Sectors

SGA0 000000000 SA0 SGA1 000000001 SA1 SGA2 000000010 SA2 SGA3 000000011 SA3 SGA4 000000100 SA4 SGA5 000000101 SA5 SGA6 000000110 SA6 SGA7 000000111 SA7

01 SGA8 0000

X X X SA8 to SA1010

11 SGA9 0001XXXXXSA11 to SA14

SGA10 0010XXXXXSA15 to SA18 SGA11 0011XXXXXSA19 to SA22 SGA12 0100XXXXXSA23 to SA26 SGA13 0101XXXXXSA27 to SA30 SGA14 0110XXXXXSA31 to SA34 SGA15 0111XXXXXSA35 to SA38 SGA16 1000XXXXXSA39 to SA42 SGA17 1001XXXXXSA43 to SA46 SGA18 1010XXXXXSA47 to SA50 SGA19 1011XXXXXSA51 to SA54 SGA20 1100XXXXXSA55 to SA58 SGA21 1101XXXXXSA59 to SA62 SGA22 1110XXXXXSA63 to SA66

SGA23 1 1 1 1

X X X SA67 to SA6901

SGA24 111111XXX SA70

MBM29PDS322TE/BE

FUNCTIONAL DESCRIPTION

■■■■

Simultaneous Operation

The device has feature, which is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional features (read, program, er ase, erase-suspend read, and erase-suspend program). The bank selection can be selected by bank address (A

The device has two banks which contain

Bank 1 (4 KW × eight sectors, 32 KW × seven sectors) and Bank 2 (32 KW × fifty-six sectors).

The simultaneous operation can not execute multi-function mode in the same bank. Table 8 shows the possible combinations for simultaneous operation. (Refer to Figure 12 Back-to-Back Read/Write Timing Diagram.)

Case Bank 1 Status Bank 2 Status

1 Read mode Read mode 2 Read mode Autoselect mode 3 Read mode Program mode 4 Read mode Erase mode * 5 Autoselect mode Read mode 6 Program mode Read mode 7 Erase mode * Read mode

20 to A15) with zero latency.

Table 8 Simultaneous Operation

10/11

*: An erase operation may also be suspended to read from or program to a sector not being erased.

Read Mode

The device has two control functions which must be satisfied in order to obtain data at the outputs. CE power control and should be used for a device selection. OE

is the output control and should be used as the

gate data to the output pins if a device is selected. Address access time (tACC) is equal to delay from stable addresses to valid output data. The chip enable access

time (t

CE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable

access time (t have been stable for at least t it is necessary to input hardware reset or to change CE

OE) is the delay from the f alling edge of OE to valid data at the output pins. (Assuming the addresses

ACC-tOE time.) When reading out data without changing addresses after power-up,

pin from “H” or “L”.

Page Mode Read

The device is capable of fast Page mode read operation. This mode provides faster read access speed for random locations within a page. The Page size of the device is 4 words, within the appropriate Page being selected by the higher address bits A

20 to A2 and the LSB bits A1 and A0 within that page. This is an asynchronous

operation with the microprocessor supplying the specific word location. The random or initial page access is equal to tACC and subsequent Page read access (as long as the locations

specified by the microprocessor fall within that Page) is equivalent to t and OE Page mode accesses are obtained by keeping A

is the output control and should be used to gate data to the output pins if the device is selected. Fast

20 to A2 constant and changing A1 and A0 to select the specific

PAC C. Here again, CE selects the device

word, within that page. See Figure 5.4 for timing specifications.

is the

MBM29PDS322TE/BE

10/11

Standby Mode

There are two ways to implement the standb y mode on the de vice , one using both the CE other via the RESET

pin only.

and RESET pins; the

When using both pins, a CMOS standby mode is achie v ed with CE

and RESET inputs both held at VCC ± 0.3 V. Under this condition, the current consumed is less than 5 µA Max. During Embedded Algorithm operation, V active current (ICC2) is required ev en CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes.

When using the RESET

pin only, a CMOS standby mode is achiev ed with RESET input held at VSS ± 0.3 V (CE = “H” or “L”). Under this condition the current consumed is less than 5 µA Max. Once the RESET pin is taken high, the device requires t

In the standby mode, the outputs are in the high impedance state, independently of the OE

RH as wake up time for outputs to be valid for read access.

input.

Automatic Sleep Mode

There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption.

To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE

, WE, and OE on the mode.

Under the mode, the current consumed is typically 50 µA (CMOS Level). During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,

the mode is canceled automatically, and the device reads the data for changed addresses.

Output Disable

With the OE

input at a logic high level (VIH), output from the device is disabled. This will cause the output pins

to be in a high impedance state.

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the device outputs by toggling address A addresses are DON’T CARES except A

6, A3, A2, A1, and A0. (See Table 3.)

ID (10.0 V to 11.0 V) on address pin A9. Two

0 from VIL to VIH. All

The manufacturer and de vice codes may also be read via the command register, for instances when the de vice is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in Table 4. (Refer to Autoselect Command section.)

In the command Autoselect mode, the bank addresses BA; (A

20 to A12) must point to a specific bank during the

third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while array data can be read from the other bank.

A read cycle from address (BA)00h returns the manufacturer’s code (Fujitsu = 04h). And a read cycle from address (BA)01h, (BA)0Eh to (BA)0Fh returns the device code. (See Tables 5.1 to 5.4.)

In case of applying V

ID on A9, since both Bank 1 and Bank 2 enter Autoselect mode, the simultaneous oper ation

can not be executed.

+ 46 hidden pages