FUJITSU MB90455 DATA SHEET

查询MB90455供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90455 Series

MB90F455 (S) /F456 (S) /F457 (S)
MB90455 (S) /456 (S) /457 (S) /V495G

DESCRIPTION

■

MB90455 series devices are general-purpose high-performance 16-bit micro controllers designed for process
control of consumer products, which require high-speed real-time processing.

The system, inheriting the architecture of F
guages, expanded addressing mode , enhanced multiply-divide instructions, and enriched bit-processing instruc­tions. Furthermore, employment of 32-bit accumulator achieves processing of long-word data (32 bits).

The peripheral resources of MB90455 series include the following:
8/10-bit A/D converter, UART 1, 8/16-bit PPG timer , 16-bit input-output timer (16-bit free-run timer, input capture

0, 1, 2, 3 (ICU)).

2

MC”, an abbreviation for FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd.

*: “F

2

MC* family, employs additional instruction ready for high-level lan-

DS07-13728-3E

FEATURES

■

••••

Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allowed among frequency division by two on oscillation clock, and
multiplication of 1 to 4 times of oscillation clock (for 4-MHz oscillation clock, 4 MHz to 16 MHz).

• Operation by sub-clock (8.192 kHz) is allowed.

• Minimum execution time of instruction: 62.5 ns (when operating with 4-MHz oscillation cloc k, and 4-time m ulti­plied PLL clock).

(Continued)

PACKAGE

■

48-pin plastic-LQFP

(FPT-48P-M26)

MB90455 Series

••••

16 Mbyte CPU memory space

• 24-bit internal addressing

••••

Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

••••

Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

••••

Increased processing speed

• 4-byte instruction queue

••••

Powerful interrupt function with 8 levels and 34 factors

••••

Automatic data transfer function independent of CPU

• Expanded intelligent I/O service function (EI

••••

Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Time-base timer mode (a mode that operates oscillation clock, sub clock, time-base timer and cloc k timer only)

• Clock mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

2

OS): Maximum of 16 channels

••••

Process

•CMOS technology

••••

I/O port

• General-purpose input/output port (CMOS output): 34 por ts(MB90F455/F456/F457, MB90455/456/457) (in­cluding 4 high-current output ports) (When sub clock is not used, 36 ports(MB90F455S/F456S/F457S,
MB90455S/456S/457S))

••••

Timer

• Time-base timer, clock timer, watchdog timer: 1 channel

• 8/16-bit PPG timer: 8-bit x 4 channels, or 16-bit x 2 channels

• 16-bit reload timer: 2 channels

• 16-bit input/output timer

- 16-bit free run timer: 1 channel

- 16-bit input capture: (ICU): 4 channels
Interrupt request is issued upon latching a count value of 16-bit free run timer by detection of an edge on pin
input.

••••

UART 1: 1 channel

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available

(Continued)

2

(Continued)

••••

DTP/External interrupt: 4 channels

• Module for activation of expanded intelligent I/O service (EI

••••

Delay interrupt generator module

• Generates interrupt request for task switching.

••••

8/10-bit A/D converter: 8 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time)

••••

Program patch function

• Address matching detection for 2 address pointers.

2

OS), and generation of external interrupt.

MB90455 Series

3

MB90455 Series

PRODUCT LINEUP

■

Part Number

Parameter

Classification Flash ROM Mask ROM Evaluation product

ROM capacity

RAM capacity 2 Kbytes 6 Kbytes

Clock

Process CMOS
Package LQFP-48 (0.50 mm width) PGA256
Operating power supply voltage 3.5 V to 5.5 V
Special power supply for

emulator*

CPU functions

Low power consumption
(standby) mode

I/O port

Time-base timer

Watchdog timer

16-bit input/
output timer

16-bit reload timer

Clock timer

1

16-bit free-run
timer

Input capture

MB90F455 (S) /

F456 (S) /F457 (S)

MB90F455 (S) : 24 Kbytes
MB90F456 (S) : 32 Kbytes
MB90F457 (S) : 64 Kbytes

MB90F455/F456/F457 :

2 systems

MB90F455S/F456S/F457S :

1 system

 None

Number of basic instructions
Instruction bit length
Instruction length
Data bit length

Minimum instruction execution time : 62.5 ns (at 16-MHz machine clock)
Interrupt processing time : 1.5 µs at minimum (at 16-MHz machine clock)
Sleep mode/Clock mode/Time-base timer mode/

Stop mode/CPU intermittent
General-purpose input/output ports (CMOS output) : 34 ports (36 ports*

including 4 high-current output ports (P14 to P17)
18-bit free-run counter

Interrupt cycle : 1.024 ms, 4.096 ms, 16.834 ms, 131.072 ms
(with oscillation clock frequency at 4 MHz)

Reset generation cycle: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms
(with oscillation clock frequency at 4 MHz)

Number of channels: 1
Interrupt upon occurrence of overflow

Number of channels: 4
Retaining free-run timer value set by pin input (rising edge, falling edge, and
both edges)

Number of channels: 2
16-bit reload timer operation
Count clock cycle: 0.25 µs, 0.5 µs, 2.0 µs
(at 16-MHz machine clock frequency)
External event count is allowed.

15-bit free-run counter
Interrupt cycle: 31.25 ms, 62.5 ms, 12 ms, 250 ms, 500 ms, 1.0 s, 2.0 s
(with 8.192 kHz sub clock)

MB90455 (S) /

456 (S) /457 (S)

MB90455 (S) : 24 Kbytes
MB90456 (S) : 32 Kbytes
MB90457 (S) : 64 Kbytes

MB90455/456/457 :

2 systems

MB90455S/456S/457S :

1 system

: 351 instructions
: 8 bits and 16 bits
: 1 byte to 7 bytes
: 1 bit, 8 bits, 16 bits

MB90V495G



2 systems

4.5 V

to 5.5 V

2

)

(Continued)

4

(Continued)

Parameter

8/16-bit PPG timer

Part Number

MB90455 Series

MB90F455 (S) /

F456 (S) /F457 (S)

Number of channels: 2 (four 8-bit channels are available also)
PPG operation is allowed with four 8-bit channels or one 16-bit channel.
Outputting pulse wave of arbitrary cycle or arbitrary duty is allowed.
Count clock: 62.5 ns to 1 µs
(with 16 MHz machine clock)

MB90455 (S) /

456 (S) /457 (S)

MB90V495G

Delay interrupt generator
module

DTP/External interrupt

8/10-bit A/D converter

UART 1

*1 : Settings of DIP switch S2 f or using emulation pod MB2145-507. For details, See MB2145-507 Hardw are Manual

(2.7 Power Pin solely for Emulator).

*2 : MB90F455S/F456S/F457S, MB90455S/456S/457S

Interrupt generator module for task switching. Used for Real-time OS.
Number of inputs: 4

Activated by rising edge, falling edge, “H” level or “L” level input.
External interrupt or expanded intelligent I/O service (EI

Number of channels: 8
Resolution: Selectable 10-bit or 8-bit.
Conversion time: 6.125 µs (at 16-MHz machine clock, including sampling time)
Sequential conversion of two or more successive channels is allowed. (Setting
a maximum of 8 channels is allowed.)
Single conversion mode : Selected channel is converted only once.
Sequential conversion mode: Selected channel is converted repetitively.
Halt conversion mode : Conversion of selected channel is stopped and

activated alternately.

Number of channels: 1
Clock-synchronous transfer: 62.5 Kbps to 2 Mbps
Clock-asynchronous transfer: 9,615 bps to 500 Kbps
Communication is allowed by bi-directional serial communication function and
master/slave type connection.

2

OS) is available.

5

MB90455 Series

PACKAGES AND PRODUCT MODELS

■■■■

Packa ge MB90F455 (S) /F456 (S) /F457 (S) MB90455 (S) /456 (S) /457 (S)

FPT-48P-M26

: Yes × : No

Note : Refer to “ PACKAGE DIMENSION” for details of the package.

PRODUCT COMPARISON

■■■■

Memory space

When testing with test product for evaluation, check the differences between the product and a product to be
used actually. Pay attention to the following points:

• The MB90V495G has no built-in ROM. However, a special-purpose development tool allows the operations
as those of one with built-in ROM. ROM capacity depends on settings on a development tool.

• On MB90V495G, an image from FF4000
FF3FFFH is viewed only on FE bank and FF bank. (Modified on settings of a development tool.)

• On MB90F455 (S) /F456 (S) /F457 (S) , MB90455 (S) /456 (S) /457 (S) , an image from FF4000
is viewed on 00 bank and an image of FE0000H to FF3FFFH is viewed only on FF bank.

H to FFFFFFH is viewed on 00 bank and an image of FE0000H to

H to FFFFFFH

6

PIN ASIGNMENT

■■■■

(TOP VIEW)

X1A/P36*

X0A/P35*

P33

AVSS

P32

P31

P30

P44

P43

P42/SOT1

P41/SCK1

P40/SIN1

MB90455 Series

AVCC

AVR
P50/AN0
P51/AN1
P52/AN2
P53/AN3
P54/AN4
P55/AN5
P56/AN6
P57/AN7

P37/ADTG

P20/TIN0

4847464544434241403938
1
2
3
4
5
6
7
8
9
10
11
12

1314151617181920212223

P22/TIN1

P24/INT4

P25/INT5

P21/TOT0

P26/INT6

P23/TOT1

MD2

P27/INT7

MD1

MD0

37

24

RST

CC

V

36
35
34
33
32
31
30
29
28
27
26
25

(FPT-48P-M26)

* : MB90F455/F456/F457, MB90455/456/457 : X1A, X0A

MB90F455S/F456S/F457S, MB90455S/456S/457S : P36, P35

P17/PPG3
P16/PPG2
P15/PPG1
P14/PPG0
P13/IN3
P12/IN2
P11/IN1
P10/IN0
X1
X0
C
V

SS

7

MB90455 Series

PIN DESCRIPTION

■

Pin No. Pin name

1AVcc Vcc power input pin for A/D converter
2 AVR  Power (Vref+) input pin for A/D converter. Use as input for Vcc or lower.

Circuit
format

Description

P50 to P57

3 to 10

AN0 to AN7

P37

11

ADTG

P20

12

TIN0

P21

13

TOT0

P22

14

TIN1

P23

15

TOT1

P24 to P27

16 to 19

INT4 to INT7

20 MD2 F Input pin for specifying operation mode. Connect directly to Vss.

E

D

D

D

D

D

D

General-purpose input/output ports.
Functions as an analog input pin for A/D converter. Valid when analog

input setting is “enabled.”
General-purpose input/output port.
Function as an external trigger input pin for A/D converter. Use the pin by

setting as input port.
General-purpose input/output port.
Function as an event input pin for reload timer 0. Use the pin by setting as

input port.
General-purpose input/output port.
Function as an event output pin for reload timer 0. Valid only when output

setting is “enabled.”
General-purpose input/output port.
Function as an event input pin for reload timer 1. Use the pin by setting as

input port.
General-purpose input/output port.
Function as an event output pin for reload timer 1. Valid only when output

setting is “enabled.”
General-purpose input/output ports.
Functions as an external interrupt input pin. Use the pin by setting as input

port.

21 MD1 C Input pin for specifying operation mode. Connect directly to Vcc.
22 MD0 C Input pin for specifying operation mode. Connect directly to Vcc.
23 RST B External reset input pin.
24 Vcc  Power source (5 V) input pin.
25 Vss  Power source (0 V) input pin.

26 C 
27 X0 A Pin for high-rate oscillation.

28 X1 A Pin for high-rate oscillation.

P10 to P13

29 to 32

IN0 to IN3

8

D

Capacitor pin for stabilizing power source. Connect a ceramic capacitor of
approximately 0.1 µF.

General-purpose input/output ports.
Functions as trigger input pins of input capture channels 0 to 3. Use the

pins by setting as input ports.

(Continued)

(Continued)

Pin No. Pin name

Circuit
format

MB90455 Series

Description

P14 to P17

33 to 36

PPG0 to PPG3

P40

37

SIN1 Serial data input pin for UART. Use the pin by setting as input port.

P41

38

SCK1

P42

39

SOT1

40 P43 D General-purpose input/output port.
41 P44 D General-purpose input/output port.

42 to 45 P30 to P33 D General-purpose input/output ports.

X0A*

46

P35* General-purpose input/output port.
X1A*

47

P36* General-purpose input/output port.

G

D

D

D

A

A

General-purpose input/output ports. High-current output ports.
Functions as output pins of PPG timers 01 and 23. Valid when output

setting is “enabled.”
General-purpose input/output port.

General-purpose input/output port.
Serial clock input pin for UART. Valid only when serial clock input/output

setting on UART is “enabled.”
General-purpose input/output port.
Serial data input pin for UART. Valid only when serial data input/output

setting on UART is “enabled.”

Pin for low-rate oscillation.

Pin for low-rate oscillation.

48 AVss  Vss power source input pin for A/D converter.

* : MB90F455/F456/F457, MB90455/456/457 : X1A, X0A

MB90F455S/F456S/F457S, MB90455S/456S/457S : P36, P35

9

MB90455 Series

I/O CIRCUIT TYPE

■

Type Circuit Remarks

• High-rate oscillation feedback

X1

Clock input

X1A

A

X0

resistor, approx.1 MΩ

• Low-rate oscillation feedback
resistor, approx.10 MΩ

X0A

Standby control signal

• Hysteresis input with pull-up

Vcc

resistor.

• Pull-up resistor, approx.50 kΩ

B

R

R

Hysteresis input

• Hysteresis input

C

R

Hysteresis input

• CMOS hysteresis input

Vcc

• CMOS level output

• Standby control provided

Pch

Digital output

D

R

Digital output

Nch
Vss

Hysteresis input

10

Standby control

• CMOS hysteresis input

Vcc

• CMOS level output

• Shared for analog input pin

Pch

Digital output

E

R

Digital output

Nch
Vss

• Standby control provided

Hysteresis input

Standby control

Analog input

(Continued)

MB90455 Series

(Continued)

Type Circuit Remarks

• Hysteresis input with pull-down
resistor

R

Hysteresis input

F

R

Vss

Vcc

Pch

High-current output

• Pull-down resistor, approx. 50 kΩ

• FLASH product is not provided with
pull-down resistor.

• CMOS hysteresis input

• CMOS level output (high-current
output)

• Standby control provided

G

R

High-current output

Nch
Vss

Hysteresis input

Standby control

11

MB90455 Series

HANDLING DEVICES

■■■■

••••

Do not exceed maximum rating (preventing “latch up”)

• On a CMOS IC, latch-up may occur when applying a voltage higher than Vcc or a voltage lower than Vss to
input or output pin, which has no middle or high withstand voltage. Latch-up may also occur when a voltage
exceeding maximum rating is applied across Vcc and Vss.

• Latch-up causes drastic increase of power current, which ma y lead to destruction of elements by heat. Extreme
caution must be taken not to exceed maximum rating.

• When turning on and off analog power source, take extra care not to apply an analog power voltages (AVcc
and AVR) and analog input voltage that are higher than digital power voltage (Vcc).

••••

Handling unused pins

• Leaving unused input pins open may cause permanent destruction by malfunction or latch-up. Apply pull-up
or pull-down process to the unused pins using resistors of 2 kΩ or higher . Leav e unused input pins open under
output status, or process as input pins if they are under input status.

••••

Using external clock

• When using an external clock, drive only X0 pin and leav e X1 pin open. An e xample of using an e xternal clock
is shown below.

Using external clock

X0

Open

••••

Notes when using no sub clock

• If an oscillator is not connected to X0A and X1A pin, apply pull-down resistor to X0A pin and leav e X1A pin open.

••••

About power supply pins

• If two ore more Vcc and Vss exist, the pins that should be at the same potential are connected to each other
inside the device. For reducing unwanted emissions and preventing malfunction of strobe signals caused by
increase of ground lev el, howev er , be sure to connect the Vcc and Vss pins to the power source and the ground
externally .

• Pay attention to connect a power supply to Vcc and Vss of MB90455 series device in a lowest-possible
impedance.

• Near pins of MB90455 series device, connecting a bypass capacitor is recommended at 0.1 µF across Vcc
and Vss.

••••

Crystal oscillator circuit

• Noises around X0 and X1 pins cause malfunctions on a MB90455 series device. Design a print circuit so that
X0 and X1 pins, an crystal oscillator (or a ceramic oscillator), and bypass capacitor to the ground become as
close as possible to each other. Furthermore, avoid wires to X0 and X1 pins crossing each other as much as
possible.

• Print circuit designing that surrounds X0 and X1 pins with grounding wires, which ensures stable operation,
is strongly recommended.

X1

MB90455 series

12

MB90455 Series

••••

Caution on Operations during PLL Clock Mode

• If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. P erf ormance of this operation, howe v er ,
cannot be guaranteed.

••••

Sequence of turning on power of A/D converter and applying analog input

• Be sure to turn on digital power (Vcc) before applying signals to the A/D converter and applying analog input
signals (AN0 to AN7 pins).

• Be sure to turn off the power of A/D converter and analog input before turning off the digital power source.

• Be sure not to apply AVR exceeding AVcc when turning on and off. (No problems occur if analog and digital
power is turned on and off simultaneously.)

••••

Handling pins when A/D converter is not used

• If the A/D converter is not used, connect the pins under the following conditions: “AVcc=AVR=Vcc,” and
“Avss=Vss”

••••

Note on turning on power

• For preventing malfunctions on built-in step-down circuit, maintain a minimum of 50 µs of voltage rising time
(between 0.2 V and 2.7 V) when turning on the power.

••••

Stabilization of supply voltage

• A sudden change in the supply voltage may cause the device to malfunction even within the specified Vcc
supply voltage operating range. Therefore, the Vcc supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that Vcc ripple variations (peak-to-peak values) at
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard V
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

CC supply voltage and the coefficient

13

MB90455 Series

BLOCK DIAGRAM

■

X0,X1

RST

X0A,X1A

SOT1
SCK1

SIN1

AVcc
AVss

AN0 ~ AN7

AVR

ADTG

Clock

control circuit

Clock timer

Time-base timer

RAM

ROM/FLASH

Prescaler

UART1

8/10-bit A/D

converter (8ch)

CPU

2

F

MC-16LX core

Internal data bus

16-bit

free-run timer

Input

capture

(4ch)

16-bit

PPG timer

(2ch)

DTP/External

interrupt

16-bit

reload timer

(2ch)

IN0 ~ IN3

PPG0 ~ PPG3

INT4 ~ INT7

TIN0,TIN1
TOT0,TOT1

14

MB90455 Series

MEMORY MAP

■■■■

MB90455 series allows specifying a memory access mode “single chip mode.”

1. Memory allocation of MB90455

MB90455 series model has 24-bit wide internal address bus and up to 24-bit bus of external address bus.
A maximum of 16 Mbyte memory space of external access memory is accessible.

2. Memory map

000000H
0000C0H

000100H

Address #1*

003800H
004000H

010000H

FE0000H
FF0000H

Address #2*

FFFFFFH

(with ROM mirroring

function available)

Peripheral

RAM area

1

Register

Extension IO

area

(with ROM mirroring

function not available)

Peripheral
RAM area

Register

Extension IO

area

ROM area

(FF bank image)

ROM area*

1

ROM area

2

Product

ROM area*

ROM area

Address #1*

2

1

Address #2*

MB90F455 (S) /455 (S) 000900H FFA000H
MB90F456 (S) /456 (S) 000900H FF8000H

1

MB90F457 (S) /457 (S) 000900H FF0000H
MB90V495G 001900H 

: Internal access memory

: Access disallowed

*1 : Addresses #1 and #3 are product-specific.
*2 : On MB90F455 (S) /F456 (S) /F457 (S) , 455 (S) /456 (S) /457 (S) , to read “FE0000

“FEFFFF

H” is to read out “FF0000H” to “FFFFFFH”.

H” to

Note : When internal ROM is operating, F2MC-16LX allows viewing ROM data image on FF bank at upper-level of

00 bank. This function is called “mirroring ROM,” which allows effective use of C compiler small model.

2

F

MC-16LX assigns the same low order 16-bit address to FF bank and 00 bank, which allows referencing
table in ROM without specifying “far” using pointer.
For e xample, when accessing to “00C000

H”, ROM data at “FFC000H” is accessed actually . Howe ver , because

ROM area of FF bank exceeds 48 Kb ytes, viewing all areas is not possible on 00 bank image . Because ROM
data of “FF4000
“FF4000

H” to “FFFFFFH.”

H” to “FFFFFFH” is viewed on “004000H” to “00FFFFH” image, store a R OM data table in area

15

MB90455 Series

I/O MAP

■■■■

Address

000000

Register

abbreviation

H (Reserved area) *

Register name Reset value

Peripheral

function name

Read/

Write

000001H PDR1 Port 1 data register XXXXXXXXB Port 1 R/W
000002

H PDR2 Port 2 data register XXXXXXXXB Port 2 R/W

000003H PDR3 Port 3 data register XXXXXXXXB Port 3 R/W
000004H PDR4 Port 4 data register XXXXXXXXB Port 4 R/W
000005

H PDR5 Port 5 data register XXXXXXXXB Port 5 R/W

000006H

to

000010
000011
000012

H

H DDR1 Port 1 direction data register 00000000B Port 1 R/W
H DDR2 Port 2 direction data register 00000000B Port 2 R/W

(Reserved area) *

000013H DDR3 Port 3 direction data register 000X0000B Port 3 R/W
000014H DDR4 Port 4 direction data register XXX00000B Port 4 R/W
000015

H DDR5 Port 5 direction data register 00000000B Port 5 R/W

000016H

to

00001A
00001B
00001C

to

000025
000026

H

H ADER Analog input permission register 11111111B

H

H

H SMR1 Serial mode register 1 00000000B

(Reserved area) *

(Reserved area) *

8/10-bit
A/D converter

R/W

R/W

000027H SCR1 Serial control register 1 00000100B R/W, W
000028
000029

00002A
00002B
00002C

to

00002F

000030

000031
000032
000033

SIDR1/

H

SODR1

H SSR1 Serial status data register 1 00001000B R, R/W
H (Reserved area) *

H CDCR1

H

Serial input data register 1/ Serial
output data register 1

Communication prescaler control
register 1

XXXXXXXXB R, W

0XXX0000B UART1 R/W

(Reserved area) *

H

H ENIR

H EIRR
H (Reserved area) *
H ELVR Detection level setting register 00000000B

DTP/External interrupt permission
register

DTP/External interrupt permission
register

00000000B

XXXXXXXXB R/W

UART1

DTP/External
interrupt

DTP/External
interrupt

R/W

R/W

16

(Continued)

MB90455 Series

Address

000034

Register

abbreviation

H

Register name Reset value

00000000

Peripheral

function name

B

Read/

Write

R/W

ADCS A/D control status register

000035
000036

H 00000000B R/W, W

H

XXXXXXXX

8/10-bit
A/D converter

B W, R

ADCR A/D data register

000037H 00101XXXB R
000038

00003F

000040

000041H PPGC1

000042
000043
000044H PPGC2

000045H PPGC3

H

to

H

H PPGC0

PPG0 operation mode control
register

(Reserved area) *

PPG1 operation mode control
register

H PPG01
H (Reserved area) *

PPG0/1 count clock selection
register

PPG2 operation mode control
register

PPG3 operation mode control
register

0X000XX1B

0X000001B R/W, W

8/16-bit
PPG timer 0/1

R/W, W

000000XXB R/W

0X000XX1B

0X000001B R/W, W

8/16-bit
PPG timer 2/3

R/W, W

000046
000047

H PPG23
H

to

00004F

H

000050H

IPCP0 Input capture data register 0

000051

H XXXXXXXXB

000052H

IPCP1 Input capture data register 1

000053

H XXXXXXXXB

000054H ICS01
000055

H ICS23 00000000B

000056H

TCDT Timer counter data register

000057

H 00000000B

PPG2/3 count clock selection
register

(Reserved area) *

Input capture control status register

000000XXB R/W

XXXXXXXX

XXXXXXXX

00000000B

00000000

B

B

16-bit input/output
timer

B

R/W

R/W

R

R

000058H TCCS Timer counter control status register 00000000B R/W

000059H (Reserved area) *
00005A
00005B
00005CH
00005D

H

XXXXXXXX

IPCP2 Input capture data register 2

H XXXXXXXXB

XXXXXXXX

IPCP3 Input capture data register 3

H XXXXXXXXB

B

16-bit input/output
timer

B

R

R

(Continued)

17

MB90455 Series

Address

00005E

to

000065

000066

000067

000068

000069
00006AH

to

00006E

00006F

000070

to

00007F

000080H

to

00008F

Register

abbreviation

H

Register name Reset value

Peripheral

function name

Read/

Write

(Reserved area) *

H

H

TMCSR0

H XXXX0000B R/W

00000000

B

16-bit reload timer 0

R/W

Timer control status register

H

00000000

TMCSR1

H XXXX0000B R/W

B

16-bit reload timer 1

R/W

(Reserved area) *

H

ROM mirroring
function selection
module

W

H ROMM

H

ROM mirroring function selection
register

XXXXXXX1B

(Reserved area) *

H

(Reserved area) *

H

000090
00009D
00009E

00009F

0000A0
0000A1

0000A2
0000A7

H

to

H

H PACSR Address detection control register 00000000B

H DIRR

H LPMCR
H CKSCR Clock selection register 11111100B Clock R,R/W

H

Delay interrupt request generation/
release register

Lowe power consumption mode
control register

to

H

(Reserved area) *

XXXXXXX0B

00011000B

(Reserved area) *

Address matching
detection function

Delay interrupt
generation module

Lowe power
consumption mode

R/W

R/W

W,R/W

0000A8H WDTC Watchdog timer control register XXXXX111B Watchdog timer R,W
0000A9
0000AA

H TBTC Time-base timer control register 1XX00100B Time-base timer R/W,W

H WTC Clock timer control register 1X001000B Clock timer R,R/W

0000ABH

to

0000AD

H

(Reserved area) *

(Continued)

18

MB90455 Series

Address

0000AE
0000AF

Register

abbreviation

H FMCS
H (Reserved area) *

Flash memory control status
register

Register name Reset value

000X0000B

0000B0H ICR00 Interrupt control register 00 00000111B
0000B1

H ICR01 Interrupt control register 01 00000111B

0000B2H ICR02 Interrupt control register 02 00000111B
0000B3H ICR03 Interrupt control register 03 00000111B
0000B4H ICR04 Interrupt control register 04 00000111B
0000B5H ICR05 Interrupt control register 05 00000111B
0000B6H ICR06 Interrupt control register 06 00000111B
0000B7H ICR07 Interrupt control register 07 00000111B
0000B8H ICR08 Interrupt control register 08 00000111B
0000B9H ICR09 Interrupt control register 09 00000111B
0000BAH ICR10 Interrupt control register 10 00000111B
0000BBH ICR11 Interrupt control register 11 00000111B
0000BCH ICR12 Interrupt control register 12 00000111B

Peripheral

function name

512 k-bit flash
memory

Read/

Write

R,W,R/W

Interrupt controller R/W

0000BDH ICR13 Interrupt control register 13 00000111B
0000BEH ICR14 Interrupt control register 14 00000111B
0000BFH ICR15 Interrupt control register 15 00000111B
0000C0H

to

0000FF
001FF0

001FF2H

001FF3H

001FF5H

003900H

003901

H

H

H

PADR0

Detection address setting register 0
(low-order)

Detection address setting register 0
(middle-order)

Detection address setting register 0
(high-order)

Detection address setting register 1
(low-order)

PADR1

Detection address setting register 1
(middle-order)

Detection address setting register 1
(high-order)

TMR0/

TMRLR0

H XXXXXXXXB

16-bit timer register 0/16-bit reload
register

(Reserved area) *

XXXXXXXX

XXXXXXXXB

XXXXXXXXB

XXXXXXXX

XXXXXXXXB

XXXXXXXXB
XXXXXXXX

B

Address matching
detection function

B

B

16-bit reload
timer 0

R/W001FF1

R/W001FF4H

R,W

(Continued)

19

MB90455 Series

(Continued)

Address

003902

003903

Register

abbreviation

H

TMR1/

TMRLR1

H XXXXXXXXB

16-bit timer register 1/16-bit reload
register

Register name Reset value

XXXXXXXX

B

Peripheral

function name

16-bit reload timer 1 R,W

003904H

to

00390F

003910

003911

H

H PRLL0 PPG0 reload register L XXXXXXXXB
H PRLH0 PPG0 reload register H XXXXXXXXB R/W

(Reserved area) *

003912H PRLL1 PPG1 reload register L XXXXXXXXB R/W

003913

H PRLH1 PPG1 reload register H XXXXXXXXB R/W

8/16-bit PPG timer

003914H PRLL2 PPG2 reload register L XXXXXXXXB R/W

003915H PRLH2 PPG2 reload register H XXXXXXXXB R/W

003916

H PRLL3 PPG3 reload register L XXXXXXXXB R/W

003917H PRLH3 PPG3 reload register H XXXXXXXXB R/W

003918H

to

003BFF
003C00

to

003C0F
003C10

to

003FFF

H

H

H

H

H

(Reserved area) *

RAM (General purpose RAM)

(Reserved area) *

Read/

Write

R/W

Reset values :

0 : Reset value of this bit is “0.”
1 : Reset value of this bit is “1.”
X : Reset value of this bit is undefined.

* : “Reserved area” should not be written anything. Result of reading from “Reserved area” is undefined.

20

MB90455 Series

■■■■

INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

2

EI

Interrupt source

Reset #08 08
INT 9 instruction #09 09
Exceptional treatment #10 0A

OS

readiness

×
×
×

Interrupt vector Interrupt control register

Number Address ICR Address

H FFFFDCH High
H FFFFD8H ↑

H FFFFD4H 

Reserved × #11 0BH FFFFD0H
Reserved × #12 0CH FFFFCCH
Reserved #13 0DH FFFFC8H
Reserved #14 0EH FFFFC4H
Reserved #15 0FH FFFFC0H
Time-base timer #16 10H FFFFBCH

×
×
×
×

16-bit reload timer 0 ∆ #17 11H FFFFB8H
8/10-bit A/D converter ∆ #18 12H FFFFB4H
16-bit free-run timer overflow ∆ #19 13H FFFFB0H
Reserved #20 14H FFFFACH
Reserved #21 15H FFFFA8H

×
×

PPG timer ch0, ch1 underflow × #22 16H FFFFA4H
Input capture 0-input ∆ #23 17H FFFFA0H
External interrupt (INT4/INT5) ∆ #24 18H FFFF9CH

ICR00 0000B0H

ICR01 0000B1H

ICR02 0000B2H

ICR03 0000B3H*

ICR04 0000B4H

ICR05 0000B5H

ICR06 0000B6H*

1

1

Priority*

3

Input capture 1-input ∆ #25 19H FFFF98H

ICR07 0000B7H*

2

PPG timer ch2, ch3 underflow × #26 1AH FFFF94H
External interrupt (INT6/INT7) ∆ #27 1BH FFFF90H

ICR08 0000B8H*

1

Clock timer ∆ #28 1CH FFFF8CH
Reserved #29 1DH FFFF88H
Input capture 2-input

Input capture 3-input
Reserved #31 1FH FFFF80H
Reserved #32 20H FFFF7CH
Reserved #33 21H FFFF78H
Reserved #34 22H FFFF74H
Reserved #35 23H FFFF70H

×
× #30 1EH FFFF84H

×
×
×
×
×

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

↓

ICR12 0000BCH

16-bit reload timer 1 #36 24H FFFF6CH Low

(Continued)

21

MB90455 Series

(Continued)

2

OS

Cause of interrupt

EI

readiness

UART1 reception completed #37 25
UART1 transmission completed ∆ #38 26
Reserved #39 27
Reserved #40 28H FFFF5CH
Flash memory #41 29H FFFF58H
Delay interrupt generation

module

×
×
×

×

: Available

×

: Unavailable
: Available El

2

OS function is provided.

∆ : Available when a cause of interrupt sharing a same ICR is not used.

*1: • Peripheral functions sharing an ICR register have the same interrupt level.

• If peripheral functions share an ICR register, only one function is available when using expanded intelligent
I/O service (EI

2

OS) .

• If peripheral functions share an ICR register, a function using expanded intelligent I/O service (EI
not allow interrupt by another function.

*2: Input capture 1 is ready only for EI

2

EI

OS with Input capture 1.

2

OS, and PPG is not ready for EI2OS. Disable PPG interrupt when using

*3: Priority when two or more interrupts of a same level occur simultaneously.

Interrupt vector Interrupt control register

Number Address ICR Address

H FFFF68H

ICR13 0000BDH*

H FFFF64H ↑
H FFFF60H

ICR14 0000BEH

ICR15 0000BFH

#42 2AH FFFF54H

1

2

Priority*

High

↓

Low

OS) does

3

22

MB90455 Series

PERIPHERAL RESOURCES

■■■■

1. I/O Ports

The I/O ports are used as general-pur pose input/output ports (parallel I/O ports). The MB90455 series model
is provided with 5 ports (34 inputs). The ports function as input/output pins for peripheral functions also.

••••

I/O port functions

An I/O port, using port data resister (PDR), outputs the output data to I/O pin and input a signal input to I/O port.
The port direction register (DDR) specifies direction of input/output of I/O pins on a bit-by-bit basis.

The following summarizes functions of the ports and sharing peripheral functions :

• Port 1 : General-purpose input/output port, used also for PPG timer output and input capture inputs.

• Port 2 : General-purpose input/output port, used also for reload timer input/output and external interrupt input.

• Port 3 : General-purpose input/output port, used also for A/D converter activation trigger pin.

• Port 4 : General-purpose input/output port, used also for UART input/output.

• Port 5 : General-purpose input/output port, used also analog input pin.

••••

Port 1 pins block diagram (single-chip mode)

Peripheral

function input

Port data register (PDR)

Internal data bus

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

••••

Port 1 registers (single-chip mode)

• Port 1 registers include port 1 data register (PDR1) and port 1 direction register (DDR1).

• The bits configuring the register correspond to port 1 pins on a one-to-one basis.

PDR read

Output latch

PDR write

Port direction register (DDR)

Direction

latch

DDR write

DDR read

(SPL=1).

Peripheral

function output

Peripheral function

output permission

Pch

Pin

Nch

Standby control (SPL=1)

Relation between port 1 registers and pins

Port name Bits of register and corresponding pins

PDR1, DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

Port 1

Corresponding pins P17 P 16 P15 P14 P13 P12 P11 P10

23

MB90455 Series

••••

Port 2 pins block diagram (general-purpose input/output port)

Peripheral

function input

Port data register (PDR)

Internal data bus

Standby control : Control among Stop mode (SPL=1), Time-base timer mode (SPL=1), and clock mode

••••

Port 2 registers

• Port 2 registers include port 2 data register (PDR2) and port 2 direction register (DDR2).

• The bits configuring the register correspond to port 2 pins on a one-to-one basis.

PDR read

Output latch

PDR write

Port direction register (DDR)

Direction

latch

DDR write

DDR read

(SPL=1).

Peripheral

function output

Peripheral function

output permission

Pch

Pin

Nch

Standby control (SPL=1)

Relation between port 2 registers and pins

Port name Bits of register and corresponding pins

Port 2

PDR2,DDR2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Corresponding pins P27 P26 P25 P24 P23 P22 P21 P20

24