FUJITSU MB90350 DATA SHEET

查询MB90352供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90350 Series
MB90F352/S, MB90352/S

DESCRIPTION

■■■■

The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed f or automotive
and industrial applications. Its main feature is the on-board CAN Interface, which conf orm to V2.0 P art A and Part
B, while supporting a very flexible message buffer scheme and so off ering more functions than a normal full CAN
approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory
up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.

DS07-13737-2E

An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.

The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.

The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free

running timers. 2 channels UART constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F

■■■■

2

MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.

PACKAGE

64-pin Plastic LQFP

(FPT-64P-M09)

MB90350 Series

FEATURES

■■■■

••••

Clock

• Built-in PLL clock frequency multiplication circuit

• Selection of machine clocks (PLL clocks) is allow ed among frequency division by two on oscillation cloc k, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).

• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)

• Minimum ex ecution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multi­plied PLL clock).

• Built-in clock modulation circuit

••••

16 Mbyte CPU memory space

• 24-bit internal addressing

••••

External Bus Interface

• 4 MByte external memory space

••••

Instruction system best suited to controller

• Wide choice of data types (bit, byte, word, and long word)

• Wide choice of addressing modes (23 types)

• Enhanced multiply-divide instructions and RETI instructions

• Enhanced high-precision computing with 32-bit accumulator

••••

Instruction system compatible with high-level language (C language) and multitask

• Employing system stack pointer

• Enhanced various pointer indirect instructions

• Barrel shift instructions

••••

Increased processing speed

• 4-byte instruction queue

••••

Powerful interrupt function

• Powerful 8-level, 34-condition interrupt feature

• Up to 8 channels external interrupts are supported

••••

Automatic data transfer function independent of CPU

• Extended intelligent I/O service function (EI

• DMA : up to 16 channels

••••

Low power consumption (standby) mode

• Sleep mode (a mode that halts CPU operating clock)

• Main timer mode (a timebase timer mode switched from the main clock mode)

• PLL timer mode (a timebase timer mode switched from the PLL clock mode)

• Watch mode (a mode that operates sub clock and clock timer only)

• Stop mode (a mode that stops oscillation clock and sub clock)

• CPU blocking operation mode

••••

Process

•CMOS technology

2

OS) : up to 16 channels

••••

I/O port

• General-purpose input/output port (CMOS output)

- 49 ports (devices without S-suffix)

- 51 ports (devices with S-suffix)

2

(Continued)

MB90350 Series

(Continued)

••••

Timer

• Time-base timer, clock timer, watchdog timer : 1 channel

• 8/16-bit PPG timer : 8-bit × 10 channels, or 16-bit × 6 channels

• 16-bit reload timer : 4 channels

• 16- bit input/output timer

- 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)

- 16- bit input capture: (ICU) : 6 channels

- 16-bit output compare : (OCU) : 4 channels

••••

Full-CAN interface : 1 channel

• Compliant with Ver2.0A and Ver2.0B CAN specifications

• Flexible message buffering (mailbox and FIFO buffering can be mixed)

• CAN wake-up function

••••

UART (LIN/SCI) : 2 channels

• Equipped with full-duplex double buffer

• Clock-asynchronous or clock-synchronous serial transmission is available

2

••••

I

C interface* : 1 channel

• Up to 400 Kbit/s transfer rate

••••

DTP/External interrupt : 8 channels, CAN wakeup : 1 channel

• Module for activation of extended intelligent I/O ser vice (EI

••••

Delay interrupt generator module

2

OS), DMA, and generation of external interrupt.

• Generates interrupt request for task switching.

••••

8/10-bit A/D converter : 15 channels

• Resolution is selectable between 8-bit and 10-bit.

• Activation by external trigger input is allowed.

• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)

••••

Program patch function

• Address matching detection for 6 address pointers.

••••

Internal voltage regulator

• Supports 3 V MCU core, offering low EMI and low power consumption figures

••••

Programmable input levels

• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)

• TTL level (initial level for External bus mode)

••••

Flash security function

• Protects the content of Flash (Flash device only)

2

* : I

C license :
Purchase of Fujitsu I
ponents in an I

2

C components conveys a license under the Philips I2C Patent Rights to use, these com-

2

C system provided that the system conforms to the I2C Standard Specification as defined by

Philips.

3

MB90350 Series

PRODUCT LINEUP

■■■■

Part Number

MB90F352/S, MB90352/S*

1

MB90V340A-101/102

Parameter

CPU F
System clock

ROM

On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)

Boot-block, Flash memory

128 Kbytes

2

MC-16LX CPU

External

RAM 4 Kbytes 30 Kbytes
Emulator-specific

power supply*

2

Technology

Operating
voltage range

0.35 µm CMOS with regulator for internal power supply +
Flash memory charge pump for programming voltage

3.5 V - 5.5 V : at normal operating (not using A/D converter)

4.0 V - 5.5 V : at using A/D converter/Flash programming

4.5 V - 5.5 V : at using external bus

 Yes

0.35 µm CMOS with
regulator for internal
power supply

5 V ± 10%

Temperature range −40 °C to +105 °C (125 °C up to 16 MHz machine clock) 
Package LQFP-64 PGA-299

2 channels 3 channels

UART

Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device

2

I

C (400 kbit/s) 1 channel 1 channel

A/D
Converter

16-bit Reload Timer
(4 channels)

10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)

Operation clock frequency : fsys/2
Supports External Event Count function

15 channels

1

, fsys/23, fsys/25 (fsys = Machine clock frequency)

Signals an interrupt when overflowing

16-bit
I/O Timer
(2 channels)

Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/2

1

, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/2
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7

16-bit Output
Compare
(4 channels)

16-bit Input Capture
(6 channels)

Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.

Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event

7

(Continued)

4

Part Number

Parameter

8/16-bit
Programmable Pulse
Generator
6 channels (16-bit) /
10 channels (8-bit)

CAN Interface

MB90350 Series

MB90F352/S, MB90352/S*

1

Supports 8-bit and 16-bit operation modes
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter
Operation clock freq. : fsys, fsys/2

1

, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)

1 channel 2 channels

Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps

MB90V340A-101/102

External Interrupt
(8 channels)

Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI

2

OS) and DMA
D/A converter  1 channel
Subclock

(up to100 kHz)

devices with ‘S’-suffix and MB90V340A-102 : without subclock
devices without ‘S’-suffix and MB90V340A-101 : with subclock

Virtually all external pins can be used as general purpose I/O port
All push-pull outputs

I/O Ports

Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (30 terminals only for external bus)

Supports automatic programming, Embedded Algorithm

TM*3

Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm

Flash
Memory

Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration



Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash

*1 : The devices are under development.
*2 : It is setting of Jumper switch (TOOL V

CC) when Emulator (MB2147-01) is used.

Please refer to the Emulator hardware manual about details.

*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.

5

MB90350 Series

PIN ASSIGNMENTS

■■■■

• MB90F352/S, MB90352/S

(TOP VIEW)
(LQFP-64P)

P25/A21/IN1/ADTG

P44/SDA0/FRCK0

P45/SCL0/FRCK1

P30/ALE/IN4

P31/RD

/WR/INT10R

P32/WRL

P33/WRH

P34/HRQ/OUT4

P35/HAK
P36/RDY/OUT6

P37/CLK/OUT7

P60/AN0
P61/AN1

Vcc

/IN5

/OUT5

AVcc

VssX0X1

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49
50

C

51
52
53
54
55
56
57
58
59
60
61
62
63
64

AVs s

AVRH

RST

P63/AN3/PPG6(7)

P62/AN2/PPG4(5)

P24/A20/IN0

P23/A19/PPGF(E)

P22/A18/PPGD(C)

P21/A17/PPGB(A)

P64/AN4/PPG8(9)

P67/AN7/PPGE(F)

P65/AN5/PPGA(B)

P66/AN6/PPGC(D)

P20/A16/PPG9(8)

P17/AD15

P16/AD14

P15/AD13

P14/AD12/SCK3

10 11 12 13 14 15 161234567 98

P50/AN8/SIN2

P51/AN9/SOT2

P52/AN10/SCK2

P53/AN11/TIN3

P54/AN12/TOT3

P13/AD11/SOT3

P12/AD10/SIN3/INT11R

P56/AN14

P55/AN13

P11/AD09/TOT1

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

P42/IN6/RX1/INT9 R

P10/AD08/TIN1
P07/AD07/INT15

P06/AD06/INT14
P05/AD05/INT13
P04/AD04/INT12
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
MD0
MD1
MD2
P41/X1A*
P40/X0A*
Vss
P43/IN7/TX1

(FPT-64P-M09)

* : MB90F352/352 : X0A, X1A

MB90F352S/352S : P40, P41

6

PIN DESCRIPTION

■■■■

MB90350 Series

Pin No.

LQFP64*

46 X1
47 X0 Oscillation input pin.
45 RST

3 to 8

9

10

11

12

13

14, 15

16

17

19, 20

Pin name

P62 to P67
AN2 to AN7 Analog input pins for A/D converter.
PPG4, 6, 8,

A, C, E

P50

AN8 Analog input pin for A/D converter.

SIN2 Serial data input pin for UART2.

P51

AN9 Analog input pin for A/D converter.

SOT2 Serial data output pin for UART2.

P52
AN10 Analog input pin for A/D converter.
SCK2 Serial data output pin for UART2.

P53
AN11 Analog input pin for A/D converter.

TIN3 Event input pin for reload timer3.

P54
AN12 Analog input pin for A/D converter.
TOT3 Output pin for reload timer3.

P55, P56

AN13, AN14 Analog input pins for A/D converter.

P42

IN6 Data sample input pin for input capture ICU6.

RX1 RX input pin for CAN1.

INT9R External interrupt request input pin for INT9.

P43

IN7 Data sample input pin for input capture ICU7.

TX1 TX output pin for CAN1.

P40, P41 F

X0A, X1A B

Circuit

type

Oscillation output pin.

A

E Reset input pin.

General purpose I/O ports.

I

Output pins for PPGs.
General purpose I/O port.

O

General purpose I/O port.

I

General purpose I/O port.

I

General purpose I/O port.

I

General purpose I/O port.

I

General purpose I/O ports.

I

General purpose I/O port.

F

General purpose I/O port.

F

General purpose I/O ports
(devices with S-suffix and MB90V340A-101) .

Oscillation input pins for sub clock
(devices without S-suffix and MB90V340A-102) .

Function

(Continued)

7

MB90350 Series

Pin No.

LQFP64*

24 to 31

32

33

34

35

36

37

38

Pin name

P00 to P07

AD00 to AD07
INT8 to INT15 External interrupt request input pins for INT8 to INT15.

P10

AD08

TIN1 Event input pin for reload timer1.

P11

AD09
TOT1 Output pin for reload timer1.

P12

AD10

SIN3 Serial data input pin for UART3.

INT11R External interrupt request input pin for INT11

P13

AD11
SOT3 Serial data output pin for UART3.

P14

AD12
SCK3 Clock input/output pin for UART3.

P15

AD13

P16

AD14

Circuit

type

G

G

G

N

G

G

N

G

Function

General purpose I/O ports.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.

Input/output pins of external address data bus lower 8 bit. This function is
enabled when the external bus is enabled.

General purpose I/O port.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.

General purpose I/O.The register can be set to select whether to use a
pull-up resistor.This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 9. This function is en­abled when external bus is enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 10. This function is
enabled when external bus is enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.

(Continued)

8

MB90350 Series

Pin No.

LQFP64*

39

40 to 43

44

51

52

53

54

Pin name

P17

AD15

P20 to P23

A16 to A19

PPG9, PPGB,

PPGD, PPGF

P24

A20

IN0 Data sample input pin for input capture ICU0.

P25

A21

IN1 Data sample input pin for input capture ICU1.

ADTG Trigger input pin for A/D converter.

P44
SDA0 Serial data I/O pin for I

FRCK0 Input pin for the 16-bit I/O Timer 0

P45
SCL0 Serial clock I/O pin for I

FRCK1 Input for the 16-bit I/O Timer 1

P30

ALE

IN4 Data sample input pin for input capture ICU4.

Circuit

type

G

G

G

G

H

H

G

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.

General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a general­purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.

Output pins for A16 to A19 of the external address bus.
When the corresponding bit in the external address output control register
(HACR) is 0, the pins are enabled as high address output pins A16 to A19.

Output pins for PPGs.
General purpose I/O port. The register can be set to select whether to use

a pull-up resistor. In external bus mode, the pin is enabled as a general­purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.

Output pins for A20 of the external address bus. When the corresponding
bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pins A20.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a general­purpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.

Output pin for A21 of the external address bus. When the corresponding bit
in the external address output control register (HACR) is 0, the pin is en­abled as high address output pin A21.

General purpose I/O port

2

C 0

General purpose I/O port.

2

C 0

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Address latch enable output pin. This function is enabled when external bus
is enabled.

Function

(Continued)

9

MB90350 Series

10

Pin No.

LQFP64*

55

56

57

58

59

60

61

Pin name

P31

RD
IN5 Data sample input pin for input capture ICU5.

P32

WR

/WRL

INT10R External interrupt request input pin for INT10.

P33

WRH

P34

HRQ

OUT4 Waveform output pin for output compare OCU4.

P35

HAK

OUT5 Waveform output pin for output compare OCU5.

P36

RDY

OUT6 Waveform output pin for output compare OCU6.

P37

CLK

OUT7 Waveform output pin for output compare OCU7.

Circuit

type

G

G

G

G

G

G

G

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.

Read strobe output pin for data bus. This function is enabled when external
bus is enabled.

General purpose I/O port. The register can be set to select whether to use
pull-up resistor. This function is enabled either in single-chip mode or with
the WR

Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR
write-strobe 8 lower bits of the data bus in 16-bit access. WR
write-strobe 8 bits of the data bus in 8-bit access.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the WRH

Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.

Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.

Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the external ready function disabled.

Ready input pin. This function is enabled when both the external bus and
the external ready function are enabled.

General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the CLK output disabled.

CLK output pin. This function is enabled when both the external bus and
CLK output are enabled.

/WRL pin output disabled.

pin output disabled.

Function

/WRL pin output are enabled. WRL is used to

output pin is enabled.

is used to

(Continued)

(Continued)

Pin No.

Pin name

LQFP64*

P60, P61

62, 63

Circuit

type

I

Function

General purpose I/O ports.

AN0, AN1 Analog input pins for A/D converter.

64 AV

CC KVCC power input pin for analog circuits.

Reference voltage input for the A/D converter. This power supply must be

2 AVRH L

1AV

SS KVSS power input pin for analog circuits.

turned on or off while a voltage higher than or equal to AVRH is applied to
AV

CC.

22, 23 MD1, MD0 C Input pins for specifying the operating mode.

21 MD2 D Input pins for specifying the operating mode.
49 V

CC  Power (3.5 V to 5.5 V) input pin.

18, 48 VSS  Power (0 V) input pins.

50 C K

This is the power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic capacitor.

MB90350 Series

* : FPT-64P-M09

11

MB90350 Series

I/O CIRCUIT TYPE

■■■■

Type Circuit Remarks

Oscillation circuit

X1

Xout

• High-speed oscillation feedback
resistor = approx. 1 MΩ

A

X0

X1A

Standby control signal

Xout

Oscillation circuit

• Low-speed oscillation feedback
resistor = approx. 10 MΩ

B

X0A

Standby control signal

Mask ROM device:

• CMOS Hysteresis input pin

C

R

Hysteresis
inputs

Flash device:

• CMOS input pin

R

D

Pull-down
Resistor

Hysteresis
inputs

Mask ROM device:

• CMOS Hysteresis input pin

• Pull-down resistor valule: appro x. 50 kΩ

Flash device:

• CMOS input pin

• No Pull-down

12

CMOS Hysteresis input pin

• Pull-up resistor valule: approx. 50 kΩ

E

Pull-up
Resistor

R

Hysteresis
inputs

(Continued)

MB90350 Series

Type Circuit Remarks

• CMOS level output
(I

Pout

Nout

F

R

Hysteresis inputs

Automotive inputs
Standby control for

input shutdown

OL = 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand­by-time input shutdown function)

• Automotive input (With the standb y-time
input shutdown function)

pull-up control

pull-up
resistor

Pout

• CMOS level output
(I

OL = 4 mA, IOH = −4 mA)

• CMOS hysteresis inputs (With the stand­by-time input shutdown function)

• Automotive input (With the standb y-time
input shutdown function)

Nout

G

R

Hysteresis inputs

Automotive inputs

TTL input
Standby control for

input shutdown

• TTL input (With the standby-time input
shutdown function)

• Programmalble pullup resistor: 50 kΩ
approx.

• CMOS level output
(I

Pout

OL = 3 mA, IOH = −3 mA)

• CMOS hysteresis inputs (With the stand­by-time input shutdown function)

Nout

H

R

• Automotive input (With the standb y-time
input shutdown function)

Hysteresis inputs

Automotive inputs
Standby control for

input shutdown

(Continued)

13

MB90350 Series

Type Circuit Remarks

• CMOS level output(I

Pout

Nout

R

I

Hysteresis inputs

Automotive inputs
Standby control for

input shutdown
Analog input

• CMOS hysteresis inputs (With the stand­by-time input shutdown function)

• Automotive input (With the standb y-time
input shutdown function)

• A/D analog input

• Power supply input protection circuit

OL = 4 mA)

K

• A/D converter reference voltage power

ANE

supply input pin, with the protection cir­cuit

L

AVR

ANE

• Flash devices do not have a protection
circuit against V

CC for pin AVRH

(Continued)

14

MB90350 Series

(Continued)

Type Circuit Remarks

pull-up control

pull-up
registor

Pout

Nout

N

R

CMOS inputs

Automotive inputs

TTL input
Standby control for

input shutdown

• CMOS level output
(I

OL = 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time
input shutdown function)

• Automotive input (With the standby-time
input shutdown function)

• TTL input (With the standby-time input
shutdown function)

• Programmable pull-up registor:50 kΩ
approx

• CMOS level output
(I

Pout

OL = 4 mA, IOH = −4 mA)

• CMOS inputs (With the standby-time
input shutdown function)

Nout

R

O

CMOS inputs

Automotive inputs
Standby control for

input shutdown
Analog input

• Automotive input (With the standby-time
input shutdown function)

• A/D analog input

15

MB90350 Series

HANDLING DEVICES

■■■■

Special care is required for the following when handling the device :

• Prev e nting latch-up

• Treatment of unused pins

• Using external clock

• Precautions for when not using a sub clock signal

• Notes on during operation of PLL clock mode

• Power supply pins (V

• Pull-up/down resistors

• Crystal Oscillator Circuit

• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

• Connection of Unused Pins of A/D Converter

• Notes on Energization

• Stabilization of power supply voltage

• Initialization

• Port0 to port3 output during Power-on (External-bus mode)

• Notes on using CAN Function

• Flash security Function

CC/VSS)

1. Preventing latch-up

CMOS IC chips may suffer latch-up under the following conditions

• A voltage higher than V

• A voltage higher than the rated voltage is applied between VCC and VSS.

•The AV
Latch-up may increase the power supply current drastically, causing thermal damage to the device.

For the same reason, also be careful not to let the analog power-supply v oltage (AV
power-supply voltage.

CC power supply is applied before the VCC voltage.

CC or lower than VSS is applied to an input or output pin.

:

CC, A VRH) e xceed the digital

2. Handling unused pins

Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .

Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.

3. Using external clock

To use external clock, drive the X0 pin and leave X1 pin open.

MB90350 Series

X0

Open

X1

4. Precautions for when not using a sub clock signal

If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.

16

MB90350 Series

5. Notes on during operation of PLL clock mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.

6. Power supply pins (VCC/VSS)

• If there are multiple VCC and VSS pins, from the point of view of de vice design, pins to be of the same potential
are connected inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the V
and ground externally.

• Connect VCC and VSS to the device from the current supply source at a low impedance.

• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
V

CC and VSS in the vicinity of VCC and VSS pins of the device

CC and VSS pins to the power supply

Vcc
Vss

Vss

Vcc

Vss

Vcc

MB90350

Series

Vss

Vcc

Vss

Vcc

7. Pull-up/down resistors

The MB90350 Series does not support internal pull-up/down resistors (P ort 0 to Port 3: built-in pull-up resistors).
Use external components where needed.

8. Crystal Oscillator Circuit

Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.

It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.

9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs

Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after
turning-on the digital power supply (V

CC) .

Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AV

CC (turning on/off the analog and digital power supplies simulta-

neously is acceptable).

10. Connection of Unused Pins of A/D Converter if A/D Converter is used

Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.

17

MB90350 Series

11. Notes on Energization

To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)

12. Stabilization of power supply voltage

A sudden change in the supply voltage may cause the de vice to malfunction e ven within the specified VCC supply
voltage operating range. Therefore, the V

CC supply voltage should be stabilized.

For reference, the supply voltage should be controlled so that V
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard V

CC ripple variations (peak-to-peak value) at

CC supply voltage and the coefficient

of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.

13. Initialization

In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
turn on the power again.

14. Port 0 to port 3 output during Power-on (External-bus mode)

As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.

1/2 VCC

VCC

Port0 to Port3

Port0 to Port3 outputs
might be unstable

Port0 to Port3 outputs = Hi-Z

15. Notes on using CAN Function

To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).
If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.
Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.

16. Flash security Function

The security byte is located in the area of the flash memory.
If protection code 01
Therefore please do not write 01
Please refer to following table for the address of the security bit.

MB90F352 Embedded 1 Mbit Flash Memory FE0001

18

H is written in the security bit, the flash memory is in the protected state by security.

H in this address if you do not use the security function.

Flash memory size Address for security bit

H

BLOCK DIAGRAMS

■■■■

• MB90V340A-101/102

X0,X1
X0A,X1A

RST

*

Clock

Controller

MB90350 Series

16LX

CPU

SOT4 to SOT2
SCK4 to SCK2
SIN4 to SIN2

AVCC
AVSS
AN14 to AN0
AVRH

ADTG

DA00

PPGF to PPG8,
PPG6, PPG4,
PPG2, PPG0

SDA0
SCL0

RAM 30 K

Prescaler

3 ch

UART

3 ch

10-bit ADC

15 ch

10-bit

DAC

1 ch

8/16-bit

PPG

12/8 ch

2

C

I

Interface

1 ch

FMC-16 Bus

IO Timer 0

Input

Capture

6 ch

Output

Compare

4 ch

IO Timer 1

CAN

Controller

2 ch

16-bit Reload

Timer 4 ch

External

Bus

Interface

External
Interrupt

FRCK0

IN7 to IN4,

IN1 to IN0

OUT7 to OUT4

FRCK1

RX2 to RX1

TX2 to TX1

TIN3, TIN1

TOT3, TOT1

AD15 to AD00

A21 to A16

ALE

RD

WRL

WRH

HRQ

HAK
RDY

CLK

INT15 to INT8

(INT11R to INT9R)

* : MB90V340A-102

DMAC

19

MB90350 Series

• MB90F352/S, MB90352/S

X0,X1
X0A,X1A*

RST

Clock

Controller

16LX

CPU

SOT3, SOT2
SCK3, SCK2
SIN3, SIN2

AVCC
AVSS
AN14 to AN0

AVRH

ADTG

PPGF to PPG8
PPG6, PPG4

SDA0

SCL0

RAM

4 K

ROM/Flash

128 K

Prescaler

2 ch

UART

2 ch

10-bit ADC

15 ch

8/16-bit

PPG

10/6 ch

2

C

I

Interface

1 ch

FMC-16 Bus

IO Timer 0

Input

Capture

6 ch

Output

Compare

4 ch

IO Timer 1

CAN

Controller

1 ch

16-bit Reload

Timer 4 ch

External

Bus

Interface

External

Interrupt

FRCK0

IN7 to IN4,
IN1, IN0

OUT7 to OUT4

FRCK1

RX1

TX1

TIN3, TIN1

TOT3, TOT1

AD15 to AD00

A21 to A16

ALE

RD

WRL

WRH

HRQ

HAK
RDY

CLK

INT15 to INT8

(INT11R to INT9R)

* : Only for devices without ‘S’ Suffix

20

DMAC

MEMORY MAP

■■■■

MB90350 Series

MB90V340A-101/102

FFFFFF

H

FF0000

FEFFFF

FE0000

FDFFFF

00FFFF

008000

007FFF

007900

0078FF

ROM (FF bank)

H
H

ROM (FE bank)

H
H

H

(image of FF bank)

H
H

H
H

MB90F352/S

MB90352/S

FFFFFF

H

FF0000

FEFFFF

FE0000

FDFFFF

ROM (FF bank)

H
H

ROM (FE bank)

H
H

External access

area

C00100

H

C000FF

H

00FFFF

008000

007FFF

007900

H

H
H

H

ROM

(image of FF bank)

ROM

Peripheral Peripheral

RAM 30 K

001100

H

0010FF

H

RAM 4 K

000100

0000EF

000000

H

External access area

H
H

000100

0000EF

000000

H

H

Peripheral Peripheral

H

: No access

Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C

compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without
using the far specification in the pointer declaration.
For example, an attempt to access 00C000

H accesses the value at FFC000H in ROM.

The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00.
The image between FF8000
FF7FFF

H is visible only in bank FF.

H and FFFFFFH is visible in bank 00, while the image between FF0000H and

21

MB90350 Series

I/O MAP

■■■■

Address Register

00

H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXX

01

H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXX

02

H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXX

Abbrevia-

tion

Access Resource name Initial value

03H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXX
04

H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXX

05

H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXX

06H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXX

07

H to 0AH Reserved

0B

H Analog Input Enable Register 5 ADER5 R/W Port 5, A/D 11111111

0CH Analog Input Enable Register 6 ADER6 R/W Port 6, A/D 11111111
0D

H Reserved

0E

H Input Level Select Register 0 ILSR0 R/W Ports 00000000

0FH Input Level Select Register 1 ILSR1 R/W Ports 00000000
10

H Port 0 Direction Register DDR0 R/W Port 0 00000000

11

H Port 1 Direction Register DDR1 R/W Port 1 00000000

12H Port 2 Direction Register DDR2 R/W Port 2 XX000000
13

H Port 3 Direction Register DDR3 R/W Port 3 00000000

14

H Port 4 Direction Register DDR4 R/W Port 4 XX000000

15

H Port 5 Direction Register DDR5 R/W Port 5 XX000000

16H Port 6 Direction Register DDR6 R/W Port 6 00000000

17

H to 19H Reserved

1A

H SIN input Level Setting Register DDRA W UART2, UART3 X00XXXXX

1BH Reserved
1C

H Port 0 Pull-up Control Register PUCR0 R/W Port 0 00000000

1D

H Port 1 Pull-up Control Register PUCR1 R/W Port 1 00000000

1EH Port 2 Pull-up Control Register PUCR2 R/W Port 2 00000000
1F

H Port 3 Pull-up Control Register PUCR3 R/W Port 3 00000000

20

H to 37H Reserved

38H PPG 4 Operation Mode Control Register PPGC4 W, R/W
39

H PPG 5 Operation Mode Control Register PPGC5 W, R/W 0X000001

3A

H PPG 45 Clock Select Register PPG45 R/W 000000X0

3B

Program Address Detection Control

H

Status Register 1

PACSR1 R/W

16-bit Programable

Pulse Generator 4/5

Address Match

Detection 1

0X000XX1

00000000

(Continued)

22

MB90350 Series

Address Register

3C

H PPG 6 Operation Mode Control Register PPGC6 W, R/W

3D

H PPG 7 Operation Mode Control Register PPGC7 W, R/W 0X000001

3E

H PPG 67 Clock Select Register PPG67 R/W 000000X0

3F

H Reserved

40H PPG 8 Operation Mode Control Register PPGC8 W, R/W
41

H PPG 9 Operation Mode Control Register PPGC9 W, R/W 0X000001

42

H PPG 89 Clock Select Register PPG89 R/W 000000X0

Abbrevia-

tion

Access Resource name Initial value

0X000XX1

16-bit Programable

Pulse Generator 6/7

0X000XX1

16-bit Programable

Pulse Generator 8/9

43H Reserved
44

H PPG A operation mode control register PPGCA W, R/W

45

H PPG B operation mode control register PPGCB W, R/W 0X000001

16-bit Programable

Pulse Generator A/B

0X000XX1

46H PPG AB clock select register PPGAB R/W 000000X0
47

H Reserved

48

H PPG C Operation Mode Control Register PPGCC W,R/W

49H PPG D Operation Mode Control Register PPGCD W,R/W 0X000001
4A

H PPG CD Clock Select Register PPGCD R/W 000000X0

4B

H Reserved

16-bit Programable

Pulse Generator C/D

0X000XX1

4C

H PPG E Operation Mode Control Register PPGCE W,R/W

4DH PPG F Operation Mode Control Register PPGCF W,R/W 0X000001
4E

H PPG EF Clock Select Register PPGEF R/W 000000X0

4F

H Reserved

50H
51

52

H, 53H Reserved

54H
55
56

Input Capture Control Status
Register 0/1

H Input Capture Edge Register 0/1 ICE01 R/W, R XXX0X0XX

Input Capture Control Status
Register 4/5

H Input Capture Edge Register 4/5 ICE45 R XXXXXXXX

Input Capture Control Status

H

Register 6/7

ICS01 R/W

ICS45 R/W

ICS67 R/W

16-bit Programable

Pulse Generator E/F

Input Capture 0/1

Input Capture 4/5

Input Capture 6/7

0X000XX1

00000000

00000000

00000000

57H Input Capture Edge Register 6/7 ICE67 R/W, R XXX000XX

58

H to 5BH Reserved

5C

Output Compare Control Status

H

Register 4

OCS4 R/W

0000XX00

Output Compare 4/5

5D

Output Compare Control Status

H

Register 5

OCS5 R/W 0XX00000

(Continued)

23

MB90350 Series

Address Register

5E

Output Compare Control Status

H

Register 6

Abbrevia-

tion

Access Resource name Initial value

OCS6 R/W

0000XX00

Output Compare 6/7

5F
60

61
62H Timer Control Status Register 1 TMCSR1 R/W
63
64
65H Timer Control Status Register 2 TMCSR2 R/W XXXX0000
66
67
68H A/D Control Status Register 0 ADCS0 R/W
69
6A

Output Compare Control Status

H

Register 7

H Timer Control Status Register 0 TMCSR0 R/W
H Timer Control Status Register 0 TMCSR0 R/W XXXX0000

H Timer Control Status Register 1 TMCSR1 R/W XXXX0000
H Timer Control Status Register 2 TMCSR2 R/W

OCS7 R/W 0XX00000

16-bit Reload Timer

00000000

0

16-bit Reload Timer

00000000

1

16-bit Reload Timer

00000000

2

H Timer Control Status Register 3 TMCSR3 R/W
H Timer Control Status Register 3 TMCSR3 R/W XXXX0000

16-bit Reload Timer

3

00000000

000XXXX0

H A/D Control Status Register 1 ADCS1 R/W 0000000X

H Data Register 0 ADCR0 R 00000000

A/D Converter

6BH Data Register 1 ADCR1 R XXXXXX00
6C

H A/D Setting Register 0 ADSR0 R/W 00000000

6D

H A/D Setting Register 1 ADSR1 R/W 00000000

6E

H Reserved

6FH ROM Mirroring Register ROMM W ROM Mirror XXXXXXX1

70

H to 7FH Reserved

80

H to 8FH Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

90H to 9AH Reserved

9B
9C

DMA Descriptor Channel Specification

H

Register

H DMA Status Register L DSRL R/W 00000000

DCSR R/W

00000000

DMA
9DH DMA Status Register H DSRH R/W 00000000
9E
9F

Program Address Detection Control

H

Status Register 0

H Delayed Interrupt/Release DIRR R/W Delayed Interrupt 00000000

PACSR0 R/W

A0H Low-power Mode Control Register LPMCR W,R/W

A1

H Clock Selection Register CKSCR R,R/W

A2

H, A3H Reserved

Address Match

Detection 0

Low Power Control

Circuit

Low Power Control

Circuit

00000000

00011000

11111100

24

A4

H DMA Stop Status Register DSSR R/W DMA 00000000

(Continued)

MB90350 Series

Address Register

A5
A6

A7
A8

Automatic Ready Function Selection

H

Register

H External Address Output Control Register HACR W 00000000
H Bus Control Signal Selection Register ECSR W 0000000X
H Watchdog Timer Control Register WDTC R,W Watchdog Timer XXXXX111

Abbrevia-

tion

ARSR W

Access Resource name Initial value

0011XX00

External Memory

Access

A9H Timebase Timer Control Register TBTC W,R/W Time base timer 1XX00100
AA

H Watch Timer Control Register WTC R,R/W Watch timer 1X001000

AB

H Reserved

ACH DMA Enable Register L DERL R/W

00000000

DMA

AD

H DMA Enable Register H DERH R/W 00000000

Flash Control Status Register

AE

(Flash Devices only. Otherwise

H

FMCS R,R/W Flash Memory 000X0000

reserved)

AF

H Reserved

B0

H Interrupt Control Register 00 ICR00 W,R/W

B1

H Interrupt Control Register 01 ICR01 W,R/W 00000111

00000111

B2H Interrupt Control Register 02 ICR02 W,R/W 00000111
B3

H Interrupt Control Register 03 ICR03 W,R/W 00000111

B4

H Interrupt Control Register 04 ICR04 W,R/W 00000111

B5

H Interrupt Control Register 05 ICR05 W,R/W 00000111

B6H Interrupt Control Register 06 ICR06 W,R/W 00000111
B7

H Interrupt Control Register 07 ICR07 W,R/W 00000111

Interrupt Control

B8

H Interrupt Control Register 08 ICR08 W,R/W 00000111

B9H Interrupt Control Register 09 ICR09 W,R/W 00000111

BA

H Interrupt Control Register 10 ICR10 W,R/W 00000111

BB

H Interrupt Control Register 11 ICR11 W,R/W 00000111

BCH Interrupt Control Register 12 ICR12 W,R/W 00000111
BD

H Interrupt Control Register 13 ICR13 W,R/W 00000111

BE

H Interrupt Control Register 14 ICR14 W,R/W 00000111

BFH Interrupt Control Register 15 ICR15 W,R/W 00000111

C0

H to C9H Reserved

(Continued)

25

MB90350 Series

Address Register

CA
CB

CC
CD

CEH
CF

D0

External Interrupt Request Enable

H

Register 1

H External Interrupt Request Register 1 EIRR1 R/W XXXXXXXX
H External Interrupt Level Register 1 ELVR1 R/W 00000000
H External Interrupt Level Register 1 ELVR1 R/W 00000000

External Interrupt Source Select
Register

H PLL/Subclock Control register PSCCR W PLL XXXX0000
H DMA Buffer Address Pointer L BAPL R/W

Abbrevia-

tion

ENIR1 R/W

Access Resource name Initial value

00000000

External Interrupt 1

EISSR R/W 00000000

XXXXXXXX
D1H DMA Buffer Address Pointer M BAPM R/W XXXXXXXX
D2

H DMA Buffer Address Pointer H BAPH R/W XXXXXXXX

D3

H DMA Control Register DMACS R/W XXXXXXXX

DMA

D4H I/O Register Address Pointer L IOAL R/W XXXXXXXX
D5

H I/O Register Address Pointer H IOAH R/W XXXXXXXX

D6

H Data Counter L DCTL R/W XXXXXXXX

D7H Data Counter H DCTH R/W XXXXXXXX
D8

H Serial Mode Register 2 SMR2 W,R/W

D9

H Serial Control Register 2 SCR2 W,R/W 00000000

DA

Reception/Transmission Data Register 2RDR2/

H

TDR2

R/W 00000000

00000000

DBH Serial Status Register 2 SSR2 R,R/W 00001000

UART2

DC
DD

Extended Communication Control

H

Register 2

H Extended Status/Control Register 2 ESCR2 R/W 00000100

ECCR2

R,W,

R/W

000000XX

DEH Baud Rate Reload Register 20 BGR20 R/W 00000000
DF

H Baud Rate Reload Register 21 BGR21 R/W 00000000

E0

H to EFH Reserved

F0H to FFH External

7900

7907

H to

H

Reserved

(Continued)

26

MB90350 Series

Address Register

7908

H Reload Register L4 PRLL4 R/W

7909

H Reload Register H4 PRLH4 R/W XXXXXXXX

Abbrevia-

tion

Access Resource name Initial value

XXXXXXXX

16-bit Programable

Pulse

790A

H Reload Register L5 PRLL5 R/W XXXXXXXX

790B

H Reload Register H5 PRLH5 R/W XXXXXXXX

790CH Reload Register L6 PRLL6 R/W
790D

H Reload Register H6 PRLH6 R/W XXXXXXXX

Generator 4/5

XXXXXXXX

16-bit Programable

Pulse

790E

H Reload Register L7 PRLL7 R/W XXXXXXXX

Generator 6/7

790FH Reload Register H7 PRLH7 R/W XXXXXXXX
7910

H Reload Register L8 PRLL8 R/W

7911

H Reload Register H8 PRLH8 R/W XXXXXXXX

16-bit Programable

XXXXXXXX

Pulse

7912H Reload Register L9 PRLL9 R/W XXXXXXXX
7913

H Reload Register H9 PRLH9 R/W XXXXXXXX

7914

H Reload Register LA PRLLA R/W

7915H Reload Register HA PRLHA R/W XXXXXXXX

Generator 8/9

XXXXXXXX

16-bit Programable

Pulse

7916

H Reload Register LB PRLLB R/W XXXXXXXX

7917

H Reload Register HB PRLHB R/W XXXXXXXX

Generator A/B

7918

H Reload Register LC PRLLC R/W

7919H Reload Register HC PRLHC R/W XXXXXXXX

16-bit Programable

XXXXXXXX

Pulse

791A

H Reload Register LD PRLLD R/W XXXXXXXX

791B

H Reload Register HD PRLHD R/W XXXXXXXX

791CH Reload Register LE PRLLE R/W
791D

H Reload Register HE PRLHE R/W XXXXXXXX

Generator C/D

XXXXXXXX

16-bit Programable

Pulse

791E

H Reload Register LF PRLLF R/W XXXXXXXX

Generator E/F

791FH Reload Register HF PRLHF R/W XXXXXXXX
7920

H Input Capture Data Register 0 IPCP0 R

7921

H Input Capture Data Register 0 IPCP0 R XXXXXXXX

XXXXXXXX

Input Capture 0/1

7922H Input Capture Data Register 1 IPCP1 R XXXXXXXX
7923

H Input Capture Data Register 1 IPCP1 R XXXXXXXX

7924

H to

7927

H

7928H Input Capture Data Register 4 IPCP4 R
7929

H Input Capture Data Register 4 IPCP4 R XXXXXXXX

Reserved

XXXXXXXX

Input Capture 4/5

792A

H Input Capture Data Register 5 IPCP5 R XXXXXXXX

792B

H Input Capture Data Register 5 IPCP5 R XXXXXXXX

(Continued)

27

MB90350 Series

Address Register

792C

H Input Capture Data Register 6 IPCP6 R

792D

H Input Capture Data Register 6 IPCP6 R XXXXXXXX

Abbrevia-

tion

Access Resource name Initial value

Input Capture 6/7

H Input Capture Data Register 7 IPCP7 R XXXXXXXX

792E

H Input Capture Data Register 7 IPCP7 R XXXXXXXX

792F

7930

H to

7937

H

H Output Compare Register 4 OCCP4 R/W

7938

H Output Compare Register 4 OCCP4 R/W XXXXXXXX

7939

Reserved

Output Compare 4/5

793A

H Output Compare Register 5 OCCP5 R/W XXXXXXXX
H Output Compare Register 5 OCCP5 R/W XXXXXXXX

793B

H Output Compare Register 6 OCCP6 R/W

793C
793D

H Output Compare Register 6 OCCP6 R/W XXXXXXXX

Output Compare 6/7

H Output Compare Register 7 OCCP7 R/W XXXXXXXX

793E
793F

H Output Compare Register 7 OCCP7 R/W XXXXXXXX
H Data Register 0 TCDT0 R/W

7940
7941

H Data Register 0 TCDT0 R/W 00000000

I/O Timer 0

H Control status Register 0 TCCSL0 R/W 00000000

7942

H Control status Register 0 TCCSH0 R/W 0XXXXXXX

7943

H Data Register 1 TCDT1 R/W

7944
7945

H Data Register 1 TCDT1 R/W 00000000

I/O Timer 1

H Control status Register 1 TCCSL1 R/W 00000000

7946

H Control status Register 1 TCCSH1 R/W 0XXXXXXX

7947

H

7948

Timer Register 0/Reload Register 0

H R/W XXXXXXXX

7949

794A

H

Timer Register 1/Reload Register 1

H R/W XXXXXXXX

794B

H

794C

Timer Register 2/Reload Register 2

H R/W XXXXXXXX

794D

H

794E

Timer Register 3/Reload Register 3

H R/W XXXXXXXX

794F

TMR0/

TMRLR0

TMR1/

TMRLR1

TMR2/

TMRLR2

TMR3/

TMRLR3

R/W

R/W

R/W

R/W

16-bit Reload

Timer 0

16-bit Reload

Timer 1

16-bit Reload

Timer 2

16-bit Reload

Timer 3

XXXXXXXX

XXXXXXXX

XXXXXXXX

00000000

00000000

XXXXXXXX

XXXXXXXX

XXXXXXXX

XXXXXXXX

(Continued)

28

MB90350 Series

Address Register

7950

H Serial Mode Register 3 SMR3 W, R/W

7951

H Serial Control Register 3 SCR3 W, R/W 00000000

Reception/Transmission Data Register 3RDR3/

H

7952

H Serial Status Register 3 SSR3 R,R/W 00001000

7953

Abbrevia-

tion

TDR3

Access Resource name Initial value

R/W 00000000

UART3

7954
7955

7956
7957

7958

796D
796E
796F

7970
7971
7972

ister 3

H Extended Status/Control Register 3 ESCR3 R/W 00000100
H Baud Rate Reload Register 30 BGR30 R/W 00000000
H Baud Rate Reload Register 31 BGR31 R/W 00000000

H to

H

H CAN Direct Mode Register CDMR R/W CAN clock sync XXXXXXX0
H Reserved

2

H I

C Bus Status Register 0 IBSR0 R

2

H I

C Bus Control Register 0 IBCR0 W,R/W 00000000

H

Extended Communication Control Reg-

H

ECCR3

Reserved

ITBAL0 R/W 00000000

R,W,

R/W

I2C 10 bit Slave Address Register 0

H ITBAH0 R/W 00000000

7973

2

I

H

7974
7975
7976
7977
7978

7979

797A
797B

797C

79C1
79C2

79C3

79DF

I2C 10 bit Slave Address Mask Register
0

H ITMKH0 R/W 00111111

2

H I

C 7 bit Slave Address Register 0 ISBA0 R/W 00000000

2

H I

C 7 bit Slave Address Mask Register 0 ISMK0 R/W 01111111

2

H I

C data register 0 IDAR0 R/W 00000000

H,

H

2

H I

C Clock Control Register 0 ICCR0 R/W I2C Interface 0 00011111

H to

H

H Clock Modulator Control Register CMCR R,R/W Clock Modulator 0001X000

H to

H

ITMKL0 R/W 11111111

Reserved

Reserved

Reserved

C Interface 0

00000000

000000XX

00000000

(Continued)

29

MB90350 Series

(Continued)

Address Register

79E0

H Program Address Detection Register 0 PADR0 R/W

79E1

H Program Address Detection Register 0 PADR0 R/W XXXXXXXX
H Program Address Detection Register 0 PADR0 R/W XXXXXXXX

79E2

H Program Address Detection Register 1 PADR1 R/W XXXXXXXX

79E3
79E4

H Program Address Detection Register 1 PADR1 R/W XXXXXXXX
H Program Address Detection Register 1 PADR1 R/W XXXXXXXX

79E5
79E6

H Program Address Detection Register 2 PADR2 R/W XXXXXXXX
H Program Address Detection Register 2 PADR2 R/W XXXXXXXX

79E7
79E8

H Program Address Detection Register 2 PADR2 R/W XXXXXXXX

H to

79E9

79EF

H

H Program Address Detection Register 3 PADR3 R/W

79F0

H Program Address Detection Register 3 PADR3 R/W XXXXXXXX

79F1
79F2

H Program Address Detection Register 3 PADR3 R/W XXXXXXXX
H Program Address Detection Register 4 PADR4 R/W XXXXXXXX

79F3
79F4

H Program Address Detection Register 4 PADR4 R/W XXXXXXXX
H Program Address Detection Register 4 PADR4 R/W XXXXXXXX

79F5

H Program Address Detection Register 5 PADR5 R/W XXXXXXXX

79F6

H Program Address Detection Register 5 PADR5 R/W XXXXXXXX

79F7
79F8

H Program Address Detection Register 5 PADR5 R/W XXXXXXXX

H to

79F9

7BFF

H

H to

7C00

7CFF

7D00

7DFF

7E00

7FFF

H

H to

H

H to

H

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Reserved for CAN Interface 1. Refer to “■ CAN CONTROLLERS”

Abbrevia-

tion

Reserved

Reserved

Reserved

Access Resource name Initial value

XXXXXXXX

Address Match

Detection 0

XXXXXXXX

Address Match

Detection 1

Notes : • Initial value of “X” represents unknown value.

• Addresses in the range 0000

H to 00BFH, which are not listed in the table, are reserved for the primary

functions of the MCU. A read access to these reserved addresses results reading “X” and any write
access should not be performed.

30

MB90350 Series

CAN CONTROLLERS

■■■■

The CAN controller has the following features :

• Conforms to CAN Specification Version 2.0 Part A and B

• Supports transmission/reception in standard frame and extended frame formats

• Supports transmitting of data frames by receiving remote frames

• 16 transmitting/receiving message buffers

• 29-bit ID and 8-byte data

• Multi-level message buffer configuration

• Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as ID acceptance mask

• Two acceptance mask registers in either standard frame format or extended frame formats

• Bit rate programmable from 10 Kbits/s to 2 Mbits/s (when input clock is at 16 MHz)

List of Control Registers (1)

Address

CAN1

000080
000081
000082H
000083
000084H
000085
000086H
000087
000088H
000089
00008AH

00008B
00008CH
00008D

00008EH

00008F

Register Abbreviation Access Initial Value

H

Message buffer enable register BVALR R/W

H

Transmit request register TREQR R/W

H

Transmit cancel register TCANR W

H

Transmission complete register TCR R/W

H

Receive complete register RCR R/W

H

Remote request receiving register RRTRR R/W

H

Receive overrun register ROVRR R/W

H

Reception interrupt

H

enable register

RIER R/W

00000000
00000000

00000000
00000000

00000000
00000000

00000000
00000000

00000000
00000000

00000000
00000000

00000000
00000000

00000000
00000000

31

MB90350 Series

List of Control Registers (2)

Address

CAN1

007D00
007D01
007D02H
007D03
007D04H
007D05
007D06H
007D07
007D08H

007D09
007D0AH
007D0B
007D0CH
007D0D
007D0EH
007D0F

Register Abbreviation Access Initial Value

H

Control status register CSR

H

Last event indicator register LEIR R/W

H

Receive/transmit error counter RTEC R

H

Bit timing register BTR R/W

H

IDE register IDER R/W

H

Transmit RTR register TRTRR R/W

H

Remote frame receive waiting

H

register

Transmit interrupt

H

enable register

RFWTR R/W

TIER R/W

R/W, W

R/W, R

0XXXX0X1

00XXX000

000X0000

XXXXXXXX

00000000
00000000

11111111
X1111111

XXXXXXXX
XXXXXXXX

00000000
00000000

XXXXXXXX
XXXXXXXX

00000000
00000000

007D10H

007D11

007D12H

007D13

007D14H

007D15

007D16H

007D17

007D18H

007D19
007D1AH
007D1B

XXXXXXXX

H

H

Acceptance mask

select register

AMSR R/W

XXXXXXXX
XXXXXXXX

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

Acceptance mask register 0 AMR0 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

Acceptance mask register 1 AMR1 R/W

XXXXXXXX

H

XXXXXXXX

32

MB90350 Series

Address

CAN1

007C00

to

007C1F

007C20H

007C21

007C22H

007C23

007C24H

007C25

007C26H

007C27

007C28H

007C29
007C2AH
007C2B
007C2CH
007C2D
007C2EH
007C2F

007C30H

007C31

007C32H

007C33

List of Message Buffers (ID Registers) (1)

Register Abbreviation Access Initial Value

H

General-purpose RAM  R/W

H

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 0 IDR0 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 1 IDR1 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 2 IDR2 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 3 IDR3 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 4 IDR4 R/W

XXXXXXXX

H

XXXXXXXX

007C34H

007C35

007C36H

007C37

007C38H

007C39
007C3AH
007C3B
007C3CH
007C3D
007C3EH
007C3F

XXXXXXXX

H

XXXXXXXX

ID register 5 IDR5 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 6 IDR6 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 7 IDR7 R/W

XXXXXXXX

H

XXXXXXXX

33

MB90350 Series

List of Message Buffers (ID Registers) (2)

Address

CAN1

007C40

007C41

007C42H

007C43

007C44H

007C45

007C46H

007C47

007C48H

007C49
007C4AH
007C4B
007C4CH
007C4D
007C4EH
007C4F

Register Abbreviation Access Initial Value

H

H

XXXXXXXX
XXXXXXXX

ID register 8 IDR8 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 9 IDR9 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 10 IDR10 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 11 IDR11 R/W

XXXXXXXX

H

XXXXXXXX

007C50H

007C51

007C52H

007C53

007C54H

007C55

007C56H

007C57

007C58H

007C59
007C5AH
007C5B
007C5CH
007C5D
007C5EH
007C5F

XXXXXXXX

H

XXXXXXXX

ID register 12 IDR12 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 13 IDR13 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 14 IDR14 R/W

XXXXXXXX

H

XXXXXXXX
XXXXXXXX

H

XXXXXXXX

ID register 15 IDR15 R/W

XXXXXXXX

H

XXXXXXXX

34

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (1)

Address

CAN1

007C60

007C61

007C62H

007C63

007C64H

007C65

007C66H

007C67

007C68H

007C69
007C6AH
007C6B
007C6CH
007C6D
007C6EH
007C6F

Register Abbreviation Access Initial Value

H

DLC register 0 DLCR0 R/W XXXXXXXX

H

DLC register 1 DLCR1 R/W XXXXXXXX

H

DLC register 2 DLCR2 R/W XXXXXXXX

H

DLC register 3 DLCR3 R/W XXXXXXXX

H

DLC register 4 DLCR4 R/W XXXXXXXX

H

DLC register 5 DLCR5 R/W XXXXXXXX

H

DLC register 6 DLCR6 R/W XXXXXXXX

H

DLC register 7 DLCR7 R/W XXXXXXXX

H

007C70H

007C71

007C72H

007C73

007C74H

007C75

007C76H

007C77

007C78H

007C79
007C7AH
007C7B
007C7CH
007C7D
007C7EH
007C7F

H

DLC register 8 DLCR8 R/W XXXXXXXX

DLC register 9 DLCR9 R/W XXXXXXXX

H

DLC register 10 DLCR10 R/W XXXXXXXX

H

DLC register 11 DLCR11 R/W XXXXXXXX

H

DLC register 12 DLCR12 R/W XXXXXXXX

H

DLC register 13 DLCR13 R/W XXXXXXXX

H

DLC register 14 DLCR14 R/W XXXXXXXX

H

DLC register 15 DLCR15 R/W XXXXXXXX

H

35

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (2)

Address

CAN1

007C80

to

007C87
007C88

to

007C8F
007C90

to

007C97
007C98

to

007C9F

007CA0

to

007CA7
007CA8

to

007CAF
007CB0

to

007CB7

Register Abbreviation Access Initial Value

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Data register 0

(8 bytes)

Data register 1

(8 bytes)

Data register 2

(8 bytes)

Data register 3

(8 bytes)

Data register 4

(8 bytes)

Data register 5

(8 bytes)

Data register 6

(8 bytes)

DTR0 R/W

DTR1 R/W

DTR2 R/W

DTR3 R/W

DTR4 R/W

DTR5 R/W

DTR6 R/W

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX

007CB8

to

007CBF
007CC0

to

007CC7
007CC8

to

007CCF
007CD0

to

007CD7
007CD8

to

007CDF
007CE0

to

007CE7
007CE8

to

007CEF

H

H

H

H

H

H

H

H

H

H

H

H

H

H

Data register 7

(8 bytes)

Data register 8

(8 bytes)

Data register 9

(8 bytes)

Data register 10

(8 bytes)

Data register 11

(8 bytes)

Data register 12

(8 bytes)

Data register 13

(8 bytes)

DTR7 R/W

DTR8 R/W

DTR9 R/W

DTR10 R/W

DTR11 R/W

DTR12 R/W

DTR13 R/W

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX

36

MB90350 Series

List of Message Buffers (DLC Registers and Data Registers) (3)

Address

CAN1

007CF0

to

007CF7
007CF8

to

007CFF

Register Abbreviation Access Initial Value

H

H

H

H

Data register 14

(8 bytes)

Data register 15

(8 bytes)

DTR14 R/W

DTR15 R/W

XXXXXXXX

to

XXXXXXXX
XXXXXXXX

to

XXXXXXXX

37

MB90350 Series

INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER

■■■■

Interrupt control

register

Interrupt cause

2

EI

clear

OS

DMA ch
number

Interrupt vector

Number Address Number Address

Reset N  #08 FFFFDC
INT9 instruction N  #09 FFFFD8

H 

H 

Exception N  #10 FFFFD4H 
Reserved N  #11 FFFFD0

H

ICR00 0000B0H

Reserved N  #12 FFFFCCH
CAN 1 RX / Input Capture 6 Y1  #13 FFFFC8H

ICR01 0000B1H

CAN 1 TX/NS / Input Capture 7 Y1  #14 FFFFC4H
I2CN #15 FFFFC0H

ICR02 0000B2H

Reserved N  #16 FFFFBCH
16-bit Reload Timer 0 Y1 0 #17 FFFFB8H

ICR03 0000B3H

16-bit Reload Timer 1 Y1 1 #18 FFFFB4H
16-bit Reload Timer 2 Y1 2 #19 FFFFB0H

ICR04 0000B4H

16-bit Reload Timer 3 Y1  #20 FFFFACH
PPG 4/5 N  #21 FFFFA8H

ICR05 0000B5H

PPG 6/7 N  #22 FFFFA4H
PPG 8/9/C/D N  #23 FFFFA0H
PPG A/B/E/F N  #24 FFFF9CH
Time Base Timer N  #25 FFFF98H
External Interrupt 8 to 11 Y1 3 #26 FFFF94H
Watch Timer N  #27 FFFF90H
External Interrupt 12 to 15 Y1 4 #28 FFFF8CH
A/D Converter Y1 5 #29 FFFF88H
I/O Timer 0 / I/O Timer 1 N  #30 FFFF84H
Input Capture 4/5 Y1 6 #31 FFFF80H
Output Compare 4/5 Y1 7 #32 FFFF7CH
Input Capture 0/1 Y1 8 #33 FFFF78H
Output Compare 6/7 Y1 9 #34 FFFF74H
Reserved N 10 #35 FFFF70H
Reserved N 11 #36 FFFF6CH
UART 3 RX Y2 12 #37 FFFF68H
UART 3 TX Y1 13 #38 FFFF64H

ICR06 0000B6H

ICR07 0000B7H

ICR08 0000B8H

ICR09 0000B9H

ICR10 0000BAH

ICR11 0000BBH

ICR12 0000BCH

ICR13 0000BDH

(Continued)

38

(Continued)

Interrupt cause

2

EI

clear

OS

DMA ch
number

MB90350 Series

Interrupt vector

Number Address Number Address

Interrupt control

register

UART 2 RX Y2 14 #39 FFFF60

H

UART 2 TX Y1 15 #40 FFFF5CH
Flash Memory N  #41 FFFF58H
Delayed interrupt N  #42 FFFF54H

Y1 : Usable

2

Y2 : Usable, with EI

OS stop function

N : Unusable

Notes : • The peripheral resources sharing the ICR register have the same interrupt level.

• When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service
at a time.

• When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O
Service, the other one cannot use interrupts.

ICR14 0000BEH

ICR15 0000BFH

39

MB90350 Series

ELECTRICAL CHARACTERISTICS

■■■■

1. Absolute Maximum Ratings

Parameter Symbol

V

CC VSS − 0.3 VSS + 6.0 V

Power supply voltage

AV

CC VSS − 0.3 VSS + 6.0 V VCC = AVCC*

AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*
Input voltage VI VSS − 0.3 VSS + 6.0 V *2
Output voltage V

O VSS − 0.3 VSS + 6.0 V *2

Maximum Clamp Current ICLAMP −4.0 +4.0 mA *4
Total Maximum Clamp Current Σ|ICLAMP|  40 mA *4
“L” level maximum output current I

OL  15 mA *3

“L” level average output current IOLAV  4mA*3
“L” level maximum overall output current ΣIOL  100 mA *3
“L” level average overall output current ΣI

OLAV  50 mA *3

“H” level maximum output current IOH −15 mA *3
“H” level average output current IOHAV −4mA*3
“H” level maximum overall output current ΣI

OH −100 mA *3

“H” level average overall output current ΣIOHAV −50 mA *3

Power consumption P

Operating temperature T
Storage temperature T

D

A

STG −55 +150 °C

Rating

Unit Remarks

Min Max

+105 °C < T

 240 mW

Normal operation : maximum
frequency 16 MHz

−40 °C < T

 320 mW

Normal operation : maximum
frequency 24 MHz

−40 +105 °C

−40 +125 °C*5

(VSS = AVSS = 0 V)

1

1

A ≤ +125 °C,

A ≤ +105 °C,

(Continued)

40

MB90350 Series

(Continued)

*1:Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the

analog inputs does not exceed AV

*2:V

I and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximun

current to/from an input is limited by some means with external components, the I

rating.
*3:Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45, P50 to P56, P60 to P67
*4: • Applicable to pins: P00 to P07, P10 to P17, P20 to P25, P30 to P37, P40 to P45,

P50 to P56 (for evaluation : P50 to P55) , P60 to P67

• Use within recommended operating conditions.

• Use at DC voltage (current)

• The +B signal should always be applied a limiting resistance placed between the +B signal and the

microcontroller.

• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.

• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the V
other devices.

• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.

• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting
supply voltage may not be sufficient to operate the power-on reset.

• Care must be taken not to leave the +B input pin open.

• Sample recommended circuits:

CC when the power is switched on.

CLAMP rating supercedes the VI

CC pin, and this may affect

• Input/output equivalent circuits

Protective diode

VCC

B input (0 V to 16 V)

+

*5 : If used exceeding T

Limiting

resistance

R

A = +105 °C, be sure to contact Fujitsu for reliability limitations.

P-ch

N-ch

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

41

MB90350 Series

2. Recommended Conditions

Parameter Symbol

CC,

Power supply voltage

Smooth capacitor C

Operating temperature T

V

AV

CC

S 0.1  1.0 µF

A

(VSS = AVSS = 0 V)

Value

Min Typ Max

Unit Remarks

4.0 5.0 5.5 V Under normal operation

3.5 5.0 5.5 V

Under normal operation, when not using the
A/D converter and not Flash programming.

4.5 5.0 5.5 V When External bus is used.

3.0  5.5 V Maintains RAM data in stop mode
Use a ceramic capacitor or capacitor of bet-

ter AC characteristics. Capacitor at the VCC
should be greater than this capacitor.

−40 +105 °C

−40 +125 °C*

* : If used exceeding T

A = +105 °C, be sure to contact Fujitsu for reliability limitations.

C

C

S

C Pin Connection Diagram

Operation guaranteed range

24

(MHz)

16

CP

Internal clock f

− 40 105 125
Operation temperature T

A

(°C)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.

42

3. DC Characteristics

Parameter

Input H
voltage
(At V

CC =

5 V ± 10%)

Input L
voltage

CC =

(At V
5 V ± 10%)

Output H
voltage

Output H
voltage

Output L
voltage

Output L
voltage

Sym-

bol

IHS 0.8 VCC  VCC + 0.3 V

V

IHA 0.8 VCC  VCC + 0.3 V

V

V

IHT 2.0  VCC + 0.3 V

IHS 0.7 VCC  VCC + 0.3 V

V

IHI 0.7 VCC  VCC + 0.3 V

V

V

IHR 0.8 VCC  VCC + 0.3 V

V

IHM VCC − 0.3  VCC + 0.3 V MD input pin

ILS VSS − 0.3  0.2 VCC V

V

ILA VSS − 0.3  0.5 VCC V

V

V

ILT VSS − 0.3  0.8 V

ILS VSS − 0.3  0.3 VCC V

V

ILI VSS − 0.3  0.3 VCC V

V

V

ILR VSS − 0.3  0.2 VCC V

V

ILM VSS − 0.3  VSS + 0.3 V MD input pin

Normal

OH

V

outputs
I2C current

OHI

V

outputs
Normal

OL

V

outputs
I2C current

OLI

V

outputs

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Pin Condition

VCC = 4.5 V,
I

OH = −4.0 mA

VCC = 4.5 V,
I

OH = −3.0 mA

VCC = 4.5 V,
IOL = 4.0 mA

VCC = 4.5 V,
IOL = 3.0 mA

MB90350 Series

Value

Min Typ Max

CC − 0.5 V

V

CC − 0.5 V

V

0.4 V

0.4 V

Unit Remarks

Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P15, P44, P45,
P50)

Port inputs if
AUTOMOTIVE input
levels are selected

Port inputs if TTL input
levels are selected

P12, P15, P50 inputs if
CMOS input levels are
selected

P44, P45 inputs if
CMOS hysteresis input
levels are selected

RST

input pin (CMOS

hysteresis)

Port inputs if CMOS
hysteresis input levels
are selected (except
P12, P15, P44, P45,
P50)

Port inputs if
AUTOMOTIVE input
levels are selected

Port inputs if TTL
input levels are selected

P12, P15, P50 inputs if
CMOS input levels are
selected

P44, P45 inputs if
CMOS hysteresis input
levels are selected

RST

input pin (CMOS

hysteresis)

(Continued)

43

MB90350 Series

(Continued)

Parameter

Input leak current I

Pull-up
resistance

Pull-down
resistance

Power supply
current*

Input capacity C

Sym-

bol

IL  VCC = 5.5 V, VSS < VI < VCC −1  1 µA

P00 to P07,
P10 to P17,

R

UP

P20 to P25,
P30 to P37,

RST

R

DOWN MD2  25 50 100 kΩ

I

CC

I

CCS

I

CTS

CTSPLL6

I

CCL

I

CCLS

I

CCT

I

CCH

I

Other than C, AVCC, AVSS,

IN

AVRH, VCC, VSS,

(TA = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(T

A = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Pin Condition

Value

Min Typ Max

Unit Remarks

 25 50 100 kΩ

Except
Flash
devices

VCC = 5.0 V,
Internal frequency : 24 MHz,

 50 65 mA MB90F352

At normal operation.
V

CC = 5.0 V,

Internal frequency : 24 MHz,

 65 80 mA MB90F352

At writing FLASH memory.
V

CC = 5.0 V,

Internal frequency : 24 MHz,

 70 85 mA MB90F352

At erasing FLASH memory.
VCC = 5.0 V,

Internal frequency : 24 MHz,

 25 35 mA MB90F352

At Sleep mode.
VCC = 5.0 V,

Internal frequency : 2 MHz,

 0.3 0.8 mA MB90F352

At Main Timer mode
VCC = 5.0 V,

VCC

Internal frequency : 24 MHz,
At PLL Timer mode,

 4 7 mA MB90F352

external frequency = 4 MHz
VCC = 5.0 V,

Internal frequency: 8 kHz,
At sub operation
T

A = +25°C

 170 360 µA MB90F352

VCC = 5.0 V,
Internal frequency: 8 kHz,
At sub sleep
T

A = +25°C

 20 50 µA MB90F352

VCC = 5.0 V,
Internal frequency: 8 kHz,
At watch mode
T

A = +25°C

 10 35 µA MB90F352

VCC = 5.0 V,
At Stop mode,
T

A = +25°C

 725µA MB90F352

515pF

* : The power supply current is measured with an extern al clock.

44

4. AC Characteristics

(1) Clock Timing

Parameter Symbol Pin

Clock frequency

Clock cycle time

t

P

Input clock pulse width
Input clock rise and fall

time

Internal operating
clock frequency
(machine clock)

Internal operating
clock cycle time
(machine clock)

WH, PWL X0 10 ns

WHL, PWLL X0A 5 15.2 µs

P

t

CR, tCF X0  5 ns When using external clock

MB90350 Series

(T

A = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T

A = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Min Typ Max

f

C

CL X0A, X1A — 32.768 100 kHz

f

t

CYL

CYLL X0A, X1A 10 30.5 — µs

X0, X1 3  16 MHz When using an oscillation circuit

X0 3  24 MHz When using an external clock*

X0, X1 62.5  333 ns When using an oscillation circuit

X0 41.67  333 ns When using an external clock

24

f

CP  1.5 

16

f

CPL  8.192 50 kHz When using sub clock

41.67

t

CP 

 666 ns

62.5

CPL  20 122.1 µs When using sub clock

t

Unit Remarks

Duty ratio is about 30% to 70%.

When using main clock at
T

MHz

A ≤ +105 °C

When using main clock at

A ≤ +125 °C

T

When using main clock at
T

A ≤ +105 °C

When using main clock at

A ≤ +125 °C

T

* : When selecting the PLL clock, the range of clock frequency is limited. Use this product within range as

mentioned in “Relation among external clock frequency and machine clock frequency”.

tCYL

X0

PWH PWL

tCF tCR

tCYLL

X0A

PWHL PWLL

tCF tCR

0.8 VCC

0.2 VCC

0.8 VCC

0.2 VCC

Clock Timing

45

MB90350 Series

Guaranteed operation range

5.5

4.0

3.5
Guaranteed PLL operation range

(V)

CC

Power supply voltage

V

1.5

4

Machine clock f

(MHz)

CP

Guaranteed A/D Converter
operation range

24

Guaranteed operation range of MB90350 series

Guaranteed oscillation frequency range

24

x 6

x 4

x 3

x 2 x 1

4.0

1.5

12

16

8

3

4

8

External clock f

12

(MHz) *

C

16

Internal clock
f

(MHz)

CP

* : When using the oscillation circuit, the maximum oscillation clock frequency is 16 MHz

External clock frequency and Machine clock frequency

46

x 1/2
(PLL off)

24

(2) Reset Standby Input

Parameter Symbol Pin

Reset input
time

RSTL RST

t

MB90350 Series

(T

A = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T

A = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Value

Min Max

500  ns Under normal operation

Oscillation time of oscillator*

+ 100 µs

Unit Remarks

In Stop mode, Sub Clock

µs

mode, Sub Sleep mode
and Watch mode

100 µs

In Main timer mode and
PLL timer mode

* : Oscillation time of oscillator is the time that the amplitude reaches 90%.

In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR / ceramic oscillators,
the oscillation time is between hundreds of µs to sev eral ms . With an e xternal clock, the oscillation time is 0 ms.

Under normal operation:

t

RSTL

RST

0.2 V

CC

In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode:

tRSTL

RST

0.2 VCC 0.2 VCC

90% of
amplitude

X0

0.2 V

CC

Internal operation
clock

Internal reset

Oscillation time

of oscillator

100 µs

Oscillation stabilization

waiting time

Instruction execution

47

MB90350 Series

(3) Power On Reset

(T

A = −40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)

(T

A = −40 °C to +125 °C, VCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Parameter Symbol Pin Condition

Value

Unit Remarks

Min Max

Power on rise time t
Power off time t

VCC

VCC

3 V

VSS

R VCC

0.05 30 ms



OFF VCC 1  ms Due to repetitive operation

tR

2.7 V

0.2 V 0.2 V0.2 V

tOFF

If you change the power supply voltage too rapidly, a power on reset may occur.
We recommend that you startup smoothly by restraining voltages when changing
the power supply voltage during operation, as shown in the figure below. Perform
while not using the PLL clock. However, if voltage drops are within 1 V/s, you can
operate while using the PLL clock.

We recommend a rise of

Holds RAM data

50 mV/ms maximum.

(4) Clock Output Timing

Parameter Symbol Pin Condition

Cycle time t

CLK ↑ → CLK ↓ t

CLK

48

(T

A = −40 °C to +105 °C, VCC = 5.0 V ± 10%, VSS = 0.0 V, fCP ≤ 24 MHz)

CYC CLK 

CHCL CLK 

tCHCL

2.4 V

Value

Unit Remarks

Min Max

62.5  ns f

41.76  ns fCP = 24 MHz
20  ns f
13  ns f

CYC

t

2.4 V

0.8 V

CP = 16 MHz

CP = 16 MHz
CP = 24 MHz

(5) Bus Timing (Read)

Parameter

Sym-

bol

MB90350 Series

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Pin Condition

Value

Unit Remarks

Min Max

ALE pulse width t

LHLL ALE

tCP/2 − 10  ns

ALE, A21 to

Valid address ⇒ ALE ↓ time t

AVLL

A16, AD15

t

CP/2 − 20  ns

to AD00

ALE ↓ ⇒ Address valid time t

LLAX

ALE, AD15
to AD00

tCP/2 − 15  ns

A21 toA16,

Valid address ⇒ RD

↓ time tAVRL

AD15 to

tCP − 15  ns

AD00, RD

Valid address ⇒ Valid data
input

RD

pulse width tRLRH RD 3 tCP/2 − 20  ns

t

AVDV

RD ↓ ⇒ Valid data input tRLDV

RD

↑ ⇒ Data hold time tRHDX

RD

↓ ⇒ ALE ↑ time tRHLH RD, ALE tCP/2 − 15  ns

RD

↑ ⇒ Address valid time tRHAX

A21 to A16,
AD15 to
AD00

RD, AD15 to
AD00

RD, AD15 to
AD00

RD, A21 to
A16



 5 t

CP/2 − 60 ns

 3 tCP/2 − 50 ns

0  ns

tCP/2 − 10  ns

A21 to A16,

Valid address ⇒ CLK ↑ time t

AVCH

AD15 to

t

CP/2 − 16  ns

AD00, CLK

RD

↓ ⇒ CLK ↑ time tRLCH RD, CLK tCP/2 − 15  ns

ALE ↓ ⇒ RD

↓ time tLLRL ALE, RD tCP/2 − 15  ns

49

MB90350 Series

t

AVCH

t

RLCH

CLK

ALE

RD

A21 to A16

AD15 to AD00

2.4 V

2.4 V

0.8 V

2.4 V

0.8 V

2.4 V

t

AVLL

t

LHLL

Address

t

AVRL

t

LLAX

2.4 V

0.8 V

t

t

AVDV

LLRL

0.8 V

2.4 V

0.8 V

2.4 V

t

RLDV

t

RLRH

VIH

VIL

2.4 V

Read data

t

RHDX

t

RHLH

2.4 V

t

RHAX

2.4 V

0.8 V

VIH
VIL

50

MB90350 Series

(6) Bus Timing (Write)

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Parameter Symbol Pin Condition

A21 to A16,

Valid address ⇒ WR

↓ time tAVWL

AD15 to AD00,
WR

WR

pulse width tWLWH WR 3 tCP/2 − 20  ns

Value

Min Max

CP−15  ns

t

Unit Remarks

Valid data output ⇒ WR
time

WR ↑ ⇒ Data hold time tWHDX

WR

↑ ⇒ Address valid time tWHAX

WR

↑ ⇒ ALE ↑ time tWHLH WR, ALE tCP/2 − 15  ns

↑

tDVWH

AD15 to AD00,
WR

AD15 to AD00,
WR

A21 to A16,
WR

3 tCP/2 − 20  ns



15  ns

tCP/2 − 10  ns

WR ↓ ⇒ CLK ↑ time tWLCH WR, CLK tCP/2 − 15  ns

t

WLCH

CLK

ALE

WR (WRL, WRH)

t

AVWL

2.4 V

0.8 V

t

WLWH

2.4 V

t

WHLH

2.4 V

A21 to A16

AD15 to AD00

2.4 V

0.8 V

2.4 V

0.8 V

Address

2.4 V

0.8 V

t

DVWH

Write data

t

WHAX

2.4 V

0.8 V

t

WHDX

2.4 V

0.8 V

51

MB90350 Series

(7) Ready Input Timing

Parameter

Sym-

bol

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Pin

Test

Condition

Rated Value

Units Remarks

Min M ax

RDY setup time t

RYHS RDY



RDY hold time t

RYHH RDY 0  ns

Note : If the RDY setup time is insufficient, use the auto-ready function.

CLK

ALE

RD/WR

t

RYHS

IH

RDY
When WAIT is not used.

V

45  ns f
32  ns f

2.4 V

t

RYHH

IH

V

CP = 16 MHz
CP = 24 MHz

52

RDY
When WAIT is used.

IL

V

(8) Hold Timing

Parameter Symbol Pin Condition

MB90350 Series

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, VSS = 0.0 V, fCP ≤ 24 MHz)

Value

Min Max

Units Remarks

Pin floating ⇒ HAK
time

↓

tXHAL HAK

30 t



HAK

↑ time ⇒ Pin valid

time

tHAHV HAK tCP 2 tCP ns

Note : There is more than 1 cycle from when HRQ reads in until the HAK

HAK

Each pin

2.4V 2.4V

0.8V

t

XHAL

0.8V

High-Z

CP ns

is changed.

2.4V

t

HAHV

0.8V

53

MB90350 Series

(9) UART 2/3

Parameter Symbol Pin Condition

Serial clock cycle time t

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(T

A = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

SCYC SCK2, SCK3

Value

Min Max

8 t

CP*  ns

Unit Remarks

SCK ↓ → SOT delay time t

Valid SIN → SCK ↑ t

SCK ↑ → Valid SIN hold time t
Serial clock “H” pulse width t

Serial clock “L” pulse width t

SLOV

IVSH

SHIX

SHSL SCK2, SCK3
SLSH SCK2, SCK3 4 tCP*  ns

SCK ↓ → SOT delay time tSLOV

Valid SIN → SCK ↑ t

SCK ↑ → Valid SIN hold time t

IVSH

SHIX

* : Refer to “ (1) Clock timing” rating for t

SCK2, SCK3,

SOT2, SOT3

SCK2, SCK3,

SIN0 to SIN4

SCK2, SCK3,

SIN2, SIN3

SCK2, SCK3,

SOT2, SOT3

SCK2, SCK3,

SIN2, SIN3

SCK2, SCK3,

SIN2, SIN3

CP (internal operating clock cycle time).

Notes : • AC characteristic in CLK synchronized mode.

• C

L is load capacity value of pins when testing.

• t

CP is the machine cycle (Unit : ns)

Internal clock
operation output
pins are

L = 80 pF + 1 TTL

C

External clock
operation output
pins are
C

L = 80 pF + 1 TTL

−80 +80 ns

100  ns

60  ns

CP*  ns

4 t

 150 ns

60  ns

60  ns

54

SCK

SOT

SIN

t

SCYC

2.4 V

0.8 V

t

SLOV

2.4 V

0.8 V

t

IVSH

IH

V

IL

V

Internal Shift Clock Mode

t

SHIX

0.8 V

IH

V

IL

V

SCK

MB90350 Series

t

SLSH

IL

IL

V

t

SLOV

V

t

SHSL

IH

IH

V

V

SOT

SIN

(10) Trigger Input Timing

Parameter Symbol Pin Condition

Input pulse width

TRGH

t

tTRGL

External Shift Clock Mode

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(T

A = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

INT8 to INT15,

INT9R to INT11R,

ADTG

2.4 V

0.8 V

V
V

t

IVSH

IH

IL

 5 t

t

SHIX

IH

V

IL

V

Value

Min Max

CP  ns

Unit Remarks

INT8 to INT15,
INT9R to INT11R,
ADTG

IH

IH

V

t

TRGH

V

IL

IL

V

t

TRGL

V

55

MB90350 Series

(11) Timer Related Resource Input Timing

Parameter Symbol Pin Condition

t

TIWH TIN1, TIN3,

Input pulse width

TIN1, TIN3,
IN0, IN1,
IN4 to IN7

TIWL

t

IN0, IN1,

IN4 to IN7

IH

V

(T

A = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)

(T

A = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Unit Remarks

Min Max

t

TIWH

 4 t

IH

V

CP  ns

IL

V

t

TIWL

IL

V

(12) Timer Related Resource Output Timing

(T
(T

Parameter Symbol Pin Condition

TOT1, TOT3,

CLK ↑ ⇒ T

OUT change time tTO

PPG4, PPG6,

PPG8 to PPGF

CLK

2.4 V

TOT1, TOT3,
PPG4, PPG6
PPG8 to PPGF

A = –40°C to +105°C, VCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = 0.0 V)
A = –40°C to +125°C, VCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = 0.0 V)

Value

Unit Remarks

Min Max

 30  ns

2.4 V

0.8 V

t

TO

56

2

C Timing

(13) I

(T

A = –40°C to +105°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 24 MHz, VSS = AVSS = 0.0 V)

(T

A = –40°C to +125°C, VCC = AVCC = 5.0 V±10 %, fCP ≤ 16 MHz, VSS = AVSS = 0.0 V)

Parameter Symbol Condition

SCL clock frequency f

SCL

MB90350 Series

Standard-mode

Min Max Min Max

0 100 0 400 kHz

Fast-mode*

4

Unit

Hold time (repeated) START condition
SDA↓→SCL↓

“L” width of the SCL clock t

t

HDSTA 4.0  0.6 µs

LOW 4.7  1.3 µs

“H” width of the SCL clock tHIGH 4.0  0.6 µs
Set-up time for a repeated START condition

SCL↑→SDA↓
Data hold time

SCL↓→SDA↓↑
Data set-up time

SDA↓↑→SCL↑
Set-up time for STOP condition

SCL↑→SDA↑
Bus free time between a STOP and START

condition

t

SUSTA 4.7  0.6 µs

R = 1.7 kΩ,

t

HDDAT 0 3.45*

t

SUDAT 250  100  ns

C = 50 pF*

1

2

00.9*3µs

tSUSTO 4.0  0.6 µs

t

BUS 4.7  1.3 µs

*1 : R,C : Pull-up resistor and load capacitor of the SCL and SDA lines.
*2 : The maximum t
*3 : A Fast-mode I

t

SUDAT ≥ 250 ns must then be met.

HDDAT have only to be met if the device does not stretch the “L” width (tLOW) of the SCL signal.

2

C -bus device can be used in a Standard-mode I2C-bus system, but the requirement

*4 : For use at over 100 kHz, set the machine clock to at least 6 MHz.

SDA

t

LOW

SCL

tHDSTA tHDDAT

tSUDAT

tHIGH

tHDSTA

tSUSTA tSUSTO

tBUS

57

MB90350 Series

5. A/D Converter

(TA = −40 °C to +105 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = AVSS = 0 V)
(TA = −40 °C to +125 °C, 3.0 V ≤ AVRH, VCC = AVCC = 5.0 V ± 10%, fCP ≤ 16 MHz, VSS = AVSS = 0 V)

Parameter Symbol Pin

Min Typ Max

Resolution    10 bit
Total error    ±3.0 LSB
Nonlinearity error    ±2.5 LSB

Value

Unit Remarks

Differential
nonlinearity error

Zero reading
voltage

Full scale reading
voltage

   ±1.9 LSB

V

OT AN0 to AN14 AVSS − 1.5 AVSS + 0.5 AVSS + 2.5 LSB

VFST AN0 to AN14 AVRH − 3.5 AVRH − 1.5 AVRH + 0.5 LSB

Compare time 

Sampling time 

Analog port input
current

Analog input
voltage range

Reference
voltage range

Power supply
current

Reference
voltage current

I

AIN AN0 to AN14 −0.3  +0.3 µA

V

AIN AN0 to AN14 AVSS  AVRH V

 AVRH AVSS + 2.7  AVCC V

I

A AVCC  3.5 7.5 mA

I

AH AVCC  5 µA*

IR AVRH  600 900 µA

I

RH AVRH  5 µA*

1.0

4.5 V ≤ AV

 16,500 µs

2.0 4.0 V ≤ AV

0.5



∞ µs

4.5 V ≤ AV

1.2 4.0 V ≤ AV

CC ≤ 5.5 V

CC < 4.5 V

CC ≤ 5.5 V

CC < 4.5 V

Offset between
input channels

 AN0 to AN14  4LSB

* : IF A/D convertor is not operating, a current when CPU is stopped is applicable (V
Note : The accuracy gets worse as

|AVRH − AVSS| becomes smaller.

58

CC = AVCC = AVRH = 5.0 V) .

MB90350 Series

6. Definition of A/D Converter Terms

Resolution : Analog variation that is recognized by an A/D converter.
Non linearity

error

Differential
linearity error

Total error : Difference between an actual value and an ideal value. A total error includes zero transition

Zero reading
voltage

Full scale
reading voltage

: Deviation between a line across zero-transition line ( “00 0000 0000” ← → “00 0000 0001” )

and full-scale transition line ( “11 1111 1110” ← → “11 1111 1111” ) and actual conversion
characteristics.

: Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal

value.

error, full-scale transition error, and linear error.

: Input voltage which results in the minimum conversion value.

: Input voltage which results in the maximum conversion value.

Total error

3FF

3FE

3FD

004

Digital output

003

002

001

Actual conversion
characteristics

Ideal characteristics

0.5 LSB

AV

SS AVRH

Analog input

NT − {1 LSB × (N − 1) + 0.5 LSB}

V

Total error of digital output “N” =

1 LSB = (Ideal value)

AVRH − AV

1024

VOT (Ideal value) = AVSS + 0.5 LSB [V]

1.5 LSB

{1 LSB × (N − 1) + 0.5 LSB}

NT

V

(Actually-measured value)

Actual conversion
characteristics

1 LSB

SS

[V]

[LSB]

V

FST (Ideal value) = AVRH − 1.5 LSB [V]

V

NT : A voltage at which digital output transitions from (N − 1) to N.

(Continued)

59

MB90350 Series

(Continued)

Non linearity error Differential linearity error

3FF

3FE

3FD

004

Digital output

003

002

001

Actual conversion
characteristics

{1 LSB × (N − 1)

OT }

+ V

Actual conversion
characteristics

Ideal characteristics

OT (actual measurement value)

V

AV

SS AVRH AVSS AVRH

V

FST (actual

measurement
value)

V

NT (actual

measurement value)

N + 1

N

Digital output

N − 1

N − 2

Actual conversion
characteristics

Analog inputAnalog input

Ideal

characteristics

(N + 1) T

V

(actual measurement

VNT

(actual measurement value)

Actual conversion
characteristics

value)

Non linearity error of digital output N =

Differential linearity error of digital output N =

1 LSB =

OT : Voltage at which digital output transits from “000H” to “001H.”

V
V

FST : Voltage at which digital output transits from “3FEH” to “3FFH.”

V

NT − {1 LSB × (N − 1) + VOT}

1 LSB

V (

N+1) T − VNT

1 LSB

VFST − VOT

1022

−1 LSB [LSB]

[V]

[LSB]

60

MB90350 Series

7. Notes on A/D Converter Section

Use the device with external circuits of the following output impedance for analog inputs :
Recommended output impedance of external circuits are : Approx. 1.5 kΩ or lower (4.0 V ≤ AV

CC ≤ 5.5 V,

sampling period ≤ 0.5 µs)

If an external capacitor is used, in consideration of the effect by tap capacitance caused by external capacitors
and on-chip capacitors, capacitance of the external one is recommended to be sever al thousand times as high
as internal capacitor.

If output impedance of an external circuit is too high, a sampling period for an analog voltage ma y be insufficient.

• Analog input circuit model

Analog input

R

Comparator

C

4.5 V ≤ AVCC ≤ 5.5 V : R := 2.52 kΩ, C := 10.7 pF

4.0 V ≤ AV

CC < 4.5 V : R := 13.6 kΩ, C := 10.7 pF

Note : Use the values in the figure only as a guideline.

8. Flash Memory Program/Erase Characteristics

Parameter Conditions

Sector erase time

Min Typ Max

 115s

Value

Unit Remarks

Excludes programming
prior to erasure

A = +25 °C

Chip erase time  9  s
Word (16 bit width)

programming time

T

V

CC = 5.0 V

 16 3,600 µs

Excludes programming
prior to erasure

Except for the overhead

time of the system
Program/Erase cycle  10,000 cycle
Flash Data Retention

Time

Average

T

A = +85 °C

20 Years *

* : This value comes from the technology qualification.

(Using Arrhenius equation to translate high temperature measurements into normalized value at +85 °C)

61

MB90350 Series

ORDERING INFORMATION

■■■■

Part number Package Remarks

MB90F352PFM
MB90F352SPFM
MB90352PFM
MB90352SPFM
MB90V340A-101
MB90V340A-102

64-pin Plastic LQFP

(FPT-64P-M09)

64-pin Plastic LQFP

(FPT-64P-M09)

299-pin Ceramic PGA

(PGA-299C-A01)

For evaluation

62

PACKAGE DIMENSIONS

■■■■

MB90350 Series

64-pin Plastic LQFP

(FPT-64P-M09)

14.00±0.20(.551±.008)SQ

12.00±0.10(.472±.004)SQ

*

49

INDEX

64

116

0.65(.026)

3348

0.32±0.05

(.013±.002)

Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness including plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.

0.145±0.055

(.0057±.0022)

32

0.10(.004)

0.10(.004)
Details of "A" part

+0.20
–0.10

17

0.13(.005)

1.50
.059

0.50±0.20

"A"

M

(.020±.008)

0.60±0.15

(.024±.006)

0~8˚

+.008
–.004

(Mounting height)

0.25(.010)

0.10±0.10

(.004±.004)

(Stand off)

C

2003 FUJITSU LIMITED F64018S-c-3-5

Dimensions in mm (inches)
Note : The values in parentheses are reference values.

63

MB90350 Series

FUJITSU LIMITED

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F0405

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