FUJITSU MB90350 DATA SHEET
查询MB90352供应商
FUJITSU SEMICONDUCTOR
DATA SHEET
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90350 Series
MB90F352/S, MB90352/S
DESCRIPTION
■■■■
The MB90350-series with 1 channel FULL-CAN* interface and FLASH ROM is especially designed f or automotive
and industrial applications. Its main feature is the on-board CAN Interface, which conf orm to V2.0 P art A and Part
B, while supporting a very flexible message buffer scheme and so off ering more functions than a normal full CAN
approach. With the new 0.35 µm CMOS technology, Fujitsu now offers on-chip FLASH-ROM program memory
up to 128 Kbytes. An internal voltage booster removes the necessity for a second programming voltage.
DS07-13737-2E
An on board voltage regulator provides 3 V to the internal MCU core. This creates a major advantage in terms
of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features a 4 channel Output Compare Unit and 6 channel Input Capture Unit with 2 separate 16-bit free
running timers. 2 channels UART constitute additional functionality for communication purposes.
* : Controller Area Network (CAN) - License of Robert Bosch GmbH
Note : F
■■■■
2
MC stands for FUJITSU Flexible Microcontroller, a registered trademark of FUJITSU LIMITED.
PACKAGE
64-pin Plastic LQFP
(FPT-64P-M09)
MB90350 Series
FEATURES
■■■■
••••
Clock
• Built-in PLL clock frequency multiplication circuit
• Selection of machine clocks (PLL clocks) is allow ed among frequency division by two on oscillation cloc k, and
multiplication of 1 to 6 times of oscillation clock (for 4 MHz oscillation clock, 4 MHz to 24 MHz).
• Operation by sub-clock (up to 50 kHz : 100 kHz oscillation clock divided by two) is allowed. (devices without
S-suffix only)
• Minimum ex ecution time of instruction : 42 ns (when operating with 4-MHz oscillation clock, and 6-time multiplied PLL clock).
• Built-in clock modulation circuit
••••
16 Mbyte CPU memory space
• 24-bit internal addressing
••••
External Bus Interface
• 4 MByte external memory space
••••
Instruction system best suited to controller
• Wide choice of data types (bit, byte, word, and long word)
• Wide choice of addressing modes (23 types)
• Enhanced multiply-divide instructions and RETI instructions
• Enhanced high-precision computing with 32-bit accumulator
••••
Instruction system compatible with high-level language (C language) and multitask
• Employing system stack pointer
• Enhanced various pointer indirect instructions
• Barrel shift instructions
••••
Increased processing speed
• 4-byte instruction queue
••••
Powerful interrupt function
• Powerful 8-level, 34-condition interrupt feature
• Up to 8 channels external interrupts are supported
••••
Automatic data transfer function independent of CPU
• Extended intelligent I/O service function (EI
• DMA : up to 16 channels
••••
Low power consumption (standby) mode
• Sleep mode (a mode that halts CPU operating clock)
• Main timer mode (a timebase timer mode switched from the main clock mode)
• PLL timer mode (a timebase timer mode switched from the PLL clock mode)
• Watch mode (a mode that operates sub clock and clock timer only)
• Stop mode (a mode that stops oscillation clock and sub clock)
• CPU blocking operation mode
••••
Process
•CMOS technology
2
OS) : up to 16 channels
••••
I/O port
• General-purpose input/output port (CMOS output)
- 49 ports (devices without S-suffix)
- 51 ports (devices with S-suffix)
2
(Continued)
MB90350 Series
(Continued)
••••
Timer
• Time-base timer, clock timer, watchdog timer : 1 channel
• 8/16-bit PPG timer : 8-bit × 10 channels, or 16-bit × 6 channels
• 16-bit reload timer : 4 channels
• 16- bit input/output timer
- 16-bit free run timer : 2 channels (FRT0 : ICU0/1, FRT1 : ICU 4/5/6/7, OCU 4/5/6/7)
- 16- bit input capture: (ICU) : 6 channels
- 16-bit output compare : (OCU) : 4 channels
••••
Full-CAN interface : 1 channel
• Compliant with Ver2.0A and Ver2.0B CAN specifications
• Flexible message buffering (mailbox and FIFO buffering can be mixed)
• CAN wake-up function
••••
UART (LIN/SCI) : 2 channels
• Equipped with full-duplex double buffer
• Clock-asynchronous or clock-synchronous serial transmission is available
2
••••
I
C interface* : 1 channel
• Up to 400 Kbit/s transfer rate
••••
DTP/External interrupt : 8 channels, CAN wakeup : 1 channel
• Module for activation of extended intelligent I/O ser vice (EI
••••
Delay interrupt generator module
2
OS), DMA, and generation of external interrupt.
• Generates interrupt request for task switching.
••••
8/10-bit A/D converter : 15 channels
• Resolution is selectable between 8-bit and 10-bit.
• Activation by external trigger input is allowed.
• Conversion time : 3 µs (at 24-MHz machine clock, including sampling time)
••••
Program patch function
• Address matching detection for 6 address pointers.
••••
Internal voltage regulator
• Supports 3 V MCU core, offering low EMI and low power consumption figures
••••
Programmable input levels
• Automotive/CMOS-Schmitt (initial level is Automotive in Single chip mode)
• TTL level (initial level for External bus mode)
••••
Flash security function
• Protects the content of Flash (Flash device only)
2
* : I
C license :
Purchase of Fujitsu I
ponents in an I
2
C components conveys a license under the Philips I2C Patent Rights to use, these com-
2
C system provided that the system conforms to the I2C Standard Specification as defined by
Philips.
3
MB90350 Series
PRODUCT LINEUP
■■■■
Part Number
MB90F352/S, MB90352/S*
1
MB90V340A-101/102
Parameter
CPU F
System clock
ROM
On-chip PLL clock multiplier (×1, ×2, ×3, ×4, ×6, 1/2 when PLL stops)
Minimum instruction execution time : 42 ns (4 MHz osc. PLL × 6)
Boot-block, Flash memory
128 Kbytes
2
MC-16LX CPU
External
RAM 4 Kbytes 30 Kbytes
Emulator-specific
power supply*
2
Technology
Operating
voltage range
0.35 µm CMOS with regulator for internal power supply +
Flash memory charge pump for programming voltage
3.5 V - 5.5 V : at normal operating (not using A/D converter)
4.0 V - 5.5 V : at using A/D converter/Flash programming
4.5 V - 5.5 V : at using external bus
Yes
0.35 µm CMOS with
regulator for internal
power supply
5 V ± 10%
Temperature range −40 °C to +105 °C (125 °C up to 16 MHz machine clock)
Package LQFP-64 PGA-299
2 channels 3 channels
UART
Wide range of baud rate settings using a dedicated reload timer
Special synchronous options for adapting to different synchronous serial protocols
LIN functionality working either as master or slave LIN device
2
I
C (400 kbit/s) 1 channel 1 channel
A/D
Converter
16-bit Reload Timer
(4 channels)
10-bit or 8-bit resolution
Conversion time : Min 3 µs include sample time (per one channel)
Operation clock frequency : fsys/2
Supports External Event Count function
15 channels
1
, fsys/23, fsys/25 (fsys = Machine clock frequency)
Signals an interrupt when overflowing
16-bit
I/O Timer
(2 channels)
Supports Timer Clear when a match with Output Compare (Channel 0, 4)
Operation clock freq. : fsys, fsys/2
1
, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/2
(fsys = Machine clock freq.)
I/O Timer 0 (clock input FRCK0) corresponds to ICU 0/1
I/O Timer 1 (clock input FRCK1) corresponds to ICU 4/5/6/7, OCU 4/5/6/7
16-bit Output
Compare
(4 channels)
16-bit Input Capture
(6 channels)
Signals an interrupt when 16-bit I/O Timer match output compare registers.
A pair of compare registers can be used to generate an output signal.
Rising edge, falling edge or rising & falling edge sensitive
Signals an interrupt upon external event
7
(Continued)
4
Part Number
Parameter
8/16-bit
Programmable Pulse
Generator
6 channels (16-bit) /
10 channels (8-bit)
CAN Interface
MB90350 Series
MB90F352/S, MB90352/S*
1
Supports 8-bit and 16-bit operation modes
8-bit reload counters × 12
8-bit reload registers for L pulse width × 12
8-bit reload registers for H pulse width × 12
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler + 8-bit reload counter
Operation clock freq. : fsys, fsys/2
1
, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
1 channel 2 channels
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 message buffers for data and ID’s
Supports multiple messages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
MB90V340A-101/102
External Interrupt
(8 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
extended intelligent I/O services (EI
2
OS) and DMA
D/A converter 1 channel
Subclock
(up to100 kHz)
devices with ‘S’-suffix and MB90V340A-102 : without subclock
devices without ‘S’-suffix and MB90V340A-101 : with subclock
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
I/O Ports
Bit-wise settable as input/output or peripheral signal
Settable as CMOS schmitt trigger/ automotive inputs (default)
TTL input level settable for external bus (30 terminals only for external bus)
Supports automatic programming, Embedded Algorithm
TM*3
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Flash
Memory
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
*1 : The devices are under development.
*2 : It is setting of Jumper switch (TOOL V
CC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*3 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
MB90350 Series
PIN ASSIGNMENTS
■■■■
• MB90F352/S, MB90352/S
(TOP VIEW)
(LQFP-64P)
P25/A21/IN1/ADTG
P44/SDA0/FRCK0
P45/SCL0/FRCK1
P30/ALE/IN4
P31/RD
/WR/INT10R
P32/WRL
P33/WRH
P34/HRQ/OUT4
P35/HAK
P36/RDY/OUT6
P37/CLK/OUT7
P60/AN0
P61/AN1
Vcc
/IN5
/OUT5
AVcc
VssX0X1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
C
51
52
53
54
55
56
57
58
59
60
61
62
63
64
AVs s
AVRH
RST
P63/AN3/PPG6(7)
P62/AN2/PPG4(5)
P24/A20/IN0
P23/A19/PPGF(E)
P22/A18/PPGD(C)
P21/A17/PPGB(A)
P64/AN4/PPG8(9)
P67/AN7/PPGE(F)
P65/AN5/PPGA(B)
P66/AN6/PPGC(D)
P20/A16/PPG9(8)
P17/AD15
P16/AD14
P15/AD13
P14/AD12/SCK3
10 11 12 13 14 15 161234567 98
P50/AN8/SIN2
P51/AN9/SOT2
P52/AN10/SCK2
P53/AN11/TIN3
P54/AN12/TOT3
P13/AD11/SOT3
P12/AD10/SIN3/INT11R
P56/AN14
P55/AN13
P11/AD09/TOT1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P42/IN6/RX1/INT9 R
P10/AD08/TIN1
P07/AD07/INT15
P06/AD06/INT14
P05/AD05/INT13
P04/AD04/INT12
P03/AD03/INT11
P02/AD02/INT10
P01/AD01/INT9
P00/AD00/INT8
MD0
MD1
MD2
P41/X1A*
P40/X0A*
Vss
P43/IN7/TX1
(FPT-64P-M09)
* : MB90F352/352 : X0A, X1A
MB90F352S/352S : P40, P41
6
PIN DESCRIPTION
■■■■
MB90350 Series
Pin No.
LQFP64*
46 X1
47 X0 Oscillation input pin.
45 RST
3 to 8
9
10
11
12
13
14, 15
16
17
19, 20
Pin name
P62 to P67
AN2 to AN7 Analog input pins for A/D converter.
PPG4, 6, 8,
A, C, E
P50
AN8 Analog input pin for A/D converter.
SIN2 Serial data input pin for UART2.
P51
AN9 Analog input pin for A/D converter.
SOT2 Serial data output pin for UART2.
P52
AN10 Analog input pin for A/D converter.
SCK2 Serial data output pin for UART2.
P53
AN11 Analog input pin for A/D converter.
TIN3 Event input pin for reload timer3.
P54
AN12 Analog input pin for A/D converter.
TOT3 Output pin for reload timer3.
P55, P56
AN13, AN14 Analog input pins for A/D converter.
P42
IN6 Data sample input pin for input capture ICU6.
RX1 RX input pin for CAN1.
INT9R External interrupt request input pin for INT9.
P43
IN7 Data sample input pin for input capture ICU7.
TX1 TX output pin for CAN1.
P40, P41 F
X0A, X1A B
Circuit
type
Oscillation output pin.
A
E Reset input pin.
General purpose I/O ports.
I
Output pins for PPGs.
General purpose I/O port.
O
General purpose I/O port.
I
General purpose I/O port.
I
General purpose I/O port.
I
General purpose I/O port.
I
General purpose I/O ports.
I
General purpose I/O port.
F
General purpose I/O port.
F
General purpose I/O ports
(devices with S-suffix and MB90V340A-101) .
Oscillation input pins for sub clock
(devices without S-suffix and MB90V340A-102) .
Function
(Continued)
7
MB90350 Series
Pin No.
LQFP64*
24 to 31
32
33
34
35
36
37
38
Pin name
P00 to P07
AD00 to AD07
INT8 to INT15 External interrupt request input pins for INT8 to INT15.
P10
AD08
TIN1 Event input pin for reload timer1.
P11
AD09
TOT1 Output pin for reload timer1.
P12
AD10
SIN3 Serial data input pin for UART3.
INT11R External interrupt request input pin for INT11
P13
AD11
SOT3 Serial data output pin for UART3.
P14
AD12
SCK3 Clock input/output pin for UART3.
P15
AD13
P16
AD14
Circuit
type
G
G
G
N
G
G
N
G
Function
General purpose I/O ports.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.
Input/output pins of external address data bus lower 8 bit. This function is
enabled when the external bus is enabled.
General purpose I/O port.The register can be set to select whether to use
a pull-up resistor.This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 8.
This function is enabled when external bus is enabled.
General purpose I/O.The register can be set to select whether to use a
pull-up resistor.This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 9. This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 10. This function is
enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 11.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 12.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 13.
This function is enabled when external bus is enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 14.
This function is enabled when external bus is enabled.
(Continued)
8
MB90350 Series
Pin No.
LQFP64*
39
40 to 43
44
51
52
53
54
Pin name
P17
AD15
P20 to P23
A16 to A19
PPG9, PPGB,
PPGD, PPGF
P24
A20
IN0 Data sample input pin for input capture ICU0.
P25
A21
IN1 Data sample input pin for input capture ICU1.
ADTG Trigger input pin for A/D converter.
P44
SDA0 Serial data I/O pin for I
FRCK0 Input pin for the 16-bit I/O Timer 0
P45
SCL0 Serial clock I/O pin for I
FRCK1 Input for the 16-bit I/O Timer 1
P30
ALE
IN4 Data sample input pin for input capture ICU4.
Circuit
type
G
G
G
G
H
H
G
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Input/output pin for external bus address data bus bit 15.
This function is enabled when external bus is enabled.
General purpose I/O ports. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
Output pins for A16 to A19 of the external address bus.
When the corresponding bit in the external address output control register
(HACR) is 0, the pins are enabled as high address output pins A16 to A19.
Output pins for PPGs.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
Output pins for A20 of the external address bus. When the corresponding
bit in the external address output control register (HACR) is 0, the pin is
enabled as high address output pins A20.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. In external bus mode, the pin is enabled as a generalpurpose I/O port when the corresponding bit in the external address output
control register (HACR) is 1.
Output pin for A21 of the external address bus. When the corresponding bit
in the external address output control register (HACR) is 0, the pin is enabled as high address output pin A21.
General purpose I/O port
2
C 0
General purpose I/O port.
2
C 0
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Address latch enable output pin. This function is enabled when external bus
is enabled.
Function
(Continued)
9
MB90350 Series
10
Pin No.
LQFP64*
55
56
57
58
59
60
61
Pin name
P31
RD
IN5 Data sample input pin for input capture ICU5.
P32
WR
/WRL
INT10R External interrupt request input pin for INT10.
P33
WRH
P34
HRQ
OUT4 Waveform output pin for output compare OCU4.
P35
HAK
OUT5 Waveform output pin for output compare OCU5.
P36
RDY
OUT6 Waveform output pin for output compare OCU6.
P37
CLK
OUT7 Waveform output pin for output compare OCU7.
Circuit
type
G
G
G
G
G
G
G
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled in single-chip mode.
Read strobe output pin for data bus. This function is enabled when external
bus is enabled.
General purpose I/O port. The register can be set to select whether to use
pull-up resistor. This function is enabled either in single-chip mode or with
the WR
Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR
write-strobe 8 lower bits of the data bus in 16-bit access. WR
write-strobe 8 bits of the data bus in 8-bit access.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the WRH
Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit
mode is selected, and when the WRH
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
Hold request input pin. This function is enabled when both the external bus
and the hold function are enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the hold function disabled.
Hold acknowledge output pin. This function is enabled when both the
external bus and the hold function are enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the external ready function disabled.
Ready input pin. This function is enabled when both the external bus and
the external ready function are enabled.
General purpose I/O port. The register can be set to select whether to use
a pull-up resistor. This function is enabled either in single-chip mode or with
the CLK output disabled.
CLK output pin. This function is enabled when both the external bus and
CLK output are enabled.
/WRL pin output disabled.
pin output disabled.
Function
/WRL pin output are enabled. WRL is used to
output pin is enabled.
is used to
(Continued)
(Continued)
Pin No.
Pin name
LQFP64*
P60, P61
62, 63
Circuit
type
I
Function
General purpose I/O ports.
AN0, AN1 Analog input pins for A/D converter.
64 AV
CC KVCC power input pin for analog circuits.
Reference voltage input for the A/D converter. This power supply must be
2 AVRH L
1AV
SS KVSS power input pin for analog circuits.
turned on or off while a voltage higher than or equal to AVRH is applied to
AV
CC.
22, 23 MD1, MD0 C Input pins for specifying the operating mode.
21 MD2 D Input pins for specifying the operating mode.
49 V
CC Power (3.5 V to 5.5 V) input pin.
18, 48 VSS Power (0 V) input pins.
50 C K
This is the power supply stabilization capacitor pin. It should be connected
to a higher than or equal to 0.1 µF ceramic capacitor.
MB90350 Series
* : FPT-64P-M09
11
MB90350 Series
I/O CIRCUIT TYPE
■■■■
Type Circuit Remarks
Oscillation circuit
X1
Xout
• High-speed oscillation feedback
resistor = approx. 1 MΩ
A
X0
X1A
Standby control signal
Xout
Oscillation circuit
• Low-speed oscillation feedback
resistor = approx. 10 MΩ
B
X0A
Standby control signal
Mask ROM device:
• CMOS Hysteresis input pin
C
R
Hysteresis
inputs
Flash device:
• CMOS input pin
R
D
Pull-down
Resistor
Hysteresis
inputs
Mask ROM device:
• CMOS Hysteresis input pin
• Pull-down resistor valule: appro x. 50 kΩ
Flash device:
• CMOS input pin
• No Pull-down
12
CMOS Hysteresis input pin
• Pull-up resistor valule: approx. 50 kΩ
E
Pull-up
Resistor
R
Hysteresis
inputs
(Continued)
MB90350 Series
Type Circuit Remarks
• CMOS level output
(I
Pout
Nout
F
R
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
OL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standb y-time
input shutdown function)
pull-up control
pull-up
resistor
Pout
• CMOS level output
(I
OL = 4 mA, IOH = −4 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standb y-time
input shutdown function)
Nout
G
R
Hysteresis inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• TTL input (With the standby-time input
shutdown function)
• Programmalble pullup resistor: 50 kΩ
approx.
• CMOS level output
(I
Pout
OL = 3 mA, IOH = −3 mA)
• CMOS hysteresis inputs (With the standby-time input shutdown function)
Nout
H
R
• Automotive input (With the standb y-time
input shutdown function)
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
(Continued)
13
MB90350 Series
Type Circuit Remarks
• CMOS level output(I
Pout
Nout
R
I
Hysteresis inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• CMOS hysteresis inputs (With the standby-time input shutdown function)
• Automotive input (With the standb y-time
input shutdown function)
• A/D analog input
• Power supply input protection circuit
OL = 4 mA)
K
• A/D converter reference voltage power
ANE
supply input pin, with the protection circuit
L
AVR
ANE
• Flash devices do not have a protection
circuit against V
CC for pin AVRH
(Continued)
14
MB90350 Series
(Continued)
Type Circuit Remarks
pull-up control
pull-up
registor
Pout
Nout
N
R
CMOS inputs
Automotive inputs
TTL input
Standby control for
input shutdown
• CMOS level output
(I
OL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
• Automotive input (With the standby-time
input shutdown function)
• TTL input (With the standby-time input
shutdown function)
• Programmable pull-up registor:50 kΩ
approx
• CMOS level output
(I
Pout
OL = 4 mA, IOH = −4 mA)
• CMOS inputs (With the standby-time
input shutdown function)
Nout
R
O
CMOS inputs
Automotive inputs
Standby control for
input shutdown
Analog input
• Automotive input (With the standby-time
input shutdown function)
• A/D analog input
15
MB90350 Series
HANDLING DEVICES
■■■■
Special care is required for the following when handling the device :
• Prev e nting latch-up
• Treatment of unused pins
• Using external clock
• Precautions for when not using a sub clock signal
• Notes on during operation of PLL clock mode
• Power supply pins (V
• Pull-up/down resistors
• Crystal Oscillator Circuit
• Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
• Connection of Unused Pins of A/D Converter
• Notes on Energization
• Stabilization of power supply voltage
• Initialization
• Port0 to port3 output during Power-on (External-bus mode)
• Notes on using CAN Function
• Flash security Function
CC/VSS)
1. Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions
• A voltage higher than V
• A voltage higher than the rated voltage is applied between VCC and VSS.
•The AV
Latch-up may increase the power supply current drastically, causing thermal damage to the device.
For the same reason, also be careful not to let the analog power-supply v oltage (AV
power-supply voltage.
CC power supply is applied before the VCC voltage.
CC or lower than VSS is applied to an input or output pin.
:
CC, A VRH) e xceed the digital
2. Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the
device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should
be more than 2 kΩ .
Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above
described connection.
3. Using external clock
To use external clock, drive the X0 pin and leave X1 pin open.
MB90350 Series
X0
Open
X1
4. Precautions for when not using a sub clock signal
If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the
X1A pin open.
16
MB90350 Series
5. Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit ev en
when there is no external oscillator or external clock input is stopped. Performance of this operation, however,
cannot be guaranteed.
6. Power supply pins (VCC/VSS)
• If there are multiple VCC and VSS pins, from the point of view of de vice design, pins to be of the same potential
are connected inside of the device to prevent such malfunctioning as latch up.
To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level,
and observe the standard for total output current, be sure to connect the V
and ground externally.
• Connect VCC and VSS to the device from the current supply source at a low impedance.
• As a measure against power supply noise, connect a capacitor of about 0.1 µF as a bypass capacitor between
V
CC and VSS in the vicinity of VCC and VSS pins of the device
CC and VSS pins to the power supply
Vcc
Vss
Vss
Vcc
Vss
Vcc
MB90350
Series
Vss
Vcc
Vss
Vcc
7. Pull-up/down resistors
The MB90350 Series does not support internal pull-up/down resistors (P ort 0 to Port 3: built-in pull-up resistors).
Use external components where needed.
8. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass
capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and
make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with a ground
area for stabilizing the operation.
9. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN14) after
turning-on the digital power supply (V
CC) .
Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure
that the voltage does not exceed AVRH or AV
CC (turning on/off the analog and digital power supplies simulta-
neously is acceptable).
10. Connection of Unused Pins of A/D Converter if A/D Converter is used
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS.
17
MB90350 Series
11. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50
or more µs (0.2 V to 2.7 V)
12. Stabilization of power supply voltage
A sudden change in the supply voltage may cause the de vice to malfunction e ven within the specified VCC supply
voltage operating range. Therefore, the V
CC supply voltage should be stabilized.
For reference, the supply voltage should be controlled so that V
commercial frequencies (50 Hz to 60 Hz) fall below 10% of the standard V
CC ripple variations (peak-to-peak value) at
CC supply voltage and the coefficient
of fluctuation does not exceed 0.1 V/ms at instantaneous power switching.
13. Initialization
In the device, there are internal registers which are initialized only by a pow er-on reset. T o initialize these registers,
turn on the power again.
14. Port 0 to port 3 output during Power-on (External-bus mode)
As shown below, when power is turned on in External-Bus mode, there is a possibility that output signal of
Port 0 to Port 3 might be unstable.
1/2 VCC
VCC
Port0 to Port3
Port0 to Port3 outputs
might be unstable
Port0 to Port3 outputs = Hi-Z
15. Notes on using CAN Function
To use CAN function, please set ’1’ to DIRECT bit of CAN Direct Mode Register (CDMR).
If DIRECT bit is set to ’0’ (initial value), wait states will be performed when accessing CAN registers.
Please refer to Hardware Manual of MB90350 series for detail of CAN Direct Mode Register.
16. Flash security Function
The security byte is located in the area of the flash memory.
If protection code 01
Therefore please do not write 01
Please refer to following table for the address of the security bit.
MB90F352 Embedded 1 Mbit Flash Memory FE0001
18
H is written in the security bit, the flash memory is in the protected state by security.
H in this address if you do not use the security function.
Flash memory size Address for security bit
H
BLOCK DIAGRAMS
■■■■
• MB90V340A-101/102
X0,X1
X0A,X1A
RST
*
Clock
Controller
MB90350 Series
16LX
CPU
SOT4 to SOT2
SCK4 to SCK2
SIN4 to SIN2
AVCC
AVSS
AN14 to AN0
AVRH
ADTG
DA00
PPGF to PPG8,
PPG6, PPG4,
PPG2, PPG0
SDA0
SCL0
RAM 30 K
Prescaler
3 ch
UART
3 ch
10-bit ADC
15 ch
10-bit
DAC
1 ch
8/16-bit
PPG
12/8 ch
2
C
I
Interface
1 ch
FMC-16 Bus
IO Timer 0
Input
Capture
6 ch
Output
Compare
4 ch
IO Timer 1
CAN
Controller
2 ch
16-bit Reload
Timer 4 ch
External
Bus
Interface
External
Interrupt
FRCK0
IN7 to IN4,
IN1 to IN0
OUT7 to OUT4
FRCK1
RX2 to RX1
TX2 to TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
A21 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT11R to INT9R)
* : MB90V340A-102
DMAC
19
MB90350 Series
• MB90F352/S, MB90352/S
X0,X1
X0A,X1A*
RST
Clock
Controller
16LX
CPU
SOT3, SOT2
SCK3, SCK2
SIN3, SIN2
AVCC
AVSS
AN14 to AN0
AVRH
ADTG
PPGF to PPG8
PPG6, PPG4
SDA0
SCL0
RAM
4 K
ROM/Flash
128 K
Prescaler
2 ch
UART
2 ch
10-bit ADC
15 ch
8/16-bit
PPG
10/6 ch
2
C
I
Interface
1 ch
FMC-16 Bus
IO Timer 0
Input
Capture
6 ch
Output
Compare
4 ch
IO Timer 1
CAN
Controller
1 ch
16-bit Reload
Timer 4 ch
External
Bus
Interface
External
Interrupt
FRCK0
IN7 to IN4,
IN1, IN0
OUT7 to OUT4
FRCK1
RX1
TX1
TIN3, TIN1
TOT3, TOT1
AD15 to AD00
A21 to A16
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT15 to INT8
(INT11R to INT9R)
* : Only for devices without ‘S’ Suffix
20
DMAC
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