FUJITSU MB90242A DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

16-bit Proprietary Microcontroller

CMOS

MC-16F MB90242A Series

MB90242A

DESCRIPTION

The MB90242A is a 16-bit microcontroller optimized for “mechatronics” control applications such as hard disk drive unit control.

The instruction set is based on the AT architecture of the F language supporting instruction, expanded addressing modes, enhanced multiplication and division instructions, and improved bit processing instructions. In addition, long-word data can now be processed due to the inclusion of a 32-bit accumulator.

MC*-16, 16H family, with additional high-level

DS07-13506-1E

The MB90242A has a multiply/accumulate unit as a peripheral resource, allowing easy realization of digital filters such as IIR or FIR. The MB90242A has abundant embedded peripheral features, such as 6-channel 8/ 10-bit A/D converter, UART, 2-channel + 1-channel timer, 4-channel input capture and 4-channel external interrupt.

*1: F

MC stands for FUJITSU Flexible Microcontroller.

FEATURES

•F

MC-16F CPU Minimum execution time: 62.5 ns (32 MHz oscillation: 5.0 V ± 10%) Instruction set optimized for controller applications Improved instruction set applicable to high-level language (C) and multitasking Improved execution speed: 8-byte queue Powerful interrupt fuctions (interrupt processing time: 1.0 µ s 32 MHz oscillation) Automatic transfer function independent of instructions Extended intelligent I/O Service

(Continued)

PACKAGE

80-pin Plastic LQFP

(FPT-80P-M05)

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MB90242A Series

(Continued)

• DSP unit Speciﬁc function for calculations of IIR A maximum of 8 product resulted from signed 16-bit × 16-bit multiplications can be accumulated.

Yk = Σ bn Yk-n + Σ am Xk-m is executed in 0.625 µs (at oscillation of 32 MHz, N = M = 3)

n = 0

m = 0

The N and M value is set to a maximum of 3, independently.

• Internal RAM: 2 Kbytes (MB90242A) Depending on mode settings, data stored on RAM can be executed as CPU instructions.

• General-purpose ports: max. 38 channels

• A/D converter (analog inputs: 6 channels) Resolution: 10 bits Conversion time: min. 1.25 µ s Switchable to 8/10 bits Number of registers for storing conversion results: 4

• 8-bit UART: 1 channel

• 8/16-bit I/O simple serial interface (8 Mbps max.): 2 channels

• 16-bit free-run timer: Operating clock cycle 0.25 µ s

• 16-bit input capture: 4 channels Activated by selected edges

• 16-bit reload timer: 2 channels

• External interrupts: 4 channels

• Timebase timer: 18 bits

• Watchdog timer

• Clock gear function

• Low-power consumption modes Sleep mode Stop mode Hardware standby mode

• Packages: LQFP-80

• CMOS 0.8 µ m technology

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PRODUCT LINEUP

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MB90242A Series

Part number

Parameter

Classiﬁcation Mass production device CPU DSP unit Built-in Internal RAM* 2 Kbytes General-purpose ports Max. 38 channels A/D converter 10-bit resolution, analog inputs: 6 channels D/A converter None UART 8 bits: 1 channel

8/16-bit serial I/O

16-bit free-run timer Built-in 16-bit input capture 4 channels 16-bit reload timer 2 channels External interrupts 4 channels

Transfer direction switching function available

MB90242A

MC-16F CPU core

8/16 bits: 1 channel

Timebase timer Built-in Watchdog timer Built-in Clock gear function Built-in Package FPT-80P-M05

* :The RAM has an extra 64-byte area reserved for multiply/accumulate operations.

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MB90242A Series

PIN ASSIGNMENT

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(Top view)

VSS

X0 X1

VCC P00/D00 P01/D01 P02/D02 P03/D03 P04/D04 P05/D05 P06/D06 P07/D07 P10/D08 P11/D09 P12/D10 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15

RST

P57/ASR3/INT3

P56/RD

P55/WRL

P54/WRH

P53/HRQ

P52/HAK

P51/RDY

P50/CLK

P82/INT2/ATG

P81/INT1

P80/INT0

P75/SOD1

60595857565554535251504948474645444342

61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

123456789

P20/A00

P21/A01

P22/A02

P23/A03

P24/A04

P25/A05

P26/A06

P27/A07

1011121314151617181920

P30/A08

P31/A09

P32/A10

P33/A11

P74/SID1

P73/SCK1

P72

P34/A12

P35/A13

P36/A14

P71/TOT1

P70/TOT0

HST

P37/A15

P40/A16

P41/A17

MD2 41

MD1

MD0

OPEN

P67/AN7

P66/AN6

P63/AN3

P62/AN2

VSS

P61/AN1

P60/AN0

AVSS

AVRL

AVRH

AVCC

P47/A23/ASR2

P46/A22/ASR1/TIN1

P45/A21/ASR0/TIN0

P44/A20/SCK0

P43/A19/SOD0

P42/A18/SID0

(FPT-80P-M05)

PIN DESCRIPTION

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MB90242A Series

Pin no.

LQFP*

1 to 8 P20 to P27 F These pins cannot be used as general-purpose ports.

10 to 17 P30 to P37 F These pins cannot be used as general-purpose ports.

18 P40 F General-purpose I/O port

19 P41 F General-purpose I/O port

20 P42 F General-purpose I/O port

21 P43 F General-purpose I/O port

Pin name Circuit type Function

A00 to A07 Output pins for the lower 8 bits of the external address bus

A08 to A15 Output pins for the middle 8 bits of the external address bus

This function is available when corresponding bit of the upper address control register specifies port.

A16 External address bus output pin bit 16

This function is available when corresponding bit of the upper address control register specifies address.

This function is available when corresponding bit of the upper address control register specifies port.

A17 External address bus output pin bit 17

This function is available when corresponding bit of the upper address control register specifies address.

This function is available when corresponding bit of the upper address control register specifies port.

A18 External address bus output pin bit 18

This function is available when corresponding bit of the upper address control register specifies address.

SID0 UART #0 data input pin

This pin, as required, is used for input during UART #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

This function is available when data output of UART #0 is disabled and corresponding bit of the upper address control register specifies port.

A19 External address bus output pin bit 19

This function is available when data output of UART #0 is disabled and corresponding bit of the upper address control register specifies address.

SOD0 UART #0 data output pin

This function is available when data output of UART #0 is enabled.

* :FPT-80P-M05

(Continued)

MB90242A Series

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Pin no.

LQFP*

22 P44 F General-purpose I/O port

23 P45 F General-purpose I/O port

24 P46 F General-purpose I/O port

Pin name Circuit type Function

This function is available when clock output of UART #0 and SSI #2 are disabled and corresponding bit of the upper address control register specifies port.

A20 External address bus output pin bit 20

This function is available when clock output of UART #0 is disabled and corresponding bit of the upper address control register specifies address.

SCK0 UART #0 clock input pin

This function is available when the UART #0 clock output is enabled.

This function is available when data output of SSI #2 is disabled and corresponding bit of the upper address control register specifies port.

A21 External address bus output pin bit 21

This function is available when data output of SSI #2 is disabled and corresponding bit of the upper address control register specifies address.

ASR0 Input capature #0 data input pin

This pin, as required, is used for input during input capture #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

TIN0 16-bit timer #0 data input pin

This pin, as required, is used for input during 16-bit timer #0 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

This function is available when corresponding bit of the upper address control register specifies port.

A22 External address bus output pin bit 22

This function is available when corresponding bit of the upper address control register specifies address.

ASR1 Input capature #1 data input pin

This pin, as required, is used for input during input capture #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

TIN1 16-bit timer #1 data input pin

This pin, as required, is used for input during 16-bit timer #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

* :FPT-80P-M05

(Continued)

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MB90242A Series

Pin no.

Pin name Circuit type Function

LQFP*

25 P47 F General-purpose I/O port

This function is available when corresponding bit of the upper address control register specifies port.

A23 External address bus output pin bit 23

This function is available when corresponding bit of the upper address control register specifies address.

ASR2 Input capature #2 data input pin

This pin, as required, is used for input during input capture #2 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

26 AV

Power supply Analog circuit power supply pin

This power supply must only be turned on or off when electric potential of AV

or greater is applied to V

27 AVRH Power supply A/D converter external reference voltage input pin

This pin must only be trendy on or off when electric potential of AVRH or greater is applied to AV

. 28 AVRL Power supply A/D converter external reference voltage input pin 29 AV

Power supply Analog circuit power supply (GND) pin

30, 31 P60, P61 H N-ch open-drain I/O ports

When corresponding bit of the ADER are set to “0,” reading data register with an instruction other than read-modify-write group instructions reads the level on these pins, while data written on the data register is output on these pins directly.

AN0, AN1 A/D converter analog input pins

Set corresponding bit of the ADER to “1,” and corresponding bit of the data register to “1.”

33, 34 P62, P63 H N-ch open-drain I/O ports

AN2, AN3 A/D converter analog input pins

Set corresponding bit of the ADER to “1,” and corresponding bit of the data register to “1.”

35, 36 P66, P67 H N-ch open-drain I/O ports

AN6, AN7 A/D converter analog input pins

Set corresponding bit of the ADER to “1,” and corresponding bit of the data register to “1.”

37, 38 OPEN — Open pins

No internal connections are made.

* :FPT-80P-M05

(Continued)

MB90242A Series

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Pin no.

LQFP*

39 to 41 MD0 to MD2 C Operating mode selection input pins

42 HST

43, 44 P70, P71 F General-purpose I/O ports

45 P72 F General-purpose I/O port 46 P73 F General-purpose I/O port

47 P74 F General-purpose I/O port

48 P75 F General-purpose I/O port

49, 50 P80, P81 G General-purpose I/O ports

51 P82 F General-purpose I/O port

Pin name Circuit type Function

or V

Connect directly to V

D Hardware standby input pin

This function is available when neither output of 16-bit timer #0 nor #1 is enabled.

TOT0, TOT1 16-bit timer output pins

This function is available when outputs of both 16-bit timer #0 and #1 are enabled.

This function is available when clock output of SSI #1 is disabled.

SCK1 SSI #1 clock I/O pin

This function is always valid.

SID1 SSI #1 data input pin

This pin, as required, is used for input during SSI #1 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

This function is available when data output of SSI #1 is disabled.

SOD1 SSI #1 data output pin

This function is available when data output of SSI #1 is enabled.

This function is always valid.

INT0, INT1 External interrupt input pins

These pins, as required, are used for input while external interrupt is enabled, and it is necessary to disable input/output for other functions from these pins unless such input/output is made intentionally.

This function is always valid.

INT2 External interrupt input pin

This pin, as required, is used for input while external interrupt is enabled, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally. This pin is clamped to “LOW” level when CPU is in the “STOP” status. Use INT0 or INT1 to resume operation.

ATG A/D converter activation trigger input pin

This pin, as required, is used for input while A/D conv erter is waiting for activation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

* :FPT-80P-M05

(Continued)

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MB90242A Series

Pin no.

LQFP*

52 P50 F General-purpose I/O port

53 P51 E General-purpose I/O port

54 P52 E General-purpose I/O port

55 P53 E General-purpose I/O port

56 P54 F General-purpose I/O port

57 P55 F General-purpose I/O port

58 P56 F This pin cannot be used as a general-purpose port.

59 P57 F General-purpose I/O port

60 RST B External reset request input pin

62, 63 X0, X1 A Crystal oscillator pins (32 MHz)

* :FPT-80P-M05

Pin name Circuit type Function

This function is available when CLK output is disabled.

CLK CLK output pin

This function is available when CLK output is enabled.

This function is available when ready function is disabled.

RDY Ready input pin

This function is available when ready function is enabled.

This function is available when hold function is disabled.

HAK

HRQ Hold request input pin

WRH Write strobe output pin for the upper eight bits of the data bus

WRL Write strobe output pin for the lower eight bits of the data bus

RD Read strobe output pin for the data bus

ASR3 Input capture #3 data input pin

INT3 External interrupt #3 data input pin

Hold acknowledge output pin This function is available when hold function is enabled.

This function is available when hold function is disabled.

This function is available when hold function is enabled.

This function is available when the external bus 8-bit mode is selected or WRH pin output is disabled.

This function is available when the external bus 16-bit mode is selected and WRH pin output is enabled.

This function is available when WRL pin output is disabled.

This function is available when WRL pin output is enabled.

This pin, as required, is used for input during input capture #3 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

This pin, as required, is used for input during external interrupt #3 input operation, and it is necessary to disable input/output for other functions from this pin unless such input/output is made intentionally.

(Continued)

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MB90242A Series

(Continued)

Pin no.

LQFP*

64 V

9, 32, 61 V

65 to 72 P00 to P07 E These pins cannot be used as general-purpose ports.

73 to 80 P10 to P17 E General-purpose I/O ports

Pin name Circuit type Function

D00 to D07 I/O pins for the lower 8 bits of the external data bus

D08 to D15 I/O pins for the upper 8 bits of the external data bus

Power supply Digital circuit power supply pin Power supply Digital circuit power supply (GND) pins

This function is available when the external bus 8-bit mode is selected.

This function is available when the 16-bit bus mode is selected.

* :FPT-80P-M05

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MB90242A Series

I/O CIRCUIT TYPE

Type Circuit Remarks

A • 32 MHz

• Oscillation feedback resistor: approx. 1 M Ω

Clock stop input

Clock input

B • CMOS-level hysteresis input

(without standby control) Pull-up resistor: approx. 50 k Ω

Diffused resistor

VCC

CMOS

P-channel-type Tr N-channel-type Tr

Digital input

C • CMOS-level input

VCC

(without standby control)

P-channel-type Tr N-channel-type Tr

Diffused resistor

VSS

Digital input

CMOS

D • CMOS-level hysteresis input

(without standby control)

VCC

P-channel-type Tr N-channel-type Tr

Diffused resistor

VSS

Digital input

CMOS

(Continued)

MB90242A Series

Type Circuit Remarks

E • CMOS-level output

• TTL-Level input

Digital output

(with standby control)

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Digital output

Digital input

TTL

Standby control signal

F • CMOS-level input

CMOS-level hysteresis input

Digital output

Digital input

CMOS

Standby control signal

(with standby control)

G • CMOS-level output

CMOS-level hysteresis input

Digital output

Standby control (when interrupt disabled) available

Digital output

Digital input

CMOS

Standby interrupt disabled

⊃

H • N-ch open-drain

CMOS-level output

Digital output

CMOS-level hysteresis input Analog input (with analog input control)

Analog output Digital input

ADER

CMOS

(Continued)

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MB90242A Series

(Continued)

Type Circuit Remarks

I • CMOS-level input

Analog input

Digital output

• CMOS-level hysteresis input (with standby control)

CMOS

Standby control signal

Digital output

Analog input

Digital output

MB90242A Series

HANDLING DEVICES

1. Preventing Latchup

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Latchup may occur on CMOS ICs if voltage higher than V

or lower than V

pins other than medium-and high voltage pins or if higher than the voltage is applied between V

is applied to the input or output

and V

When latchup occurs, power supply current increases rapidly might thermally damage elements. When using, take great care not to exceed the absolute maximum ratings.

In addition, for the same reasons take care to prevent the analog power supply from exceeding the digital power supply.

2. Treatment of Unused Pins

Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down resistors.

3. Precautions when Using an External Clock

When an external clock is used, drive X0 only and X1 should be left open.

• Using an External Clock

MB90242A

4. Power Supply Pins

When there are several V within the device when the device is designed in order to prevent misoperation, such as latchup. However, all of those pins must be connected to the power supply and ground externally in order to reduce unnecessary emissions, prevent misoperation of strobe signals due to an increase in the ground level, and to observe the total output current standards.

In addition, give a due consideration to the connection in that current supply be connected to V the lowest possible impedance.

Finally, it is recommended to connect a capacitor of about 0.1 µ F between V bypass capacitor.

and V

pins, those pins that should have the same electric potential are connected

and V

near this device as a

and V

with

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MB90242A Series

5. Crystal Oscillation Circuit

Noise in the vicinity of the X0 and X1 pins will cause this device to operate incorrectly. Design the printed circuit board so that the bypass capacitor connecting X0, X1 and the crystal oscillator (or ceramic oscillator) to ground is located as close to the device as possible.

In addition, because printed circuit board artwork in which the area around the X0 and X1 pins is surrounded by ground provides stable operation, such an arrangement is strongly recommended.

6. CLK Pin

ex. 32 MHz

* : In the external bus mode, the P50/CLK pin is initially configured as a CLK output pin.

Divide by 2 circuit

P50/CLK*

STOP

P50 output P50 input

7. Cautions in Applying Power Supply

Hold the HST When the RST pin is in the “L” level, do not hold the HST pin to “L” level.

pin to the “H” level when applying power supply.

to internal blocks

CLK output

MB90242A Series

BLOCK DIAGRAM

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SCK0 SID0 SOD0

SCK1 SID1 SOD1

AV AVRH AVRL

AV AN0 to AN3 AN6 AN7 ATG

TIN0, TIN1

TOT0, TOT1

UART

Simple serial

2 2

A/D converter

Multiply/accumulate

module

16-bit

timer × 3

MC-16F bus

16-bit timer

ICU × 4

I/O port × 38

External bus interface

MC-16F

CPU

16 24

ASR0 to ASR3

P00 to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P63, P66, P67, P70 to P75

P80 to P82 D00 to D15 A00 to A23

CLK RDY HAK

HRQ WRH WRL RD

INT0 to INT3

X0 X1 RST HST MD2 to MD0

RAM

External interrupt

timer × 4

Clock controller

ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

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MB90242A Series

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= AV

Value

Parameter

Symbol

Unit Remarks

Min. Max.

CC VSS – 0.3 VSS + 7.0 V

Power supply voltage

AVCC VCC – 0.3 VCC + 7.0 V Input voltage VI*VSS – 0.3 VCC + 0.3 V Output voltage VO*VSS – 0.3 VCC + 0.3 V “L” level output current IOL  10 mA “L” level average output current IOLAV  4mA “L” level total average output current ΣIOLAV  50 mA “H” level output current IOH  –10 mA “H” level average output current IOHAV  –4 mA “H” level total average output current ΣIOHAV  –48 mA Power consumption PD  600 mW Operating temperature TA –30 +70 °C Storage temperature Tstg –55 +150 °C

* :V

and V

must not exceed V

+ 0.3 V.

= 0.0 V)

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

2. Recommended Operating Conditions

(VSS = AVSS = 0.0 V)

Parameter

Power supply voltage V

Operating temperature T

Symbol

A –30 +70 °C External bus mode

WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All

the device’s electrical characteristics are warranted when operated within these ranges. Always use semiconductor de vices within the recommended operating conditions . Operation outside

these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.

Value

Min. Max.

4.5

2.0

5.5

Unit Remarks

V V

For retaining RAM data in the stop mode

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MB90242A Series

3. DC Characteristics

(VCC = 5.0 V ±10%, VSS = AVSS = 0.0 V, TA = –30°C to +70°C)

Parameter Symbol Pin name Condition

IH1 — — 0.7 VCC — VCC + 0.3 V CMOS input

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

“H” level input current

“L” level input current

Pull-up resistor RPULL RST VCC = 5.0 V 22 — 110 kΩ

Power supply current

Input capacitance CIN Open-drain

output leakage current

VIH2 — — 2.2 — VCC + 0.3 V TTL input VIHIS — — 0.8 VCC — VCC + 0.3 V Hysteresis input VIHM MD0 to MD2 — VCC – 0.3 — VCC + 0.3 V

VIL1 ——VSS – 0.3 — 0.3 VCC V CMOS input

VIL2 ——VSS – 0.3 — 0.8 V TTL input VILIS ——VSS – 0.3 — 0.2 VCC V Hysteresis input VILM MD0 to MD2 — VSS – 0.3 — VSS + 0.3 V

All ports except

VOH

P60 to P63, P66, P67

VOL All ports

IIH1 Except RST

IIH2 —

IIH3 —

IIL1 Except RST

IIL2 —

IIL3 —

ICC VCC

ICCS VCC

ICCH VCC

Except VCC, VSS

P60 to P63,

ILEAK

P66, P67

VCC = 4.5 V IOH = –4.0 mA

VCC = 4.5 V IOL = 4.0 mA

VCC = 5.5 V VIH = 0.7 VCC

VCC = 5.5 V VIH = 2.2 V

VCC = 5.5 V VIH = 0.8 VCC

VCC = 5.5 V VIL = 0.3 VCC

VCC = 5.5 V VIL = 0.8 VCC

VCC = 5.5 V VIL = 0.2 VCC

VCC = 5.0 V ±10% FC = 32 MHz

VCC = 5.0 V ±10% FC = 32 MHz In sleep mode

VCC = 5.0 V ±10% TA = +25°C In stop mode

— — 10 — pF

— — 0.1 10 µA

Min. Typ. Max.

VCC – 0.5 ——V

— — 0.4 V

— — –10 µA CMOS input

— — –10 µA TTL input

— — –10 µA Hysteresis input

——10µA CMOS input

——10µA TTL input

——10µAHysteresis input

— 80 100 mA

—3050mA

— 0.1 10 µA

Value

Unit Remarks

In operation mode

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