CMOS 8-BANK x 262,144-WORD x 32 BIT, FCRAM Core Based
Synchronous Dynamic Random Access Memory
with Double Data Rate
DESCRIPTION
■■■■
The Fujitsu MB81P643287 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) with Fujitsu
advanced FCRAM (F ast Cycle Random Access Memory) Core Technology, containing 67,108,864 memory cells
accessible in an 32-bit format. The MB81P643287 features a fully synchronous operation referenced to clock
edge whereby all operations are synchronized at a cloc k input which enables high performance and simple user
interface coe xistence. The MB81P643287 is designed to reduce the complexity of using a standard dynamic RAM
(DRAM) which requires many control signal timin.g constraints. The MB81P643287 uses Double Data Rate (DDR)
where data bandwidth is twice of fast speed compared with regular SDRAMs.
The MB81P643287 is ideally suited for Digital Visual Systems, High Performance Graphic Adapters, Hardware
Accelerators, Buffers, and other applications where large memor y density and high effective bandwidth are
required and where a simple interface is needed.
The MB81P643287 adopts new I/O interface circuitry, SSTL_2 interface, which is capable of extremely fast data
transfer of quality under either terminated or point to point bus environment.
CL = 23.75 ns Min.4.5 ns Min.
Random Address Cycle Time30 ns Min.36 ns Min.
DQS Access Time From Clock0.1 × t
Operating Current460 mA Max.405 mA Max.
Power Down Current35 mA Max.
Note: FCRAM is a trademark of Fujitsu Limited, Japan.
Device Deselect*4DESLHHXXXXXXX
No Operation*4NOPHLHHHXXXX
Burst Stop*5BSTHLHHLXXXX
Read*6READHLHLHVLXV
Read with Auto-precharge*6 READAHLHLHVHXV
Write*6WRITHLHLLVLXV
Write with Auto-precharge*6 WRITAHLHLLVHXV
Bank Active (RAS
Precharge Single Bank*8PREHLLHLVLXX
Precharge All Banks*8PALLHLLHLVHXX
Mode Register Set/
Extended Mode Register Set
)*7ACTVHLLHHVVVV
*8,9,10
Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.
*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the rising edge of clock(CLK).
*4. NOP and DESL commands have the same effect on the part.
Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
*5. BST is effective after READ command is issued.
*6. READ , READ A, WRIT and WRITA commands should only be issued after the corresponding bank has
been activated (ACTV command). Refer to “■ STATE DIAGRAM”.
*7. ACTV command should only be issued after corresponding bank has been page closed by PRE or
PALL command.
*8. Either PRE or PALL command and MRS or EMRS command are required after power up.
*9. MRS or EMRS command should only be issued after all banks have been page closed (PRE or PALL
command), and DQs are in Hi-Z. Refer to “■ STATE DIAGRAM”.
*10. Refer to“■ MODE REGISTER TABLE”.
6
DM TRUTH TABLE (Effective during Write mode)
FunctionCommand
(n - 1)(n)
CKE
MB81P643287-50/-60
DM
0
DM
1
DM
2
DM
3
Data Mask for DQ
Data Mask for DQ
Data Mask for DQ
0 to DQ7MASK0HXHXXX
8 to DQ15MASK1HXXHXX
16 to DQ23MASK2HXXXHX
*11: The REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL
command). In case of SELF command, it should also be issued after the last read data have been appeared
on DQ. Refer to “■ STATE DIAGRAM”.
*12: CKE must bring to Low level together with REF command.
*13: The PDEN command should only be issued after the last read data have been appeared on DQ and after the
l
DPL is satisfied from last write data input.
7
MB81P643287-50/-60
OPERATION COMMAND TABLE (Applicable to single bank)(Note*13)
Current
State
Idle
RAS CAS WEAddressCommandFunctionNotes
CS
HXXXXDESL NOP
LHHHXNOPNOP
LHHLXBSTNOP*15
LHLHBA, CA, APREAD/READA Illegal*16
LHLLBA, CA, APWRIT/WRITAIllegal*16
LLHHBA, RAACTVBank Active after l
LLHLBA, APPRENOP
LLHLBA, APPALLNOP*15
LLLHXREF/SELFAuto-refresh or Self-refresh*17
RCD
Bank Active
LLLL MODE MRS
HXXXXDESL NOP
LHHHXNOPNOP
LHHLXBSTNOP*15
LHLHBA, CA, APREAD/READA Begin Read; Determine AP
LHLLBA, CA, APWRIT/WRITABegin Write; Determine AP
LLHHBA, RAACTVIllegal*16
LLHLBA, APPREPrecharge
LLHLBA, APPALLPrecharge*15
LLLHXREF/SELFIllegal
LLLL MODE MRS Illegal
Mode Register Set
(Idle after l
MRD)
*17
8
OPERATION COMMAND TABLE (Continued)
Current
State
CS
RAS CAS WEAddressCommandFunctionNotes
HXXXXDESL
MB81P643287-50/-60
NOP (Continue Burst to End →
Bank Active)
Read
Write
LHHHXNOP
LHHLXBSTTerminate Burst → Bank Active
LHLHBA, CA, APREAD/READA
LHLLBA, CA, APWRIT/WRITAIllegal
LHHHXNOPNOP (Idle after l
LHHLXBSTNOP (Idle after l
RP)
RP)*15
LHLHBA, CA, APREAD/READA Illegal*16
LHLLBA, CA, APWRIT/WRITAIllegal*16
LLHHBA, RAACTVIllegal*16
LLHLBA, APPRENOP*16
LLHLBA, APPALLNOP*15
LLLHXREF/SELFIllegal
LLLL MODE MRS Illegal
HXXXXDESLNOP (Bank Active after l
LHHHXNOPNOP (Bank Active after l
LHHLXBSTNOP (Bank Active after l
RCD)
RCD)
RCD)*15
LHLHBA, CA, APREAD/READA Illegal*16
LHLLBA, CA, APWRIT/WRITAIllegal*16
LLHHBA, RAACTVIllegal*19
LLHLBA, APPREIllegal*16
LLHLBA, APPALLIllegal
LLLHXREF/SELFIllegal
LLLL MODE MRS Illegal
11
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
CS
RAS CAS WEAddressCommandFunctionNotes
Write
Recovering
Write
Recovering
with Autoprecharge
HXXXXDESLNOP (Bank Active after l
LHHHXNOPNOP (Bank Active after l
LHHLXBSTNOP (Bank Active after l
WRD)
WRD)
WRD)*15
LHLHBA, CA, APREAD/READA Illegal*16
LHLLBA, CA, APWRIT/WRITANew Write; Determine AP
LLHHBA, RAACTVIllegal*16
LLHLBA, APPREIllegal*16
LLHLBA, APPALLIllegal
LLLHXREF/SELFIllegal
LLLL MODE MRS Illegal
HXXXXDESLNOP (Idle after l
LHHHXNOPNOP (Idle after l
WAL)
WAL)
LHHLXBSTIllegal
LHLHBA, CA, APREAD/READA Illegal*16
LHLLBA, CA, APWRIT/WRITAIllegal*16
LLHHBA, RAACTVIllegal*16
LLHLBA, APPREIllegal*16
LLHLBA, APPALLIllegal
Refreshing
LLLHXREF/SELFIllegal
LLLL MODE MRS Illegal
HXXXXDESLNOP (Idle after l
LHHXXNOP/BSTNOP (Idle after l
LHLXX
LLHXX
LLLXX
READ/READA/
WRIT/WRITA
ACTV/
PRE/PALL
REF/SELF/
MRS
Illegal
Illegal
Illegal
RFC)
RFC)
12
MB81P643287-50/-60
OPERATION COMMAND TABLE (Continued)
Current
State
Mode
Register
Setting
Abbreviations: RA = Row Address BA = Bank Address
Notes: *14. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.
*15. Entry may affect other banks.
*16. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state
*17. Illegal if any bank is not idle.
*18. Must mask preceding data that don‘t satisfy lDPL.
*19. Legal if other bank specified in BA is idle state and lRRD is satisfied for that bank.
*20. Must mask preceding data that don‘t satisfy lWRD.
Exit Self-refresh
(Self-refresh Recovery →
Idle after t
PDEX + lSCD or lXSNR)
Exit Self-refresh
(Self-refresh Recovery →
Idle after t
PDEX + lSCD or lXSNR)
SCD or lXSNR
Selfrefresh
Recovery
Power
Down
HHLHHHXI dle after lSCD or lXSNR
HHLHHLXIllegal
HHLHLXXIllegal
HHLLXXXIllegal
HLXXXX XIllegal
HXXXXX XInvalid
LHHXXX X
LHLHHH X
Power Down Exit → Return to original
state after t
PDEX
Power Down Exit → Return to original
state after tPDEX
LHLHHLXIllegal
LHLHLXXIllegal
LHLLXXXIllegal
LLXXXX XNOP (Maintain Power Down Mode)
14
COMMAND TRUTH TABLE FOR CKE (continued)
Current
State
All
Banks
Idle
CKE
(n-1)
CKE
(n)
HHHXXX XNOP
HHLHXXVRefer to the Command Truth Table.
HHLLHXVRefer to the Command Truth Table.
HHLLLHXAuto-refresh
HHLLLL VMode Register Set*21
HLHXXXXPower Down Entry*22
HLLHHHXPower Down Entry*22
HLLHHLXIllegal
HLLHLXXIllegal
HLLLHXXIllegal
HLLLLH XSelf-refresh Entry*22
HLLLLL XIllegal
RASCASWEAddressFunctionNotes
CS
MB81P643287-50/-60
Bank Active
LXXXXX XInvalid
HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal
LHXXXX XInvalid
LLXXXX XInvalid
15
MB81P643287-50/-60
COMMAND TRUTH TABLE FOR CKE (continued)
Current
State
CKE
(n-1)
CKE
(n)
RASCASWEAddressFunctionNotes
CS
Bank
Activating,
Read, Write,
Write
Recovering,
Precharging
Any State
Other Than
Listed Above
Refresh
Notes: *21. Refer to “■ MODE REGISTER TABLE”.
*22. PDEN and SELF command should only be issued after the last read data have been appeared on DQ.
*23. The Clock Suspend mode is not supported on this device and it is illegal if CKE is brought to Low during
HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal*23
LHXXXX XInvalid
LLXXXX XInvalid
LXXXXX XInvalid
HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal*23
HLHLLLXIllegal
HLLHHHXIllegal
HLLHHLXIllegal
HLLHLXXIllegal
HLLLXXXIllegal
LLXXXX XInvalid
LHXXXX XInvalid
HHXXXX XRefer to the Command Truth Table.
the Burst Read or Write mode.
16
MB81P643287-50/-60
STATE DIAGRAM
■■■■
MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION
Second command
(same bank)
First
command
MRS
MRS ACTV READ
l
MRDlMRDlMRDlMRDlMRDlMRDlMRD
READA
WRIT
WRITA
BST
*1
PREPALLREFSELF
ACTV
READ
READA
WRIT
WRITA
BST
PRE
PALL
lRCD*4lRCDlRCD*4lRCD1lRASlRAS
*5, 6
BL/2
+ l
RP
BL/2
+ l
*6
lWALlWAL
*5, 6
RP
* 4
1
lWRD
*7
lWRD1
1
*4, 7
11*3lBSNC*3lBSNC1
lRWD
* 3
*3, 4
lRWD1
* 4
1
1
BL/2
+ l
RP
lDPL
*4
*4
*4,7
*4
1
BL/2
+ l
RP
lDPL
*4
*4
BL/2
+ l
*4,7
lWAL*4lWAL*6lWAL
*4
1
*4
1
lRPlRP11*41
*5
lRPAlRPA111lRPA
lRP
RP
*6
*5, 6
BL/2
+ l
RP
*6
lWAL
*6
*5, 6
lRP
*5
lRPA
REF
SELFX
Notes: *1. BL/2 = t
*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. l
RAS must be satisfied.
*5. Assume all outputs are in High-Z state.
*6. Assume all other banks are in idle state.
*7. l
DPL and lWRD are specified from last data input and assumed preceding pair of write data are masked
by DM
Illegal Command
l
RFClRFClRFClRFClRFClRFClRFC
l
XSNRlXSNRlXSNRlXSNRlXSNRlXSNRlXSNR
CK× BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)
0 toDM3 input.
17
MB81P643287-50/-60
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION
Second command
(other bank)
First
command
MRS
*8
*10
MRS ACTV
l
MRDlMRDlMRDlMRDlMRDlMRDlMRD
READ
*8
READA
WRIT
*8
WRITA
*8
BST
*9
PREPALLREFSELF
*2, 9
ACTV
READ
READA
WRIT
WRITA
BST
PRE
PALL
*5, 6
BL/2 +
l
RP
lWAL
*5, 6
lRP
*6
lRRD
*6
111
*6
1
*6
1
*6
*6
1
*6
1
*6
1
*5
*11
1
*11
1
*11
1
* 3
*11
1
*11
11lRAS
lRWD*3lRWD11*41
*4
1
*7
*4
* 3, 4
1
lRWD
* 3, 4
lRWD1BL/2 +
lWRD*7lWRD111
BL/2
+ l
1
1
*4
WRD
*11
*11
*4
BL/2
+ l
WRD
1
*111*3, 11
lBSNC
*111*3, 111*3, 11
*4
*4
11lWAL*6lWAL
*3, 11
lBSNC11*41
*11
1
11*41
l
RP
lDPL
*4,7
lRPAlRPA111lRPA
BL/2 +
l
RP
lRP
*6
*6
*5, 6
BL/2 +
l
RP
lWAL
*5, 6
lRP
lRPA
*6
*5
18
REF
SELFX
l
RFClRFClRFClRFClRFClRFClRFC
l
XSNRlXSNRlXSNRlXSNRlXSNRlXSNRlXSNR
MB81P643287-50/-60
Notes: *1. BL/2 = t
*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. l
RAS must be satisfied.
*5. Assume all outputs are in High-Z state.
*6. Assume the other bank(s) is in idle state.
*7. l
DPL and lWRD are specified from last data input and assumed preceding pair of write data are masked
by DM
*8. Assume the other bank(s) is in active state and l
*9. Assume the other bank(s) is in active state and l
*10. Second command have to follow the minimum clock latency or delay time of single bank operation in
other bank (second command is asserted.)
*11. Assume other banks are not in READA/WRITA state.
Illegal Command.
CK× BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)
0 to DM3 input.
RCD is satisfied.
RAS is satisfied.
19
MB81P643287-50/-60
Fig. 2 - STATE DIAGRAM (Simplified for Single Bank Operation)
MODE
REGISTER
SET
POWER
DOWN
WRIT
PDEX
WRITE
MRS
PDEN
WRIT
WRITA
WRIT
IDLE
ACTV
BANK
ACTIVE
READA
READ
READ
SELF
SELFX
REF
BST
READ
SELF-
REFRESH
AUTO
REFRESH
READ
20
POWER
ON
APPLIED
with PDEN
WRITA
WITH AUTO
PRECHARGE
PDEX and 8 PRE (or 1 PALL)
POWER
WRITE
READA
PRE or
PALL
PRECHARGE
DEFINITION OF ALLOWS
Manual
Input
WRITA
PALL
PRE or
PRE or
PALL
READA
READ WITH
AUTO
PRECHARGE
Automatic
Sequence
MB81P643287-50/-60
FUNCTIONAL DESCRIPTION
■■■■
DDR, Double Data Rate Function
The regular SDRAM read and write cycle have only used the rising edge of external clock input. When clock
signal goes to High from Low at the read mode, the read out data will be available at every rising clock edge
after the specified latency up to burst length. The MB81P643287 DDR FCRAM features a twice of data tr ansf er
rate within a same clock period by transferring data at every rising and falling clock edge. Refer to Figure 3.
FCRAM
TM
The MB81P643287 utilizes FCRAM core technology. The FCRAM is an acronym of F ast Cycle Random Access
Memory and provides very fast random cycle time, low latency and lo w power consumption than regular DRAMs.
CLOCK INPUT (CLK, CLK
)
The MB81P643287 adopts differential clock scheme. CLK is a master clock and its rising edge is used to latch
all command and address inputs. CLK
is a complementary clock input.
The MB81P643287 implements Delay Lock ed Loop (DLL) circuit. This internal DLL tracks the signal cross point
between CLK and CLK
and generate some clock cycle delay for the output buffer control at Read mode.
The internal DLL circuit requires some Lock-on time for the stable delay time generation. In order to stabilize
the delay, a constant stable clock input f or l
stable clock input f or l
SCD period is also required after Self-refresh exit as specified lSCD prior to the any command.
PCD period is required during the Power-up initialization and a constant
POWER DOWN (CKE)
CKE is a synchronous input signal and enables power down mode.
When all banks are in idle state, CKE controls P ower Down (PD) and Self-refresh mode. The PD and Self-refresh
is entered when CKE is brought to Low and exited when it returns to High.
During the Power Down and Self-refresh mode, both CLK and CLK
are disabled after specified time.
CKE does not have a Cloc k Suspend function unlike CKE pin of regular SDRAMs, and it is illegal to bring CKE
into Low if any read or write operation is being performed. For the detail, refer to Timing Diagrams.
It is recommended to maintain CKE to be Low until V
DD gets in the specified operating range in order to assure
the power-up initialization.
CHIP SELECT (CS
CS
enables all commands inputs, RAS, CAS , and WE, and address input. When CS is High, all command signals
)
are negated but internal operation such as burst cycle will not be suspended.
COMMAND INPUTS (RAS
As well as regular SDRAMs, each combination of RAS
, CAS and WE)
, CAS and WE input in conjunction with CS input at a
rising edge of the CLK determines SDRAM operation. Refer to “■FUNCTION TRUTH TABLE”.
21
MB81P643287-50/-60
BANK ADDRESS (BA
0
to BA
2
)
The MB81P643287 has eight internal banks and each bank is organized as 256K words by 32-bit.
Bank selection by BA occurs at Bank Active command (A CTV) f ollowed by read (READ or READA), write (WRIT
or WRITA), and Precharge(PRE) command.
ADDRESS INPUTS (A
0
to A10)
Address input selects an arbitrary location of a total of 2,097,152 words of each memory cell matrix within each
bank. A total of twenty address input signals are required to decode such a matrix. DDR SDRAM adopts an
address multiplexer in order to reduce the pin count of the address line. At a Bank Active command (ACTV),
eleven Ro w addresses are initially latched as well as three Bank addresses and the remainder of se ven Column
addresses are then latched by a Column address strobe command of either a read command (READ or READ A)
or write command (WRIT or WRITA).
DATA STROBE (DQ S
DQS
0 to DQS3 are bi-directional signal and represent byte 0 to byte 3, respectiv ely . During Read operation, DQS0
0
to DQS3)
to DQS3 provides the read data strobe signal that is intended to use input data strobe signal at the receiver
circuit of the controller(s). It turns Low before first data is coming out and toggle High to Low or Low to High till
end of burst read. Refer to Figure 3 for the timing example.
The CAS Latency is specified to the first Low to High transition of these DQS
During the write operation, DQS
behavior of read data strobe, the first rising edge of DQS
falling edge of DQS
count. Therefore, DQS
Note that DQS
0 to DQS3 signal latches second input data. This sequence shall be continued till end of burst
0 to DQS3 must be provided from controller that drives write data.
0 to DQS3 input signal should not be tristated from High at the end of write mode.
0 to DQS3 are used to latch write data and Data Mask signals. As well as the
0 to DQS3 input latches first input data and following
0 to DQS3 output.
0
DATA INPUTS AND OUTPUTS (DQ
Input data is latched by DQS
command input. Output data is obtained together with DQS
to DQ31)
0 to DQS3 input signal and written into memory at the clock following the write
0 to DQS3 output signals at programmed read CAS
latency.
The polarity of the output data is identical to that of the input. Data is valid after DQS
transitions (t
WRITE DATA MASK (DM
DM
0 to DM3 are active High enable inputs and represent byte 0 to byte 3 respectively. DM0 to DM3 have a data
input mask function, and are also sampled by DQS
During write cycle, DM
QSQ) as specified in Data Valid Time (tDV).
0
to DM3)
0 to DQS3 input signal together with input data.
0 to DM3 provide byte mask function. When DMx = High is latched by a DQS0 to DQS3
0 to DQS3 output signal
signal edge, data input at the same edge of DQS0 to DQS3 is masked.
During read cycle, all DM
Refer to DM
0 to DM3 TRUTH TABLE.
0 to DM3 are inactive and do not have any effect on read operation.
22
MB81P643287-50/-60
BURST MODE OPERATION AND BURST TYPE
The burst mode provides f aster memory access and MB81P643287 read and write operations are b urst oriented.
The burst mode is implemented by k eeping the same Row address and b y automatic strobing Column address
in every single clock edge till progr ammed b urst length(BL). Access time of b urst mode is specified as t
internal column address counter operation is determined by a mode register which defines burst type(BT) and
burst count length(BL) of 2, 4 or 8 bits of boundary . In order to terminate or to mov e from the current b urst mode
to the next stage while the remaining burst count is more than 2, the following combinations will be required.
Current StageNext StageMethod (Assert the following command)
Burst ReadBurst ReadRead Command
ACC. The
1st Step
Burst Stop Command (BST)
Burst Read Burst Write
2nd StepWrite Command after l
BSNC
Burst WriteBurst WriteWrite Command
1st Step
Data Mask Input
Burst WriteBurst Read
2nd StepRead Command after l
WRD from last data input
Burst ReadPrechargePrecharge Command
1st Step
Data Mask Input
Burst WritePrecharge
2nd StepPrecharge Command after l
DPL from last data input
The burst type is sequential only. The sequential mode is an incremental decoding scheme within a boundary
address to be determined by count length, it assigns +1 to the previous (or initial) address until reaching the end
of boundary address and then wraps round to the least significant address(= 0). If the first access of column
address is even (0), the next address will be odd (1), or vice-versa.
The Burst Stop command (BST) terminates the burst read operation except f or a case that Auto-precharge option
is asserted. When the BST command is issued during the burst read operation, the all output buffers, DQs and
DQS
0 to DQS3, will turn to High-Z state after some latencies that to be matched with programmed CAS latency
and internal bank state remains active state.
In a case of terminating the burst write operation, the BST command should not be issued at any time during
burst write operation. Refer to previous page for the write interrupt and termination rule.
PRECHARGE AND PRECHARGE OPTION (PRE, PALL)
The DDR SDRAM memory core is the same as conventional DRAMs’, requiring precharge and refresh operations. Precharge rewrites the bit line and to reset the internal Row address line and is ex ecuted by the precharge
operation (PRE or PALL). With the precharge operation, DDR SDRAM will automatically be in standby state
after specified precharge time (l
The precharged bank is selected by combination of AP and bank address (BA) when precharge command is
issued. If AP = High, all banks are precharged regardless of BA (PALL command). If AP = Low, a bank to be
selected by BA is precharged (PRE command).
The auto-precharge enters precharge mode at the end of burst mode of read or write without Precharge command
issue. This auto-precharge is entered by AP = High when a Read (READ) or Write (WRIT) command is issued.
Applying BST is illegal if the Auto-precharge option is used.
Refer to “■FUNCTION TRUTH TABLE”.
RP, lRPA).
AUTO-REFRESH (REF)
Auto-refresh uses the internal refresh address counter. The MB81P643287 Auto-refresh command (REF) automatically generates Bank Active and Precharge command internally. All banks of SDRAM should be precharged prior to the Auto-refresh command. The Auto-refresh command should also be issued within every 8
µs period.
SELF-REFRESH ENTRY (SELF)
Self-refresh function provides automatic refresh by an internal timer as well as Auto-refresh and will continue
the refresh operation until cancelled by SELFX.
The Self-refresh mode is entered by applying an Auto-refresh command in conjunction with CKE = Lo w (SELF).
Once MB81P643287 enters the self-refresh mode, all inputs except f or CKE can be either logic high or low le v el
state and outputs will be in a High-Z state. During Self-refresh mode, CKE = Low should be maintained. SELF
command should only be issued after last read data has been appeared on DQ.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
prior to the self-refresh mode entry.
SELF-REFRESH EXIT (SELFX)
To exit Self-refresh mode, CKE must bring to High for at least 2 clock cycles together with NOP condition.
Refer to Timing Diagram f or the detail procedure. It is recommended to issue at least one A uto-refresh command
just after the l
WARNING: A stable clock for l
RFC period to avoid the violation of refresh period.
SCD period with a constant duty cycle must be supplied prior to applying any read
command to insure the DLL is locked against the latest device conditions.
Note: When the burst refresh method is used, a total of 4096 auto-refresh commands within 4 ms must be asserted
both before the self-refresh entry and after the self-refresh exit.
24
MB81P643287-50/-60
MODE REGISTER SET (MRS)
The mode register of SDRAM provides a variety of different operations. The register consists of four operation
fields; Burst Length, Burst Type, CAS Latency, and Test Mode Entry (This Test Mode Entry must not be used).
Refer to MODE REGISTER TABLE.
The mode register can be programmed by the Mode Register Set command (MRS). Each field is set by the
address line. Once a mode register is programmed, the contents of the register will be held until re-progr ammed
by another MRS command (or part loses power). MRS command should only be issued on condition that all
banks are in idle state and all DQS are in High-Z. The condition of the mode register is undefined after the powerup stage. It is required to set each field at power-up initialization.
Refer to POWER-UP INITIALIZATION below.
Note: The Extended Mode Register Set command (EMRS) and its DLL Enable function of EMRS field is only used
at power-on sequence.
POWER-UP INITIALIZATION
The MB81P643287 internal condition at and after power-up will be undefined. It is required to follow the f ollowing
Power On Sequence to execute read or write operation.
1.Apply V
signals to be Low state (or at least CKE to be Low state).
2.Apply V
3.Apply VREF and VTT. (VTT is applied to the system).
4.Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200 µs.
5.After the minimum of 200 µs stable power and clock, apply NOP condition and take CKE to be High
state.
6.Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every
banks.
7.Issue EMRS to enable DLL, DE = Low.
8.Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for l
period is required to lock the DLL.
9.Apply minimum of two Auto-refresh command (REF).*
10. Program the mode register by Mode Register Set command (MRS) with DR = Low.*
DD voltage to all VDD pins before or at the same time as VDDQ pins and attempt to maintain all input
DD voltage to all VDDQ pins before or at the same time as VREF and VTT.
PCD*
2
2
1
*1:The l
PCD depends on operating clock period. The lPCD is counted from “DLL Reset” at step-8 to any command
input at step-10.
*2:The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
POWER-DOWN
The MB81P643287 uses multiple power supply v oltage . It is required to follow the reversed sequence of above
Power On Sequence.
*3: These RESERVED field in EMRS must be set as 0.
RESERVED *
0
A
0DLL Enable
1DLL Disable
3
DLL Enable (DE)
0
DE
27
MB81P643287-50/-60
ABSOLUTE MAXIMUM RATINGS (See WARNING)
■■■■
ParameterSymbolValueUnit
Voltage of V
Voltage at Any Pin Relative to V
Short Circuit Output CurrentI
DD Supply Relative to VSSVDD, VDDQ–0.5 to +3.6V
SSVIN, VOUT–0.5 to +3.6V
OUT±50mA
Power DissipationPD2.0W
Storage TemperatureT
STG–55 to +125°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
■■■■
(Referenced to VSS)
ParameterNotesSymbolMin.Typ.Max.Unit
V
DD2.32.52.7V
Supply Voltage
V
DDQVDDVDDVDDV
V
SS, VSSQ000V
Input Reference Voltage*1VREFVDDQ × 0.49 VDDQ × 0.5 VDDQ × 0.51V
Termination Voltage*2V
Single Ended SSTL DC Level Input High Voltage*3V
Single Ended SSTL DC Level Input Low Voltage*3V
TTVREF - 0.04VREFVREF + 0.04V
IH (DC)VREF + 0.25—VDDQ + 0.1V
IL (DC)- 0.1—VREF - 0.25V
Single Ended SSTL AC Level Input High Voltage *3, *5VIH (AC)VREF + 0.35——V
Single Ended SSTL AC Level Input Low Voltage *3, *5V
Differential DC Level Input Voltage Range*3V
IL (AC)——VREF - 0.35V
IN (DC)- 0.1—VDDQ + 0.1V
Differential DC Level Differential Input Voltage*3 VSWING (DC)0.5—VDDQ + 0.2V
Differential AC Level Differential Input Voltage*3 V
Differential AC Level Input Crosspoint Voltage*3V
Notes: *1. VREF is expected to track variations in the DC level of VDDQ of the transmitting device. Peak-to-Peak
noise level on V
*2. V
TT is used for SSTL_2 bus and is not applied to the device. VTT is expected to be set equal to VREF
and must be track variations in the DC level of VREF.
*3. Applicable when signal(s) is terminated to the V
*4. V
ISO means {VIN(CLK) + VIN(CLK)} / 2. Refer to Differential Input Signal Definition.
*5. Overshoot limit: V
50% of pulse amplitude.
*6. Undershoot limit: V
50%of pulse amplitude.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
REF may not exceed ± 2% of the supplied DC va lue.
TT of SSTL_2 bus.
IH (Max.) = VDD + 1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
IL (Min.) = VSS -1.0V for pulse width ≤ 4 ns acceptable, pulse width measured at
Differential Input Signal Definition
Fig. 4 - Differential Input Signal Offset Voltage (For Clock Input)
DQ Output in High-ZtHZ-0.70.7-0.80.8-1.01.0-1.11.1-1.31.3ns
DQ & DM Input Pulse Widtht
DQS Falling Edge to Clock Hold
Time
DQS Falling Edge to Clock
Setup Time
DIPW2.0—2.4—3.0—3.6—4.2—ns
t
DSCH1.5—1.5—1.5—1.8—2.1—ns
tDSCS1.5—1.5—1.5—1.8—2.1—ns
34
MB81P643287-50/-60
LATENCY
(The latency values on these parameters are fixed regardless of clock period.)
ParameterNotes
Symbol
MB81P643287-50MB81P643287-60
Min.Max.Min.Max.
Unit
RAS
Cycle Time *13
RAS Active Time
RAS Precharge TimelRP2—2—tCK
RAS to CAS Delay Time
RAS to RAS Bank Active Delay TimelRRD1—1—tCK
Precharge All Bank to Active
Read Command to Write
Command Delay
Last Input Data to Read Command *14
Delay
Last Input Data to Precharge Command
Lead Time *14
Write with Auto Precharge Command to
Active command Delay *14
Mode Register Access to Next Command
Input Delay
CL = 3
lRC
CL = 25—5—tCK
CL = 3
lRAS
CL = 23733337333tCK
CL = 3
lRCD
CL = 22—2—tCK
CL = 3
lRPA
CL = 23—3—tCK
CL = 3
lRWD
CL = 2BL/2+2—BL/2+2—tCK
lWRD2.5—2.5—tCK
lDPL2.5—2.5—tCK
lWALBL/2+3+lRP—BL/2+3+lRP—tCK
lMRD2—2—tCK
6—6—tCK
411000411000tCK
3—3—tCK
4—4—tCK
BL/2+3—BL/2+3—tCK
CAS to CAS DelaylCCD1—1—tCK
CAS Bank DelaylCBD1—1—tCK
Precharge Power Down Exit to Next
Command Input Delay
Minimum Stable Clock Input After Self- *15
refresh Exit Before READ Command Input
Minimum Stable Clock Input After Self-
refresh Exit Before non-READ Command
Input
Minimum Stable Clock Input for
DLL Lock-on in Power-up
Initialization sequence. *16
Auto-refresh Cycle TimelRFC12—12—tCK
tCK≤ 7.5ns
tCK≤ 10.5ns630—630—tCK
lPDEXP2—2—tCK
lSCD400—400—tCK
l
XSNR12—12—tCK
400—400—tCK
l
PCD
35
MB81P643287-50/-60
LATENCY - FIXED VALUES
(The latency values on these parameters are fixed regardless of clock period.)
ParameterNotes Symbol MB81P643287-50MB81P643287-60Unit
BST Command to Output in High-Z
BST Command to New Command Input *17
DM to Input Data DelaylDQD00tCK
Precharge to Output in High-Z
CKE Low to Command/Address Input InactivelCKE11tCK
CL = 3
CL = 222tCK
CL = 3
CL = 222tCK
CL = 3
CL = 222tCK
l
BSH
lBSNC
lROH
33tCK
33tCK
33tCK
36
MB81P643287-50/-60
Notes: *1. AC characteristics are measured after f ollowing the POWER-UP INITIALIZATION procedure and stab le
clock input with constant clock period and with 50% duty cycle.
*2. Access Times assume input slew rate of 1ns/volt between V
V
DDQ/2, with SSTL_2 output load conditions. Refer to AC TEST LOAD CIRCUIT.
*3. V
REF = 1.25V is a typical reference level for measuring timing of input signals.
Transition times are measured between V
IH(Min.) and VIL(Max.) unless otherwise noted.
Refer to AC TEST CONDITIONS.
*4. This parameter is measured from the cross point of CLK and CLK
*5. This parameter is measured from signal transition point of DQS
*6. The specific requirement is that DQS be valid (HIGH or LOW) on or before this CLK edge. The case
shown (DQS going from High-Z to logic LOW) applies when no writes were previously in progress on
the bus. If a previous write was in progress, DQS could be HIGH at this time, depending on t
*7. t
T is defined as the transition time between VIH (AC)(Min.) and VIL (AC)(Max.).
*8. Total of 4096 REF command must be issued within t
REF (Max.). tAREF is a reference value f or distrib uted
refresh and specifies the time between one REF command to next REF command e xcept for a condition
where CKE = Low during Self-refresh mode.
*9. This parameter is scalable by actual clock period (t
jitters on clock input, T
A and level of VDD and VDDQ.The internal DLL circuit can adjust delay time against
CK) and affected by an abrupt change of duty cycle,
the change of following condition :
T
A < 0.1 °C / 20 ns,
V
DD < 1 mV / 10 ns,
V
DDQ < 1 mV / 10 ns,
if change rate is bigger than these values, frequency dependent A C par ameters aff ected b y DLL jitters.
*10. More than 2 signal edge of DQS
0 toDQS3 should not be input within 1 clock (tCK) cycle.
*11. Low-Z (Low Impedance State) is specified and measured at V
*12. t
QSPST, tQSHZ and tHZ are specified where output buffer is no longer driven.
*13. Actual clock count of l
*14. Assume t
DQSS = 1 × tCK. If actual tDQSS is within specified minimum and maximum range, those par ameters
can be assumed t
RC will be sum of clock count of lRAS and lRP.
DQSS = 1 × tCK.
*15. Applicable also if device oper ating conditions such as supply voltages , case temperature , and/or cloc k
frequency (t
*16. Clock period must satisfy specified t
CK difference must be 0.2 ns or less) is changed during any operation.
CK and it must be stable.
*17. Assume BST is effective to read operation (issued prior to the end of burst read).
REF+0.35V to VREF-0.35V, where VREF is
input.
0 toDQS3 input crossing VREF level.
DSS.
TT± 200mV.
37
MB81P643287-50/-60
Fig. 5 - AC TEST LOAD CIRCUIT (SSTL_2, Class II)
Output
measurement
point
RS = 25 Ω
Output
VDDQ
0.5 × V
DDQ
Device
Under
Test
V
DDQ
VREF
Z0 = 50 Ω
TT = 0.5 × VDDQVTT = 0.5 × VDDQ
V
RT2 = 50 ΩRT1 = 50 Ω
VREF = 0.5 × VDDQ
CL = 20 pF
V
SS
Note: AC characteristics are measured in this condition. This load circuit is not applicable f or DC Test.
AC TEST CONDITIONS
ParametersSymbolValueUnit
Single-end Input
Input High Level V
Input Low Level V
Note: Back to back Write with A uto-precharge (WRITA) command to the different bank in active state
is possible. However, an y new command to the same bank applied WRITA command can only
be issued after l
WAL.
MB81P643287-50/-60
TIMING DIAGRAM - 16: AUTO-REFRESH ENTRY AND EXIT
CLK
CLK
IRFC (Min.)
Command
REF
NOPAny
TIMING DIAGRAM - 17: SELF-REFRESH ENTRY AND EXIT
IRFC (Min.)
CKE
t
QCKEHtIStPDEXIXSNR or ISCD *
CLK
CLK
Command
DQS (Output)
DQ
0 toDQ31
(Output)
Q
NOP
Hi-Z
Hi-Z
SELF
Last Data Output
Don't Care
Note * :CKE must maintain High level and stable clock must be provided during the l
After Self-refresh exit, l
XSNR must be satisfied for at least specified period before any command
(except for read) input.
ACTVNOPNOP
SCD period.
TIMING DIAGRAM - 18: MODE REGISTER SET
CLK
CLK
IMRD
Command
NOP
MRS
NOP
Any
Note: MRS command must be issued after the last data is appeared on each DQ.
51
MB81P643287-50/-60
SCITT TEST MODE
■■■■
ABOUT SCITT
SCITT (Static Component Interconnection Test Technology) is an XNOR circuit based test technology that is
used for testing interconnection between SDRAM and SDRAM controller on the printed circuit boards. SCITT
provides inexpensiv e board level test mode in combination with boundary-scan. The basic idea is simple, consider
all output of SDRAM as output of XNOR circuit and each output pin has a unique mapping on the input of
SDRAM. The ideal schematic block diagram is as shown below.
TEST
Control
µC
SDRAM
Boundary
Scan
xAddress
Bus
XNOR
CORE
ASIC
SDRAM Controller
Data Bus
TEST Control : CAS, CS, CKE
xAddress Bus : A
0 to A10, BA0 to BA2, RAS, DM0 to DM3, CLK, CLK, WE
Data Bus: DQ0 to DQ31, DQS0 to DQS3
It is static and provides easy test pattern that result in a high diagnostic resolution for detecting all open/short
faults.
52
MB81P643287-50/-60
SCITT TEST SEQUENCE
The followings are the SCITT test sequence. SCITT Test can be executed after power-on and prior to Precharge
command in“■ FUNCTION DESCRIPTION POWER-UP INITIALIZATION”. Once Precharge command is issued
to SDRAM, it never get back to SCITT Test Mode during regular operation unless reset power supply for the
purpose of a fail-safe way in get in and out of test mode.
1.Maintain all input signals (except CLK,CLK
CLK and CLK
to be complementary state.
2.Apply VDD voltage to all VDD pins before or at the same time as VDDQ pins.
3.Apply V
4.Apply V
DD voltage to all VDDQ pins before or at the same time as VREF and VTT.
REF and VTT (VTT is applied to the system).
5.Maintain stable power for a minimum of 100µs.
6.Enter SCITT test mode.
7.Execute SCITT test.
8.Exit from SCITT mode.
It is required to follow Power On Sequence to execute read or write operation.
9.Start clock after all power supplies reached in a specified operating range and maintain stable condition
for a minimum of 200µs.
10. After the minimum of 200µs stable power and clock, apply NOP condition and take CKE to be High
state.
11. Issue Precharge All Banks (PALL) command or Precharge Single Bank (PRE) command to every
banks.
12. Issue EMRS to enable DLL, DE = Low.
13. Issue Mode Register Set command (MRS) to reset DLL, DR = High. An additional clock input for l
period is required to lock the DLL.
14. Apply minimum of two Auto-refresh command (REF).*
15. Program the mode register by Mode Register Set command (MRS) with DR = Low.*
The 6,7,8 steps define the SCITT mode available. It is possible to skip these steps if necessary (Refer to “■ FUNCTION DESCRIPTION POWER-UP INITIALIZATION”).
) to be Low state (or at least CKE to be Low) and maintain
PCD*
2
2
1
Notes: *1. The l
command input at step-15.
*2. The Mode Register Set command (MRS) can be issued before two Auto-refresh cycle.
PCD depends on operating clock period. The lPCD is counted from “DLL Reset” at step-13 to any
53
MB81P643287-50/-60
COMMAND TRUTH TABLE Note *1
ControlInputOutput
0
DM
10
,
to
2
DM
3
CAS
CSCKEWERAS
A
BA
0
to A
0
to BA
SCITT mode entry H→L *2LL X XXX
SCITT mode exitL→H *
SCITT mode
output enable *
4
LLHVV VVVVVV
3
H *5L
*5
XX XXXXXX
Notes: *1. L = Logic Low, H = Logic High, V = Valid, X = either L or H
*2. The SCITT mode entry command assumes the first CAS
falling edge with CS = CKE = L and CLK,CLK
signals are complementary after power on.
*3. The SCITT mode exit command assumes the first CAS
rising edge after the test mode entry.
*4. Refer the test code table.
*5. CS
= H or CKE = L is necessary to disable outputs in SCITT mode exit.
CLKCLK
HL
LH
DQ
to
DQ
0
31
DQS
to
DQS
0
3
XX
54
MB81P643287-50/-60
TEST CODE TABLE
DQ
0 to DQ31 and DQS0 to DQS3 output data is static and is determined by following logic during the SCITT mode
EPDTest mode exit to power on sequence delay time10—ns
tTLZCS, CKE to output in Low-Z time0—ns
t
THZCS, CKE to output in High-Z time020ns
t
TCA
Test mode access time from control signals
(clock enable & chip select)
—40ns
tTIATest mode Input access time—20ns
t
TOHTest mode Output Hold time0—ns
t
ETDTest mode entry to test delay time10—ns
tTIHTest mode input hold time30—ns
56
TIMING DIAGRAMS
V
DD
CS
CKE
MB81P643287-50/-60
TIMING DIAGRAM - 1: POWER-UP TIMING DIAGRAM
100 µs Pause Time
Test Mode Entry Point
CAS
CLK
CLK
or
CLK
CLK
*1
*2
*3
t
ETD
Notes: *1. CAS shall be staid either High or Low at power on.
*2 . All output buffers maintains in High-Z state regardless of the state of control signals e xcept
for CAS
*3. CAS
as long as the above timing is maintained.
must not be brought from High to Low.
57
MB81P643287-50/-60
TIMING DIAGRAM - 2 : SCITT TEST ENTRY AND EXIT *1
VCC
Pause 100 µs
t
TStTHtEPDTest Mode
Next power on sequence
and normal operation
CAS
CS
PD
CLK
CLK
or
H L
L
L
*3
tETD
58
CLK
CLK
*2
Entry
Exit
Notes: *1. If entry and exit operation have not been done correctly, CAS , CS, CKE pins will ha ve some
problems.
*2. PRE or PALL commands must not be asserted. Test mode is disable by those commands.
*3. Outputs must be disabled by CS
= H or CKE = L before Exit.
MB81P643287-50/-60
TIMING DIAGRAM - 3: OUTPUT CONTROL (1)
VDD
CAS
CS
CKE
DQ
DQS0 to DQS3
0 to DQ31
Memory device
output buffer status
This is not bus line level
Entry
DQ turn to Low-Z at CS = L and CKE = H
High-Z
CAS must not brought from High to Low
DQ turn to High-Z at CS = H
t
THZtTLZ
Time (b)Time (a)Time (c)
High-ZLow-ZHigh-Z
VDD
CAS
CS
CKE
DQ
0 to DQ31
DQS0 to DQS3
Memory device
output buffer status
This is not bus line level
TIMING DIAGRAM - 4: OUTPUT CONTROL (2)
Entry
CAS must not brought from High to Low
DQ turn to Low-Z at CS = L and CKE = H
High-Z
DQ turn to High-Z at CKE = L
t
THZtTLZ
High-ZLow-ZHigh-Z
Time (b)Time (a)Time (c)
59
MB81P643287-50/-60
TIMING DIAGRAM - 5: TEST TIMING (1)
CAS
CS
CKE
Under
Check
Pins
DQ0 to DQ31
DQS0 to DQS3
A0
A1
A2
Test mode
Entry Command
tETD
Test mode
Entry
Under test
DQ becomes Low-Z at CS = L and CKE = H
tTCA
tTIA
Valid
tTIA
tTOHtTOH
Valid
tTIA
Valid
tTLZ
60
MB81P643287-50/-60
TIMING DIAGRAM - 6: TEST TIMING (2)
CAS
CS-#1
CS-#2
CKE
Under
Check
Pins
A
A1
A2
Test mode
Entry
L
L
H
Tested #1 device
tTIHtTIH
0
Under test
tTIAtTIAtTIA
Changed under test devices
Tested #2 device
tTCA
tTLZ
tTHZ
tTIA
t
TIH
Test mode
Exit
tTIA
DQ
0 to DQ31
DQS0 to DQS3
tTOHtTOH
ValidValidValid
Valid
tTOH
Valid
61
MB81P643287-50/-60
TIMING DIAGRAM - 7: TEST TIMING (3)
CAS
CS-#1
CS-#2
CKE
Under
Check
Pins
A
A1
A2
Test mode
Entry
L
L
H
Tested #1 device
tTIHtTIH
0
Under test
tTIAtTIAtTIA
Changed under test devices
Tested #2 device
tTHZ
tTCA
tTLZ
tTIA
t
TIH
Test mode
Exit
tTIA
DQ
0 to DQ31
DQS0 to DQS3
tTOHtTOH
ValidValidValid
Valid
tTOH
Valid
62
ORDERING INFORMATION
■■■■
Part numberPackageRemarks
MB81P643287-50FN
MB81P643287-60FN
86-pin plastic TSOP(II)
(FPT-86P-M01)
MB81P643287-50/-60
63
MB81P643287-50/-60
PACKAGE DIMENSIONS
■■■■
86-pin plastic TSOP (II)
(FPT-86P-M01)
8644
INDEX
LEAD No.
1
0.22
.009 –.002
0.50(.020)TYP
+0.05
–0.04
+.002
22.22±0.10(.875±.004)*
0.10(.004)
21.00(.827)REF
M
0.10(.004)
43
(.004±.002)
(STAND OFF)
*: Resin protrusion.(Each side: 0.15 (.006) Max.)
Details of "A" part
0.25(.010)
0.45/0.75
(.018/.030)
1.20(.047)MAX
(Mounting height)
0.10±0.05
0~8°
11.76±0.20(.463±.008)
10.16±0.10(.400±.004)
"A"
0.145
.006 –.001
+0.05
–0.03
+.002
C
1996 FUJITSU LIMITED F86001S-1C-1
Dimensions in mm (inches).
MB81P643287-50/-60
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://www.fujitsu.co.jp/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
FUJITSU MICROELECTRONICS ASIA PTE. LTD.
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTRONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in standard
applications (computers, office automation and other office
equipments, industrial, communications, and measurement
equipments, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage, or
where extremely high levels of reliability are demanded (such as
aerospace systems, atomic energy controls, sea floor repeaters,
vehicle operating controls, medical devices for life support, etc.)
are requested to consult with FUJITSU sales representatives before
such use. The company will not be responsible for damages arising
from such use without prior approval.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
F0010
FUJITSU LIMITED Printed in Japan
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