FUJITSU MB81P643287-50, MB81P643287-60 DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

DS05-11402-2E

MEMORY

CMOS

TM

8 x 256K x 32 BIT, FCRAM

CORE

BASED DOUBLE DATA RATE SDRAM

MB81P643287-50/-60

CMOS 8-BANK x 262,144-WORD x 32 BIT, FCRAM Core Based

Synchronous Dynamic Random Access Memory

with Double Data Rate

DESCRIPTION

■■■■

The Fujitsu MB81P643287 is a CMOS Synchronous Dynamic Random Access Memory (SDRAM) with Fujitsu
advanced FCRAM (F ast Cycle Random Access Memory) Core Technology, containing 67,108,864 memory cells
accessible in an 32-bit format. The MB81P643287 features a fully synchronous operation referenced to clock
edge whereby all operations are synchronized at a cloc k input which enables high performance and simple user
interface coe xistence. The MB81P643287 is designed to reduce the complexity of using a standard dynamic RAM
(DRAM) which requires many control signal timin.g constraints. The MB81P643287 uses Double Data Rate (DDR)
where data bandwidth is twice of fast speed compared with regular SDRAMs.

The MB81P643287 is ideally suited for Digital Visual Systems, High Performance Graphic Adapters, Hardware
Accelerators, Buffers, and other applications where large memor y density and high effective bandwidth are
required and where a simple interface is needed.

The MB81P643287 adopts new I/O interface circuitry, SSTL_2 interface, which is capable of extremely fast data
transfer of quality under either terminated or point to point bus environment.

PRODUCT LINE

■■■■

Clock Frequency

Burst Mode Cycle Time

MB81P643287

Parameter

-50 -60

CL = 3 200 MHz Max. 167 MHz Max.
CL = 2 133 MHz Max. 111 MHz Max.
CL = 3 2.5 ns Min. 3.0 ns Min.

CL = 2 3.75 ns Min. 4.5 ns Min.
Random Address Cycle Time 30 ns Min. 36 ns Min.
DQS Access Time From Clock 0.1 × t
Operating Current 460 mA Max. 405 mA Max.
Power Down Current 35 mA Max.

Note: FCRAM is a trademark of Fujitsu Limited, Japan.

CK + 0.2 ns Max. 0.1 × tCK + 0.2 ns Max.

MB81P643287-50/-60

FEATURES

■■■■

• Double Data Rate

• Bi-directional Data Strobe Signal

• Eight bank operation

• Burst read/write operation

• Programmable burst length and CAS latency

• Byte write control by DM

• Standby Power Down Mode

PACKAGE

■■■■

0 to DM3

• 4096 Auto-refresh cycles in 32 ms

• SSTL_2 (class 2) for all signals

DD: +2.5V Supply ± 0.2V tolerance

•V

•VDDQ: +2.5V Supply ± 0.2V tolerance

86-pin plastic TSOP(II)

(FPT-86P-M01)

(Normal Bend)

2

PIN ASSIGNMENTS

■■■■

MB81P643287-50/-60

86-pin TSOP (II)

(TOP VIEW)

(Normal Bend)

VDD

DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7

DQS0

VDD

DM0

WE
CAS
RAS

CS
BA
BA0
BA1

A10/AP

A
A1
A2

DM2

VDD

DQS2

DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

2

21
22
23
24

0

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
DQS1
VSS
DM1
VREF
CLK
CLK
CKE
A

9

A8
A7
A6
A5
A4
A3
DM3
VSS
DQS3
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS

(FPT-86P-M01)

3

MB81P643287-50/-60

DESCRIPTIONS

■■■■

Pin Number Symbol Function

1, 3, 9, 15, 29, 35, 41, 43, 49, 55, 75, 81 V

DD, VDDQ Supply Voltage

6, 12, 32, 38, 44, 46, 52, 58, 72, 78, 84, 86 V

2, 4, 5, 7, 8, 10, 11, 13, 31, 33, 34, 36, 37, 39,

40, 42, 45, 47, 48, 50, 51, 53, 54, 56, 74, 76,

77, 79, 80, 82, 83, 85

14, 30, 57, 73 DQS0 to DQS3 Data Strobe

16, 28, 59, 71 DM0 to DM3 Input Mask

17 WE
18 CAS
19 RAS Row Address Strobe
20 CS

21, 22, 23 BA

24 AP Auto Precharge Enable

24, 25, 26, 27, 60, 61, 62, 63, 64, 65, 66 A

67 CKE Power Down

SS, VSSQ Ground

• Byte 0: DQ

0 to DQ31 Data I/O

DQ

• Byte 1: DQ8 to DQ15

• Byte 2: DQ16 to DQ23

• Byte 3: DQ24 to DQ31

•DQS

•DQS1: for DQ8 to DQ15

•DQS2: for DQ16 to DQ23

•DQS3: for DQ24 to DQ31

Write Enable
Column Address Strobe

Chip Select

2, BA1, BA0 Bank Select (Bank Address)

0 to A10 Address Input

•Row: A

• Column: A0 to A6

0 to DQ7

0: for DQ0 to DQ7

0 to A10

68 CLK Clock Input
69 CLK

Clock Input

70 VREF Input Reference Voltage

4

BLOCK DIAGRAM

■■■■

CLK
CLK

CLOCK

BUFFER

MB81P643287-50/-60

Fig. 1 - MB81P643287 BLOCK DIAGRAM

To each block

CKE

CS

RAS

CAS

WE

AP

A

0 to A10

BA0, BA1,

BA2

Enable

COMMAND

DECODER

ADDRESS

BUFFER/

REGISTER

CONTROL

SIGNAL

LATCH

MODE

REGISTER

11

RAS

CAS

WE

ROW
ADDRESS

Bank-7

Bank-1

Bank-0

DRAM
CORE

(2048 × 128 × 32)

DM0 to

DM3

DQ0 to

DQ

DQS0 to

DQS3

COLUMN
ADDRESS
COUNTER

I/O DATA
BUFFER/

31

REGISTER

&

DQS

GENERATOR

V

DDQ, VSSQ

DLL

Clock Buffer

32

7

COLUMN
ADDRESS

I/O

DD

V
VREF

VSS/VSSQ

5

MB81P643287-50/-60

FUNCTION TRUTH TABLE (Note*1)

■■■■

MRS/

EMRS

2-0

RAS CAS WE BA

HLL LLV L VV

10/

A

AP A

9-7A6-0

COMMAND TRUTH TABLE (Note *2, and *3)

Function Notes Symbol CKE CS

Device Deselect *4 DESL H H X X X X X X X
No Operation *4 NOP H L H H H X X X X
Burst Stop *5 BST H L H H L X X X X
Read *6 READ H L H L H V L X V
Read with Auto-precharge *6 READA H L H L H V H X V
Write *6 WRIT H L H L L V L X V
Write with Auto-precharge *6 WRITA H L H L L V H X V
Bank Active (RAS
Precharge Single Bank *8 PRE H L L H L V L X X
Precharge All Banks *8 PALL H L L H L V H X X
Mode Register Set/

Extended Mode Register Set

)*7ACTVHLLHHVVVV

*8,9,10

Notes: *1. V = Valid, L = Logic Low, H = Logic High, X = either L or H, Hi-Z = High Impedance.

*2. All commands are assumed to be valid state transitions.
*3. All inputs for command are latched on the rising edge of clock(CLK).
*4. NOP and DESL commands have the same effect on the part.

Unless specifically noted, NOP will represent both NOP and DESL command in later descriptions.
*5. BST is effective after READ command is issued.
*6. READ , READ A, WRIT and WRITA commands should only be issued after the corresponding bank has

been activated (ACTV command). Refer to “■ STATE DIAGRAM”.
*7. ACTV command should only be issued after corresponding bank has been page closed by PRE or

PALL command.
*8. Either PRE or PALL command and MRS or EMRS command are required after power up.
*9. MRS or EMRS command should only be issued after all banks have been page closed (PRE or PALL

command), and DQs are in Hi-Z. Refer to “■ STATE DIAGRAM”.
*10. Refer to“■ MODE REGISTER TABLE”.

6

DM TRUTH TABLE (Effective during Write mode)

Function Command

(n - 1) (n)

CKE

MB81P643287-50/-60

DM

0

DM

1

DM

2

DM

3

Data Mask for DQ
Data Mask for DQ
Data Mask for DQ

0 to DQ7 MASK0HXHXXX
8 to DQ15 MASK1 H X X H X X
16 to DQ23 MASK2HXXXHX

Data Mask for DQ24 to DQ31 MASK3 H X X X X H

CKE TRUTH TABLE

0

Current

State

Function Notes Command

CKE

(n-1)

(n)

RAS CAS WE AP

CS

BA0
BA

to

A

to

2

DQ

10

A

Idle Auto-refresh *11 REF H H L L L H X X X —
Idle Self-refresh Entry
Self-

refresh
Self-

refresh

Self-refresh Continue — L L X X X X X X X Hi-Z

Self-refresh Exit SELFX

*11
*12

SELF H L L L L H X X X Hi-Z

LHL H H H X X XHi-Z
LHH X X X X X XHi-Z

HLL H H H X X XHi-Z

Idle Power Down Entry *13 PDEN

HLHX X X X X XHi-Z

Power
Down

Power Down Continue — L L X X X X X X X Hi-Z

DQ

to

0

31

Power
Down

Power Down Exit PDEX

LHL H H H X X XHi-Z
LHH X X X X X XHi-Z

*11: The REF and SELF commands should only be issued after all banks have been precharged (PRE or PALL

command). In case of SELF command, it should also be issued after the last read data have been appeared

on DQ. Refer to “■ STATE DIAGRAM”.
*12: CKE must bring to Low level together with REF command.
*13: The PDEN command should only be issued after the last read data have been appeared on DQ and after the

l

DPL is satisfied from last write data input.

7

MB81P643287-50/-60

OPERATION COMMAND TABLE (Applicable to single bank)(Note*13)

Current

State

Idle

RAS CAS WE Address Command Function Notes

CS

HXXX X DESL NOP

LHHH X NOP NOP
L H H L X BST NOP *15
L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA Illegal *16
L L H H BA, RA ACTV Bank Active after l
L L H L BA, AP PRE NOP
L L H L BA, AP PALL NOP *15
L L L H X REF/SELF Auto-refresh or Self-refresh *17

RCD

Bank Active

LLLL MODE MRS

HXXX X DESL NOP

LHHH X NOP NOP
L H H L X BST NOP *15
L H L H BA, CA, AP READ/READA Begin Read; Determine AP
L H L L BA, CA, AP WRIT/WRITA Begin Write; Determine AP
L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Precharge
L L H L BA, AP PALL Precharge *15
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

Mode Register Set
(Idle after l

MRD)

*17

8

OPERATION COMMAND TABLE (Continued)

Current

State

CS

RAS CAS WE Address Command Function Notes

HXXX X DESL

MB81P643287-50/-60

NOP (Continue Burst to End →
Bank Active)

Read

Write

LHHH X NOP
L H H L X BST Terminate Burst → Bank Active
L H L H BA, CA, AP READ/READA
L H L L BA, CA, AP WRIT/WRITA Illegal

L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Terminate Burst, Precharge
L L H L BA, AP PALL Terminate Burst, Precharge *15
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

HXXX X DESL

LHHH X NOP
L H H L X BST Illegal
L H L H BA, CA, AP READ/READA

L H L L BA, CA, AP WRIT/WRITA

NOP (Continue Burst to End →
Bank Active)

Terminate Burst, New Read;
Determine AP

NOP (Continue Burst to End →
Write Recovering)

NOP (Continue Burst to End →
Write Recovering)

Terminate Burst, Start Read;
Determine AP

Terminate Burst, New Write;
Determine AP

*20

L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Terminate Burst, Precharge *18

L L H L BA, AP PALL Terminate Burst, Precharge
L L L H X REF/SELF Illegal

LLLL MODE MRS Illegal

*15,

*18

9

MB81P643287-50/-60

OPERATION COMMAND TABLE (Continued)

Current

State

CS

RAS CAS WE Address Command Function Notes

HXXX X DESL

NOP (Continue Burst to End →
Precharge)

Read With
Auto­Precharge

Write with
Auto
Precharge

LHHH X NOP
L H H L X BST Illegal

L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA Illegal
L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Illegal *16
L L H L BA, AP PALL Illegal
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

HXXX X DESL

LHHH X NOP
L H H L X BST Illegal

L H L H BA, CA, AP READ/READA Illegal
L H L L BA, CA, AP WRIT/WRITA Illegal *16
L L H H BA, RA ACTV Illegal *16

NOP (Continue Burst to End →
Precharge)

NOP (Continue Burst to End →
Write Recovering with Precharge)

NOP (Continue Burst to End →
Write Recovering with Precharge)

10

L L H L BA, AP PRE Illegal *16
L L H L BA, AP PALL Illegal
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

OPERATION COMMAND TABLE (Continued)

Current

State

CS

RAS CAS WE Address Command Function Notes

H X X X X DESL NOP (Idle after l

MB81P643287-50/-60

RP)

Precharging

Bank
Activating

L H H H X NOP NOP (Idle after l
L H H L X BST NOP (Idle after l

RP)
RP)*15

L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA Illegal *16
L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE NOP *16
L L H L BA, AP PALL NOP *15
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

H X X X X DESL NOP (Bank Active after l

L H H H X NOP NOP (Bank Active after l
L H H L X BST NOP (Bank Active after l

RCD)
RCD)
RCD)*15

L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA Illegal *16
L L H H BA, RA ACTV Illegal *19
L L H L BA, AP PRE Illegal *16
L L H L BA, AP PALL Illegal
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

11

MB81P643287-50/-60

OPERATION COMMAND TABLE (Continued)

Current

State

CS

RAS CAS WE Address Command Function Notes

Write
Recovering

Write
Recovering
with Auto­precharge

H X X X X DESL NOP (Bank Active after l

L H H H X NOP NOP (Bank Active after l
L H H L X BST NOP (Bank Active after l

WRD)
WRD)
WRD)*15

L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA New Write; Determine AP
L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Illegal *16
L L H L BA, AP PALL Illegal
L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

H X X X X DESL NOP (Idle after l

L H H H X NOP NOP (Idle after l

WAL)
WAL)

L H H L X BST Illegal
L H L H BA, CA, AP READ/READA Illegal *16
L H L L BA, CA, AP WRIT/WRITA Illegal *16
L L H H BA, RA ACTV Illegal *16
L L H L BA, AP PRE Illegal *16
L L H L BA, AP PALL Illegal

Refreshing

L L L H X REF/SELF Illegal
LLLL MODE MRS Illegal

H X X X X DESL NOP (Idle after l

L H H X X NOP/BST NOP (Idle after l
LHLX X

LLHX X

LLLX X

READ/READA/

WRIT/WRITA

ACTV/

PRE/PALL

REF/SELF/

MRS

Illegal

Illegal

Illegal

RFC)
RFC)

12

MB81P643287-50/-60

OPERATION COMMAND TABLE (Continued)

Current

State

Mode
Register
Setting

Abbreviations: RA = Row Address BA = Bank Address

Notes: *14. All entries assume the CKE was High during the proceeding clock cycle and the current clock cycle.

*15. Entry may affect other banks.
*16. Illegal to bank in specified state; entry may be legal in the bank specified by BA, depending on the state

*17. Illegal if any bank is not idle.
*18. Must mask preceding data that don‘t satisfy lDPL.
*19. Legal if other bank specified in BA is idle state and lRRD is satisfied for that bank.
*20. Must mask preceding data that don‘t satisfy lWRD.

CS

RAS CAS WE Address Command Function Notes

H X X X X DESL NOP (Idle after l

L H H H X NOP NOP (Idle after l
L H H L X BST Illegal

LHLX X

LLXX X

CA = Column Address AP = Auto Precharge

of that bank.

READ/READA/

WRIT/WRITA

ACTV/PRE/

PALL/REF/
SELF/MRS

MRD)
MRD)

Illegal

Illegal

13

MB81P643287-50/-60

COMMAND TRUTH TABLE FOR CKE

Current

State

Self­refresh

CKE
(n-1)

CKE

(n)

RAS CAS WE Address Function Notes

CS

HXXXXX XInvalid

LHHXXX X

LHLHHH X

L H L H H L X Illegal
L H L H L X X Illegal
L H L L X X X Illegal
LLXXXX XNOP (Maintain Self-refresh)
LXXXXX XInvalid

H H H X X X X Idle after l

Exit Self-refresh
(Self-refresh Recovery →
Idle after t

PDEX + lSCD or lXSNR)

Exit Self-refresh
(Self-refresh Recovery →
Idle after t

PDEX + lSCD or lXSNR)

SCD or lXSNR

Self­refresh
Recovery

Power
Down

H H L H H H X I dle after lSCD or lXSNR
H H L H H L X Illegal
H H L H L X X Illegal
H H L L X X X Illegal
HLXXXX XIllegal
HXXXXX XInvalid

LHHXXX X

LHLHHH X

Power Down Exit → Return to original
state after t

PDEX

Power Down Exit → Return to original

state after tPDEX
L H L H H L X Illegal
L H L H L X X Illegal
L H L L X X X Illegal
LLXXXX XNOP (Maintain Power Down Mode)

14

COMMAND TRUTH TABLE FOR CKE (continued)

Current

State

All
Banks
Idle

CKE
(n-1)

CKE

(n)

HHHXXX XNOP
H H L H X X V Refer to the Command Truth Table.
H H L L H X V Refer to the Command Truth Table.
H H L L L H X Auto-refresh
HHLLLL VMode Register Set *21
H L H X X X X Power Down Entry *22
H L L H H H X Power Down Entry *22
H L L H H L X Illegal
H L L H L X X Illegal
H L L L H X X Illegal
HLLLLH XSelf-refresh Entry *22
HLLLLL XIllegal

RAS CAS WE Address Function Notes

CS

MB81P643287-50/-60

Bank Active

LXXXXX XInvalid

HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal

LHXXXX XInvalid
LLXXXX XInvalid

15

MB81P643287-50/-60

COMMAND TRUTH TABLE FOR CKE (continued)

Current

State

CKE
(n-1)

CKE

(n)

RAS CAS WE Address Function Notes

CS

Bank
Activating,
Read, Write,
Write
Recovering,
Precharging

Any State
Other Than
Listed Above

Refresh

Notes: *21. Refer to “■ MODE REGISTER TABLE”.

*22. PDEN and SELF command should only be issued after the last read data have been appeared on DQ.
*23. The Clock Suspend mode is not supported on this device and it is illegal if CKE is brought to Low during

HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal *23

LHXXXX XInvalid
LLXXXX XInvalid
LXXXXX XInvalid

HHXXXX XRefer to the Command Truth Table.
HLXXXX XIllegal *23
H L H L L L X Illegal
H L L H H H X Illegal
H L L H H L X Illegal
H L L H L X X Illegal
H L L L X X X Illegal

LLXXXX XInvalid
LHXXXX XInvalid

HHXXXX XRefer to the Command Truth Table.

the Burst Read or Write mode.

16

MB81P643287-50/-60

STATE DIAGRAM

■■■■

MINIMUM CLOCK LATENCY OR DELAY TIME FOR SINGLE BANK OPERATION

Second command

(same bank)

First
command

MRS

MRS ACTV READ

l

MRD lMRD lMRD lMRD lMRD lMRD lMRD

READA

WRIT

WRITA

BST

*1

PRE PALL REF SELF

ACTV

READ

READA

WRIT

WRITA

BST

PRE

PALL

lRCD*4lRCD lRCD*4lRCD 1lRAS lRAS

*5, 6

BL/2

+ l

RP

BL/2

+ l

*6

lWAL lWAL

*5, 6

RP

* 4

1

lWRD

*7

lWRD 1

1

*4, 7

11*3lBSNC*3lBSNC 1

lRWD

* 3

*3, 4

lRWD 1

* 4

1

1

BL/2

+ l

RP

lDPL

*4

*4

*4,7

*4

1

BL/2

+ l

RP

lDPL

*4

*4

BL/2

+ l

*4,7

lWAL*4lWAL*6lWAL

*4

1

*4

1

lRP lRP 11*41

*5

lRPA lRPA 111lRPA

lRP

RP

*6

*5, 6

BL/2
+ l

RP

*6

lWAL

*6

*5, 6

lRP

*5

lRPA

REF

SELFX

Notes: *1. BL/2 = t

*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. l

RAS must be satisfied.

*5. Assume all outputs are in High-Z state.
*6. Assume all other banks are in idle state.
*7. l

DPL and lWRD are specified from last data input and assumed preceding pair of write data are masked

by DM

Illegal Command

l

RFC lRFC lRFC lRFC lRFC lRFC lRFC

l

XSNR lXSNR lXSNR lXSNR lXSNR lXSNR lXSNR

CK × BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)

0 to DM3 input.

17

MB81P643287-50/-60

MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTIPLE BANK OPERATION

Second command

(other bank)

First
command

MRS

*8

*10

MRS ACTV

l

MRD lMRD lMRD lMRD lMRD lMRD lMRD

READ

*8

READA

WRIT

*8

WRITA

*8

BST

*9

PRE PALL REF SELF

*2, 9

ACTV

READ

READA

WRIT

WRITA

BST

PRE

PALL

*5, 6

BL/2 +

l

RP

lWAL

*5, 6

lRP

*6

lRRD

*6

111

*6

1

*6

1

*6

*6

1

*6

1

*6

1

*5

*11

1

*11

1

*11

1

* 3

*11

1

*11

11lRAS

lRWD*3lRWD 11*41

*4

1

*7

*4

* 3, 4

1

lRWD

* 3, 4

lRWD 1 BL/2 +

lWRD*7lWRD 11 1

BL/2

+ l

1

1

*4

WRD

*11

*11

*4

BL/2

+ l

WRD

1

*111*3, 11

lBSNC

*111*3, 111*3, 11

*4

*4

1 1lWAL*6lWAL

*3, 11

lBSNC 11*41

*11

1

11*41

l

RP

lDPL

*4,7

lRPA lRPA 111lRPA

BL/2 +

l

RP

lRP

*6

*6

*5, 6

BL/2 +

l

RP

lWAL

*5, 6

lRP

lRPA

*6

*5

18

REF

SELFX

l

RFC lRFC lRFC lRFC lRFC lRFC lRFC

l

XSNR lXSNR lXSNR lXSNR lXSNR lXSNR lXSNR

MB81P643287-50/-60

Notes: *1. BL/2 = t

*2. Assume PALL command does not affect any operation on the other bank(s).
*3. Assume no I/O conflict.
*4. l

RAS must be satisfied.

*5. Assume all outputs are in High-Z state.
*6. Assume the other bank(s) is in idle state.
*7. l

DPL and lWRD are specified from last data input and assumed preceding pair of write data are masked

by DM
*8. Assume the other bank(s) is in active state and l
*9. Assume the other bank(s) is in active state and l
*10. Second command have to follow the minimum clock latency or delay time of single bank operation in

other bank (second command is asserted.)
*11. Assume other banks are not in READA/WRITA state.

Illegal Command.

CK × BL / 2. (Example: In case of BL = 4, BL/2 means 2 clocks.)

0 to DM3 input.

RCD is satisfied.
RAS is satisfied.

19

MB81P643287-50/-60

Fig. 2 - STATE DIAGRAM (Simplified for Single Bank Operation)

MODE

REGISTER

SET

POWER

DOWN

WRIT

PDEX

WRITE

MRS

PDEN

WRIT

WRITA

WRIT

IDLE

ACTV

BANK

ACTIVE

READA
READ

READ

SELF

SELFX

REF

BST

READ

SELF-

REFRESH

AUTO

REFRESH

READ

20

POWER

ON

APPLIED

with PDEN

WRITA

WITH AUTO

PRECHARGE

PDEX and 8 PRE (or 1 PALL)

POWER

WRITE

READA

PRE or

PALL

PRECHARGE

DEFINITION OF ALLOWS

Manual
Input

WRITA

PALL

PRE or

PRE or

PALL

READA

READ WITH

AUTO

PRECHARGE

Automatic
Sequence