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FR81
User Manual
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Fujitsu FR81 User Manual

FUJITSU MICROELECTRONICS CONTROLLER MANUAL
PROGRAMMING MANUAL
CM71-00105-1E
FR81 Family
32-BIT MICROCONTROLLER
FR81 Family
32-BIT MICROCONTROLLER
PROGRAMMING MANUAL
For the information for microcontroller supports, see the following web site.
FUJITSU MICROELECTRONICS LIMITED
PREFACE
■ Objectives and targeted reader
FR81 Family is a 32 bit single chip microcontroller with CPU of new RISC Architecture as the core. FR81 Family has specifications that are optimum for embedded use requiring high performance CPU processing power.
This manual explains the programming model and execution instructions for engineers developing a product using this FR81 Family Microcontroller, especially the programmers who produce program s using assembly language of the assembler for FR/FR80/FR81 Family.
For the rules of assembly grammar language and the method of use of Assembler Programs, kindly refer to "FR Family Assembler Manual".
*: FR, the abbreviation of Fujitsu RISC controller, is a line of products of Fujitsu Microel ectroni cs Limited. Other company names and brand names are the trademarks or registered trademarks of their respective
owners.
■ Organization of this Manual
This manual consists of the following 7 chapters and 1 supplement.
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
This chapter describes the features of FR81 Family CPU and its differences from hitherto FR Family.
CHAPTER 2 MEMORY ARCHITECTURE
This chapter describes Memory Architecture of the CPU of FR81 Family. Memory Architecture is the method of allocation of memory space and access to this memory space.
CHAPTER 3 PROGRAMMING MODEL
This chapter describes registers in the CPU existing as programming model of FR81 Family CPU.
CHAPTER 4 RESET AND "EIT" PROCESSING
This chapter describes resetting of FR81 Family CPU and EIT processing. EIT processing is the generic term for exceptions, interruption and trap.
CHAPTER 5 PIPELINE OPERATION
This chapter describes pipeline operation and delay divergence, the salient feature of FR81 Family CPU.
CHAPTER 6 INSTRUCTION OVERVIEW
This chapter describes outline of commands of FR81 Family CPU.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
This chapter describes Execution Instructions of FR81 Family CPU in Reference Format in the alphabetical order.
APPENDIX
It contains instruction list and instruction map of FR81 Family CPU.
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• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third­party's intellectual property right or other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.
• Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved.
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CONTENTS
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU ............................................................ 1
1.1 Features of FR81 Family CPU ............................................................................................................ 2
1.2 Changes from the earlier FR Family ................................................................................................... 4
CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 7
2.1 Address Space ................................................................................................................................... 8
2.1.1 Direct Address Area ..................................................................................................................... 8
2.1.2 Vector Table Area .......................................................................................................................... 9
2.1.3 20-bit Addressing Area & 32-bit Addressing Area ....................................................................... 11
2.2 Data Structure ................................................................................................................................... 12
2.2.1 Byte Data .............. ... ... .... ...................................... .... ... ... ....................................... . ..................... 12
2.2.2 Half Word Data ............................................... ... ... .... ... ....................................... ... ... .. ................. 12
2.2.3 Word Data ................................................................................................................................... 12
2.2.4 Byte Order .................. .... ... ... ....................................... ... ... .... ...................................................... 13
2.3 Word Alignment ................................................................................................................................ 14
2.3.1 Program Access ......................................................................................................................... 14
2.3.2 Data Access ............................................................................................................................... 14
CHAPTER 3 PROGRAMMING MODEL .......................................................................... 15
3.1 Register Configuration ...................................................................................................................... 16
3.2 General-purpose Registers ............................................................................................................... 17
3.2.1 Configuration of General-purpose Registers ............................................................................... 17
3.2.2 Special Usage of General-purpose Registers ............................................................................ 18
3.2.3 Relation between Stack Pointer and R15 .................................................................................... 18
3.3 Dedicated Registers ......................................................................................................................... 19
3.3.1 Configuration of Dedicated Registers .......................................................................................... 19
3.3.2 Program Counter (PC) ................................................................................................................. 20
3.3.3 Program Status (PS) ................................................................................................................... 20
3.3.4 System Status Register (SSR) .................................................................................................... 21
3.3.5 Interrupt Level Mask Register (ILM) ............................................................................................ 22
3.3.6 Condition Code Register (CCR) .................................................................................................. 23
3.3.7 System Condition Code Register (SCR) .................................................................................... 25
3.3.8 Return Pointer (RP) ..................................................................................................................... 26
3.3.9 System Stack Pointer (SSP) ....................................................................................................... 27
3.3.10 User Stack Pointer (USP) ............................................................................................................ 28
3.3.11 Table Base Register (TBR) ......................................................................................................... 29
3.3.12 Multiplication/Division Register (MDH, MDL) ............................................................................... 30
3.3.13 Base Pointer (BP) ........................................................................................................................ 32
3.3.14 FPU Control Register (FCR) ................................. ....................................... ... .... ... ...................... 32
3.3.15 Exception status register (ESR) .................................................................................................. 37
3.3.16 Debug Register (DBR) ................................................................................................................. 39
3.4 Floating-point Register ...................................................................................................................... 40
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CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 41
4.1 Reset ................................................................................................................................................ 42
4.2 Basic Operations in EIT Processing ................................................................................................. 43
4.2.1 Types of EIT Processing and Prior Preparation .......................................................................... 43
4.2.2 EIT Processing Sequence ........................................ ... ... ....................................... ... ... ... ............. 44
4.2.3 Recovery from EIT Processing .................................................................................................... 45
4.3 Processor Operation Status .............................................................................................................. 46
4.4 Exception Processing .......................... ....................................... ... ... ... ............................................. 48
4.4.1 Invalid Instruction Exception ........................................................................................................ 48
4.4.2 Instruction Access Protection Violation Exception ....................................................................... 49
4.4.3 Data Access Protection Violation Exception ................................................................................ 49
4.4.4 FPU Exception ... ... ... ... .... ...................................... .... ... ... ....................................... ... ................... 50
4.4.5 Instruction Break .......................................................................................................................... 51
4.4.6 Guarded Access Break ................................ ... ... ... .... ...................................... .... ... ... ................... 52
4.5 Interrupts .......................... ............. .......... ............. ............. ............. ............. ............ .......................... 53
4.5.1 General interrupts ........................................................................................................................ 53
4.5.2 Non-maskable Interrupts (NMI) ................................................................................................... 55
4.5.3 Break Interrupt ...... ... ... ....................................... ... .... ... ....................................... ... ...................... 55
4.5.4 Data Access Error Interrupt ......................................................................................................... 56
4.6 Traps ............................. .......... .......... ......... ....... ......... .......... .......... ......... .......... ................................ 57
4.6.1 INT Instructions ....................................... .... ... ... ....................................... ... ... .... ......................... 57
4.6.2 INTE Instruction ........................................................................................................................... 57
4.6.3 Step Trace Traps ........................................................................................................................ 58
4.7 Multiple EIT processing and Priority Levels ...................................................................................... 60
4.7.1 Multiple EIT Processing ............................................................................................................... 60
4.7.2 Priority Levels of EIT Requests ......... ... ....................................... ... ... .... ...................................... 61
4.7.3 EIT Acceptance when Branching Instruction is Executed ........................................................... 62
4.8 Timing When Register Settings Are Reflected ................................................................................. 63
4.8.1 Timing when the interrupt enable flag (I) is requested ................................................................ 63
4.8.2 Timing of Reflection of Interrupt Level Mask Register (ILM) ....................................................... 64
4.9 Usage Sequence of General Interrupts ............................................................................................ 65
4.9.1 Preparation while using general interrupts .................................................................................. 65
4.9.2 Processing during an Interrupt Processing Routine .................................................................... 66
4.9.3 Points of Caution while using General Interrupts ........................................................................ 66
4.10 Precautions .......................... .......................................... .......................................... ......................... 67
4.10.1 Exceptions in EIT Sequence and RETI Sequence ...................................................................... 67
4.10.2 Exceptions in Multiple Load and Multiple Store Instructions ....................................................... 67
4.10.3 Exceptions in Direct Address Transfer Instruction ....................................................................... 67
CHAPTER 5 PIPELINE OPERATION ............................................................................. 69
5.1 Instruction execution based on Pipeline ........................................................................................... 70
5.1.1 Integer Pipeline ............................................................................................................................ 70
5.1.2 Floating Point Pipeline ................................................................................................................. 72
5.2 Pipeline Operation and Interrupt Processin g .................................... ... ... .... ... ................................... 73
5.2.1 Mismatch in Acceptance and Cancellation of Interrupt ............................................................... 73
5.2.2 Method of preventing the mismatched pipeline conditions .......................................................... 73
5.3 Pipeline hazards ............................... ...................................... .... ... ... ................................................ 74
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5.3.1 Occurrence of data hazard .......................................................................................................... 74
5.3.2 Register Bypassing ............................... ... .... ... ... ... ....................................... ... .... ... ... ................... 74
5.3.3 Interlocking .................................................................................................................................. 75
5.3.4 Interlocking produced by reference to R15 after Changing the Stack flag (S) ............................ 75
5.3.5 Structural Hazard ......................................................................................................................... 75
5.3.6 Control Hazard ............................................................................................................................ 76
5.4 Non-block loading ............................................................................................................................. 77
5.5 Delayed branching processing ......................................................................................................... 78
5.5.1 Example of branching with non-delayed branching instructions .................................................. 78
5.5.2 Example of processing of delayed branching instruction ............................................................ 79
CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 81
6.1 Instruction System ............................ ...................................... .... ... ... ................................................ 82
6.1.1 Integer Type Instructions ............................................................................................................. 82
6.1.2 Floating Point Type Instructions .................................................................................................. 84
6.2 Instructions Formats ......................................................................................................................... 85
6.2.1 Instructions Notation Formats ...................................................................................................... 85
6.2.2 Addressing Formats .................................... ... ....................................... ... ... ... ............................. 86
6.2.3 Instruction Formats ...................................................................................................................... 87
6.2.4 Register designated Field .................................................................. .... ... ... ... .... ......................... 91
6.3 Data Format ...................................................................................................................................... 93
6.3.1 Data Format Used by Integer Type Instructions (Common with All FR Family) .......................... 93
6.3.2 Format Used for Floating Point Type Instructions ....................................................................... 94
6.4 Read-Modify-Write type Instructions ................................................................................................. 96
6.5 Branching Instructions and Delay Slot .............................................................................................. 97
6.5.1 Delayed Branching Instructions ................................................................................................... 97
6.5.2 Specific example of Delayed Branching Instructions ................................................................... 98
6.5.3 Non-Delayed Branching Instructions ........................................................................................... 99
6.6 Step Division Instructions ............................................................................................................... 100
6.6.1 Signed Division .......................................................................................................................... 100
6.6.2 Unsigned Division ...................................................................................................................... 101
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS .............................................. 103
7.1 ADD (Add 4bit Immediate Data to Destination Register) ................................................................ 105
7.2 ADD (Add Word Data of Source Register to Destination Register) ................................................ 107
7.3 ADD2 (Add 4bit Immediate Data to Destination Register) .............................................................. 109
7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ....................... 111
7.5 ADDN (Add Immediate Data to Destination Register) .................................................................... 113
7.6 ADDN (Add Word Data of Source Register to Destination Register) ............................................. 115
7.7 ADDN2 (Add Immediate Data to Destination Register) .................................................................. 117
7.8 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 119
7.9 AND (And Word Data of Source Register to Data in Memory) ....................................................... 121
7.10 AND (And Word Data of Source Register to Destination Register) ................................................ 123
7.11 ANDB (And Byte Data of Source Register to Data in Memory) ...................................................... 125
7.12 ANDCCR (And Condition Code Register and Immediate Data) ..................................................... 127
7.13 ANDH (And Halfword Data of Source Register to Data in Memory) ............................................... 129
7.14 ASR (Arithmetic shift to the Right Direction) ..... ... ... ... .... ...................................... .... ... ... ................. 131
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7.15 ASR (Arithmetic shift to the Right Direction) ..... ... ... ... .... ...................................... .... ... ... ................. 133
7.16 ASR2 (Arithmetic shift to the Right Direction) ................................................................................. 135
7.17 BANDH (And 4bit Immediate Data to Higher 4bit of Byte Data in Memory) ................................... 137
7.18 BANDL (And 4bit Immediate Data to Lower 4bit of Byte Dat a in Me m or y) .......................... ........... 139
7.19 Bcc (Branch relative if Condition satisfied) ..................................................................................... 141
7.20 Bcc:D (Branch relative if Condition satisfied) .................................................................................. 143
7.21 BEORH (Eor 4bit Immediate Data to Higher 4bit of Byte Data in Memory) .................................... 145
7.22 BEORL (Eor 4bit Immediate Data to Lower 4bit of Byte Data in Me mor y) .... ... ... ........................... 147
7.23 BORH (Or 4bit Immediate Data to Higher 4bit of Byte Data in Memory) ........................................ 149
7.24 BORL (Or 4bit Immediate Data to Lower 4bit of Byte Dat a in Me m or y) ........................................ . 151
7.25 BTSTH (Test Higher 4bit of Byte Data in Memory) ......................................................................... 153
7.26 BTSTL (Test Lower 4bit of Byte Data in Memory) .......................................................................... 155
7.27 CALL (Call Subroutine) .............. ... .... ... ... ... ....................................... ... ... .... ... ................................. 157
7.28 CALL (Call Subroutine) .............. ... .... ... ... ... ....................................... ... ... .... ... ................................. 159
7.29 CALL:D (Call Subroutine) ............................................................................................................... 161
7.30 CALL:D (Call Subroutine) ............................................................................................................... 163
7.31 CMP (Compare Immediate Data and Destination Register) ........................................................... 165
7.32 CMP (Compare Word Data in Source Register and Destination Register) .................................... 167
7.33 CMP2 (Compare Immediate Data and Destination Register) ......................................................... 169
7.34 DIV0S (Initial Setting Up for Signed Division) ................................................................................. 171
7.35 DIV0U (Initial Setting Up for Unsigned Division) ............................................................................. 173
7.36 DIV1 (Main Process of Division) ..................................................................................................... 175
7.37 DIV2 (Correction When Remain is zero) ........................................................................................ 177
7.38 DIV3 (Correction When Remain is zero) ........................................................................................ 179
7.39 DIV4S (Correction Answer for Signed Division) ............................................................................. 181
7.40 DMOV (Move Word Data from Direct Address to Register) ........................................................... 183
7.41 DMOV (Move Word Data from Register to Direct Address) ........................................................... 185
7.42 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) ....... 187
7.43 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) ....... 189
7.44 DMOV (Move Word Data from Direct Address to Pre Decrement Register Indirect Address) ....... 191
7.45 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) ....... 193
7.46 DMOVB (Move Byte Data from Direct Address to Register) .......................................................... 195
7.47 DMOVB (Move Byte Data from Register to Direct Address) .......................................................... 197
7.48 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) ...... 199
7.49 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) ...... 201
7.50 DMOVH (Move Halfword Data from Direct Address to Register) ................................................... 203
7.51 DMOVH (Move Halfword Data from Register to Direct Address) ................................................... 205
7.52 DMOVH (Move Halfword Data from Direct Address to Post Increment Register Indirect Address)
......................................................................................................................................................... 207
7.53 DMOVH (Move Halfword Data from Post Increment Register Indirect Address to Direct Address)
......................................................................................................................................................... 209
7.54 ENTER (Enter Function) ................... ... ... ... ... .... ...................................... .... ... ... ... ........................... 211
7.55 EOR (Exclusive Or Word Data of Source Register to Data in Memory) ......................................... 213
7.56 EOR (Exclusive Or Word Data of Source Register to Destination Register) .................................. 215
7.57 EORB (Exclusive Or Byte Data of Source Register to Data in Mem or y) ........................................ 217
7.58 EORH (Exclusive Or Halfword Data of Source Register to Data in Me m or y) ................................. 219
7.59 EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... 221
7.60 EXTSH (Sign Extend from Byte Data to Word Data) ........ ... ... .... ... ...................................... .... ... ... . 223
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7.61 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. 225
7.62 EXTUH (Unsign Extend from Byte Data to Word Data) .................................................................. 227
7.63 FABSs (Single Precision Floating Point Absolute Value) ............................................................... 229
7.64 FADDs (Single Precision Floating Point Add) ... ... ... ....................................... ... ... .... ....................... 230
7.65 FBcc (Floating Point Conditional Branch) ....................................................................................... 232
7.66 FBcc:D (Floating Point Conditional Branch with Delay Slot) .......................................................... 234
7.67 FCMPs (Single Precision Floating Point Compare) ........................................................................ 236
7.68 FDIVs (Single Precision Floating Point Division) .................................... .... ... ................................. 238
7.69 FiTOs (Convert from Integer to Single Precision Floating Point) .................................................... 240
7.70 FLD (Single Precision Floating Point Data Load) ............. ....................................... ... ... ... .............. 242
7.71 FLD (Single Precision Floating Point Data Load) ............. ....................................... ... ... ... .............. 243
7.72 FLD (Single Precision Floating Point Data Load) ............. ....................................... ... ... ... .............. 244
7.73 FLD (Single Precision Floating Point Data Load) ............. ....................................... ... ... ... .............. 245
7.74 FLD (Single Precision Floating Point Data Load) ............. ....................................... ... ... ... .............. 246
7.75 FLD (Load Word Data in Memory to Floating Register) ................................................................. 247
7.76 FLDM (Single Precision Floating Point Data Load to Multip le Re gister) .... ... ................................. 248
7.77 FMADDs (Single Precision Floating Point Multiply and Add) ......................................................... 250
7.78 FMOVs (Single Precision Floating Point Move) ............................. ... ... ... ....................................... . 252
7.79 FMSUBs (Single Precision Floating Point Multiply and Subtract) ................................................... 253
7.80 FMULs (Single Precision Floating Point Multiply) ... ... ....................................... ... .... ... .................... 255
7.81 FNEGs (Single Precision Floating Point sign reverse) ................................................................... 257
7.82 FSQRTs (Single Precision Floating Point Square Root) ................................................................ 258
7.83 FST (Single Precision Floating Point Data Store) ... ... ....................................... ... .... ... .................... 259
7.84 FST (Single Precision Floating Point Data Store) ... ... ....................................... ... .... ... .................... 260
7.85 FST (Single Precision Floating Point Data Store) ... ... ....................................... ... .... ... .................... 261
7.86 FST (Single Precision Floating Point Data Store) ... ... ....................................... ... .... ... .................... 262
7.87 FST (Single Precision Floating Point Data Store) ... ... ....................................... ... .... ... .................... 263
7.88 FST (Store Word Data in Floating Point Register to Memory) ........................................................ 264
7.89 FSTM (Single Precision Floating Point Data Store from Multiple Register) .................................... 265
7.90 FsTOi (Convert from Single Precision Floating Point to Integer) .................................................... 267
7.91 FSUBs (Single Precision Floating Point Subtract) ................................................................... ... ... . 269
7.92 INT (Software Interrupt) .................................................... ... ... ....................................... . ................ 271
7.93 INTE (Software Interrupt for Emulator) ....................................... ... ... ... ... ........................................ 273
7.94 JMP (Jump) .................................................................................................................................... 275
7.95 JMP:D (Jump) ................................................................................................................................. 277
7.96 LCALL (Long Call Subroutine) ........................................................................................................ 279
7.97 LCALL:D (Long Call Subroutine) .................................................................................................... 280
7.98 LD (Load Word Data in Memory to Register) ................................... ... ... .... ... ................................. 281
7.99 LD (Load Word Data in Memory to Register) ................................... ... ... .... ... ................................. 283
7.100 LD (Load Word Data in Memory to Register) ...... ... ....................................... ... ... .... ....................... 285
7.101 LD (Load Word Data in Memory to Register) ...... ... ....................................... ... ... .... ....................... 287
7.102 LD (Load Word Data in Memory to Register) ...... ... ....................................... ... ... .... ....................... 289
7.103 LD (Load Word Data in Memory to Register) ...... ... ....................................... ... ... .... ....................... 291
7.104 LD (Load Word Data in Memory to Register) ...... ... ....................................... ... ... .... ....................... 292
7.105 LD (Load Word Data in Memory to Program Status Register) ................................................ ... ... . 294
7.106 LDI:20 (Load Immediate 20bit Data to Destination Register) ......................................................... 296
7.107 LDI:32 (Load Immediate 32 bit Data to Destination Register) ........................................................ 298
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7.108 LDI:8 (Load Immediate 8bit Data to Destination Register) ............................................................. 300
7.109 LDM0 (Load Multiple Registers) ..................................................................................................... 302
7.110 LDM1 (Load Multiple Registers) ..................................................................................................... 304
7.111 LDUB (Load Byte Data in Memory to Register) .............................................................................. 306
7.112 LDUB (Load Byte Data in Memory to Register) .............................................................................. 308
7.113 LDUB (Load Byte Data in Memory to Register) .............................................................................. 310
7.114 LDUB (Load Byte Data in Memory to Register) .............................................................................. 312
7.115 LDUH (Load Halfword Data in Memory to Register) ....................................................................... 313
7.116 LDUH (Load Halfword Data in Memory to Register) ....................................................................... 315
7.117 LDUH (Load Halfword Data in Memory to Register) ....................................................................... 317
7.118 LDUH (Load Halfword Data in Memory to Register) ....................................................................... 319
7.119 LEAVE (Leave Function) ................................................................................................................ 320
7.120 LSL (Logical Shift to the Left Direction) ......................................... ... ... ........................................... 322
7.121 LSL (Logical Shift to the Left Direction) ......................................... ... ... ........................................... 324
7.122 LSL2 (Logical Shift to the Left Direction) ........................................................................................ 326
7.123 LSR (Logical Shift to the Right Direction) ....................................................................................... 328
7.124 LSR (Logical Shift to the Right Direction) ....................................................................................... 330
7.125 LSR2 (Logical Shift to the Right Direction) ..................................................................................... 332
7.126 MOV (Move Word Data in Source Register to Destination Register) ............................................. 334
7.127 MOV (Move Word Data in Source Register to Destination Register) ............................................. 336
7.128 MOV (Move Word Data in Program Status Register to Destination Register) ................................ 338
7.129 MOV (Move Word Data in Source Register to Destination Register) ............................................. 340
7.130 MOV (Move Word Data in Source Register to Program Status Register) ...................................... 342
7.131 MOV (Move Word Data in General Purpose Register to Floating Point Register) ......................... 344
7.132 MOV (Move Word Data in Floating Point Register to General Purpose Register) ......................... 345
7.133 MUL (Multiply Word Data) .............................................................................................................. 346
7.134 MULH (Multiply Halfword Data) ...................................................................................................... 348
7.135 MULU (Multiply Unsigned Word Data) ............................................................................................ 350
7.136 MULUH (Multiply Unsigned Halfword Data) . .... ... ... ... .... ...................................... .... ... ... ................. 352
7.137 NOP (No Operation) ....................................................................................................................... 354
7.138 OR (Or Word Data of Source Register to Data in Memory) ............................................................ 356
7.139 OR (Or Word Data of Source Register to Destination Register) ..................................................... 358
7.140 ORB (Or Byte Data of Source Register to Data in Memory) ........................................................... 360
7.141 ORCCR (Or Condition Code Register and Immediate Data) .. .... ...................................... ... .... ... .... 362
7.142 ORH (Or Halfword Data of Source Register to Data in Memory) ................................................... 364
7.143 RET (Return from Subroutine) ........................................................................................................ 366
7.144 RET:D (Return from Subroutine) .................................................................................................... 368
7.145 RETI (Return from Interrupt) ... ... ... ....................................... ... .... ... ................................... .............. 370
7.146 SRCH0 (Search First Zero bit position distance From MSB) .......................................................... 373
7.147 SRCH1 (Search First One bit position distance From MSB) ......................... ... ... ........................... 375
7.148 SRCHC (Search First bit value change position distance From MSB) ........................................... 377
7.149 ST (Store Word Data in Register to Memory) ................................................................................. 379
7.150 ST (Store Word Data in Register to Memory) ................................................................................. 381
7.151 ST (Store Word Data in Register to Memory) ................................................................................. 383
7.152 ST (Store Word Data in Register to Memory) ................................................................................. 385
7.153 ST (Store Word Data in Register to Memory) ................................................................................. 387
7.154 ST (Store Word Data in Register to Memory) ................................................................................. 389
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7.155 ST (Store Word Data in Register to Memory) ................................................................................. 390
7.156 ST (Store Word Data in Program Status Register to Memory) ....................................................... 392
7.157 STB (Store Byte Data in Register to Memory) ................................................................................ 394
7.158 STB (Store Byte Data in Register to Memory) ................................................................................ 396
7.159 STB (Store Byte Data in Register to Memory) ................................................................................ 398
7.160 STB (Store Byte Data in Register to Memory) ................................................................................ 400
7.161 STH (Store Halfword Data in Register to Memory) ......................................................................... 401
7.162 STH (Store Halfword Data in Register to Memory) ......................................................................... 403
7.163 STH (Store Halfword Data in Register to Memory) ......................................................................... 405
7.164 STH (Store Halfword Data in Register to Memory) ......................................................................... 407
7.165 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 408
7.166 STM0 (Store Multiple Registers) ..................................................................................................... 410
7.167 STM1 (Store Multiple Registers) ..................................................................................................... 412
7.168 SUB (Subtract Word Data in Source Register from Destination Register) ..................................... 414
7.169 SUBC (Subtract Word Data in Source Register and Carry bit from Destination Register) ............. 416
7.170 SUBN (Subtract Word Data in Source Register from Destination Register) ................................... 418
7.171 XCHB (Exchange Byte Data) .......................................................................................................... 420
APPENDIX ......................................................................................................................... 423
APPENDIX A Instruction Lists ............................................................................................................ 424
A.1 Meaning of Symbols .. ... ... .... ...................................... .... ... ... ....................................... ... ................. 425
A.1.1 Mnemonic and Operation Columns ...................................... ... ... ... ....................................... . 425
A.1.2 Operation Column ................................................................................................................. 430
A.1.3 Format Column ...................................................................................................................... 431
A.1.4 OP Column ............................................................................................................................ 431
A.1.5 CYC Column .......................................................................................................................... 432
A.1.6 FLAG Column ........................................................................................................................ 433
A.1.7 RMW Column ............................. ... ... ....................................... ... ... .... .................................... 433
A.1.8 Reference Column ................................................................................................................. 433
A.2 Instruction Lists .............................................................................................................................. 434
A.3 List of Instructions that can be positioned in the Delay Slot ........................................................... 448
APPENDIX B Instruction Maps ........................................................................................................... 450
B.1 Instruction Maps ............................................................................................................................. 451
B.2 Extension Instruction Maps ............................................................................................................ 452
APPENDIX C Supplemental Explanation about FPU Exception Processing ...................................... 455
C.1 Conformity with IEEE754-1985 Standard ...................................................................................... 455
C.2 FPU Exceptions ............................................................................................................................. 456
C.3 Round Processing .. ... ... ....................................... ... ... .... ...................................... .... ... ... ................. 458
INDEX...................................................................................................................................461
ix
x CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 1
CHAPTER 1
OVERVIEW OF FR81 FAMILY
CPU
This chapter describes the features of FR81 Family CPU and the changes from the earlier FR Family.
1.1 Features of FR81 Family CPU
1.2 Changes from the earlier FR Family
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.1
FR81 Family

1.1 Features of FR81 Family CPU

FR81 Family CPU is meant for 32 bit RISC controller having proprietary FR81 architecture of Fujitsu. The FR81 architecture is optimized for microcontrollers by using the FR family instruction set and including improved floating-point, memory protection, and debug functions.
■ General-purpose Register Architecture
It is load/store architecture based on 16 numbers of 32-bit General-purpose registers R0 to R15. The architecture also has instructions that are suitable for embedded uses such as memory to memory transfer, bit processing etc.
■ Linear Space for 32-bit (4G bytes) addressing
Address space is controlled for each byte unit. Linear specification of Address is made based on 32-bit address.
■ 16-bit fixed instruction length (excluding immediate data transfer instructions)
It is 16-bit fixed length instruction format excluding 32/20-bit immediate data transfer instruction. It enables securing high object efficiency.
■ Floating point calculation unit (FPU)
FR81 Family supports single precision floating point calculation (IEEE754 compliant). It has 16 pieces of 32-bit floating point registers from FR0 to FR15. A single instruction can execute a product-sum operation type calculation (multiplication, or addition/subtraction). The instruction length of a floating point type instruction is 32 bits
■ Pipeline Configuration
High speed one-instruction one-cycle processing of the basic instructions based on 5-stage pipeline operation can be carried out. Pipeline has following 5-stage configuration.
• IF Stage: Load Instruction
• ID Stage: Interpret Instruction
• EX Stage: Execute Instruction
• MA Stage: Memory Access
• WB Stage: Write to register FR81 Family has the 6-stage pipeline configuration to execute floating point type instructions.
■ Non-blocking load
In FR81 Family, non-blocking loading is carried out m aking execution of LD (load) instructions efficient. A maximum of four LD (Load) instructions can be issued in anticipation. In non-blocking, succeeding instruction is executed without waiting for the completion o f a load instruction, in case general-purpose register storing the value of load instruction is not referred by the succeeding instruction.
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CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
FR81 Family
■ Harvard Architecture
An instruction can be executed efficiently based on Harvard Architecture where instruction bus for instruction access and data bus for data access are independent.
■ Multiplication Instruction
Multiplication/division computation can be executed at the instructio n level based on an in-built mult iplier. 32-bit multiplication, signed or unsigned, is executed in 5 cycles. 16-bit multiplication is executed in 3 cycles.
■ Step Division Instruction
32-bit ÷ 32-bit division, signed or unsigned, can be executed based on combination of step division instructions.
■ Direct Addressing Instruction for peripheral access
Address of 256 words/ 256 half-words/ 256 bytes from the top of address space (low order address) can be directly specified. It is convenient for address specification in the I/O Register of the peripheral resource.
1.1
■ High-speed interrupt processing complete within 6 cycles
Acceptance of interruption is processed at a high speed within 6 cycles. A 16-level priority order is given to the request for interruption. Masking in line with the priority order can be carried out based on interruption mask level of the CPU.
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 3
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.2
FR81 Family

1.2 Changes from the earlier FR Family

FR81 Family has partial addition and deletion of instructions and operational changes from the earlier FR Family (FR30 Family, FR60 Family etc.).
■ Instructions that cannot be used in FR81/FR80 Family
Following instructions cannot be used in FR81/FR80 Family.
• Coprocessor Instructions (COPOP, COPLD, COPST, COPSV)
• Resource Instructions (LDRES, STRES) Undefined Instruction Exceptions and not the Coprocessor Error Trap occur when execution of
Coprocessor Instruction is attempted. Undefined In struction Exceptions occur when execution of Resource Instruction is attempted.
■ Instructions added to FR81/FR80 Family
Following instructions have been added in FR81/FR80 Family. These instructions have replaced the bit search module embedded as a peripheral function.
• SRCH1 (Bit Search Instruction Detection of First "1" bit from MSB to LSB)
• SRCH0 (Bit Search Instruction Detection of first "0" bit from MSB to LSB)
• SRCHC (Bit Search Instruction Detection of Change point from MSB to LSB) see "Chapter 7 Detailed Execution Instructions" and "Appendix A 2 Instruction Lists" for operation of Bit
Search Instructions.
■ Adding floating point type instructions
Floating point type instructions and 16 pieces of 32-bit floating point registers (FR0 to FR15) have been added in FR81 Family.
■ Privilege mode
Privilege mode has been added in FR81 family. Privilege mode and user mode are two CPU operation modes.
■ Exception processing
Exception processing has been improved for FR81 Family. The following exceptions have been added.
• FPU exception
• Instruction access protection violation exception
• Data access protection violation exception
• Invalid instruction exception (Changing definition from undefined instruction exception)
• Data access error exception
• FPU absence exception
4 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
FR81 Family
■ Operation of INTE Instructions during Step Execution
In FR81 Family, trap processing is initiate d based on INTE instructions even during step execution based on step trace trap.
In hitherto FR Family, trap processing is not initiated based on INTE inst ruct ions during step execution. For trap processing based on step trace trap and INTE instructions, see “4.6 Traps”.
1.2
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 5
CHAPTER 1 OVERVIEW OF FR81 FAMILY CPU
1.2
FR81 Family
6 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 2
MEMORY ARCHITECTURE
This chapter explains the memory architecture of FR81 Family CPU. Memory architecture refers to allocation of memory spaces and methods used to access memory.
2.1 Address Space
2.2 Data Structure
2.3 Word Alignment
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 7
CHAPTER 2 MEMORY ARCHITECTURE
2.1

2.1 Address Space

The address space of FR81 Family CPU is 32 bits (4Gb yte).
CPU controls the address spaces in byte units. An address on the address space is accessed from the CPU by specifying a 32-bit value. Address space is indicated in Figure 2.1-1.
Figure 2.1-1 Address space
FR81 Family
Direct address area General addressing
0000 0000 H 0000 0100 H
0000 0200 H
0000 0400 H
000F FC00H
0010 0000H
FFFF FFFFH
Byte data
Half-word data
Word data
Vector table initial area
Program or data area
Address space is also called memory space. It is a logical address space as seen from the CPU. Addresses cannot be changed. Logical address as seen from the CPU, and the physical address actually allocated to memory or I/O are identical.

2.1.1 Direct Address Area

In the lower address in the address space, there is a direct address area. Direct address area directly specifies an address in the direct address specification instruction. This area
accesses only based on operand data in the instruction without the use of general-purpose registers. The size of the address area that can be specified by direct addressing varies according to the data type being accessed.
000F FC00
TBR initial value
H TBR
The correspondence between data type and area specified by direct address is as follows.
• byte data access: 0000 0000
• half-word data access: 0000 0000H to 0000 01FF
• word data access: 0000 0000H to 0000 03FF
to 0000 00FF
H
H
H
H
The method of using the 8-bit address data contained in the operand of instructions that specify direct addresses is as follows:
8 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
FR81 Family
0000 0000H
FFFF FFFFH
TBR
1 Kbyte
Number
EIT source
FF
H
FEH FDH FCH
00H
000H 004H 008H 00CH
3FCH
Entry address for INT instruction Entry address for INT instruction
Entry address for INT instruction Entry address for INT instruction
Entry address for reset processing
Memory space
Vect or table area
• byte data access: Lower 8 bits of the address are used as it is
• half word data access: Value is doubled and used as lower 9 bits of the address
• word data access: Value is quadrupled and used as lower 10 bits of the address
The relation between data types specified by direct address and memory address is shown in Figure 2.1-2.
CHAPTER 2 MEMORY ARCHITECTURE
2.1
Figure 2.1-2
[Example 1] Byte data: DMOVB R13,@58H
[Example 2] Half-word data: DMOVH R13,@58H
[Example 3] Word data: DMOV R13,@58H
Relation between data type specified by direct address and memory address
Memory space
58
Object code:1A58H
Object code:192C
R13 12345678
Right 2-bit shift
Object c ode:1816
No data shift
Right 1-bit shift
H 58HLeft 1-bit shift
H 58HLeft 2-bit shi
f
t
0000 0058HR13 12345678
0000 0058
0000 0058
H
78
Memory space
H
5678
Memory space
HR13 12345678
1345678

2.1.2 Vector Table Area

An area of 1Kbyte from the address shown in the Table Base Register (TBR) is called the EIT Vector Table Area.
Table Base Register (TBR) represents the top address of the vector table area. In this vector table area, the entry addresses of EIT processing (Exception processing, Interrupt processing, Trap processing) are described. The relation between Table Base Register (TBR) and vector table area is shown in Figure 2.1-3.
Figure 2.1-3 Relation between Table Base Register (TBR) and Vector Table Area addresses
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 9
CHAPTER 2 MEMORY ARCHITECTURE
2.1
FR81 Family
Table 2.1-1
Offset from
TBR
3FC
H
3F8
H
3F4
H
3F0
H
3EC
H
3E8
H
3E4
H
3E0
H
3DC
H
3D8
H
3D4
H
3D0
H
3CC
H
3C8
H
3C4
H
3C0
H
3BC
H
to
304
H
300
H
2FC
H
2F8
H
2F4
H
to
000
H
As a result of reset, the value of Table Base Register (TBR) is initialized to 000F FC00 vector table area extends from 000F FC00
to 000F FFFFH. By rewriting the Table Base Register (TBR),
H
, and the range of
H
the vector table area can be allocated to any desired location.
A vector table is composed of entry addresses for each EIT processing programs. Each vector table contains values whose use is fixed according to the CPU architecture, and values that vary according to the type of built-in peripheral functions. The structure of vector table area is shown in Table 2.1-1.
Structure of Vector Table Area
Vector
number
00
H
01
H
02
H
03
H
04
H
05
H
06
H
07
H
08
H
09
H
0A
H
0B
H
0C
H
0D
H
0E
H
0F
H
0F
H
to
3E
H
3F
H
40
H
41
H
42
H
to
FF
H
Model-
dependence
EIT value description Remarks
No reset No system reserved No system reserved Disabled No system reserved Disabled No system reserved Disabled No FPU exception
No
No
Instruction access protection violation exception
Data access protection
violation exception No Data access error interrupt No INTE instruction For use in the emulator No Instruction break No system reserved No Step trace trap No system reserved No Invalid instruction exception No NMI request
General interrupt
Yes
(used in external interrupt,
interrupt from peripheral
Refer to the Hardware Manual for each model
function) No General interrupts Used in Delayed interrupt No system reserved Used in REALOS No system reserved Used in REALOS
No Used in INT instruction
For vector tables of actual models, refer to the hardware manuals for each model.
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CHAPTER 2 MEMORY ARCHITECTURE
FR81 Family

2.1.3 20-bit Addressing Area & 32-bit Addressing Area

The lower portion of the address space extending from 0000 0000H to 000F FFFFH (1Mbyte) will be the 20-bit addressing area. The overall address space from 0000 0000 addressing space.
If all the program locations and data locations are positioned within the 20-bit addressing area, a compact and high-speed program can be realized as compared to a 32-bit addressing area.
In a 20-bit addressing area, as the address values are within 20 bits, the LDI:20 instruction can be used for immediate loading of address information. The instruction length (Code size) of LDI:20 instruction is 4bytes. By using LDI:20 instruction, the program becomes more compact than when using LDI:32 instruction of instruction length 6bytes.
Example of 20-bit Addressing
Code size LDI:20 #label20,Ri ; 4 bytes JMP @Ri ; 2 bytes
to FFFF FFFFH will be 32-bit
H
2.1
Total 6 bytes
Example of 32-bit Addressing
Code size LDI:32 #label32,Ri ; 6 bytes JMP @Ri ; 2 bytes
Total 8 bytes
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 11
CHAPTER 2 MEMORY ARCHITECTURE
MSBbit76543210LSB
2.2
FR81 Family

2.2 Data Structure

FR81 Family CPU has three data types namely byte data (8-bits), half word data (16-bits) and word data (32-bits). The byte order is big endian.

2.2.1 Byte Data

This is a data type having 8 bits as unit. Bit order is l ittle endian, MSB side becomes bit7 and LSB side becomes bit0. The structure of byte data is shown in Figure 2.2-1.
Figure 2.2-1

2.2.2 Half Word Data

This is a data type having 16 bits (2byte) as unit . Bit order is little endian, MSB side is bit15 while LSB side is bit0. Bit15 to bit8 of MSB side represent the higher bytes wh ile bit7 to bit0 of LSB side represent the lower bytes. The structure of half word data is shown in Figure 2.2-2.
Figure 2.2-2
MSB
bit
Higher bytes Lower bytes
Structure of byte data
Structure of Half Word Data
LSB
789101112131415 6543210

2.2.3 Word Data

This is a data type having 32 bits (4byte) as unit . Bit order is little endian, MSB side is bit31 while LSB side is bit0. Bit31 to bit16 of the MSB side become the higher half word, while bit1 5 to bit0 of the LSB side become the lower half word. The structure of word data is shown in Figure 2.2-3.
Figure 2.2-3
MSB
bit31
Higher half word Lower half word
12 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
Structure of Word Data
16 1524 23 8 7 0
LSB
FR81 Family

2.2.4 Byte Order

The byte order of FR81 Family CPU is big endian. When word data or half word data are allocated to address spaces, the higher bytes are placed in the lower address side while the lower bytes are placed in the higher address side. The arrangement of big endian byte data is shown in Figure 2.2-4.
CHAPTER 2 MEMORY ARCHITECTURE
2.2
Byte
Half word
Word
For example, if a word data was written on the memory (RAM) at address location 0004 1234 memory space, the highest byte will be stored at location 0004 1234 at location byte 0004 1237
Address
MSB
Address Address +1
MSB
MSB
Higher byte Lower byte
Address Address +1 Address +2 Address +3
Highest byte Lowest byte
Higher half word Lower half word
.
H
Figure 2.2-4
LSB
Big Endian Byte Orde
LSB
while the lowest byte will be stored
H
H
LSB
of the
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 13
CHAPTER 2 MEMORY ARCHITECTURE
2.3
FR81 Family

2.3 Word Alignment

The data type used determines restrictions on the designation of memory addresses (word alignment).

2.3.1 Program Access

Unit of instruction length is half word (2byte) and all instructions are allocated to addresses which are multiples of 2 (2n location).
At the time of execution of the instruction, bit0 of the program counter (PC) automatically becomes "0", and is always at an even address. In a branched instruction, even if an odd address is generated as a result of branch destination address calculation, the bit0 of the address will be assigned "0" and branched to an even address.
There is no address exception in program access.

2.3.2 Data Access

There are following restrictions on addresses for data access depending upon the data type used.
Word data
Data is assigned to addresses that are multiples of 4 (4n location). The restriction of multiples of 4 on addresses is called ‘word boundary’. If the specified address is not a multiple of 4, the lower two bits of the address are set to "00" forcibly.
Half-word data
Data is assigned to addresses that are multiples of 2 (2n locations). The restr iction of multiples of 2 on addresses is called ‘half-word boundary’. If the specified address is not a multiple of 2, the lower 1 bit of the address is set to "0" forcibly.
Byte data
There is no restriction on allocation of addresses.
During word and half-word data access, condition that lower bit of an address has to be "0" is applicable only for the result of computation of an effective address. Values still under calcula tion are used as they are.
14 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
CHAPTER 3
PROGRAMMING MODEL
This chapter describes the programming model of FR81 Family CPU.
3.1 Register Configuration
3.2 General-purpose Registers
3.3 Dedicated Registers
3.4 Floating-point Register
CM71-00105-1E FUJITSU MICROELECTRONICS LIMITED 15
CHAPTER 3 PROGRAMMING MODEL
3.1
FR81 Family

3.1 Register Configuration

FR81 Family CPU uses three types of registers, namely, general-purpose registers, dedicated registers and floating point registers.
General-purpose registers are registers that store computation data and address information. They comprise 16 registers from R0 to R15. Dedicated registers are registers that store information for specific applications.
Floating point registers are registers that store calculation inform ation for floating point calculations . They are comprised of 16 registers from FR0 to FR15.
16 FUJITSU MICROELECTRONICS LIMITED CM71-00105-1E
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