Fujitsu FLM0910-8F Schematic [ru]

1
Edition 1.2 August 1999
FLM0910-8F
X, Ku-Band Internally Matched FET
Item
Gate-Source Voltage
Total Power Dissipation
Storage Temperature
Channel Temperature
Symbol
V
DS
V
GS
15
-5
42.8
-65 to +175
175
Tc = 25°C
V
V
W
°C
°C
P
T
T
stg
T
ch
Condition Unit
Rating
ABSOLUTE MAXIMUM RATING (Ambient Temperature Ta=25°C)
Fujitsu recommends the following conditions for the reliable operation of GaAs FETs:
1. The drain-source operating voltage (VDS) should not exceed 10 volts.
2. The forward and reverse gate currents should not exceed 32.0 and -4.4 mA respectively with gate resistance of 100.
Item
Saturated Drain Current Transconductance
Pinch-off Voltage
Gate Source Breakdown Voltage
Power-added Efficiency
3rd Order Intermodulation Distortion
Output Power at 1dB G.C.P.
Power Gain at 1dB G.C.P.
Symbol
I
DSS
- 3400 5200
- 3400
-
-0.5 -1.5 -3.0
-5.0 - -
6.5 7.5 -
-29-
38.5 39.0 -
VDS = 5V, I
DS
= 170mA
VDS = 5V, I
DS
= 2200mA
VDS = 5V, V
GS
= 0V
IGS = -170µA
VDS =10V, IDS = 0.65 I
DSS (Typ.),
f =9.5 ~10.5 GHz, ZS=ZL= 50 ohm
f = 10.5 GHz, f = 10 MHz 2-Tone Test P
out
= 28.5dBm S.C.L.
mA
mS
V
dB
%
-44 -46 - dBc
dBm
V
g
m
V
p
V
GSO
P
1dB
G
1dB
Drain Current
- 2200 2600 mA
I
dsr
IM
3
η
add
Gain Flatness
--±0.6 dB∆G
Test Conditions Unit
Limit Typ.
Max.Min.
ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C)
Channel to Case
Thermal Resistance
- 3.0
3.5
°C/W
R
th
G.C.P.: Gain Compression Point, S.C.L.: Single Carrier Level
CASE STYLE: IB
10V x I
dsr
x R
th
Channel Temperature Rise
--
80
°C
T
ch
DESCRIPTION
The FLM0910-8F is a power GaAs FET that is internally matched for standard communication bands to provide optimum power and gain in a 50 ohm system.
Fujitsu’s stringent Quality Assurance Program assures the highest reliability and consistent performance.
FEATURES
• High Output Power: P
1dB
= 39.0dBm (Typ.)
• High Gain: G
1dB
= 7.5dB (Typ.)
• High PAE: η
add
= 29% (Typ.)
• Low IM3= -46dBc@Po = 28.5dBm
• Broad Band: 9.5 ~ 10.5GHz
• Impedance Matched Zin/Zout = 50
2
FLM0910-8F
X, Ku-Band Internally Matched FET
OUTPUT POWER & IM3 vs. INPUT POWER
VDS=10V f1 = 10.5 GHz f2 = 10.51 GHz 2-tone test
16 18 20 22 24 26
Input Power (S.C.L.) (dBm) S.C.L.: Single Carrier Level
27
29
31
33
25
23
-50
-40
-30
-20
Output Power (S.C.L.) (dBm)
IM
3
P
out
IM
3
(dBc)
POWER DERATING CURVE
20
10
40
50
30
0
50 100 150 200
Case Temperature (°C)
Total Power Dissipation (W)
OUTPUT POWER vs. FREQUENCY
9.5
Pin=32dBm
30dBm
28dBm
26dBm
10.510.0
Frequency (GHz)
34
35
36
37
38
39
40
Output Power (dBm)
VDS=10V P
1dB
OUTPUT POWER vs. INPUT POWER
VDS=10V f = 10.0 GHz
2420 22 26 28 30 32 34
Input Power (dBm)
30
32
34
36
38
40
28
20
30
40
10
Output Power (dBm)
η
add
P
out
η
add
(%)
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