FUJITSU DS07-13707-3E DATA SHEET

MB90520A

	FUJITSU SEMICONDUCTOR		DS07-13707-3E
	DATA SHEET

16-bit Proprietary Microcontroller

CMOS

F2MC-16LX MB90520A/520B Series

MB90522A/523A/522B/523B/F523B/V520A

■ DESCRIPTION

The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications in consumer products that require high-speed real-time processing.

The microcontroller instruction set is based on the AT architecture of the F2MC* family with additional instructions for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word (32-bit) data.

The MB90520A/520B series peripheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI) , extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU) 0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.

* : F2MC stands for FUJITSU Flexible MicroController, a registered trademark of FUJITSU LIMITED.

■FEATURES

•Clock

•Internal PLL clock multiplication circuit

•Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four (For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .

(Continued)

■ PACKAGES

120-pin, Plastic, LQFP

120-pin, Plastic, QFP

(FPT-120P-M05)

(FPT-120P-M13)

MB90520A/520B Series

(Continued)

•Sub-clock (32.768 KHz) operation available

Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V)

•16MB CPU memory space

Internal 24-bit addressing

•Instruction set optimized for controller applications

Rich data types (bit, byte, word, long-word) Extended addressing modes (23 types)

Enhanced signed multiplication and division instructions and RETI instruction Enhanced calculation precision using a 32-bit accumulator

•Instruction set designed for high-level language (C) and multi-tasking

System stack pointer

Enhanced pointer-indirect instructions and barrel shift instructions

•Faster execution speed

4-byte instruction queue

ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)

•Program patch function : An address match detection function (2 × addresses)

•Interrupt function

32 programmable interrupts with 8 levels

•Automatic data transmission function independent of CPU operation

Extended intelligent I/O service function (EI2OS) : Up to 16 channels

•Low-power consumption (stand-by) modes

Sleep mode (CPU operating clock stops, peripherals continue to operate.) Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.) Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.) Stop mode (Main oscillation and sub-clock both stop.)

CPU intermittent operation mode

Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)

•Process

CMOS technology

•I/O ports

General-purpose I/O ports (CMOS input/output) : 53 ports General-purpose I/O ports (inputs with pull-up resistors) : 24 ports General-purpose I/O ports (Nch open-drain outputs) : 8 ports

•Timers

Timebase timer, clock timer, watchdog timer : 1 channel each 8/16-bit PPG timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel

16-bit reload timers 0 and 1 : 2 channels 16-bit I/O timers :

16-bit free-run timers 0 and 1 : 2 channels

16-bit input capture 0 : 2 channels (2 channels per unit)

16-bit output compare 0 and 1 : 8 channels (4 channels per unit)

8/16-bit up/down counter/timers 0 and 1 : 8-bit × 2 channels or 16-bit × 1 channel Clock output function : 1 channel

•Communications macro (communication interface) Extended I/O serial interfaces 0 and 1 : 2 channels

UART (full-duplex, double-buffered, SCI : Can also be used for synchronous serial transfer) : 1 channel

2

MB90520A/520B Series

•External event interrupt control function

DTP/external interrupts : 8 channels (Can be set to detect rising edges, falling edges, “H” levels, or “L” levels) Wake-up interrupts : 8 channels (Detects “L” levels only)

Delayed interrupt generation module : 1 channel (for task switching)

•Analog/digital conversion

8/10-bit A/D converter : 8 channels (Can be initiated by an external trigger. Minimum conversion time = 10.2 µs for a 16 MHz machine clock)

8-bit D/A converter : 2 channels (R-2R type. Settling time = 12.5 µs for a 16 MHz machine clock)

•Display function

LCD controller/driver : 32 × segment drivers + 4 × common drivers

•Other

Supports serial writing to flash memory. (Only on versions with on-board flash memory.)

Note : The MB90520A and 520B series cannot be used in external bus mode. Always set these devices to singlechip mode.

3

MB90520A/520B Series

■ PRODUCT LINEUP

Part
Number	MB90522A	MB90523A		MB90522B	MB90523B	MB90F523B	MB90V520A
Parameter
Classification		Mask ROM				Flash ROM	Evaluation
							product
ROM size	64 Kbytes	128 Kbytes		64 Kbytes	128 Kbytes	128 Kbytes
RAM size				4 Kbytes			6 Kbytes
Separate emulator							No
power supply*1
Process				CMOS
Operating power	3.0 V to 5.5 V			2.7 V to 5.5 V		3.0 V to 5.5 V
supply voltage*2
Internal regulator circuit		not mounted				mounted
	Number of instructions : 340
	Instruction sizes : 8-bit, 16-bit
CPU functions	Instruction length : 1 byte to 7 bytes
	Data sizes : 1-bit, 8-bit, 16-bit
	Minimum instruction execution time : 62.5 ns (for a 16 MHz machine clock)

Interrupt processing time : 1.5 s min. (for a 16 MHz machine clock)

	Low power operation		Sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode,
	(standby modes)		and CPU intermittent operation mode
			General-purpose I/O ports (CMOS outputs) : 53
	I/O ports		General-purpose I/O ports (inputs with pull-up resistors) : 24
			General-purpose I/O ports (Nch open drain outputs) : 8
			Total : 85
			18-bit counter
	Timebase timer		Interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
			(for a 4 MHz base oscillation)
			Reset trigger period
	Watchdog timer		• For a 4 MHz base oscillation : 3.58, 14.33, 57.23, 458.75 ms
			• For 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s
		16-bit	Number of channels : 2
		freerun
			Generates an interrupt on overflow
		timer
	16-bit	16-bit	Number of channels : 8
	I/O	output
			Pin change timing : Free run timer register value equals output compare register value.
	timers	compare
		16-bit	Number of channels : 2
		input	Saves the value of the freerun timer register when a pin input occurs (rising edge, falling
		capture	edge, either edge) .
			Number of channels : 2
	16-bit reload timer		Count clock frequency : 0.125, 0.5, or 2.0 s for a 16 MHz machine clock
			Can be used to count an external event clock.
			(Continued)

4

MB90520A/520B Series

(Continued)

	Part
	Number	MB90522A	MB90523A	MB90522B	MB90523B	MB90F523B	MB90V520A
	Parameter
	Clock timer	15-bit timer
		Interrupt interval : 0.438, 0.5, or 2.0 µs for sub-clock frequency = 32.768 kHz
	8/16-bit PPG timer	Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
		Can generate a pulse waveform output with specified period and 0 to 100% duty ratio.
	8/16 -bit up/down	Number of channels : 1 (Can be used in 2 × 8-bit channel mode)
		External event inputs : 6 channels
	counter/timers
		Reload/compare function : 8-bit × 2 channels
	Clock monitor	Clock output frequency : Machine clock/21 to machine clock/28
	Delayed interrupt	Interrupt generation module for task switching. (Used by REALOS.)
	generation module
		Input channels : 8
	DTP/External	Generates interrupts to the CPU on rising edges, falling edges with input “H” level, or “L”
	interrupts	level.
		Can be used for external event interrupts and to activate EI2OS.
	Wakeup interrupts	Input channels : 8
		Triggered by “L” level.
		Number of channels : 8
	8/10-bit A/D converter	Resolution : 8-bit or 10-bit selectable
		Conversion can be performed sequentially for multiple consecutive channels.
	(successive
		• Single-shot conversion mode : Converts specified channel once only.
	approximation type)
		• Continuous conversion mode : Repeatedly converts specified channel.
		• Intermittent conversion mode : Converts specified channel then halts temporarily.
	8-bit D/A converter	Number of channels : 2
	(R-2R type)	Resolution : 8-bit
		Number of channels : 1
	UART (SCI)	Clock synchronous transfer : 62.5 Kbps to 1 Mbps
		Clock asynchronous transfer : 1202 bps to 31250 bps
		Supports bi-directional and master-slave communications.
	Extended I/O serial	Number of channels : 2
		Clock synchronous transfer : 31.25 Kbps to 1 Mbps (Using internal shift clock)
	interface
		Transmission format : Selectable LSB-first or MSB-first
		Number of common outputs : 4
		Number of segment outputs : 32
	LCD controller/driver	Number of power supply pins for LCD drive : 4
		LCD display memory : 16 bytes
		Divider resistor for LCD drive : Internal

*1 : As for the necessity of a DIP switch setting (S2) when using the emulation pod (MB2145-507) . Refer to the hardware manual for the emulation pod (MB2145-507) fomr details.

*2 : Take note of the maximum operating frequency and A/D converter precision restrictions when operating at 3.0 V to 3.6 V. See the “Electrical Characteristics” section for details.

5

MB90520A/520B Series

■ PACKAGES AND CORRESPONDING PRODUCTS

Package		MB90522A	MB90523A	MB90522B	MB90523B	MB90F523B	MB90V520A
FPT-120P-M05							×
(LQFP)
FPT-120P-M13							×
(QFP)
PGA-256C-A01		×	×	×	×	×
(PGA)
: Available,		× : Not available

Note : See the “■ PACKAGE DIMENSIONS” section for more details.

6

MB90520A/520B Series

■ PIN ASSIGNMENT

(TOP VIEW)

P31/CKOT

P32/OUT0

P33/OUT1

P34/OUT2

P35/OUT3

P36/PG00

P37/PG01

VCC

P40/PG10

P41/PG11

P42/SIN0

P43/SOT0

P44/SCK0

P45/SIN1

P46/SOT1

P47/SCK1

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG7

PA0/SEG8

PA1/SEG9

PA2/SEG10

PA3/SEG11

PA4/SEG12

PA5/SEG13

				ADTG	ZIN0/INT7			BIN0		AIN0		IC11		IC10		IC01
	P30		VSS P27/		P26/		P25/		P24/		P23/		P22/		P21/
120		119		118	117		116		115		114		113		112
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31		32		33	34		35		36		37		38		39
PA6/SEG14		PA7/SEG15		VSS		C	P50/SIN2/AIN1		P51/SOT2/BIN1		P52/SCK2/ZIN1			DVCC		DVSS

P20/IC00	P17/WI7		P16/WI6		P15/WI5		P14/WI4		P13/WI3
111	110		109		108		107		106

40	41		42		43		44		45
P53/DA0	P54/DA1			AVCC		AVRH		AVRL		AVSS

P12/WI2		P11/WI1		P10/WI0			P07	P06/INT6		P05/INT5		P04/INT4		P03/INT3		P02/INT2		P01/INT1		P00/INT0			VCC		X1		X0		VSS
105		104		103		102		101		100		99		98		97		96		95		94		93		92		91

46		47		48		49		50		51		52		53		54		55		56		57		58		59		60
P60/AN0		P61/AN1		P62/AN2		P63/AN3		P64/AN4		P65/AN5		P66/AN6		P67/AN7			VCC	P70/TI0/OUT4		P71/TO0/OUT5		P72/TI1/OUT6		P73/TO1/OUT7		P74/COM0		P75/COM1

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

RST

MD0

MD1

MD2

HST

V3

V2

V1

V0

P97/SEG31

P96/SEG30

P95/SEG29

P94/SEG28

P93/SEG27

P92/SEG26

P91/SEG25

X0A

X1A

P90/SEG24

P87/SEG23

P86/SEG22

P85/SEG21

P84/SEG20

P83/SEG19

P82/SEG18

P81/SEG17

P80/SEG16 VSS

P77/COM3

P76/COM2

(FPT-120P-M05) (FPT-120P-M13)

7

MB90520A/520B Series

■ PIN DESCRIPTIONS

	Pin No.				Circuit
		Pin Name				Function
	LQFP-120*1
					Type
	QFP-120*2
	92, 93	X0, X1			A	Oscillator pin
	74, 73	X0A, X1A			B	Sub-oscillator pin
	89 to 87	MD0 to			C	Input pins for setting the operation mode.
		MD2				Connect directly to VCC or VSS.
	90				C	External reset input pin
			RST
	86				C	Hardware standby input pin
			HST
						General-purpose I/O ports
		P00 to				The settings in the pull-up resistor setup register (RDR0) are enabled
	95 to 101		P06		D	when ports are set as inputs.
						The RDR0 settings are ignored when ports are set as outputs.
		INT0 to				Event input pins for ch.0 to ch.6 of the DTP/external interrupt circuit
		INT6
						General-purpose I/O port
	102		P07		D	The settings in the pull-up resistor setup register (RDR0) are enabled when
						ports are set as inputs.
						The RDR0 settings are ignored when ports are set as outputs.
						General-purpose I/O ports
		P10 to				The settings in the pull-up resistor setup register (RDR1) are enabled when
	103 to 110		P17		D	ports are set as inputs.
						The RDR1 settings are ignored when ports are set as outputs.
		WI0 to				Event input pins for the wakeup interrupts.
			WI7
		P20, P21,				General-purpose I/O ports
		P22, P23
	111, 112,
					E	Trigger input pins for input capture units (ICU) 0 and 1.
	113, 114	IC00, IC01,				Input operates continuously when channels 0 and 1 of input capture units
		IC10, IC11				(ICU) 0 and 1 are operating. Accordingly, output to the pins from other func-
						tions that share this pin must be suspended unless performed intentionally.
			P24			General-purpose I/O port
	115				E
		AIN0				Also can be used as the count clock A input to 8/16-bit up/down counter/
						timer 0.
			P25			General-purpose I/O port
	116				E
		BIN0				Also can be used as the count clock B input to 8/16-bit up/down counter/
						timer 0.
			P26			General-purpose I/O port
	117	ZIN0			E	Also can be used as the control clock Z input to 8/16-bit up/down counter/
						timer 0.
		INT7				Event input pin for ch.7 of the DTP/external interrupt circuit

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

8

MB90520A/520B Series

	Pin No.				Circuit
		Pin Name				Function
	LQFP-120*1
					Type
	QFP-120*2
			P27			General-purpose I/O port
	118				E	External trigger input to the 8/10-bit A/D converter
						Input operates continuously when the 8/10-bit A/D converter is performing
			ADTG
						input. Accordingly, output to the pin from other functions that share this
						pin must be suspended unless performed intentionally.
	120		P30		E	General-purpose I/O port
			P31			General-purpose I/O port
	1				E
			CKOT			Output pin for clock monitor function
						The clock monitor is output when clock monitor output is enabled.
			P32			General-purpose I/O port
						Only available when waveform output from output compare 0 is disabled.
	2				E
			OUT0			Event output pin for ch.0 of output compare unit 0 (OCU)
						Only available when event output is enabled for output compare unit 0.
			P33			General-purpose I/O port
						Only available when waveform output from output compare 1 is disabled.
	3				E
			OUT1			Event output pin for ch.1 of output compare unit 0 (OCU)
						Only available when event output is enabled for output compare unit 0.
			P34			General-purpose I/O port
						Only available when waveform output from output compare 2 is disabled.
	4				E
			OUT2			Event output pin for ch.2 of output compare unit 0 (OCU)
						Only available when event output is enabled for output compare unit 0.
			P35			General-purpose I/O port
						Only available when waveform output from output compare 3 is disabled.
	5				E
			OUT3			Event output pin for ch.3 of output compare unit 0 (OCU)
						Only available when event output is enabled for output compare unit 0.
			P36			General-purpose I/O port
						Only available when waveform output from PG00 is disabled.
	6				E
			PG00			Output pin for 8/16-bit PPG timer 0
						Only available when waveform output is enabled for PG00.
			P37			General-purpose I/O port
						Only available when waveform output from PG01 is disabled.
	7				E
			PG01			Output pin for 8/16-bit PPG timer 0
						Only available when waveform output is enabled for PG01.
	*1 : FPT-120P-M05
	*2 : FPT-120P-M13
						(Continued)

9

MB90520A/520B Series

	Pin No.		Circuit
		Pin Name		Function
	LQFP-120*1
			Type
	QFP-120*2
				General-purpose I/O ports
				Only available when waveform outputs from PG10 and PG11 are disabled.
		P40, P41	D	The settings in the pull-up resistor setup register (RDR4) are enabled
	9, 10			when ports are set as inputs. The RDR4 settings are ignored when ports
				are set as outputs.
		PG10,		Output pins for 8/16-bit PPG timer 1
		PG11		Only available when waveform output is enabled for PG10 and PG11.
				General-purpose I/O port
		P42		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports are set as inputs. The RDR4 settings are ignored when ports
	11		D	are set as outputs.
				UART (SCI) serial data input pin
		SIN0		Input operates continuously when the UART is performing input.
				Accordingly, output to the pin from other functions that share this pin must
				be suspended unless performed intentionally.
				General-purpose I/O port
		P43		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports are set as inputs. The RDR4 settings are ignored when ports
	12		D
				are set as outputs.
		SOT0		UART (SCI) serial data output pin
				Only available when serial data output is enabled for the UART (SCI) .
				General-purpose I/O port
		P44		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports are set as inputs. The RDR4 settings are ignored when ports
	13		D
				are set as outputs.
		SCK0		UART (SCI) serial clock input/output pin
				Only available when serial clock output is enabled for the UART (SCI) .
				General-purpose I/O port
		P45		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports set as inputs. The RDR4 settings are ignored when ports set
	14		D	are as outputs.
				Data input pin for extended I/O serial interface 1
		SIN1		Input operates continuously when the performing serial input. Accordingly,
				output to the pin from other functions that share this pin must be
				suspended unless performed intentionally.
				General-purpose I/O port
		P46		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports set as inputs. The RDR4 settings are ignored when ports are
	15		D
				set as outputs.
		SOT1		Data output pin for extended I/O serial interface 1
				Only available when serial data output is enabled for SOT1.
	*1 : FPT-120P-M05
	*2 : FPT-120P-M13
				(Continued)

10

MB90520A/520B Series

	Pin No.		Circuit
		Pin Name		Function
	LQFP-120*1
			Type
	QFP-120*2
				General-purpose I/O port
		P47		The settings in the pull-up resistor setup register (RDR4) are enabled
				when ports are set as inputs. The RDR4 settings are ignored when ports
	16		D
				are set as outputs.
		SCK1		Serial clock input/output pin for extended I/O serial interface 1
				Only available when serial clock output is enabled for SCK1.
		P50		General-purpose I/O port
				Data input pin for extended I/O serial interface 2
		SIN2		Input operates continuously when the performing serial input.
	35		E	Accordingly, output to the pin from other functions that share this pin must
				be suspended unless performed intentionally.
		AIN1		Also can be used as the count clock A input to 8/16-bit up/down counter/
				timer 1.
		P51		General-purpose I/O port
		SOT2		Data output pin for extended I/O serial interface 2
	36		E	Only available when serial data output is enabled for SOT2.
		BIN1		Also can be used as the count clock B input to 8/16-bit up/down counter/
				timer 1.
		P52		General-purpose I/O port
		SCK2		Serial clock input/output pin for extended I/O serial interface 2
	37		E	Only available when serial clock output is enabled for SCK2.
		ZIN1		Also can be used as the control clock Z input to 8/16-bit up/down counter/
				timer 1.
	40, 41	P53, P54	I	General-purpose I/O ports
		DA0, DA1		Analog output pins for ch.0 and ch.1 of the 8-bit D/A converter
				General-purpose I/O ports
		P60 to P67		Port input is enabled when the analog input enable register (ADER) is set
	46 to 53		K	to the ports.
		AN0 to		Analog inputs for the 8/10-bit A/D converter
				Analog input is enabled when the analog input enable register (ADER) is
		AN7
				set.
		P70, P72		General-purpose I/O ports
				Event input pins for 16-bit reload timers 0 and 1
		TI0, TI1		Input operates continuously when 16-bit reload timers 0 and 1 input an
	55, 57		E	external clock. Accordingly, output to these pins from other functions that
				share the pins must be suspended unless performed intentionally.
		OUT4,		Event output pins for ch. 4 and ch. 6 of output compare unit 1 (OCU)
		OUT6		Only available when event output from output compare 1 is enabled.

*1 : FPT-120P-M05

*2 : FPT-120P-M13

(Continued)

11

MB90520A/520B Series

	Pin No.		Circuit
		Pin Name		Function
	LQFP-120*1
			Type
	QFP-120*2
				General-purpose I/O ports
		P71, P73		Only available when event outputs from 16-bit reload timers 0 and 1 are
				disabled.
	56, 58	TO0, TO1	E	Output pins for 16-bit reload timers 0 and 1.
				Only available when output is enabled for 16-bit reload timers 0 and 1.
		OUT5,		Event output pins for ch. 5 and ch. 7 of output compare unit 1 (OCU)
		OUT7		Only available when event output from output compare 1 is enabled.
				General-purpose I/O ports
		P74 to P77		Only available when the LCD controller/driver control register is set to the
	59 to 62		L	ports.
		COM0 to		Common pins for the LCD controller/driver
				Only available when the LCD controller/driver control register is set to the
		COM3
				common outputs.
				General-purpose I/O ports
		P80 to P87		Only available when the LCD controller/driver control register is set to the
	64 to 71		L	ports.
		SEG16 to		LCD segment output pins for the LCD controller/driver
				Only available when the LCD controller/driver control register is set to the
		SEG23
				segment outputs.
		P90,		General-purpose I/O ports (Support up to IOL = 10 mA)
				Only available when the LCD controller/driver control register is set to the
		P91 to P97
	72,			ports.
			M
	75 to 81	SEG24,		LCD segment output pins for the LCD controller/driver
		SEG25 to		Only available when the LCD controller/driver control register is set to the
		SEG31		segment outputs.
	17 to 24	SEG0 to	F	LCD segment 00 to 07 pins for the LCD controller/driver
		SEG7
				General-purpose I/O ports
		PA0 to PA7		Only available when the LCD controller/driver control register is set up to
	25 to 32		L	the ports.
		SEG8 to		LCD segment 08 to 15 pins for the LCD controller/driver
				Only available when the LCD controller/driver control register is set to the
		SEG15
				segment outputs.
	*1 : FPT-120P-M05
	*2 : FPT-120P-M13
				(Continued)

12

MB90520A/520B Series

(Continued)

	Pin No.		Circuit
		Pin Name		Function
	LQFP-120*1
			Type
	QFP-120*2
				Capacitor connection pin for stabilizing power supply
	34	C	G	Connect an external ceramic capacitor of approximately 0.1 F. If operat-
				ing at 3.3 V or lower, connect to VCC.
	82 to 85	V0 to V3	N	Power supply input pins for the LCD controller/driver
	8, 54, 94	VCC	Power	Power supply input pins for the digital circuit
			supply
	33, 63, 91, 119	VSS	Power	GND level power supply input pins for the digital circuit
			supply
				Power supply input for the analog circuit
	42	AVCC	H	Ensure that a voltage greater than AVCC is applied to VCC before turning
				the analog power supply on or off.
				“H” reference voltage for the A/D converter
	43	AVRH	J	Ensure that a voltage greater than AVRH is applied to AVCC before turning
				the power supply to this pin on or off.
	44	AVRL	H	“L” reference voltage for the A/D converter
	45	AVSS	H	GND level power supply input pin for the analog circuit
	38	DVCC	H	“H” reference voltage for the D/A converter
				Ensure that this voltage does not exceed VCC.
	39	DVSS	H	“L” reference voltage for the D/A converter
				Apply the same voltage level as VSS.
	*1 : FPT-120P-M05
	*2 : FPT-120P-M13

13

MB90520A/520B Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• High-speed oscillation feedback

X0

resistor

Clock input

Approx. 1 MΩ

Nch

Pch

A

X1

Pch

Nch

Standby control signal

• Low-speed oscillation feedback

X0A

resistor

Clock input

Approx. 10 MΩ

Nch

Pch

X1A

B

Pch

Nch

Standby control signal

•

Hysteresis input

C

R

Hysteresis input

•

Selectable pull-up option

Pull-up connect/

• CMOS hysteresis input

• CMOS level output

disconnect selection

VCC

Pch

signal

• With standby control

D

Pch

Digital output

Digital output

Nch

R

VSS

Hysteresis input

IOL = 4 mA

Standby control

• CMOS hysteresis input

VCC

• CMOS level output

Pch

Digital output

• With standby control

E

Digital output

Nch

R

VSS

IOL = 4 mA

Hysteresis input

Standby control

(Continued)

14

MB90520A/520B Series

Type

Circuit

Remarks

• Segment output pins

VCC

F

R

Nch

VSS

• Capacitor connection pin

VCC

(This is an N.C. pin on the

G

Pch

MB90522A and MB90523A.)

Nch

VSS

• Analog power supply input

VCC

protection circuit

H

Pch

AVP

Nch

VSS

• CMOS hysteresis input

VCC

• CMOS level output

Pch

Digital output

(CMOS output is not available when

analog output is operating.)

Digital output

• Also used as analog output

I

Nch

(Analog output has priority)

VSS

• With standby control

IOL = 4 mA

R

Hysteresis input

Standby control

Analog output

• A/D converter ref+ power supply

VCC

input pin

Pch

(Incorporates power supply

Pch

ANE

J

Nch

AVP

protection circuit.)

ANE

Nch

VSS

(Continued)

15

MB90520A/520B Series

(Continued)

Type

Circuit

Remarks

• CMOS hysteresis input

VCC

• CMOS level output

Pch

Digital output

• Also used as analog input.

Digital output

• With standby control

K

Nch

VSS

IOL = 4 mA

R

Hysteresis input

Standby control

Analog input

• CMOS hysteresis input

VCC

• CMOS level output

Pch

Digital output

• Also used as segment output pin.

• With standby control

Digital output

(only available when segment

Nch

L

output is not operating.)

VSS

IOL = 4 mA

R

Hysteresis input

Standby control

Segment output/common output

• CMOS hysteresis input

VCC

• N-ch open-drain output

Pch

• Also used as segment output pin.

• With standby control

Open drain

(only available when segment

Nch

M

output is not operaing.)

VSS

IOL = 10 mA

R

Hysteresis input

Standby control

Segment output

• Reference voltage pin for LCD

VCC

controller

Pch

N

R

Nch

VSS

IOL = 10 mA

16

MB90520A/520B Series

■ HANDLING DEVICES

Take note of the following points when handling devices :

•Do not exceed maximum rated voltage (to prevent latch-up)

•Supply voltage stability

•Power-on precautions

•Power supply pins

•Crystal oscillator circuit

•Notes on using an external clock

•Precautions when not using sub-clock mode

•Treatment of unused pins

•Treatment of N.C. pins

•Treatment of pins when A/D converter is not used

•Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

•Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins

•Conditions when output from ports 0 and 1 is undefined

•Initialization

•Notes on using the DIV A, Ri and DIVW A, RWi instructions

•Notes on using REALOS

Device Handling Precautions

•Do not exceed maximum rated voltage (to prevent latch-up)

Latch-up occurs in CMOS ICs if a voltage greater than VCC or less than VSS is applied to an input or output pin (other than a high or medium withstand voltage pin) or if the voltage applied between VCC and VSS exceeds the rating. If latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. Therefore, ensure that maximum ratings are not exceeded in circuit operation.

Similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (AVCC, AVRH, DVCC) and analog input voltages do not exceed the digital voltage (VCC) .

Also ensure that the voltages applied to the LCD power supply pins (V3 to V0) do not exceed the power supply voltage (VCC) .

•Supply voltage stability

Rapid changes in supply voltage may cause the device to misoperate, even if the voltage remains within the allowed operating range. Accordingly, ensure that the VCC supply is stable.

The standard for power supply voltage stability is a peak-to-peak VCC ripple voltage at the mains supply frequency (50 to 60 Hz) of 10% or less of VCC and a transient voltage change rate of 0.1 V/ms or less when

turning the power supply on or off.

•Power-on precautions

To prevent misoperation of the internal regulator circuit at power-on, ensure that the power supply rising time (0.2 V to 2.7 V) is at least 50 s.

•Power supply pins

When multiple VCC and VSS pins are provided, connect all VCC and VSS pins to power supply or ground externally. Although pins at the same potential are connected together in the internal device design so as to prevent misoperation such as latch-up, connecting all VCC and VSS pins appropriately minimizes unwanted radiation, prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output current rating.

Also, ensure that the impedance of the VCC and VSS connections to the power supply are as low as possible.

17

MB90520A/520B Series

Connection of a bypass capacitor of approximately 0.1 µF between VCC and VSS is recommended to prevent power supply noise. Connect the capacitor close to the VCC and VSS pins.

•Crystal oscillator circuit

Noise on the X0 and X1 pins can be a cause of device misoperation. Place the X0 and X1 pins, crystal oscillator (or ceramic oscillator) , and bypass capacitor to ground as close together as possible. Also, design the circuit board so that the X0 and X1 pin wiring does not cross other wiring.

Surrounding the X0/X1 and X0A/X1A pins with ground in the printed circuit board design is recommended to ensure stable operation.

•Notes on using an external clock

When using an external clock, drive the X0 pin only and leave the X1 pin open. The figure below shows an example of how to use an external clock.

Example of how to use an external clock

	X0
Open circuit	X1

MB90520A/520B series

•Precautions when not using sub-clock mode

Connect an oscillator to X0A and X1A, even if not using sub-clock mode.

•Treatment of unused pins

Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup. Always pull-up or pull-down unused pins using a 2 kΩ or larger resistor.

If some I/O pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins.

•Treatment of N.C. pins

Always leave N.C. (non connect) pins open circuit.

•Treatment of pins when A/D converter not used

When not using the A/D converter and D/A converter, always connect AVCC = DVCC = AVRH = VCC and AVSS = AVRL = VSS.

•Sequence for connecting and disconnecting the A/D converter power supply and analog input pins

Do not apply voltage to the A/D and D/A converter power supply (AVCC, AVRH, AVRL, DVCC, DVSS) or analog inputs (AN0 to AN7) until the digital power supply (VCC) is turned on.

When turning the device off, turn off the digital power supply after disconnecting the A/D converter power supply and analog inputs. When turning the power on or off, ensure that AVRH and DVCC do not exceed AVCC (turning the analog and digital power supplies on and off simultaneously is OK) .

•Shared use of general-purpose I/O ports and LCD controller/driver SEG/COM pins

The SEG08 to SEG31 and COM0 to COM3 pins are shared with general-purpose I/O ports. The electrical ratings for SEG08 to SEG23 and COM0 to COM3 are the same as for CMOS outputs and the electrical ratings for SEG24 to SEG31 are the same as for N-ch open-drain ports.

18

MB90520A/520B Series

•Conditions when output from ports 0 and 1 is undefined

After turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabilization delay time controlled by the regulator circuit (during the power-on reset) . The figure below shows the timing.

Note that this undefined output period does not occur on products without an internal regulator circuit as these products do not have an oscillation stabilization delay time.

Timing chart for undefined output from ports 0 and 1

Oscillation stabilization delay time*2

VCC (Power supply pin)

PONR (Power-on reset) signal RST (External asynchronous reset) signal RST (Internal reset) signal Oscillation clock signal KA (Internal operating clock A) signal

KB (Internal operating clock B) signal PORT (port output) signal

Regulator circuit stabilization delay time*1

Undefined output time

*1 : Regulator circuit oscillation stabilization delay time : 217/Oscillation clock frequency (approx. 8.19 ms for a 16 MHz oscillation clock frequency)

*2 : Oscillation stabilization delay time : 218/Oscillation clock frequency (approx. 16.38 ms for a 16 MHz oscillation clock frequency)

Note : See the “■PRODUCT LINEUP” section for details of which MB90520A/520B series products have an internal regulator circuit.

•Initialization

The device contains internal registers that are only initialized by a power-on reset. To initialize these registers, restart the power supply.

•Notes on using the DIV A, Ri and DIVW A, RWi instructions

Set the corresponding bank registers (DTB, ADB, USB, SSB) to “00H” when using the signed division instructions “DIV A, Ri” and “DIVW A, RWi”.

If the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder value produced by the instruction is not stored in the instruction operand register.

•Notes on using REALOS

The extended intelligent I/O service (EI2OS) cannot be used when using REALOS.

Caution on Operations during PLL Clock Mode

If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.

19

MB90520A/520B Series

• BLOCK DIAGRAM

			F2MC-16LX
				CPU
	X0, X1	Main clock
		Sub-clock	Clock controller*1
	X0A, X1A
			(Includes
	RST
			timebase timer)
	HST
	P07			Port 0*2
		7	7	DTP/
	P00/INT0 to P06/INT6
				external
				interrupt
				circuit

			Port 2
	P24/AIN0	3	8/16-bit
	P25/BIN0		up/down
	P26/ZIN0/INT7		counter/
			timer 0, 1
			16-bit
			I/O timer 1
	P20/IC00	2	Input
	P21/IC01		capture 0
			(ICU)
	P22/IC10
			16-bit
	P23/IC11
			freerun
	P32/OUT0		timer 0
			Output
	P33/OUT1	4 compare 0
	P34/OUT2		(OCU)
	P35/OUT3		Clock
	P31/CKOT
			output
	P30		Port 3
	P36/PG00	2	8/16-bit
	P37/PG01
	P40/PG10	2	PPG
			timer 0, 1
	P41/PG11
	P42/SIN0		UART
	P43/SOT0
			(SCI)
	P44/SCK0
	P45/SIN1
	P46/SOT1		SIO ch.1
	P47/SCK1
			Port 4*2

					Port 1*2
8		8
					Wakeup
P10/WI0 to P17/WI7					interrupts

Other pins

MD0 to MD2, C,

VCC, VSS

	8
Ports 8, 9*3, A	P80/SEG16 to P87/SEG23
24	8
	P90/SEG24 to P97/SEG31
LCD	8
	PA0/SEG08 to PA7/SEG15
controller/	8
	SEG00 to SEG07
driver	4
4	V0 to V3
	4
	P74/COM0 to P77/COM3

Port 7

16-bit
reload
timer 0
16-bit						P70/TI0/OUT4
reload
						P71/TO0/OUT5
timer 1
						P72/TI1/OUT6
16-bit
						P73/TO1/OUT7
I/O timer 2
Output	4
compare 1
(OCU)
16-bit
freerun
timer 1

Internal data bus

Port 6

8

8

P60/AN0 to P67/AN7

8/10-bit

AVCC

AVSS

A/D

AVRH

converter

AVRL

Port 2

P27/ADTG

Interrupt controller

Port 5

P50/SIN2/AIN1

SIO ch.2

P51/SOT2/BIN1

P52/SCK2/ZIN1

P53/DA0

8-bit

2

P54/DA1

D/A

converter

DVCC

× 2 ch

DVSS

RAM

ROM

*1 : The clock control circuit includes the watchdog timer and timebase timer low power consumption control circuits.

*2 : Incorporates a pull-up register setting register. CMOS level input and output.

*3 : As this port shares pins with the LCD output, the port uses N-ch open-drain circuits.

20

MB90520A/520B Series

■ MEMORY MAP

Single chip mode with mirror function

	FFFFFFH
		ROM area
	Address #1
	FE0000H
	010000H
		ROM area
		(image of
	Address #2	FF bank)
	004000H
	002000H
	Address #3
		RAM Registers
	000100H
	0000C0H
		Peripherals
	000000H

Part No.	Address #1*	Address #2*	Address #3*
MB90522A/B	FF0000H	004000H	001100H
MB90523A/B	FE0000H	004000H	001100H
MB90F523B	FE0000H	004000H	001100H
MB90V520A			001900H

: Internal memory access

: Access prohibited

* : The values of addresses #1, #2, and #3 vary by product.

Note : The upper part of 00 bank contains a mirror of the ROM data in FF bank. This is called the mirror ROM function and enables use of the C compiler’s small memory model. As the lower 16 bits of the FF bank and 00 bank addresses are the same, tables located in ROM can be referenced without needing to declare far pointers.

For example, accessing 00C000H actually accesses the contents of ROM at FFC000H. Note that, as the FF bank ROM area exceeds 48 KBytes, the entire ROM image cannot be mirrored in 00 bank. Accordingly, as ROM data from FF4000H to FFFFFFH is mirrored in 004000H to 00FFFFH, always locate ROM data tables in the range FF4000H to FFFFFFH.

21

MB90520A/520B Series

■ I/O MAP

		Abbreviated
	Address	Register	Register Name	Peripheral Name	Initial Value
		Name
	000000H	PDR0	Port 0 data register	Port 0	XXXXXXXXB
	000001H	PDR1	Port 1 data register	Port 1	XXXXXXXXB
	000002H	PDR2	Port 2 data register	Port 2	XXXXXXXXB
	000003H	PDR3	Port 3 data register	Port 3	XXXXXXXXB
	000004H	PDR4	Port 4 data register	Port 4	XXXXXXXXB
	000005H	PDR5	Port 5 data register	Port 5	XXXXXXXXB
	000006H	PDR6	Port 6 data register	Port 6	XXXXXXXXB
	000007H	PDR7	Port 7 data register	Port 7	XXXXXXXXB
	000008H	PDR8	Port 8 data register	Port 8	XXXXXXXXB
	000009H	PDR9	Port 9 data register	Port 9	XXXXXXXXB
	00000AH	PDRA	Port A data register	Port A	XXXXXXXXB
	00000BH	LCDCMR	Port 7/COM pin selection register	Port 7,	XXXX 0 0 0 0B
				LCD controller/driver
	00000CH	OCP4	OCU compare register ch.4	16-bit I/O timer	XXXXXXXXB
	00000DH				XXXXXXXXB
	00000EH		(Access prohibited)
	00000FH	EIFR	Wakeup interrupt flag register	Wakeup interrupts	XXXXXXX0B
	000010H	DDR0	Port 0 direction register	Port 0	0 0 0 0 0 0 0 0B
	000011H	DDR1	Port 1 direction register	Port 1	0 0 0 0 0 0 0 0B
	000012H	DDR2	Port 2 direction register	Port 2	0 0 0 0 0 0 0 0B
	000013H	DDR3	Port 3 direction register	Port 3	0 0 0 0 0 0 0 0B
	000014H	DDR4	Port 4 direction register	Port 4	0 0 0 0 0 0 0 0B
	000015H	DDR5	Port 5 direction register	Port 5	XXX 0 0 0 0 0B
	000016H	DDR6	Port 6 direction register	Port 6	0 0 0 0 0 0 0 0B
	000017H	DDR7	Port 7 direction register	Port 7	0 0 0 0 0 0 0 0B
	000018H	DDR8	Port 8 direction register	Port 8	0 0 0 0 0 0 0 0B
	000019H	DDR9	Port 9 direction register	Port 9	0 0 0 0 0 0 0 0B
	00001AH	DDRA	Port A direction register	Port A	0 0 0 0 0 0 0 0B
	00001BH	ADER	Analog input enable register	Port 6, A/D converter	1 1 1 1 1 1 1 1B
	00001CH	OCP5	OCU compare register ch.5	16-bit I/O timer	XXXXXXXXB
	00001DH				XXXXXXXXB
	00001EH		(Access prohibited)
	00001FH	EICR	Wakeup interrupt enable register	Wakeup interrupts	0 0 0 0 0 0 0 0B

(Continued)

22

MB90520A/520B Series

		Abbreviated
	Address	Register	Register Name	Peripheral Name	Initial Value
		Name
	000020H	SMR	Serial mode register		0 0 0 0 0 0 0 0B
	000021H	SCR	Serial control register	UART	0 0 0 0 0 1 0 0B
		SIDR/	Serial input data register/
	000022H			(SCI)	XXXXXXXXB
		SODR	Serial output data register
	000023H	SSR	Serial status register		0 0 0 0 1 X 0 0B
	000024H	SMCS1	Serial mode control status register 1	Extended I/O serial	XXXX 0 0 0 0B
	000025H				0 0 0 0 0 0 1 0B
				interface 1
	000026H	SDR1	Serial data register 1		XXXXXXXXB
	000027H	CDCR	Communication prescaler control	Communication prescaler	0 XXX 1 1 1 1B
			register	register
	000028H	SMCS2	Serial mode control status register 2	Extended I/O serial	XXXX 0 0 0 0B
	000029H				0 0 0 0 0 0 1 0B
				interface 2
	00002AH	SDR2	Serial data register 2		XXXXXXXXB
	00002BH		(Access prohibited)
	00002CH	OCS45	OCU control status register ch.45		0 0 0 0 XX 0 0B
	00002DH			16-bit I/O timer	XXX 0 0 0 0 0B
	00002EH	OCS67	OCU control status register ch.67		0 0 0 0 XX 0 0B
	00002FH				XXX 0 0 0 0 0B
	000030H	ENIR	DTP/interrupt enable register		0 0 0 0 0 0 0 0B
	000031H	EIRR	DTP/interrupt request register	DTP /external interrupt	XXXXXXXXB
	000032H	ELVR	Request level setting register	circuit	0 0 0 0 0 0 0 0B
	000033H				0 0 0 0 0 0 0 0B
	000034H	OCP6	OCU compare register ch.6	16-bit I/O timer	XXXXXXXXB
	000035H				XXXXXXXXB
	000036H	ADCS	A/D control status register		0 0 0 0 0 0 0 0B
	000037H			8/10-bit A/D converter	0 0 0 0 0 0 0 0B
	000038H	ADCR	A/D data register		XXXXXXXXB
	000039H				0 0 0 0 1 XXXB
	00003AH	DADR0	D/A converter data register ch.0		XXXXXXXXB
	00003BH	DADR1	D/A converter data register ch.1	8-bit D/A converter	XXXXXXXXB
	00003CH	DACR0	D/A control register 0		XXXXXXX 0B
	00003DH	DACR1	D/A control register 1		XXXXXXX 0B
	00003EH	CLKR	Clock output enable register	Clock monitor function	XXXX 0 0 0 0B

(Continued)

23

MB90520A/520B Series

		Abbreviated
	Address	Register	Register Name	Peripheral Name	Initial Value
		Name
	00003FH		(Access prohibited)
	000040H	PRLL0	PPG0 reload register L		XXXXXXXXB
	000041H	PRLH0	PPG0 reload register H		XXXXXXXXB
	000042H	PRLL1	PPG1 reload register L		XXXXXXXXB
				8/16-bit PPG timer 0, 1
	000043H	PRLH1	PPG1 reload register H		XXXXXXXXB
	000044H	PPGC0	PPG0 operation mode control register		0 X 0 0 0 XX 1B
	000045H	PPGC1	PPG1 operation mode control register		0 X 0 0 0 0 0 1B
	000046H	PPGOE	PPG0, 1 output control register		0 0 0 0 0 0 0 0B
	000047H		(Access prohibited)
	000048H	TMCSR0	Timer control status register ch.0		0 0 0 0 0 0 0 0B
	000049H			16-bit reload timer 0	XXXX 0 0 0 0B
	00004AH	TMR0/	16-bit timer register ch.0/		XXXXXXXXB
	00004BH	TMRLR0	16-bit reload register ch.0		XXXXXXXXB
	00004CH	TMCSR1	Timer control status register ch.1		0 0 0 0 0 0 0 0B
	00004DH			16-bit reload timer 1	XXXX 0 0 0 0B
	00004EH	TMR1/	16-bit timer register ch.1/		XXXXXXXXB
	00004FH	TMRLR1	16-bit reload register ch.1		XXXXXXXXB
	000050H	IPCP0	ICU data register ch.0		XXXXXXXXB
	000051H				XXXXXXXXB
	000052H	IPCP1	ICU data register ch.1	16-bit I/O timer	XXXXXXXXB
	000053H				XXXXXXXXB
	000054H	ICS01	ICU control status register		0 0 0 0 0 0 0 0B
	000055H		(Access prohibited)
	000056H	TCDT0	Freerun timer data register 0		0 0 0 0 0 0 0 0B
	000057H			16-bit I/O timer	0 0 0 0 0 0 0 0B
	000058H	TCCS0	Freerun timer control status register 0		0 0 0 0 0 0 0 0B
	000059H		(Access prohibited)
	00005AH	OCP0	OCU compare register ch.0		XXXXXXXXB
	00005BH				XXXXXXXXB
	00005CH	OCP1	OCU compare register ch.1	16-bit I/O timer	XXXXXXXXB
	00005DH				XXXXXXXXB
	00005EH	OCP2	OCU compare register ch.2		XXXXXXXXB
	00005FH				XXXXXXXXB

(Continued)

24

MB90520A/520B Series

		Abbreviated
	Address	Register	Register Name		Peripheral Name	Initial Value
		Name
	000060H	OCP3	OCU compare register ch.3			XXXXXXXXB
	000061H					XXXXXXXXB
	000062H	OCS01	OCU control status register ch.0, ch.1		16-bit I/O timer	0 0 0 0 XX 0 0B
	000063H					XXX 0 0 0 0 0B
	000064H	OCS23	OCU control status register ch.2, ch.3			0 0 0 0 XX 0 0B
	000065H					XXX 0 0 0 0 0B
	000066H	TCDT1	Freerun timer data register 1			0 0 0 0 0 0 0 0B
	000067H				16-bit I/O timer	0 0 0 0 0 0 0 0B
	000068H	TCCS1	Freerun timer control status register 1			0 0 0 0 0 0 0 0B
	000069H		(Access prohibited)
	00006AH	LCR0	LCDC control register 0		LCD controller/driver	0 0 0 1 0 0 0 0B
	00006BH	LCR1	LCDC control register 1			0 0 0 0 0 0 0 0B
	00006CH	OCP7	OCU compare register ch.7		16-bit I/O timer	XXXXXXXXB
	00006DH					XXXXXXXXB
	00006EH		(Access prohibited)
	00006FH	ROMM	ROM mirror function selection register		ROM mirror function	XXXXXXX1B
					selection module
	000070H
	to	VRAM	Data memory for LCD display		LCD controller/driver	XXXXXXXXB
	00007FH
	000080H	UDCR0	Up/down count register 0			0 0 0 0 0 0 0 0B
	000081H	UDCR1	Up/down count register 1		8/16-bit up/down	0 0 0 0 0 0 0 0B
	000082H	RCR0	Reload compare register 0			0 0 0 0 0 0 0 0B
					counter/timer 0, 1
	000083H	RCR1	Reload compare register 1			0 0 0 0 0 0 0 0B
	000084H	CSR0	Counter status register 0			0 0 0 0 0 0 0 0B
	000085H		(Reserved) *3
	000086H	CCR0	Counter control register 0		8/16-bit up/down	X 0 0 0 0 0 0 0B
	000087H					0 0 0 0 0 0 0 0B
					counter/timer 0, 1
	000088H	CSR1	Counter status register 1			0 0 0 0 0 0 0 0B
	000089H		(Reserved) *3
	00008AH	CCR1	Counter control register 1		8/16-bit up/down	X 0 0 0 0 0 0 0B
	00008BH				counter/timer 0, 1	X 0 0 0 0 0 0 0B
	00008CH	RDR0	Port 0		Port 0	0 0 0 0 0 0 0 0B
			input pull-up resistor setup register
	00008DH	RDR1	Port 1		Port 1	0 0 0 0 0 0 0 0B
			input pull-up resistor setup register
						(Continued)

25

MB90520A/520B Series

		Abbreviated
	Address	Register	Register Name	Peripheral Name	Initial Value
		Name
	00008EH	RDR4	Port 4	Port 4	0 0 0 0 0 0 0 0B
			input pull-up resistor setup register
	00008FH		(Access prohibited)
	to
			(Area reserved for system use) *4
	00009DH
	00009EH	PACSR	Address detection control register	Address match detection	0 0 0 0 0 0 0 0B
				function
	00009FH	DIRR	Delayed interrupt request output/clear	Delayed interrupt	XXXXXXX 0B
			register	generation module
	0000A0H	LPMCR	Low power consumption mode control	Low power consumption	0 0 0 1 1 0 0 0B
			register
				(standby) mode
	0000A1H	CKSCR	Clock selection register		1 1 1 1 1 1 0 0B
	0000A2H
	to		(Access prohibited)
	0000A7H
	0000A8H	WDTC	Watchdog timer control register	Watchdog timer	XXXXXXXXB
	0000A9H	TBTC	Timebase timer control register	Timebase timer	1 XX 0 0 0 0 0B
	0000AAH	WTC	Clock timer control register	Clock timer	1 X 0 0 1 0 0 0B
	0000ABH
	to		(Access prohibited)
	0000ADH
	0000AEH	FMCS	Flash memory control status register	1 Mbit flash memory	0 0 0 X 0 0 0 0B
	0000AFH		(Access prohibited)
	0000B0H	ICR00	Interrupt control register 00		0 0 0 0 0 1 1 1B
	0000B1H	ICR01	Interrupt control register 01		0 0 0 0 0 1 1 1B
	0000B2H	ICR02	Interrupt control register 02		0 0 0 0 0 1 1 1B
	0000B3H	ICR03	Interrupt control register 03		0 0 0 0 0 1 1 1B
	0000B4H	ICR04	Interrupt control register 04		0 0 0 0 0 1 1 1B
	0000B5H	ICR05	Interrupt control register 05		0 0 0 0 0 1 1 1B
	0000B6H	ICR06	Interrupt control register 06	Interrupt controller	0 0 0 0 0 1 1 1B
	0000B7H	ICR07	Interrupt control register 07		0 0 0 0 0 1 1 1B
	0000B8H	ICR08	Interrupt control register 08		0 0 0 0 0 1 1 1B
	0000B9H	ICR09	Interrupt control register 09		0 0 0 0 0 1 1 1B
	0000BAH	ICR10	Interrupt control register 10		0 0 0 0 0 1 1 1B
	0000BBH	ICR11	Interrupt control register 11		0 0 0 0 0 1 1 1B
	0000BCH	ICR12	Interrupt control register 12		0 0 0 0 0 1 1 1B
	0000BDH	ICR13	Interrupt control register 13		0 0 0 0 0 1 1 1B

(Continued)

26

MB90520A/520B Series

(Continued)

	Abbreviated
Address	Register	Register Name		Peripheral Name	Initial Value
	Name
0000BEH	ICR14	Interrupt control register 14		Interrupt controller	0 0 0 0 0 1 1 1B
0000BFH	ICR15	Interrupt control register 15			0 0 0 0 0 1 1 1B
0000C0H
to		(Access prohibited) *1
0000FFH
000100H
to		(RAM area) *2
00####H
00####H
to		(Reserved area) *3
001FEFH
001FF0H		Detection address setting register 0			XXXXXXXXB
		(low byte)
001FF1H	PADR0	Detection address setting register 0			XXXXXXXXB
		(middle byte)
001FF2H		Detection address setting register 0			XXXXXXXXB
		(high byte)		Address match
001FF3H		Detection address setting register 1		detection function	XXXXXXXXB
		(low byte)
001FF4H	PADR1	Detection address setting register 1			XXXXXXXXB
		(middle byte)
001FF5H		Detection address setting register 1			XXXXXXXXB
		(high byte)
001FF6H
to		(Reserved area) *3
001FFFH

Initial value notation

0: Initial value of bit is “0”.

1: Initial value of bit is “1”.

X : Initial value of bit is undefined.

*1 : Access is prohibited to the address range 0000C0H to 0000FFH. See the “■ MEMORY MAP” section.

*2 : See the “■ MEMORY MAP” section for details of the “ (RAM area) ”.

*3 : “ (Reserved areas) ” are addresses used internally by the system and may not be used.

*4 : The “ (Area reserved for system use) ” contains setting registers used by the evaluation tools.

Notes : • LPMCR, CKSCR, and WDTC are initialized by some types of reset and not by others. The initial values listed are for the case when the registers are initialized.

•The boundary address “####H” between the “ (RAM area) ” and “ (Reserved area) ” differs depending on the product. See the “■ MEMORY MAP” section for details.

•OCU compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and OCU compare registers ch.4 to ch.7 use 16-bit freerun timer 1. Note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (ICU) .

27

MB90520A/520B Series

■ INTERRUPTS, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS

	Interrupt	EI2OS	Interrupt Vector		Interrupt Control Register		Priority
		Support	No.	Address	ICR	Address
	Reset	×	#08	FFFFDCH			High
	INT 9 instruction	×	#09	FFFFD8H
	Exception	×	#10	FFFFD4H
	8/10-bit A/D converter		#11	FFFFD0H	ICR00	0000B0H
	Timebase timer	×	#12	FFFFCCH
	DTP0/DTP1		#13	FFFFC8H
	(external interrupt 0/external interrupt 1)				ICR01	0000B1H
	16-bit freerun timer 0 overflow	×	#14	FFFFC4H
	Extended I/O serial interface 1		#15	FFFFC0H	ICR02	0000B2H
	Wakeup interrupt	×	#16	FFFFBCH
	Extended I/O serial interface 2		#17	FFFFB8H
					ICR03	0000B3H
	DTP2/DTP3		#18	FFFFB4H
	(external interrupt 2/external interrupt 3)
	8/16-bit PPG timer 0 counter borrow	×	#19	FFFFB0H
					ICR04	0000B4H
	DTP4/DTP5		#20	FFFFACH
	(external interrupt 4/external interrupt 5)
	8/16-bit up/down counter/timer 0		#21	FFFFA8H
	compare match
					ICR05	0000B5H
	8/16-bit up/down counter/timer 0		#22	FFFFA4H
	overflow, up/down direction change
	8/16-bit PPG timer 1 counter borrow	×	#23	FFFFA0H
					ICR06	0000B6H
	DTP6/DTP7		#24	FFFF9CH
	(external interrupt 6/external interrupt 7)
	Output compare 1 (OCU) ch.4, ch.5 match		#25	FFFF98H	ICR07	0000B7H
	Clock timer	×	#26	FFFF94H
	Output compare 1 (OCU) ch.6, ch.7 match		#27	FFFF90H	ICR08	0000B8H
	16-bit freerun timer 1 overflow	×	#28	FFFF8CH
	8/16-bit up/down counter/timer 1		#29	FFFF88H
	compare match
					ICR09	0000B9H
	8/16-bit up/down counter/timer 1		#30	FFFF84H
	overflow, up/down direction change
	Input capture 0 (ICU) capture		#31	FFFF80H	ICR10	0000BAH
	Input capture 1 (ICU) capture		#32	FFFF7CH
	Output compare 0 (OCU) ch.0 match		#33	FFFF78H	ICR11	0000BBH
	Output compare 0 (OCU) ch.1 match		#34	FFFF74H

(Continued)

28

MB90520A/520B Series

(Continued)

	Interrupt	EI2OS	Interrupt Vector		Interrupt Control Register		Priority
		Support	No.	Address	ICR	Address
	Output compare 0 (OCU) ch.2 match		#35	FFFF70H	ICR12	0000BCH
	Output compare 0 (OCU) ch.3 match		#36	FFFF6CH
	UART (SCI) receive complete		#37	FFFF68H	ICR13	0000BDH
	16-bit reload timer 0		#38	FFFF64H
	UART (SCI) send complete		#39	FFFF60H	ICR14	0000BEH
	16-bit reload timer 1		#40	FFFF5CH
	Flash memory	×	#41	FFFF58H	ICR15	0000BFH
	Delayed interrupt generation module	×	#42	FFFF54H			Low

: Supported

× : Not supported

: Supported, includes EI2OS stop function

29

MB90520A/520B Series

■ PERIPHERAL RESOURCES

1.I/O Ports

•The I/O ports can be used as general-purpose I/O ports (parallel I/O ports) . The MB90520A and 520B series have 11 ports (85 pins) . The ports share pins with the inputs and outputs of the peripheral functions.

•The port data registers (PDR) are used to output data to the I/O pins and capture the input signals from the I/O ports.

Similarly, the port direction registers (DDR) set the I/O direction (input or output) for each individual port bit.

•The following tables list the I/O ports and peripheral functions with which they share pins.

		Pin Name	Pin Name (Peripheral)	Peripheral Function that Shares Pin
		(Port)
	Port 0	P00 − P06	INT0 − INT6	External interrupts
		P07		Not shared
	Port 1	P10 − P17	WI0 − WI7	Wakeup interrupts
		P20 − P23	IN00 − IN11	Input capture (unit 0)
	Port 2	P24, P25	AIN0, BIN0	8/16-bit up/down counter/timer 0
		P26	ZIN0/INT7	8/16-bit up/down counter/timer 0, external interrupt
		P30		Not shared
	Port 3	P31	CKOT	Clock monitor function
		P32 − P35	OUT0 − OUT3	Output compare (unit 0)
		P36, P37	PPG00, PPG01	8/16-bit PPG timer 0
		P40, P41	PPG10, PPG11	8/16-bit PPG timer 1
	Port 4	P42 − P44	SIN0, SOT0, SCK0	UART (SCI)
		P45 − P47	SIN1, SOT1, SCK1	Extended I/O serial interface 0
		P50 − P52	SIN2/AIN1,	8/16-bit up/down counter/timer 0
			SOT1/BIN1,
	Port 5			Extended I/O serial interface 1
			SCK1/ZIN1
		P53, P54	DA0, DA1	8-bit D/A converter
	Port 6	P60 − P67	AN0 − AN7	8/16-bit A/D converter
			TIN0/OUT4,
		P70 − P73	TOT0/OUT5,	16-bit reload timers 0, 1
	Port 7		TIN1/OUT6,	Output compare (unit 1)
			TOT1/OUT7
		P74 − P77	COM0 − COM3	LCD control driver common output
	Port 8	P80 − P87	SEG16 − SEG23	LCD control driver segment output
	Port 9	P90 − P97	SEG24 − SEG31	LCD control driver segment output
	Port A	PA0 − PA7	SEG8 − SEG15	LCD control driver segment output

Notes

•Port 9 contains general-purpose I/O ports with N-ch open-drain output circuits.

•Connect an external pull-up resistor when using port 9 pins as outputs.

•Port 6 shares pins with the analog inputs. When using port 6 as a general-purpose port, ensure that the corresponding analog input enable register (ADER) bits are set to “0”. ADER is initialized to “FF H” after a reset.

30