The Fujitsu 5V-Only Flash memory cards are electrically erasable and programmable memory cards capable of
storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin
package. Internal circuit is protected by two metal panels, one at the top and the other at the bottom of the card,
that help to reduce chip damage from electrostatic discharge.
A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit
bus configuration. All cards are portable and operate on low power at high speed.
In accordance with the Personal Computer Memory Card Internal Association (PCMCIA) and Japan Electrical
Industry Development Association (JEID A) industry standard specifications, Flash memory cards offer additional
EEPROM memory that is used to store attribute data. The attribute memory is a Flash memory card option.
(See page 3 for description of the three available options.)
PRODUCT LINE & FEATURES
■
• Meet PCMCIA and JEIDA industry standards for 68-pin memory card
Type I : 85.6 mm × 54.0 mm × 3.3 mm
•+5 V±5% power supply program and erase
• Command control for Automated Program / Automated Erase operation
• Erase Suspend Read / Program Capability (Only Erase Suspend Read is possible for MB98A81063)
• 128 KB Sector Erase (at ×16 mode)
• Any Combination of Sectors Erase and Full Chip Erase
• Detection of completion of program/erase operation with Data
• Ready/Busy Output with R/B (Except for MB98A81063)
• Reset Function with RESET pin (Except for MB98A81063)
The data in the common and attribute memory can be read with “OE=VIL” and “WE=VIH”. The address is selected
with A
The following 1) and 2) are the descriptions for Common Memory Read and Attribute Memory Read mode.
(1) Common Memory Read
(2) Attribute Memory Read
2.Standby Mode
3.Output Disable Mode
4.Write Mode
(1) Common Memory Wr ite
(2) Attribute Memory Write
5.Command Definitions
6.Automated Program Capability
7.Automated Chip Erase Capability
to A24. And CE1 and CE2 select output mode (× 8/× 16 output mode, See “FUNCTION TRUTH TABLES”.).
0
- Two modes of Common Memory Read, reading the data in memory array and Intelligent ID are available.
The card enter each Read mode by writing “Read Memory/Reset Command” or “Intelligent ID Read Command”.
The card automatically resets to the condition of Common Memory Read mode upon initial power-up.
- The data on the attribute memory can be read with “REG
- An address on attribute memory can be selected with A
-CE1 and CE2 at “VIH” place the card in Standby mode. D0 to D15 are placed in a high-Z state independent of
the status “OE
- The outputs are disabled with OE and WE at “VIH”. D0 to D15 are placed in high-Z state.
- The card is in Write mode with “OE
- Commands can be written at the Write mode. See “5.Command Definitions”.
- Two types of the Write mode, “WE
-REG
- Attribute memory is not controlled by writing Commands. And attribute memory has the Data polling function,
- User can select the card operation by writing the specific address and data sequences into the command
- Programming operation can swich the data from “1” to “0”.
- The data is programmed on a byte-by-byte or word-by-word basis.
- The card will automatically provide adequate internally generated programming pulses and verify the
- Addresses are latched at falling edge of WE
- We can check whether a byte (word) progr amming operation is completed successfully b y sequence flug with
- Any commands written to the chip during programming operation will be ignored.
- We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to pre-
- The card returns to Common Memory Read mode automatically after the chip erasing is completed.
at L-level selects Attrib ute memory and “OE=VIH”, “WE and CE=VIL” place it in write mode. Two types of
the write mode, “WE
which can detect whether the attribute memory status is in programming operation. When the read operation
is executed at programming cycle, the opposite data is output from D
written data is output from D
register. If incollect address and data are written or improper sequence is done, the card is reseted to read
mode. See “COMMAND DEFINISION TABLE”.
programmed cell margine by writing four bus cycle operation. The card returns to Common Memory Read
mode automatically after the programming is completed.
rising edge of WE or CE on the command write cycle begins programming operation.
R/B
(Except for MB98A81063), Data Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
program prior to erase. Upon executing the Erase command sequence the chip automatically will program
and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timing during these operations.
”, “WE” and “REG”.
=VIH” and “WE and CE=VIL”.
control” and “CE control” are available.
control” and “CE control” are available.
pin at the completion of programming operation.
7
or CE and data is latched at rising edge of WE or CE. The fourth
- Whether or not chip erase operation is completed successfully can be checked by sequence flug with R/B
(Except for MB98A81063), Data
- Any commands written to the chip during programming operation will be ignored.
8.Automated Sector Erase Capability
- We can execute the erase operation on any sectors by 6 bus cycle operation.
- A time-out of 50 µs (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase
command(s) for other sector than the sector that sector erase command have been valid.
- Multiple sectors in a chip can be erased concurrently . This sequence is followed with writes of 30H to addresses
in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs,
otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend during
this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50 µs (typ.)
time out from the rising edge of WE
window is still open can be monitored with D
- Sector Erase does not require the user to pre-program prior to erase. The chip automatically programs “0” to
all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any controls
or timing during these operations.
- The card returns to Common Memory Read mode automatically after the sector erasing is completed.
- Whether or not sector erase operation is completed successfully can be checked by sequence flug with R/B
Data Polling or Toggle Bit function. The sequence flug must be read from the address of the sector inv olv ed in
erase operation. See “WRITE OPERATION STATUS”.
9.Erase Suspend
- Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or
program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is
possible for MB98A81063). This command is applicab le only during the sector erase oper ation (including the
sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the
chip erase or programming operation. Writing this command during the time-out will result in immediate
termination of the time-out period. The addresses are “don’t cares” in wrinting the Erase Suspend or Resume
commands in the chip.
- When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase
Suspend Read mode. User can read the data from other sectors than those in suspention. The read operation
from sectors in suspention results D
non-busy sectors by writing program commands for MB98A81183 and MB98A8xx7x.
- A read from a sector being erase suspended may result in invalid data.
10. Intelligent Identifier (ID) Read Mode
- Each common memory can execute an Intelligent Identifier oper ation, initiated by writing Intelligent ID command
(90H). Following the command write, a read cycle from address 00H retrieves the manufacture code, and a
read cycle from address 01H returns the device code as follows. To terminate the operation, it is necessary
to write Read/Reset command.
Part NumberMaker CodeDevice Code
MB98A8106304 h / 0404 hA4 h / A4A4 h
MB98A8118304 h / 0404 hD5 h / D5D5 h
MB98A81273/81373/1473/8157304 h / 0404 h3D h / 3D3D h
Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.
pulse for the last Sector Erase command pulse. Whether the sector er ase
and D11.
3
toggling for MB98A81183 and MB98A8xx7x. User can program to
2/D10
,
11. Hardware Reset (not applied for MB98A81063)
- The Card may be reset by driving the RESET pin to VIH. The RESET pin must be kept High (VIH) for at least
500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs after
the RESET pin is driven High. If a hardware reset occurs during a program operation, the data at that particular
location will be indeterminate.
- When the RESET pin is high and the internal reset is complete, the Card goes to standby mode and cannot
be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET pulse. Once
the RESET pin is taken low, the Card requires 500 ns of wake up time until outputs are valid for read access.
- If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be
used after this.
- The card has WP (Write Protect) switch for write lockout.
- T o a void initiation of a write cycle during V
than 3.2 V (typically 3.7 V). If V
CC
< V
circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be
ignored until the V
level is greater than V
CC
logically correct to prevent unintentional writes when V
-If V
would be less than V
CC
operation will not resume ev en if V
during program/erase operation, the operation will stop. And after that, the
LKO
returns recommended voltage level. Theref ore, prog ram command must
CC
be written again because the data on the address interrupted program operation is invalid. And regarding
interrupting erase operation, there is possibility that the erasing sector(s) cannot be used.
- Noise pulses of less than 5 ns (typical) on OE
FUNCTION TRUTH TABLE
■
MAIN MEMORY FUNCTION*1
power-up and power-do wn, a write cycle is locked out f or VCC less
CC
, the command register is disabled and all internal program/erase
LKO
It is the users responsibility to ensure that the control pins are
LKO.
is above 3.2 V.
CC
, CE or WE will not initiate a write cycle.
ModeRESET*3 REG
CE2CE1A0OEWE
WP
*2
Data Input/Output
D8 to D
D0 to D
15
WP SW
7
Hardware Reset HXXXXXXXHigh-Z
Standby
Read (×8 No.1)
Read (×8 No.1)H
Read (×8 No.2)
Read (×16)LD
Write (×8 No.1)
Output DisableHHigh-ZP
L
Write (×8 No.1)
Output DisableH
Write (×8 No.2)
Output DisableHHigh-ZP
Write (×16)
XHHXXXXHigh-Z
OUT
D
(Even Byte)
OUT
D
(Odd Byte)
High-Z
OUT
D
(Even Byte)
HL
H
L
L
LHX
X
L
L
High-Z
OUT
D
(Odd Byte)
H
HL
L
H
High-Z
D
(Odd Byte)
HL
IN
H
L
L
X
D
(Odd Byte)
LD
High-Z
IN
P or NP
IN
IN
L
Output DisableHHigh-ZP
NP
NP
P
NP
NP
Output DisableXXXXHHXHigh-ZP or NP
Notes:
*1:H =V
, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect
IH
*2:L-level is output when WPSW = NP. H-level is output when WPSW = P.
*3:Not available for MB98A81063.
CA: Chip Address.(address in chip selected by A
SA: Sector Address(address in 64 KB selected by A
PA:Program Address(address to be programmed)
RA: Read Address(address to be read)
IA:Intelligent ID read address (Manufacture Code 0000H, Device Code 0002H)
PD: Programming data
RD: Read data
ID:Intelligent Identifier (ID) Code
CCMA1, CCMA2:Command adddress for chip erase
SCMA1, SCMA2:Command address for sector erase
PCMA1, PCMA2:Command address for program
RCMA1, RCMA2:Command address for Read/Reset
ICMA1, ICMA2:Command address for intelligent ID read
14
, A22, A23 and A24)
0
, A17, A18, A19, A20, A21, A22, A23 and A24)
0
See “Command Address Table for
8-bit Mode” in page 16.
CA: Chip Address.(address in chip selected by A
SA: Sector Address(address in 128 KB selected by A
, A23 and A24)
22
, A18, A19, A20, A21, A22, A23 and A24)
17
PA:Program Address(address to be programmed)
RA: Read Address(address to be read)
IA:Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)
PD: Programming data
RD: Read data
ID:Intelligent Identifier (ID) Code
CCMA1, CCMA2:Command address for chip erase
SCMA1, SCMA2:Command address for sector erase
PCMA1, PCMA2:Command address for program
RCMA1, RCMA2:Command address for Read/Reset
See “Command Address Table for
16-bit Mode” in page 16.
ICMA1, ICMA2:Command address for intelligent ID read
*1: Address number is not contained “A
CCMA1(CA AND 000001h) OR AAAAh(CA AND 000001h) OR AAAhCA
CCMA2(CA AND 000001h) OR 5554h(CA AND 000001h) OR 554hCA
SCMA1(SA AND 000001h) OR AAAAh(SA AND 000001h) OR AAAhCA
SCMA2(SA AND 000001h) OR 5554h(SA AND 000001h) OR 554hCA
PCMA1(PA AND 000001h) OR AAAAh(PA AND 000001h) OR AAAhCA
PCMA2(PA AND 000001h) OR 5554h(PA AND 000001h) OR 554hCA
RCMA1(RA AND 000001h) OR AAAAh(RA AND 000001h) OR AAAhCA
RCMA2(RA AND 000001h) OR 5554h(RA AND 000001h) OR 554hCA
ICMA1(IA AND 000001h) OR AAAAh(IA AND 000001h) OR AAAhCA
ICMA1(IA AND 000001h) OR 5554h(IA AND 000001h) OR 554hCA