FUJITSU DS05-30333-3E DATA SHEET

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FUJITSU SEMICONDUCTOR

DATA SHEET

MEMORY

5V-ONLY FLASH MEMORY CARD

MB98A81063-15/MB98A81183-15/MB98A81273-15/ MB98A81373-15/MB98A81473-15/MB98A81573-15

1M/2M/4M/8M/16M/32M-BYTE 5V-ONLY

FLASH ERASABLE AND PROGRAMMABLE MEMORY CARD

DS05-30333-3E

DESCRIPTION

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The Fujitsu 5V-Only Flash memory cards are electrically erasable and programmable memory cards capable of storing and retrieving large amounts of data. The memory circuits are housed in a credit-card sized 68-pin package. Internal circuit is protected by two metal panels, one at the top and the other at the bottom of the card, that help to reduce chip damage from electrostatic discharge.

A unique feature of the Fujitsu memory cards allows the user to organize the card into either an 8-bit or a 16-bit bus configuration. All cards are portable and operate on low power at high speed.

In accordance with the Personal Computer Memory Card Internal Association (PCMCIA) and Japan Electrical Industry Development Association (JEID A) industry standard specifications, Flash memory cards offer additional EEPROM memory that is used to store attribute data. The attribute memory is a Flash memory card option. (See page 3 for description of the three available options.)

PRODUCT LINE & FEATURES

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• Meet PCMCIA and JEIDA industry standards for 68-pin memory card Type I : 85.6 mm × 54.0 mm × 3.3 mm

•+5 V±5% power supply program and erase

• Command control for Automated Program / Automated Erase operation

• Erase Suspend Read / Program Capability (Only Erase Suspend Read is possible for MB98A81063)

• 128 KB Sector Erase (at ×16 mode)

• Any Combination of Sectors Erase and Full Chip Erase

• Detection of completion of program/erase operation with Data

• Ready/Busy Output with R/B (Except for MB98A81063)

• Reset Function with RESET pin (Except for MB98A81063)

• Write protect function with WP switch

•Low V

Write Inhibit

Polling or Toggle bit.

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

PACKAGE

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CRD-68P-M17

MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

DESCRIPTIONS

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DESCRIPTION TABLE

Common Memory Attribute Memory

Part Number

Memory Device

MB98A81063 4M bit Flash Memory × 21M × 8/512K × 16 MB98A81183 8M bit Flash Memory × 22M × 8/1M × 16

Organization

(W × bit)

Access

Time

Memory

Device

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Organization

(W × bit)

Access

Time

MB98A81273 16M bit Flash Memory × 24M × 8/2M × 16 MB98A81373 16M bit Flash Memory × 48M × 8/4M × 16

150 ns

max.

16K bit

EEPROM × 1

2K × 8

250 ns

max.

MB98A81473 16M bit Flash Memory × 816M × 8/8M × 16 MB98A81573 16M bit Flash Memory × 16 32M × 8/16M × 16

DIFFERENCES

MB98A81063 MB98A81183 MB98A81273 MB98A81373 MB98A81473 MB98A81573

Density 1MB 2MB 4MB 8MB 16MB 32MB Memory Device 4M bit 8M bit 16M bit ←←← Quantity 2224816 Read 1 B unit ←←←←← Program 1 B unit ←←←←← Chip Erase 512 KB unit 1 MB unit 2 MB unit ←←← Sector Erase 64 KB unit ←←←←← Number of

Sectors Erase Suspend

Read

16 32 64 128 256 512

Yes Yes Yes Yes Yes Yes

Erase Suspend Program

Address A

No Yes Yes Yes Yes Yes

to A

A0 to A

A0 to A RESET No Yes Yes Yes Yes Yes R/B No Yes Yes Yes Yes Yes

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

DESCRIPTIONS (Continued)

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ADDRESS MAP (for × 16 mode, not contained A0)

FFFFFFh

DFFFFFh

BFFFFFh

chip15, 14

chip13, 12

9FFFFFh

7FFFFF

5FFFFFh

3FFFFFh

1FFFFFh 0FFFFFh

07FFFFh 000000h

chip11,10

chip9, 8

chip7, 6

chip5, 4

chip3, 2

chip1, 0

MB98A81063MB98A81183 MB98A81273 MB98A81373 MB98A81473 MB98A81573

chip1, 0

chip3, 2

chip1, 0

chip7, 6

chip5, 4

chip3, 2

chip1, 0

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

PIN ASSIGNMENTS

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Pin No. Symbol Pin No. Symbol Pin No. Symbol Pin No. Symbol

1 GND 18 N.C. 35 GND 52 N.C. 2D

19 A

36 CD1 53 A22/N.C.* 3D 4D 5D 6D 7CE 8A

124 A541 D

9OE

10 A 11 A 12 A 13 A 14 A

15 WE 32 D

20 A 21 A 22 A 23 A

25 A 26 A 27 A 28 A 29 A 30 D 31 D

37 D

38 D

39 D

40 D

42 CE259N.C.

43 N.C. 60 N.C.

44 N.C. 61 REG

45 N.C. 62 BVD2

46 A

47 A

48 A

49 A20/N.C.* 66 D

54 A23/N.C.* 55 A24/N.C.* 56 N.C. 57 N.C. 58 RESET/N.C.

63 BVD1 64 D 65 D

16 R/B/N.C.* 33 WP 50 A21/N.C.* 67 CD2 17 V

34 GND 51 V

68 GND

* : See “DESCRIPTIONS”.

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

PIN DESCRIPTIONS

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Symbol Pin Name Input/Output Function

to A

to D

1 Card Enable for Lower Byte Input

2 Card Enable for Upper Byte Input

REG

Address Input Input Address Inputs, A0 to A24.

Data Inputs/Outputs.

Data Input/Output Input/Output

This data bus size (8-bit or 16-bit) is selected with CE

1 and CE2.

Active Low.

-Lower byte (D0 to D7) is selected for read/write/ erase function of flash memory cards.

Active Low.

-Upper byte (D8 to D15) is selected for read/write / erase function of flash memory cards.

Active Low.

Attribute Memory Select Input

-Attribute memory is selected for read/write function of identification data of flash memory cards. (N.C. or “FF” data or attribute data.)

, CD2 Card Detect Output

CD1

Output Enable Input

Write Enable Input

Active Low.

-Output enable for flash memory cards. Active Low.

-Write enable for flash memory cards. These pins detect if the card has been correctly

inserted. Both pins are tied to GND internally. Write controller for flash memory cards.

WP Write Protect Output

This pin outputs the Protect/Non Protect status of “WP Switch”.

BVD1, BVD2 Battery Voltage Detect Output Both pins are tied to V RESET Hardware Reset Input

R/B V

Ready/Busy Output Power Supply — Power Supply Voltage. (+5.0 V ±5%)

The card may be reset by driving the RESET pin to V

System can be detect the completion of program or erase operation.

GND Ground — System Ground. N.C. Non Connection —

PIN LOCATIONS

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Fig. 1 - BOTTOM VIEW (CONNECTOR SIDE)

internally.

Front Side

Back Side

MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

BLOCK DIAGRAM

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MB98A81063, MB98A81183, MB98A81273 and MB98A81373

Internal circuit

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GND

Address

R/B*1

D0 to D

CE1 CE2

REG

RESET*1

510 K

100 K

Internal circuit

Buffer I/O Buffer Decoder WP Control

RESET WE OE CE

(EVEN BYTE)

4M Flash chip × 1 (81063) 8M Flash chip × 1 (81183) 16M Flash chip × 1 (81273) 16M Flash chip × 2 (81273

(ODD BYTE)

4M Flash chip × 1 (81063) 8M Flash chip × 1 (81183) 16M Flash chip × 1 (81273) 16M Flash chip × 2 (81373)

Address

I/O

R/B

Address

I/O

R/B

10 K

BVD1 BVD2

CD1 CD2

*1: Not available for MB98A81063.

WP Switch

Fig. 2.1 - Block Diagram

WE OE CE

Attribute memory

16K EEPROM

Address

I/O

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BLOCK DIAGRAM (Continued)

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MB98A81473 and MB98A81573

Internal circuit

GND

R/B

Address

D0 to D

CE1 CE2

REG

RESET

100 K

510 K

Internal circuit

Control circuit

Buffer I/O Buffer Decoder WP Control

RESET WE OE CE

(EVEN BYTE) 16M Flash chip × 4 (81473) 16M Flash chip × 8 (81573)

(ODD BYTE) 16M Flash chip × 4 (81473) 16M Flash chip × 8 (81573)

Address

I/O

R/B

Address

I/O

R/B

Address

I/O

BVD1

10 K

WP Switch

WE OE CE

Attribute memory

16K EEPROM

BVD2

CD1 CD2

Fig. 2.2 - Block Diagram

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

CHIP AND SECTOR DECODING

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• Chip can be selected with;

- A

, A22, A23 and A24 for × 8-bit mode No.1.

- A

, A23 and A24 for × 8-bit mode No.2 and × 16-bit mode.

• Sector per each chip can be selected with A

ERASE SECTOR DECODING TABLE

*2 A20*1 A

Sector 31 1 1 1 1 1 Sector 30 1 1 1 1 0 Sector 29 1 1 1 0 1

•

Total 32 sectors*1*2

per 1 chip

•

Sector 2 0 0010 Sector 1 0 0 0 0 1 Sector 0 0 0000

•

, A18, A19, A20 and A21.

Sector Address (SA)

•

*1:A20 is not available for MB98A81063. MB98A81063 has 8 sectors. *2:A

is not available for MB98A81063 and MB98A81183. MB98A81063 has 8

sectors and MB98A81183 has 16 sectors.

CARD CHIP / SECTOR CONFIGURATION

UPPER BYTE LOWER BYTE

Chip 15 Chip 14 Chip 13 Chip 12 Chip 11 Chip 10

•

Chip 5 Chip 4 Sector 2 (64K × 8 bits) Sector 2 (64K × 8 bits) Chip 3 Chip 2 Sector 1 (64K × 8 bits) Sector 1 (64K × 8 bits)

Chip1 Chip 0

D7 D

EVEN ADDRESS BYTE

ODD ADDRESS BYTE

•

× 16 bit mode

× 8 bit mode No. 1

(16M Flash Chip

Sector 31

Sector 0 (64K × 8 bits) Sector 0 (64K × 8 bits)

Chip 1

)

(64K × 8 bits) Sector 31*2(64K × 8 bits)

•

Chip 0

(16M Flash Chip*1)

•

Card Chip Configuration for 32MB Card Sector Configuration for 2 Chips

*1:4M Flash Chip for MB98A81063. 8M Flash chip for

MB98A81183.

*2:Sector 7 for MB98A81063. Sector 15 for MB98A81183.

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

FUNCTION DESCRIPTIONS

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1. Read Mode

The data in the common and attribute memory can be read with “OE=VIL” and “WE=VIH”. The address is selected with A The following 1) and 2) are the descriptions for Common Memory Read and Attribute Memory Read mode.

(1) Common Memory Read

(2) Attribute Memory Read

2. Standby Mode

3. Output Disable Mode

4. Write Mode

(1) Common Memory Wr ite

(2) Attribute Memory Write

5. Command Definitions

6. Automated Program Capability

7. Automated Chip Erase Capability

to A24. And CE1 and CE2 select output mode (× 8/× 16 output mode, See “FUNCTION TRUTH TABLES”.).

- Two modes of Common Memory Read, reading the data in memory array and Intelligent ID are available. The card enter each Read mode by writing “Read Memory/Reset Command” or “Intelligent ID Read Command”. The card automatically resets to the condition of Common Memory Read mode upon initial power-up.

- The data on the attribute memory can be read with “REG

- An address on attribute memory can be selected with A

-CE1 and CE2 at “VIH” place the card in Standby mode. D0 to D15 are placed in a high-Z state independent of the status “OE

- The outputs are disabled with OE and WE at “VIH”. D0 to D15 are placed in high-Z state.

- The card is in Write mode with “OE

- Commands can be written at the Write mode. See “5.Command Definitions”.

- Two types of the Write mode, “WE

-REG

- Attribute memory is not controlled by writing Commands. And attribute memory has the Data polling function,

- User can select the card operation by writing the specific address and data sequences into the command

- Programming operation can swich the data from “1” to “0”.

- The data is programmed on a byte-by-byte or word-by-word basis.

- The card will automatically provide adequate internally generated programming pulses and verify the

- Addresses are latched at falling edge of WE

- We can check whether a byte (word) progr amming operation is completed successfully b y sequence flug with

- Any commands written to the chip during programming operation will be ignored.

- We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to pre-

- The card returns to Common Memory Read mode automatically after the chip erasing is completed.

at L-level selects Attrib ute memory and “OE=VIH”, “WE and CE=VIL” place it in write mode. Two types of

the write mode, “WE which can detect whether the attribute memory status is in programming operation. When the read operation

is executed at programming cycle, the opposite data is output from D written data is output from D

register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See “COMMAND DEFINISION TABLE”.

programmed cell margine by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed.

rising edge of WE or CE on the command write cycle begins programming operation. R/B

(Except for MB98A81063), Data Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.

program prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timing during these operations.

”, “WE” and “REG”.

=VIH” and “WE and CE=VIL”.

control” and “CE control” are available.

pin at the completion of programming operation.

or CE and data is latched at rising edge of WE or CE. The fourth

=VIL”, “OE=VIL” and “WE=VIH”.

to A11 pin. And CE1 and CE2 select output mode.

(I7), and the same data (O7) as the

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

FUNCTION DESCRIPTIONS (Continued)

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- Whether or not chip erase operation is completed successfully can be checked by sequence flug with R/B (Except for MB98A81063), Data

- Any commands written to the chip during programming operation will be ignored.

8. Automated Sector Erase Capability

- We can execute the erase operation on any sectors by 6 bus cycle operation.

- A time-out of 50 µs (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase command(s) for other sector than the sector that sector erase command have been valid.

- Multiple sectors in a chip can be erased concurrently . This sequence is followed with writes of 30H to addresses in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs, otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50 µs (typ.) time out from the rising edge of WE window is still open can be monitored with D

- Sector Erase does not require the user to pre-program prior to erase. The chip automatically programs “0” to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any controls or timing during these operations.

- The card returns to Common Memory Read mode automatically after the sector erasing is completed.

- Whether or not sector erase operation is completed successfully can be checked by sequence flug with R/B Data Polling or Toggle Bit function. The sequence flug must be read from the address of the sector inv olv ed in erase operation. See “WRITE OPERATION STATUS”.

9. Erase Suspend

- Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase (only data read is possible for MB98A81063). This command is applicab le only during the sector erase oper ation (including the sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the chip erase or programming operation. Writing this command during the time-out will result in immediate termination of the time-out period. The addresses are “don’t cares” in wrinting the Erase Suspend or Resume commands in the chip.

- When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase Suspend Read mode. User can read the data from other sectors than those in suspention. The read operation from sectors in suspention results D non-busy sectors by writing program commands for MB98A81183 and MB98A8xx7x.

- A read from a sector being erase suspended may result in invalid data.

10. Intelligent Identifier (ID) Read Mode

- Each common memory can execute an Intelligent Identifier oper ation, initiated by writing Intelligent ID command (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code, and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is necessary

to write Read/Reset command.

Part Number Maker Code Device Code

MB98A81063 04 h / 0404 h A4 h / A4A4 h MB98A81183 04 h / 0404 h D5 h / D5D5 h MB98A81273/81373/1473/81573 04 h / 0404 h 3D h / 3D3D h

Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.

pulse for the last Sector Erase command pulse. Whether the sector er ase

and D11.

toggling for MB98A81183 and MB98A8xx7x. User can program to

2/D10

11. Hardware Reset (not applied for MB98A81063)

- The Card may be reset by driving the RESET pin to VIH. The RESET pin must be kept High (VIH) for at least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs after the RESET pin is driven High. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate.

- When the RESET pin is high and the internal reset is complete, the Card goes to standby mode and cannot be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET pulse. Once the RESET pin is taken low, the Card requires 500 ns of wake up time until outputs are valid for read access.

- If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used after this.

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

FUNCTION DESCRIPTIONS (Continued)

■

12. Data Protection

- The card has WP (Write Protect) switch for write lockout.

- T o a void initiation of a write cycle during V than 3.2 V (typically 3.7 V). If V

< V circuits are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V

level is greater than V

logically correct to prevent unintentional writes when V

-If V

would be less than V

operation will not resume ev en if V

during program/erase operation, the operation will stop. And after that, the

LKO

returns recommended voltage level. Theref ore, prog ram command must

be written again because the data on the address interrupted program operation is invalid. And regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used.

- Noise pulses of less than 5 ns (typical) on OE

FUNCTION TRUTH TABLE

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MAIN MEMORY FUNCTION*1

power-up and power-do wn, a write cycle is locked out f or VCC less

, the command register is disabled and all internal program/erase

LKO

It is the users responsibility to ensure that the control pins are

LKO.

is above 3.2 V.

, CE or WE will not initiate a write cycle.

Mode RESET*3 REG

CE2CE1A0OE WE

Data Input/Output

D8 to D

D0 to D

WP SW

Hardware Reset H XXXXXXX High-Z

Standby

Read (×8 No.1)

Read (×8 No.1) H

Read (×8 No.2)

Read (×16) L D

Write (×8 No.1)

Output Disable H High-Z P

Write (×8 No.1)

Output Disable H

Write (×8 No.2)

Output Disable H High-Z P

Write (×16)

XHHXXXX High-Z

OUT

(Even Byte)

OUT

(Odd Byte)

High-Z

OUT

(Even Byte)

LHX

High-Z

OUT

(Odd Byte)

High-Z

(Odd Byte)

High-Z

P or NP

Output Disable H High-Z P

Output Disable XXXXHHX High-Z P or NP

Notes:

*1:H =V

, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect

*2:L-level is output when WPSW = NP. H-level is output when WPSW = P. *3:Not available for MB98A81063.

MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

FUNCTION TRUTH TABLE (Continued)

■

ATTRIBUTE MEMORY FUNCTION*1

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Mode RESET*3 REG

Standby

Read (×8 No.1)

CE2CE1A0OE WE

XHHXXXX High-Z

Read (×8 No.1) H H

Data Input/Output

D8 to D

D0 to D

High-Z

WP SW

OUT

P or NP

LHX

Read (×8 No.2)

Read (×16) L D

Write (×8 No.1)

High-Z

OUT

Output Disable H High-Z P Write (×8 No.1)

High-Z

INVALID

NP Output Disable H Write (×8 No.2)

INVALID

High-Z

NP Output Disable H High-Z P

Write (×16)

INVALID

NP Output Disable H High-Z P

Output Disable XXXXHHX High-Z P or NP

Notes:

*1:H = V

, L = VIL, X = Either VIL or VIH, WP SW = Write Protect Switch, P = Protect, NP = Non Protect

*2:L-level is output when WPSW = NP. H-level is output when WPSW = P. *3:Not available for MB98A81063.

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MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

COMMAND DEFINITION TABLE

■

Command table for 8-bit Mode

Command

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase

Suspend

Sector Erase

Resume

Bus

Cycle

1st Bus

Write Cycle

Write Read

CA F0H RA RD

Write Write Write Read

RCMA1 AAH RCMA2 55H RCMA1 F0H RA RD

Write Write Write Read

ICMA1 AAH ICMA2 55H ICMA1 90H IA ID

Write Write Write Write

PCMA1 AAH PCMA2 55H PCMA1 A0H PA PD

Write Write Write Write Write Write

SCMA1 AAH SCMA2 55H SCMA1 80H SCMA1 AAH SCMA2 55H SA 30H

Write Write Write Write Write Write

CCMA1 AAH CCMA2 55H CCMA1 80H CCMA1 AAH CCMA2 55H CCMA1 10H

Write

CA B0H

Write

CA 30H

2nd Bus

Write/Read

Cycle

3rd Bus Write

Cycle

4th Bus

Write/Read

Cycle

5th Bus Write

Cycle

6th Bus Write

Cycle

Notes:

CA: Chip Address. (address in chip selected by A SA: Sector Address (address in 64 KB selected by A PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0002H)

PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code

CCMA1, CCMA2: Command adddress for chip erase SCMA1, SCMA2: Command address for sector erase PCMA1, PCMA2: Command address for program RCMA1, RCMA2: Command address for Read/Reset ICMA1, ICMA2: Command address for intelligent ID read

, A22, A23 and A24)

, A17, A18, A19, A20, A21, A22, A23 and A24)

See “Command Address Table for 8-bit Mode” in page 16.

MB98A81063-15/81183-15/81273-15/81373-15/81473-15/81573-15

Command Table for 16-bit Mode*1

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Command

Bus

Cycle

Read/Reset 1 2

Read/Reset 2 4

Read Intelligent ID Codes

Byte Program 4

Sector Erase 6

Chip Erase 6

Sector Erase

Suspend

Sector Erase

Resume

1st Bus

Write Cycle

Write Read

— F0F0H RA RD

Write Write Write Read

RCMA1 AAAAH RCMA2 5555H RCMA1 F0F0H RA RD

Write Write Write Read

ICMA1 AAAAH ICMA2 5555H ICMA1 9090H IA ID

WriteWriteWriteWrite

PCMA1 AAAAH PCMA2 5555H PCMA1 A0A0H PA PD

WriteWriteWriteWriteWriteWrite

SCMA1 AAAAH SCMA2 5555H SCMA1 8080H SCMA1 AAAAH SCMA2 5555H SA 3030H

WriteWriteWriteWriteWriteWrite

CCMA1 AAAAH CCMA2 5555H CCMA1 8080H CCMA1 AAAAH CCMA2 5555H CCMA1 1010H

Write

CA B0B0H

Write

CA 3030H

2nd Bus

Write/Read

Cycle

3rd Bus

Write Cycle

4th Bus

Write/Read

Cycle

5th Bus

Write Cycle

6th Bus

Notes:

CA: Chip Address. (address in chip selected by A SA: Sector Address (address in 128 KB selected by A

, A23 and A24)

, A18, A19, A20, A21, A22, A23 and A24)

PA: Program Address (address to be programmed) RA: Read Address (address to be read) IA: Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)

PD: Programming data RD: Read data ID: Intelligent Identifier (ID) Code

CCMA1, CCMA2: Command address for chip erase SCMA1, SCMA2: Command address for sector erase PCMA1, PCMA2: Command address for program RCMA1, RCMA2: Command address for Read/Reset

See “Command Address Table for 16-bit Mode” in page 16.

ICMA1, ICMA2: Command address for intelligent ID read *1: Address number is not contained “A

”.

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COMMAND DEFINITION TABLE (Continued)

■

Command Address Table for 8-bit Mode

Command

Address

CCMA1 (CA AND 000001h) OR AAAAh (CA AND 000001h) OR AAAh CA CCMA2 (CA AND 000001h) OR 5554h (CA AND 000001h) OR 554h CA

SCMA1 (SA AND 000001h) OR AAAAh (SA AND 000001h) OR AAAh CA SCMA2 (SA AND 000001h) OR 5554h (SA AND 000001h) OR 554h CA PCMA1 (PA AND 000001h) OR AAAAh (PA AND 000001h) OR AAAh CA PCMA2 (PA AND 000001h) OR 5554h (PA AND 000001h) OR 554h CA

RCMA1 (RA AND 000001h) OR AAAAh (RA AND 000001h) OR AAAh CA RCMA2 (RA AND 000001h) OR 5554h (RA AND 000001h) OR 554h CA

ICMA1 (IA AND 000001h) OR AAAAh (IA AND 000001h) OR AAAh CA ICMA1 (IA AND 000001h) OR 5554h (IA AND 000001h) OR 554h CA

MB98A81063 MB98A81183

MB98A81273, 81373, 81473,

Command Address Table for 16-bit Mode

Command

Address

CCMA1 5555h 555h CA CCMA2 2AAAh 2AAh CA

SCMA1 5555h 555h CA

MB98A81063 MB98A81183

MB98A81273, 81373, 81473,

81573

SCMA2 2AAAh 2AAh CA PCMA1 5555h 555h CA PCMA2 2AAAh 2AAh CA

RCMA1 5555h 555h CA RCMA2 2AAAh 2AAh CA

ICMA1 5555h 555h CA ICMA1 2AAAh 2AAh CA

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