FUJITSU DS05-20868-3E DATA SHEET

查询MBM29F002BC-55供应商

FUJITSU SEMICONDUCTOR

DATA SHEET

FLASH MEMORY

CMOS

2M (256K × 8) BIT

MBM29F002TC

FEATURES

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• Single 5.0 V read, write, and erase

Minimizes system level power requirements

• Compatible with JEDEC-standard commands

Pinout and software compatible with single-power supply Flash Superior inadvertent write protection

• 32-pin TSOP(I) (Package Suffix: PFTN-Normal Bend Type, PFTR-Reverse Bend Type) 32-pin PLCC (Package Suffix: PD)

• Minimum 100,000 write/erase cycles

• High performance

55 ns maximum access time

• Sector erase architecture

One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes Any combination of sectors can be erased. Also supports full chip erase

• Boot Code Sector Architecture

T = Top sector B = Bottom sector

• Embedded Erase™ Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded Program™ Algorithms

Automatically programs and verifies data at specified address

•Data

•Low V

• Hardware RESET pin

• Erase Suspend/Resume

• Sector protection

• Temporary sector unprotection

Polling and Toggle Bit feature for detection of program or erase cycle completion

write inhibit ≤ 3.2 V

Resets internal state machine to the read mode

Supports reading or programming data to a sector not being erased

Hardware method that disables any combination of sector from write or erase operation

Temporary sector unprotection via the RESET

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DS05-20868-3E

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Embedded Erase™, Embedded Program™ and ExpressFlash™ are trademarks of Advanced Micro Devices, Inc.

MBM29F002TC

PACKAGE

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32-pin plastic TSOP(I)

Marking Side

(FPT-32P-M24)

32-pin plastic TSOP(I)

Marking Side

(FPT-32P-M25)

32-pin plastic QFJ (PLCC)

Marking Side

(LCC-32P-M02)

MBM29F002TC

GENERAL DESCRIPTION

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The MBM29F002TC/BC is a 2 M-bit, 5.0 V-Only Flash memory organized as 256K bytes of 8 bits each. The MBM29F002TC/BC is offered in a 32-pin TSOP(I) and 32-pin PLCC packages. This device is designed to be programmed in-system with the standard system 5.0 V V erase operations. The device can also be reprogrammed in standard EPROM programmers.

The standard MBM29F002TC/BC offers access times between 55 ns and 90 ns allowing oper ation of high-speed microprocessors without wait states. To eliminate bus contention the de vice has separate chip enable (CE enable (WE), and output enable (OE) controls.

The MBM29F002TC/BC is command set compatible with JEDEC standard E to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and er ase operations. Reading data out of the de vice is similar to reading from 12.0 V Flash or EPROM devices.

The MBM29F002TC/BC is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Each sector can be programmed and verified in less than 0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before ex ecuting the erase operation. During erase, the device automatically times the er ase pulse widths and v erifies proper cell margin.

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supply. A 12.0 V VPP is not required for program or

PROMs. Commands are written

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), write

This device also features a sector erase architecture. The sector erase mode allows for sectors of memory to be erased and reprogrammed without affecting other sectors. A sector is typically erased and verified within 1 second (if already completely preprogrammed). The MBM29F002TC/BC is erased when shipped from the factory .

The MBM29F002TC/BC device also f eatures hardware sector protection. This feature will disab le both program and erase operations in any number of secotrs (0 through 6)

Fujitsu has implemented an Erase Suspend feature that enab les the user to put erase on hold f or any period of time to read data from or program data to a non-busy sector. Thus, true background erase can be achieved.

The device f eatures single 5.0 V power supply operation for both read and program functions . Internally generated and regulated voltages are provided for the program and erase operations. A low V inhibits write operations during power transitions. The end of program or erase is detected by Data Polling of DQ

, or by the Toggle Bit I feature on DQ6. Once the end of a program or erase cycle has been completed, the

device automatically resets to the read mode. The MBM29F002TC/BC also has a hardware RESET

Program or Embedded Erase operations will be terminated. The internal state machine will then be reset into the read mode. The RESET during the Embedded Program or Embedded Erase operation, the de vice will be automatically reset to a read mode. This will enable the system microprocessor to read the boot-up firmware from the Flash memory.

Fujitsu's Flash technology combines years of EPROM and E of quality, reliability , and cost eff ectiv eness. The MBM29F002TC/BC memory electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte at a time using the EPROM programming mechanism of hot electron injection.

pin may be tied to the system reset circuity. Therefore, if a system reset occurs

pin. When this pin is driven low , execution of an y Embedded

detector automatically

PROM experience to produce the highest levels

MBM29F002TC

FLEXIBLE SECTOR-ERASE ARCHITECTURE

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• One 16K byte, two 8K bytes, one 32K byte, and three 64K bytes

• Individual-sector, multiple-sector, or bulk-erase capability

• Individual or multiple-sector protection is user definable

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3FFFFH

16K byte

3BFFFH

8K byte

39FFFH

8K byte

37FFFH

32K byte

2FFFFH

64K byte

1FFFFH

64K byte

0FFFFH

64K byte

00000H

MBM29F002TC Sector Architecture MBM29F002BC Sector Architecture

64K byte 64K byte

64K byte 32K byte

8K byte 8K byte

16K byte

3FFFFH 2FFFFH

1FFFFH 0FFFFH 07FFFH 05FFFH

03FFFH 00000H

MBM29F002TC

PRODUCT LINE UP

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Part No. MBM29F002TC/BC

= 5.0 V ± 5% -55 — —

Ordering Part No.

= 5.0 V ± 10% — -70 -90

Max. Address Access Time (ns) 55 70 90 Max. CE

Access Time (ns) 55 70 90

Max. OE Access Time (ns) 30 30 35

BLOCK DIAGRAM

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DQ0 to DQ

RESET

CE OE

State

Control

Command

Program Voltage

Generator

Erase Voltage

Generator

Chip Enable

Output Enable

Logic

STB

Input/Output

Buffers

Data Latch

A0 to A

STB

Low V

Detector

Timer for

Program/Erase

Address

Latch

Y-Decoder

X-Decoder

Y-Gating

Cell Matrix

MBM29F002TC

CONNECTION DIAGRAMS

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PLCC

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A A A A A

A WE V

RESET

4 3 2 1 32 31 30

A A A A A A A A DQ

29 28 27 26 25 24 23 22 21

A A A A A OE A CE DQ

14 15 16 17 18 19 20

DQ3DQ 4DQ 5DQ

LCC-32P-M02

TSOP (I)

Marking Side

8 9 10

Standard Pinout

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

OE A CE DQ DQ DQ DQ DQ V DQ DQ DQ A A A A

7 6 5 4 3

2 1

0 0 1 2 3

FPT-32P-M24

A A A A A A A

RESET

V WE

A A A A A A

Marking Side

8 7 6

Reverse Pinout

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

A A A A DQ DQ DQ V DQ DQ DQ DQ DQ CE A OE

3 2 1 0

2 SS

FPT-32P-M25

MBM29F002TC

LOGIC SYMBOL

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Table 1 MBM29F002TC/BC Pin Configuration

Pin Function

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to A

to DQ

A 0 to A

DQ0 to DQ

CE OE WE

RESET

OE WE Write Enable

RESET

Hardware Reset Pin/Sector Protection

N.C. No Internal Connection

Table 2 MBM29F002TC/BC User Bus Operations

Operation CE

OE WE A

A1A6A9A10DQ0 to DQ7RESET

Auto-Select Manufacturer Code (1) L L H L L L V Auto-Select Device Code (1) L L H H L L V

Address Inputs

Data Inputs/Outputs

Chip Enable

Output Enable

Unlock

Device Ground

Device Power Supply

LCode H

Read (3) L L H A

A1A

A9A

OUT

H Standby HXXXXXXX HIGH-Z H Output Disable LHHXXXXX HIGH-Z H Write (Program/Erase) L H L A Enable Sector Protection (2) L V

Verify Sector Protection (2) L L H L H L V Temporary Sector Unprotection X X X X X X X X X V

A1A

A9A

XXXVIDXX H

LCode H

Reset (Hardware) XXXXXXXX HIGH-Z L

Legend: Notes:

L = VIL, H = VIH, X = VIL or VIH, = Pulse Input. See DC Characteristics for voltage levels.

1.Manufacturer and device codes ma y also be accessed via a command register write sequence. Refer to Table 6.

2.Refer to the section on Sector Protection.

3.WE

can be VIL if OE is VIL, OE at VIH initiates the write operations.

MBM29F002TC

ORDERING INFORMATION

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Standard Products

Fujitsu standard products are available in several packages. The order number is formed by a combination of:

MBM29F002 T C -70 PFTN

PACKAGE TYPE PFTN = 32-Pin Thin Small Outline Package

(TSOP) Standard Pinout

PFTR = 32-Pin Thin Small Outline Package

(TSOP) Reverse Pinout

PD = 32-Pin Rectangular Plastic Leaded

Chip Carrier (PLCC)

SPEED OPTION See Product Selector Guide

C = Device Revision BOOT CODE SECTOR ARCHITECTURE

T = Top sector B = Bottom sector

DEVICE NUMBER/DESCRIPTION MBM29F002 2 Mega-bit (256K × 8-Bit) CMOS Flash Memory

5.0 V-only Read, Write, and Erase

MBM29F002TC

FUNCTIONAL DESCRIPTION

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Read Mode

The MBM29F002TC/BC has two control functions which must be satisfied in order to obtain data at the outputs.

is the power control and should be used for a de vice selection. OE is the output control and should be used

CE to gate data to the output pins if a device is selected.

Address access time (t access time (t

) is the delay from stable addresses and stable CE to valid data at the output pins. The output

enable access time is the delay from the falling edge of OE addresses have been stable for at least t

) is equal to the delay from stable addresses to valid output data. The chip enable

ACC

to valid data at the output pins (assuming the

time).

ACC-tOE

Standby Mode

There are two ways to implement the standb y mode on the MBM29F002TC/BC de vices, one using both the CE and RESET

When using both pins, a CMOS standby mode is achie ved with CE

pins; the other via the RESET pin only.

and RESET inputs both held at V

Under this condition the current consumed is less than 5 µA. A TTL standby mode is achieved with CE RESET Algorithm operation, V access time (t

When using the RESET

pins held at VIH. Under this condition the current is reduced to approximately 1 mA. During Embedded

Active current (I

) from either of these standby modes.

pin only, a CMOS standby mode is achieved with RESET input held at V

) is required even CE = VIH. The device can be read with standard

CC2

±0.3 V (CE

= “H” or “L”). Under this condition the current consumed is less than 5 µA. A TTL standby mode is achiev ed with RESET 1 mA. Once the RESET

pin held at VIL (CE = “H” or “L”). Under this condition the current required is reduced to approximately

pin is taken high, the device requires 500 ns of wake up time before outputs are valid

for read access. In the standby mode the outputs are in the high impedance state, independent of the OE

input.

Output Disable

With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state.

±0.3 V. and

Autoselect

The autoselect mode allows the reading out of a binary code from the device and will identify its manuf acturer and type. This mode is intended for use b y prog r amming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.

To activate this mode, the programming equipment must force V identifier bytes may then be sequenced from the device outputs by toggling address A addresses are don't cares except A

, A1, A6 and A10. (See Table 3.)

The manufacturer and device codes may also be read via the command register, for instances when the MBM29F002TC/BC is erased or programmed in a system without access to high voltage on the A command sequence is illustrated in Table 6. (Refer to Autoselect Command section.)

Byte 0 (A

= VIL) represents the manufacturer's code (Fujitsu = 04H) and b yte 1 (A0 = VIH) represents the device

identifier code for MBM29F002TC = B0H, MBM29F002BC = 34H. These two b ytes are giv en in the table 3. All identifiers for manuf actures and device will exhibit odd parity with DQ the proper device codes when executing the Autoselect, A

The Autoselect mode also f acilitates the determination of sector protection in the system. By performing a read operation at the address location XX02H with the higher order address bits A desired sector address, the device will return 01H for a protected sector and 00H for a non-protected sector.

(11.5 V to 12.5 V) on address pin A9. Two

from VIL to VIH. All

defined as the parity bit. In order to read

must be VIL. (See Table 3.)

, A14, A15, A16 and A17 set to the

pin. The

MBM29F002TC

Table 3 .1 MBM29F002TC/BC Sector Protection Verify Autoselect Codes

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Type A

to A

Manufacture’s Code X V

MBM29F002TC X V

Code (HEX)

04H

B0H

Device Code

MBM29F002BC X V

Sector Protection

Sector

Addresses

34H

01H*

* :Outputs 01H at protected sector addresses and outputs 00H at unprotected sector addresses.

Table 3 .2 Expanded Autoselect Code Table

Type Code DQ

Manufacture’s Code 04H 00000100

MBM29F002TCB0H 10110000

Device Code

MBM29F002BC34H 00110100

Sector Protection 01H 00000001

Table 4 Sector Address Tables (MBM29F002TC)

Address Range

SA0 0 0 X X X 00000H to 0FFFFH SA1 0 1 X X X 10000H to 1FFFFH SA2 1 0 X X X 20000H to 2FFFFH SA3 1 1 0 X X 30000H to 37FFFH SA4 1 1 1 0 0 38000H to 39FFFH SA5111013A000H to 3BFFFH SA6 1 1 1 1 X 3C000H to 3FFFFH

Table 5 Sector Address Tables (MBM29F002BC)

Address Range

SA0 0 0 0 0 X 00000H to 03FFFH SA1 0 0 0 1 0 04000H to 05FFFH SA2 0 0 0 1 1 06000H to 07FFFH SA3 0 0 1 X X 08000H to 0FFFFH SA4 0 1 X X X 10000H to 1FFFFH SA5 1 0 X X X 20000H to 2FFFFH SA6 1 1 X X X 30000H to 3FFFFH

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Write

Device erasure and progr amming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device.

The command register itself does not occupy any addressab le memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.

to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on

Sector Protection

The MBM29F002TC/BC features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 6) equipment at the user's site. The device is shipped with all sectors unprotected.

The sector protection feature is enabled using prog ramming

T o activ ate this mode, the programming equipment must f orce V V

= 11.5 V), CE = VIL. The sector addresses (A13, A14, A15, A16, and A17) should be set to the sector to be

protected. Tables 4 and 5 define the sector address for each of the seven (7) individual sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE protection waveforms and algorithm.

To verify programming of the protection circuitry, the programming equipment must force V with CE A device will produce 00H for unprotected sector. In this mode, the lower order addresses, except for A and A codes.

It is also possible to determine if a sector is protected in the system by writing an Autoselect command. P erforming a read operation at the address location XX02H, where the higher order addresses (A are the desired sector address will produce a logical “1” at DQ codes.

and OE at VIL and WE at VIH. Scanning the sector addresses (A13, A14, A15, A16, and A17) while (A10, A6,

, A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the

are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect man ufacturer and de vice

on address pin A9 and control pin OE, (suggest

pulse. See figures 14 and 21 for sector

on address pin A9

, A1, A6,

, A14, A15, A16, and A17)

for a protected sector . See Table 3 f or A utoselect

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Temporary Sector Unprotection

This feature allows temporary unprotection of previously protected sectors of the MBM29F002TC/BC device in order to change data. The Sector Unprotection mode is activated by setting the RESET V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected again. Refer to Figures 14 and 21.

Table 6 MBM29F002TC/BC Command Definitions

pin to high voltage (12

Command Sequence

Read/Reset* 1 XXXH F0H ——————————

Reset/Read* 3 555H AAH 2AA H 55H 555H F0H RA RD — — — —

Manufacture Code 3 555H AAH 2AAH 55H 555H 90H 00H 04H — — — —

Device Code 3 555H AAH 2AAH 55H 555H 90H 01H ID — — — —

Byte Pro g ram 4 555H AAH 2AAH 55H 555H A0H PA PD — — — —

Chip Erase 6 555H AAH 2 AAH 55H 555H 80H 555H AAH 2AAH 55H 555H 10H

Sector E rase 6 555H AAH 2AAH 55 H 555H 80H 555H AAH 2AAH 55H SA 30H

Sector Erase Suspend Erase can be suspended during sector erase with Addr (“H” or “L”), Data (B0H)

Sector Erase Resume Erase can be resumed after suspend with Addr (“H” or “L”), Data (30H)

Notes:

*: Either of the two reset commands will reset the device.

1.Address bits A Sector Address (SA).

2.Bus operations are defined in Table 2.

3.RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of

the WE

SA = Address of the sector to be erased. The combination of A

any sector.

4.RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE ID = Device Code (Refer to the section on Sector Protection Verify Autoselect Codes.)

Bus

Write

Cycles

Req'd

pulse.

First Bus

Write Cycle

Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data

to A17 = X = “H” or “L” for all address commands except or Program Address (PA) and

Second Bus

Write Cycle

Third Bus

Write Cycle

Fourth Bus

Read/Write

Cycle

, A16, A15, A14, and A13 will uniquely select

Fifth Bus

Write Cycle

Sixth Bus

Write Cycle

Command Definitions

Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Table 6 defines the valid register command sequences. Note that the Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase operation is in prog ress. Moreo v er , both Read/Reset commands are functionally equivalent, resetting the device to the read mode.

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Read/Reset Command

The read or reset operation is initiated by writing the read/reset command sequence into the command register . Microprocessor read cycles retrieve arra y data from the memory . The de vice remains enabled f or reads until the command register contents are altered.

The device will automatically power-up in the read/reset state . In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

Autoselect Command

Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A voltage onto the address lines is not generally desirable system design practice.

The device contains an autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register . Following the command write, a read cycle from address XX00H retrie ves the manuf acture code of 04H. A read cycle from address XX01H returns the device code D5H. (See Table 3).

to a high voltage. However, multiplexing high

All manufacturer and device codes will exhibit odd parity with the DQ Sector state (protection or unprotection) will be informed by address XX02H. Scanning the sector addresses (A

logical “1” at device output DQ To terminate the operation, it is necessary to write the read/reset command sequence into the register and also

to write the Autoselect command during the operation, ex ecute it after writing Read/Reset command sequence.

, A16, A15, A14, and A13) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce a

for a protected sector.

defined as the parity bit.

Byte Programming

The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are follo wed by the progr am set-up command and data write cycles. Addresses are latched on the falling edge of CE

or WE, whichever happens first. The rising edge of CE or WE (whiche ver happens first) begins programming.

CE Upon executing the Embedded Program Algorithm command sequence, the system is further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin.

This automatic programming operation is completed when the data on DQ bit at which time the device returns to the read mode and addresses are no longer latched. (See T able 7, Hardware Sequence Flags.) Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time. Data programmed.

or WE, whichever happens later and the data is latched on the rising edge of

required to provide

not

is equivalent to data written to this

Polling must be performed at the memory location which is being

Any commands written to the chip during this period will be ignored. If a hardware reset occurs during the programming operation, it is impossible to guarantee the data are being written.

Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so ma y either hang up the device or result in an apparent success according to the data polling algorithm but a read from reset/read mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s.

Figure 16 illustrates the Embedded Programming

Algorithm using typical command strings and bus operations.

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Chip Erase

Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.

Chip erase does Algorithm command sequence the device will automatically program and v erify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations.

The automatic erase begins on the rising edge of the last WE when the data on DQ mode.

Figure 17 illustrates the Embedded Erase™ Algorithm using typical command strings and bus operations.

require the user to program the device prior to erase . Upon ex ecuting the Embedded Erase

not

pulse in the command sequence and terminates

is “1” (see Write Operation Status section) at which time the device returns to read the

Sector Erase

Sector erase is a six bus cycle operation. There are two “unloc k” write cycles. These are f ollow ed by writing the “set-up” command. Two more “unlock” write cycles are then follo wed by the Sector Er ase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE (Data = 30H) is latched on the rising edge of WE. After time-out of 50 erase command, the sector erase operation will begin.

Multiple sectors may be erased concurrently b y writing the six bus cycle oper ations on Table 6. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of the last WE edge of the WE occurs within the 50 sector erase timer window is still open, see section DQ Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once ex ecution has begun will corrupt the data in that sector . In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section f or DQ

, Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with

any number of sectors (0 to 6).

will initiate the ex ecution of the Sector Erase command(s). If another falling

s time-out window the timer is reset. (Monitor DQ3 to determine if the

, Sector Erase Timer .) Any command other than Sector

s from the rising edge of the last sector

, while the command

Sector erase does all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is during these operations.

The automatic sector erase begins after the 50 µs time out from the rising edge of the WE sector erase command pulse and terminates when the data on DQ at which time the device returns to the read mode. Data polling must be perf ormed at an address within any of the sectors being erased.

Figure 17 illustrates the Embedded Erase™ Algorithm using typical command strings and bus operations.

require the user to program the device prior to erase . The device automatically progr ams

not

required to provide any controls or timings

not

pulse for the last

is “1” (see Write Operation Status section)

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