Fujitsu CS81 User Manual
CS81 Series Standard Cell
CS81
(1.8V)
High-Speed
Devices
T-LVTTL
P-CML
LVDS
SSTL
HSTL
ADC/DAC
2.5V
CMOS
AGP USBPCI
AGP USB DevicesPCI Bus
3.3V
CMOS
High-Speed
Interface
Analog
Interface
2.5V CMOS
2.5V Device
3.3V Device
3.3V TTL
1.8V Device
1.8V CMOS
1.8V
CMOS
PLL
Clock Input
0.18µm CMOS Technology
Features
▼
• 0.13µm effective channel length
• 3 to 5 layers of metal interconnects
• Very high density: 110K raw gates/mm
2
• Up to 28 million gates
• Core power supply voltage: 1.8V to 1.1V
• 5 nW/gate/MHz power dissipation at 1.1V
• 11 ps gate delay at 1.8V and 1 fan-out
• Junction temperature range: –40 to +125°C
• I/Os: 3.3V, 2.5V, 1.8V, 5V tolerant
• High-density diffused RAMs and ROMs
• High-speed mixed-signal macros
• Analog PLLs
• Wide selection of advanced packaging options
• Proven design methodology and tool support
• Two cell libraries: high-performance and
high-density
Description
▼
Fujitsu’s CS81, a 0.18µm (0.13µm L
) standard-cell
eff
product, is based on Fujitsu’s state-of-the-art CMOS
process technology, a deep sub-micron process designed
for today’s high-density and low-power SOC products.
The cell library, which is optimized for synthesis-based
designs, has accurate timing and power-characterized
data, cell areas, and statistical wire-load models. The
CS81 standard-cell library contains both high-performance and high-density cells, giving designers the
option of combining both types of standard cell blocks
on the same chip. The CS81 library supports popular
third-party tools and data-exchange file standards.
The CS81 chip cores can operate at 1.8V to 1.1V. The
I/Os, operating at 1.8V, 2.5V, 3.3V, or 5V tolerance, can
conveniently interface with various types of devices.
Interface options include low-swing, high-speed I/Os
and high-speed bus interface I/Os.
Both inline and staggered I/O pad configurations are
available. Inline pads are available in both 70µm and
44µm pad pitch. The 70µm pads are wire bonded,
whereas the 44µm pads are used with TAB. The 66µm
wire-bond stagger pads can be used for optimizing the
die area of pad-limited designs.
CS81 I/O Interface Capabilities
In addition to the traditional QFP packages, the CS81
family is available in TAB, EBGA, FBGA, and Flipchip BGA packages.
CS81 offers a rich set of ADCs and DACs, PLLs, highspeed RAMs and ROMs, as well as a variety of other
embedded functions. The following blocks will be available in the near future:
• Special high-speed I/Os:
T-LVTTL, P-CML, LVDS, SSTL, and HSTL
• Special-purpose Interfaces:
PCI, AGP, and USB
Design Methodology
Fujitsu’s design methodology ensures first-time silicon success by integrating proprietary point tools with popular,
sign-off-quality, industry-standard CAD tools such as:
• Logic design rule checker
• Delay calculator
• Quasi 3-D parasitic extraction tool
Fujitsu’s clock-driven design methodology is devised for low
power and low skew. The methodology identifies the bestsuited clock distribution strategy for a given design and
CS81 Series Standard Cell
predicts performance in advance. Fujitsu supports co-simulation, emulation and high-level floor-planning to optimize the power, timing, and size of the design. This
enables the designer to make effective architectural-level
decisions to achieve optimal design solutions.
Fujitsu’s design methodology supports cycle-based simulators and formal verification, as well as static timing analysis and the more conventional VHDL and Verilog simulators. Fujitsu’s design-for-test strategy includes boundary
scan (JTAG) and full and partial scan, as well as a built-in
self-test for memory.
Applications
CS81 offers high-density standard cells for very low-power
applications. Also provided in CS81 are high-performance
and area-optimized memories, mixed-signal blocks, analog functions, a rich set of IP Cores and Mega Macros,
and various I/O interfaces. The CS81 ASIC design kit,
combined with its supported EDA tool sets, is poised for
chip developments that require ease-of-tool use, proven
design flow and a quick time to market.
Mixed-Signal Macros
• A/D Converters
- 8-bit: 50 MS/s high-speed 3.3V
- 8-bit: 25 MS/s high-speed 3.3V
- 8-bit: 1 MS/s 3.3V
• D/A Converters
- 10-bit: 30 MS/s 3.3V
- 8-bit: 50 MS/s 3.3V
- 8-bit: 1 MS/s 3.3V
Multiplier Compiler
• Multiplicand (m): 4 ≤m ≤ 32
• Multiplier (n): 4 ≤n ≤ 32 (even numbers only)
Memory Macros
• SRAM Compiler: single and dual port (1RW/1R),
up to 72K bits per block
• High-speed SRAMs, up to 144K bits
• High-density SRAMs (1 RW)
512K ~ 1.1M bits (under development)
• Register files: 2R/2W
• ROM Compiler: up to 512K bits per block
Phase-Locked Loops
• Analog: up to 800 MHz
I/Os
• 1.8V, 2.5V, and 3.3V CMOS (2.5V is under
development)
• Slew-rate controlled
• Capable of driving large loads: 2, 4, 8, and 12 mA
sinking current
• Transceivers under development: P-CML, LVDS, PCI,
SSTL, and GTL
• AGP 2X and 4X
• 2.5 Gbps with clock recovery and
Serdes (under development)
• To be developed: 5V tolerant buffers
SOC IP Cores
• ARC 32-bit RISC
• 10/100 MAC
• 64/256 QAM
• MPEG2 Decoder/Demultiplexer
• 8VSB TV Demodulator
• AC3 Dolby Voice Decoder
• JPEG Encoder and Decoder
• PCI – 33/66 MHz, 32/64 bit cores
• USB Host Controller/Device
2
• I
C
• IDE (ATA3) Host Controller
• Smart Card I/F
• IRDA I/R Interface
• To be developed:
- ARM 7TDMI Hard Macro
- Oak DSP Hard Macro
- More IPs are being added
ASIC Design Kit and EDA Support
Verilog Logic Simulators Verilog-XL, NC Verilog,
from Cadence, Synopsys, VCS, Model-sim (Verilog)
and Mentor
VHDL/VITAL Logic VSS, Model-sim (VHDL)
Simulators from Synopsys, V-System, Leapfrog
Cadence, and Mentor
Synthesis, DFT, and STA Design Compiler, Test
tools from Synopsys Compiler, and PrimeTime
Other EDA Tools Chrysalis Design Verifyer
and Cadence DP
Fujitsu Microelectronics, Inc.
Loading...