FUJITSU CS81 Service Manual

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FUJITSU SEMICONDUCTOR

DATA SHEET

Semicustom

CMOS

Standard cell array

CS81 Series

DESCRIPTION

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The CS81 series of 0.18 µm CMOS standard cell arrays is a line of highly integrated CMOS ASICs f eaturing high speed and low power consumption at the same time.

DS06-20206-1E

This series incorporates up to 40 million gates which have a gate delay time of 11 ps, resulting in both integr ation and speed about three times higher than conventional products.

In addition, this series can operate at a power-supply voltage of up to 1.1 V, substantially reducing power consumption.

FEATURES

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• Technology : 0.18 µm silicon-gate CMOS, 3- to 5-layer wiring capable of integrating a mixture of highspeed processes and cells on a single chip (under development)

• Supply voltage : +1.8 V ± 0.15 V (typical) to +1.1 V ± 0.1 V

• Junction temperature range : −40 to +125 °C (standard specification)

• Gate delay time : t

• Gate power consumption : 5 nW/MHz/BC (1.1 V, 2-NAND, F/O = 1)

• High-load drive capability : I

• Output buffer cells with noise reduction circuits

• Inputs with on-chip input pull-up/pull-down resistors (33 kΩ typical) and bidirectional buffer cells

• Buffer cell dedicated to crystal oscillator

• Special interfaces (P-CML, LVDS, PCI, AGP, USB, SDRAM-I/F, SSTL, etc. under development)

• IP macros (CPU, DSP, PCI, IEEE1394, USB, IrDA, PLL, ADC, DAC, etc. under development)

• Capable of incorporating compiled cells (RAM/ROM/multiplier, etc.)

• Configurable internal bus circuits

• Advanced hardware/software co-design environment

• Short-term development using a timing driven layout tool

• Support for static timing sign-off

Dramatically reducing the time for generating test vectors for timing verification and the simulation time

• Hierarchical design environment for supporting large-scale circuits

• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) ,

supporting development with minimized timing trouble after trial manufacture

• Support for memory (RAM/ROM) SCAN

• Support for memory (RAM) BIST

• Support for boundary SCAN

= 11 ps (1.8 V, inverter, F/O = 1)

= 2/4/8/12 mA mixable

(Continued)

CS81 Series

(Continued)

• Support for path delay test

• A variety of package options (TQFP, HQFP, EBGA, FBGA, TAB-BGA, FCBGA)

MACRO LIBRARY (Including macros being prepared)

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1. Logic cells (about 400 types)

• Adder • Decoder

• AND-OR Inverter • Non-SCAN Flip Flop

•Clock Buffer •Inverter

•Latch •Buffer

• NAND • OR-AND Inverter

•AND •OR

•NOR •Selector

• SCAN Flip Flop • BUS Driver

•ENOR •EOR

•AND-OR •Others

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2. IP macros

CPU/DSP Interface macro PCI, IEEE1394, USB, IrDA, etc.

Multimedia processing macros JPEG, MPEG, etc. Mixed signal macros ADC, DAC, OPAMP, etc. Compiled macros RAM, ROM, multiplier, adder, multiplier-accumulator, etc. PLL Analog PLL, digital PLL

FR, SPARClite, standard CPU (under preparation) Communications DSP, DSP for AV

3. Special I/O interface macros

• T-LVTTL • SSTL • HSTL • P-CML

• LVDS • PCI • AGP • USB

• IEEE1394

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CS81 Series

COMPILED CELLS

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Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS81 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.)

1. Clock synchronous single-port RAM (1 address, 1 RW)

Column type Memory capacity Word range Bit range Unit

4 16 to 72 K 16 to 1 K 1 to 72 Bit

16 64 to 72 K 64 to 4 K 1 to 18 Bit

2. Clock synchronous dual-port RAM (2 addresses, 1 RW/ 1 R)

Column type Memory capacity Word range Bit range Unit

4 16 to 72 K 16 to 1 K 1 to 72 Bit

16 64 to 72 K 64 to 4 K 1 to 18 Bit

3. Clock synchronous ROM

Column type Memory capacity Word range Bit range Unit

8 128 to 512 K 32 to 4 K 4 to 128 Bit

16 128 to 512 K 64 to 8 K 2 to 64 Bit

HIGH-CAPACITY MEMORY

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•

Clock synchronous single port RAM (1 address, 1 RW)

Column type Memory capacity Word range Bit range Unit

Under development

CS81 Series

ABSOLUTE MAXIMUM RATINGS

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Parameter Symbol Application

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Rating

Min. Max.

= 0 V)

Unit

Power supply voltage V

Input voltage

Output voltage V

Storage temperature T

Power-supply pin current

VDD, V

DDE

1.8 V input pin VSS − 0.5

3.3 V input pin V

1.8 V output pin VSS − 0.5

3.3 V output pin V Plastic package −55 +125 °C

Per VDD/V

Per V

(Internal) VSS − 0.5 +2.5 V

DDI

(External) VSS − 0.5 +4.0 V

+ 0.5

DDI

( ≤ 2.5 V)

+ 0.5

− 0.5

DDE

( ≤ 4.0 V)

+ 0.5

DDI

( ≤ 2.5 V)

+ 0.5

− 0.5

DDI/VDDE

pin  TBD mA

DDE

( ≤ 4.0 V)

L type output buffer IOL = 2 mA ±13 mA

Output current

M type output buffer I

H type output buffer I V type output buffer I

= 4 mA ±13 mA

= 8 mA ±13 mA

= 12 mA ±26 mA

*1 : Do not apply any voltage of 1.1 V or more between the LVDS (resistor built-in type) differential inputs. *2 : Maximum supply current which can be supplied constantly.

*3 : Maximum output current which can be supplied constantly . Exceeding the r ating is allowed only within 1 second

for only one LSI pin. The maximum rating of the P-CML output buffer is 20 mA.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

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