Fujitsu CM71-00101-5E User Manual

FUJITSU SEMICONDUCTOR

CONTROLLER MANUAL

CM71-00101-5E

FR Family

32-BIT MICROCONTROLLER

INSTRUCTION MANUAL

FR Family

32-BIT MICROCONTROLLER

INSTRUCTION MANUAL

FUJITSU LIMITED

PREFACE

■ Objectives and intended reader

The FR* family CPU core features proprietary Fujitsu architecture and is designed for controller applications using 32-bit RISC based comp uting. The architecture is optimized for use in mi crocontroller CPU cores for built-in control applications where high-speed control is required.

This manual is written for engineers involved in the development of products using the FR family of microcontrollers. It is designed specifically for programmers working in assembly lang uage for use with FR family assemblers, and describes the various instructions used with FR family. Be sure to read the entire manual carefully.

Note* that the use or non-use of coprocessors, as well as coprocessor specifications depends on the functions of individual FR family products.

For information about coprocessor specifications, users should consult the coprocessor section of the product documentation. Also, for the rules of assembly language grammar and the use of assembler programs, refer to the "FR Family Assembler Manual".

* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.

■ Trademark

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

■ Organization of this manual

This manual consists of the following 7 chapters and 1 appendix:

CHAPTER 1 FR FAMILY OVERVIEW

This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations.

CHAPTER 2 MEMORY ARCHITECTURE

This chapter describes memory space in the FR family CPU.

CHAPTER 3 REGISTER DESCRIPTIONS

This chapter describes the registers used in the FR family CPU.

CHAPTER 4 RESET AND "EIT" PROCESSING

This chapter describes reset and "EIT" processing in the FR family CPU.

CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU

This chapter presents precautionary information related to the use of the FR family CPU.

CHAPTER 6 INSTRUCTION OVERVIEW

This chapter presents an overview of the instructions used with the FR family CPU.

CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS

This chapter presents each of the execution instructions used by the FR family assembler, in reference format.

APPENDIX

The appendix section includes lists of CPU instruction s used in the FR family, as well as i nstruction map diagrams.

• The contents of this document are subject to change without notice. Customers are advised to consult with sales representatives before ordering.

• The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information.

• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein.

• The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions.

• Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

• The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

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CONTENTS

CHAPTER 1 FR FAMILY OVERVIEW .............................................................................. 1

1.1 Features of the FR Family CPU Core ............... .......................................................................... ........ 2

1.2 Sample Configuration of an FR Family Device ................................................................................... 3

1.3 Sample Configuration of the FR Family CPU ..................................................................................... 4

CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 5

2.1 FR Family Memory Space .................................................................................................................. 6

2.1.1 Direct Address Area ...................................................................................................................... 7

2.1.2 Vector Table Area .......................................................................................................................... 8

2.2 Bit Order and Byte Order ..................................... ....................................... ... ... ... ............................. 10

2.3 Word Alignment ................................................................................................................................ 11

CHAPTER 3 REGISTER DESCRIPTIONS ...................................................................... 13

3.1 FR Family Register Configuration ..................................................................................................... 14

3.2 General-purpose Registers ............................................................................................................... 15

3.3 Dedicated Registers ......................................................................................................................... 17

3.3.1 Program Counter (PC) ................................................................................................................. 18

3.3.2 Program Status (PS) ................................................................................................................... 19

3.3.3 Table Base Register (TBR) ......................................................................................................... 23

3.3.4 Return Pointer (RP) ..................................................................................................................... 25

3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) ................................ .... ... ... ... ... .... ......... 27

3.3.6 Multiplication/Division Register (MD) ........................................................................................... 29

CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 31

4.1 Reset Processing .............................................................................................................................. 33

4.2 Basic Operations in "EIT" Processing ............................................................................................... 34

4.3 Interrupts ....................... ............. ............. ............. ............. ............. ............. ............ .......................... 37

4.3.1 User Interrupts ............................................................................................................................. 38

4.3.2 Non-maskable Interrupts (NMI) ................................................................................................... 40

4.4 Exception Processing .......................................... ... ... .... ... ... ... ....................................... ... ................ 42

4.4.1 Undefined Instruction Exceptions ... ... ... ... ....................................... ... .... ... ... ................................ 43

4.5 Traps ............................. .......... .......... ...... .......... ......... .......... .......... ......... .......... ................................ 44

4.5.1 "INT" Instructions ......................................................................................................................... 45

4.5.2 "INTE" Instruction ........................................................................................................................ 46

4.5.3 Step Trace Traps ......................................................................................................................... 47

4.5.4 Coprocessor Not Found Traps .................... ... ... ... .... ...................................... .... ... ... ... ................ 48

4.5.5 Coprocessor Error Trap .. ...................................... .... ... ... ... .... ... ...................................... ............. 49

4.6 Priority Levels ................................................................................................................................... 51

CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ............. 53

5.1 Pipeline Operation ........ ... .............................................................................. ... ... .... ... ... ................... 54

5.2 Pipeline Operation and Interrupt Processin g ................. ... ... ... .... ...................................................... 55

5.3 Register Hazards .............................................................................................................................. 56

5.4 Delayed Branching Processing ......................................................................................................... 58

5.4.1 Processing Non-delayed Branching Instructions ......................................................................... 60

5.4.2 Processing Delayed Branching Instructions ................................................................................ 61

CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 63

6.1 Instruction Formats ................................. ....................................... ... ... ... .... ...................................... 64

6.2 Instruction Notation Formats ............................................................................. ... .... ... ... ... ................ 66

CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ................................................ 67

7.1 ADD (Add Word Data of Source Register to Destination Register) .................................................. 72

7.2 ADD (Add 4-bit Immediate Data to Destination Register) ................................................................. 73

7.3 ADD2 (Add 4-bit Immediate Data to Destination Register) ............................................................... 74

7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ......................... 75

7.5 ADDN (Add Word Data of Source Register to Destination Register) ............................................... 76

7.6 ADDN (Add Immediate Data to Destination Register) ...................................................................... 77

7.7 ADDN2 (Add Immediate Data to Destination Register) .................................................................... 78

7.8 SUB (Subtract Word Data in Source Register from Destination Register) ....................................... 79

7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) ............... 80

7.10 SUBN (Subtract Word Data in Source Register from Destination Register) ..................................... 81

7.11 CMP (Compare Word Data in Source Register and Destination Register) ...................................... 82

7.12 CMP (Compare Immediate Data of Source Register and Destination Register) .............................. 83

7.13 CMP2 (Compare Immediate Data and Destination Register) ........................................................... 84

7.14 AND (And Word Data of Source Register to Destination Register) .................................................. 85

7.15 AND (And Word Data of Source Register to Data in Memory) ......................................................... 86

7.16 ANDH (And Half-word Data of Source Register to Data in Memory) ................................................ 88

7.17 ANDB (And Byte Data of Source Register to Data in Memory) ........................................................ 90

7.18 OR (Or Word Data of Source Register to Destination Register) ....................................................... 92

7.19 OR (Or Word Data of Source Register to Data in Memory) .............................................................. 93

7.20 ORH (Or Half-word Data of Source Register to Data in Memory) .................................................... 95

7.21 ORB (Or Byte Data of Source Register to Data in Memory) ............................................................. 97

7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) .................................... 99

7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) ......................................... 100

7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ................................ 102

7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory ) ................. ... ... ................. 104

7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................ 106

7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Da ta in Mem or y) ............................... 108

7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ..................................... 110

7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Me m ory ) ............................... ... . 112

7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................. 114

7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 116

7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) ....................................................................... 118

7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) ..................................................................... 119

7.34 MUL (Multiply Word Data) .............................................................................................................. 120

7.35 MULU (Multiply Unsigned Word Data) ............................................................................................ 122

7.36 MULH (Multiply Half-word Data) ..................................................................................................... 124

7.37 MULUH (Multiply Unsigned Half-word Data) .......................... ....................................... ... ... .... ... ... . 126

7.38 DIV0S (Initial Setting Up for Signed Division) ................................................................................. 128

7.39 DIV0U (Initial Setting Up for Unsigned Division) ............................................................................. 130

7.40 DIV1 (Main Process of Division) ..................................................................................................... 132

7.41 DIV2 (Correction when Remainder is 0) ......................................................................................... 134

7.42 DIV3 (Correction when Remainder is 0) ......................................................................................... 136

7.43 DIV4S (Correction Answer for Signed Division) ............................................................................. 137

7.44 LSL (Logical Shift to the Left Direction) ...................................................................... ... ... ... ........... 138

7.45 LSL (Logical Shift to the Left Direction) ...................................................................... ... ... ... ........... 139

7.46 LSL2 (Logical Shift to the Left Direction) ........................................................................................ 140

7.47 LSR (Logical Shift to the Right Direction) ....................................................................................... 141

7.48 LSR (Logical Shift to the Right Direction) ....................................................................................... 142

7.49 LSR2 (Logical Shift to the Right Direction) ..................................................................................... 143

7.50 ASR (Arithmetic Shift to the Right Direction) ................................. ...................................... .... .. ..... 144

7.51 ASR (Arithmetic Shift to the Right Direction) ................................. ...................................... .... .. ..... 145

7.52 ASR2 (Arithmetic Shift to the Right Direction) ................................................................................ 146

7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) ........................................................ 147

7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) ........................................................ 148

7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) ............................................................ 149

7.56 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 150

7.57 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 151

7.58 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 152

7.59 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 153

7.60 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 154

7.61 LD (Load Word Data in Memory to Register) ................................... ....................................... ... ... . 155

7.62 LD (Load Word Data in Memory to Program Status Reg iste r) ................................ ... .................... 157

7.63 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 159

7.64 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 160

7.65 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 161

7.66 LDUB (Load Byte Data in Memory to Register) .............................................................................. 162

7.67 LDUB (Load Byte Data in Memory to Register) .............................................................................. 163

7.68 LDUB (Load Byte Data in Memory to Register) .............................................................................. 164

7.69 ST (Store Word Data in Register to Memory) ................................................................................. 165

7.70 ST (Store Word Data in Register to Memory) ................................................................................. 166

7.71 ST (Store Word Data in Register to Memory) ................................................................................. 167

7.72 ST (Store Word Data in Register to Memory) ................................................................................. 168

7.73 ST (Store Word Data in Register to Memory) ................................................................................. 169

7.74 ST (Store Word Data in Register to Memory) ................................................................................. 170

7.75 ST (Store Word Data in Program Status Register to Memory) ....................................................... 171

7.76 STH (Store Half-word Data in Register to Memory) ....................................................................... 172

7.77 STH (Store Half-word Data in Register to Memory) ....................................................................... 173

7.78 STH (Store Half-word Data in Register to Memory) ....................................................................... 174

7.79 STB (Store Byte Data in Register to Memory) ................................................................................ 175

7.80 STB (Store Byte Data in Register to Memory) ................................................................................ 176

7.81 STB (Store Byte Data in Register to Memory) ................................................................................ 177

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7.82 MOV (Move Word Data in Source Register to Destination Register) ............................................. 178

7.83 MOV (Move Word Data in Source Register to Destination Register) ............................................. 179

7.84 MOV (Move Word Data in Program Status Register to Destination Register) ................................ 180

7.85 MOV (Move Word Data in Source Register to Destination Register) ............................................. 181

7.86 MOV (Move Word Data in Source Register to Program Status Register) ...................................... 182

7.87 JMP (Jump) .................................................................................................................................... 184

7.88 CALL (Call Subroutine) .............. ... .... ... ... ....................................... ... ... ... .... .................................... 185

7.89 CALL (Call Subroutine) .............. ... .... ... ... ....................................... ... ... ... .... .................................... 186

7.90 RET (Return from Subroutine) ........................................................................................................ 187

7.91 INT (Software Interrupt) .................................................................... ... ... .... ... ................................. 188

7.92 INTE (Software Interrupt for Emulator) ................... ... ....................................... ... .... ... ... ................. 190

7.93 RETI (Return from Interrupt) ............. ... ....................................... ... ... ... ... ........................................ 192

7.94 Bcc (Branch Relative if Condition Satisfied) ................................................................................... 194

7.95 JMP:D (Jump) ................................................................................................................................. 196

7.96 CALL:D (Call Subroutine) ............................................................................................................... 197

7.97 CALL:D (Call Subroutine) ............................................................................................................... 199

7.98 RET:D (Return from Subroutine) .................................................................................................... 201

7.99 Bcc:D (Branch Relative if Condition Satisfied) ................................................................................ 203

7.100 DMOV (Move Word Data from Direct Address to Register) ........................................................... 205

7.101 DMOV (Move Word Data from Register to Direct Address) ........................................................... 206

7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address)

......................................................................................................................................................... 207

7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)

......................................................................................................................................................... 209

7.104 DMOV (Move Word Data from Direct Add ress to Pre-decrement Register Indirect Address)

......................................................................................................................................................... 211

7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address)

......................................................................................................................................................... 213

7.106 DMOVH (Move Half-word Data from Direct Address to Register) .................................................. 215

7.107 DMOVH (Move Half-word Data from Register to Direct Address) .................................................. 216

7.108 DMOVH (Move Half-word Data from Direc t Address to Post Increment Register Indirect Address)

......................................................................................................................................................... 217

7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)

......................................................................................................................................................... 219

7.110 DMOVB (Move Byte Data from Direct Address to Register) .......................................................... 221

7.111 DMOVB (Move Byte Data from Register to Direct Address) .......................................................... 222

7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address)

......................................................................................................................................................... 223

7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address)

......................................................................................................................................................... 225

7.114 LDRES (Load Word Data in Memory to Resource) ........................................................................ 227

7.115 STRES (Store Word Data in Resource to Memory) ....................................................................... 228

7.116 COPOP (Coprocessor Operation) .................................................................................................. 229

7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) ............................................... 231

7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) .............................................. 233

7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) ............................................... 235

7.120 NOP (No Operation) ....................................................................................................................... 237

7.121 ANDCCR (And Condition Code Register and Immediate Data) . ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... . 238

7.122 ORCCR (Or Condition Code Register and Imm edi at e Da ta) ............................ .............................. 239

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7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 240

7.124 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 241

7.125 EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... 242

7.126 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. 243

7.127 EXTSH (Sign Extend from Byte Data to Word Data) ........... ... .... ... ... .......................................... ... . 244

7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) .............................................................. 245

7.129 LDM0 (Load Multiple Registers) ..................................................................................................... 246

7.130 LDM1 (Load Multiple Registers) ..................................................................................................... 248

7.131 STM0 (Store Multiple Registers) ..................................................................................................... 250

7.132 STM1 (Store Multiple Registers) ..................................................................................................... 252

7.133 ENTER (Enter Function) ................... ... ... ... ... ....................................... ... .... ... ... ... ........................... 254

7.134 LEAVE (Leave Function) ................................................................................................................ 256

7.135 XCHB (Exchange Byte Data) .......................................................................................................... 258

APPENDIX ......................................................................................................................... 261

APPENDIX A Instruction Lists .................................................................................................................... 262

A.1 Symbols Used in Instruction Lists .................................................................................................. 263

A.2 Instruction Lists ............................................................................ ... ... ... .... ... ... .............................. 265

APPENDIX B Instruction Maps ................................................................................................................... 274

B.1 Instruction Map ............................................................................................................................... 275

B.2 "E" Format ...................................................................................................................................... 276

INDEX...................................................................................................................................277

Main changes in this edition

Page Changes (For details, refer to main body.)

Be sure to refer to the "Check Sheet" for the latest cautions on development. is changed. ("Check Sheet" is seen at the following support page... is deleted.)

"■ Objectives and intended reader" is changed.

( "FR" → "FR*" )

"■ Objectives and intended reader" is changed. ( " *: " is added. )

"PREFACE" is changed. ( "■ Trademark" is added. )

"PREFACE" is changed. ( "The company names and brand names herein are the trademarks or registered trademarks of their respective owners." is added. )

"Table 2.1-1 Structure of a Vector Table Area" is changed.

For 3F8H, ( "No" → "Yes" )

"● Lowest Bit Value of Program Counter" is changed.

( "incremented by one, and therefore" → "incremented and therefore" )

"Figure 3.3-4 "ILM" Register Functions" is changed. ( A line from ILM to COMP is added. )

"Figure 3.3-7 Sample of Table Base Register (TBR) Operation" is changed.

( "31" → "bit31" )

"■ System Stack Pointer (SSP), User Stack Pointer (USP)" is changed.

( "ST R13", "@-R15" → "ST R13, @-R15" )

The title of "Figure 3.3-12 Example of Stack Pointer Operation in Execution of Instruction "ST R13", "@R15" when "S" Flag = 0" is changed.

( "ST R13", "@-R15" → "ST R13, @-R15" )

The title of "Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13", "@R15" when "S" Flag = 1" is changed.

( "ST R13", "@-R15" → "ST R13, @-R15" )

"■ Recovery from EIT handler" is changed.

( "4.2 Basic Operations in "EIT" Processing ■ Recovery from EIT handler" → "■ Recovery from EIT handler"of "4.2 Basic Operations in "EIT" Processing" )

"4.3 Interrupts" is changed.

( "External" → "User" )

"■ Sources of Interrupts" is changed.

( "External" → "User" )

Page Changes (For details, refer to main body.)

"4.3.1 User Interrupts" is changed.

( "External" → "User" ), ( "external" → "user" )

"■ Overview of User Interrupts" is changed.

( "External" → "User" )

"■ Overview of User Interrupts" is changed. ( "Interrupts are referred to as "external" when they originate outside the CPU." is deleted. )

"■ Conditions for Acceptance of User Interrupt Requests" is changed.

( "External" → "User" )

"■ Conditions for Acceptance of User Interrupt Requests" is changed.

( "The CPU accepts interrupts" → "The CPU accepts user interrupts" )

"■ Operation Following Acceptance of an User Interrupt" is changed.

( "External" → "User" ), ( "external" → "user" )

"■ How to Use User Interrupts" is changed.

( "External" → "User" ), ( "external" → "user" )

"Figure 4.3-1 How to Use User Interrupts" is changed.

( "External" → "User" )

"Table 4.6-1 Priority of "EIT" Requests" is changed.

( "External" → "User"), ("INT" → "INTE")

"■ Examples of Programing Delayed Branching Instructions" is changed. ( The position of comment ";not satisfy" is changed. )

( R12 → R13)

"● Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results stored at operand 2" is changed. ( The position of R2 is changed. )

"7.1 ADD (Add Word Data of Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1010 0110 0010 0011" is added. )

"7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)" is changed. ( "Instruction bit pattern : 1010 0111 0010 0011" is added. )

"7.8 SUB (Subtract Word Data in Source Register from Destination Register)" is changed. ( "Instruction bit pattern : 1010 1100 0010 0011" is added. )

"7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)" is changed. ( "Instruction bit pattern : 1010 1101 0010 0011" is added. )

"7.10 SUBN (Subtract Word Data in Source Register from Destination Register)" is changed. ( "Instruction bit pattern : 1010 1110 0010 0011" is added. )

"7.11 CMP (Compare Word Data in Source Register and Destination Register)" is changed. ( "Instruction bit pattern : 1010 1010 0010 0011" is added. )

"7.14 AND (And Word Data of Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1000 0010 0010 0011" is added. )

xii

Page Changes (For details, refer to main body.)

101

"7.15 AND (And Word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0100 0010 0011" is added.)

"7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0101 0010 0011" is added. )

"7.17 ANDB (And Byte Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1000 0110 0010 0011" is added. )

"7.18 OR (Or Word Data of Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1001 0010 0010 0011" is added.)

"7.19 OR (Or Word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 0100 0010 0011" is added. )

"7.20 ORH (Or Half-word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 0101 0010 0011" is added. )

"7.21 ORB (Or Byte Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 0110 0010 0011" is added. )

"7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1001 1010 0010 0011" is added. )

"7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 1100 0010 0011" is added. )

103

105

121

123

125

127

129

131

133

"7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 1101 0010 0011" is added. )

"7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)" is changed. ( "Instruction bit pattern : 1001 1110 0010 0011" is added. )

"7.34 MUL (Multiply Word Data)" is changed. ( "Instruction bit pattern : 1010 1111 0010 0011" is added. )

"7.35 MULU (Multiply Unsigned Word Data)" is changed. ( "Instruction bit pattern : 1010 1011 0010 0011" is added. )

"7.36 MULH (Multiply Half-word Data)" is changed. ( "Instruction bit pattern : 1011 1111 0010 0011" is added. )

"7.37 MULUH (Multiply Unsigned Half-word Data)" is changed. ( "Instruction bit pattern : 1011 1011 0010 0011" is added. )

"7.38 DIV0S (Initial Setting Up for Signed Division)" is changed. ( "Instruction bit pattern : 1001 0111 0100 0010" is added. )

"7.39 DIV0U (Initial Setting Up for Unsigned Division)147/308" is changed. ( "Instruction bit pattern : 1001 0111 0101 0010" is added. )

"7.40 DIV1 (Main Process of Division)" is changed. ( "Instruction bit pattern : 1001 0111 0110 0010" is added. )

135

"7.41 DIV2 (Correction when Remainder is 0)" is changed. ( "Instruction bit pattern : 1001 0111 0111 0010" is added. )

xiii

Page Changes (For details, refer to main body.)

136

137

138

141

144

147

148

149

"7.42 DIV3 (Correction when Remainder is 0)" is changed. ( "Instruction bit pattern : 1001 1111 0110 0000" is added. )

"7.43 DIV4S (Correction Answer for Signed Division)" is changed. ( "Instruction bit pattern : 1001 1111 0111 0000" is added. )

"7.44 LSL (Logical Shift to the Left Direction)" is changed. ( "Instruction bit pattern : 1011 0110 0010 0011" is added. )

"7.47 LSR (Logical Shift to the Right Direction)" is changed. ( "Instruction bit pattern : 1011 0010 0010 0011" is added. )

"7.50 ASR (Arithmetic Shift to the Right Direction)" is changed. ( "Instruction bit pattern : 1011 1010 0010 0011" is added. )

"7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)" is changed. ( "Instruction bit pattern : 1001 1111 1000 0011

: 1000 0111 0110 0101 : 0100 0011 0010 0001" is added. )

"7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)" is changed. ( "Instruction bit pattern : 1001 1011 0101 0011

: 0100 0011 0010 0001" is added. )

"7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)" is changed. ( "Instruction bit pattern : 1100 0010 0001 0011" is added. )

150

151

153

154

156

157

158

159

160

"7.56 LD (Load Word Data in Memory to Register)"is changed. ( "Instruction bit pattern : 0000 0100 0010 0011" is added. )

"7.57 LD (Load Word Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0000 0010 0011" is added. )

"7.59 LD (Load Word Data in Memory to Register)" is changed.

( "o4" → "u4" )

"7.60 LD (Load Word Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0111 0000 0011" is added. )

"7.61 LD (Load Word Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0111 1000 0100" is added. )

"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.

Flag change: ( "Ri" → "R15")

"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed. ( "Instruction bit pattern : 0000 0111 1001 0000" is added. )

"7.63 LDUH (Load Half-word Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0101 0010 0011" is added. )

"7.64 LDUH (Load Half-word Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0001 0010 0011" is added. )

162

"7.66 LDUB (Load Byte Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0110 0010 0011" is added. )

xiv

Page Changes (For details, refer to main body.)

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165

166

168

169

170

171

172

173

"7.67 LDUB (Load Byte Data in Memory to Register)" is changed. ( "Instruction bit pattern : 0000 0010 0010 0011" is added. )

"7.69 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0100 0010 0011" is added. )

"7.70 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0000 0010 0011" is added. )

"7.72 ST (Store Word Data in Register to Memory)" is changed.

( "o4" → "u4" )

"7.73 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0111 0000 0011" is added. )

"7.74 ST (Store Word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0111 1000 0100" is added. )

"7.75 ST (Store Word Data in Program Status Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0111 1001 0000" is added. )

"7.76 STH (Store Half-word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0101 0010 0011" is added. )

"7.77 STH (Store Half-word Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0001 0010 0011" is added. )

175

176

178

179

180

181

183

184

"7.79 STB (Store Byte Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0110 0010 0011" is added. )

"7.80 STB (Store Byte Data in Register to Memory)" is changed. ( "Instruction bit pattern : 0001 0010 0010 0011" is added. )

"7.82 MOV (Move Word Data in Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1000 1011 0010 0011" is added. )

"7.83 MOV (Move Word Data in Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1011 0111 0101 0011" is added. )

"7.84 MOV (Move Word Data in Program Status Register to Destination Register)" is changed. ( "Instruction bit pattern : 0001 0111 0001 0011" is added. )

"7.85 MOV (Move Word Data in Source Register to Destination Register)" is changed. ( "Instruction bit pattern : 1011 0011 0101 0011" is added. )

"7.86 MOV (Move Word Data in Source Register to Program Status Register)" is changed. ( "Instruction bit pattern : 0000 0111 0001 0011" is added. )

"7.87 JMP (Jump)" is changed. ( "Instruction bit pattern : 1001 0111 0000 0001" is added. )

Page Changes (For details, refer to main body.)

"7.88 CALL (Call Subroutine)" is changed.

( "extension for use as the branch destination address" → "extension" )

"7.88 CALL (Call Subroutine)" is changed.

( "CALL 120H" →

185

" CALL label ... label: ; CALL instruction address + 122

" )

"7.88 CALL (Call Subroutine)" is changed. ( "Instruction bit pattern : 1101 0000 1001 0000" is added. )

186

187

188

189

191

192

193

194

195

"7.89 CALL (Call Subroutine)" is changed. ( "Instruction bit pattern : 1001 0111 0001 0001" is added. )

"7.90 RET (Return from Subroutine)" is changed. ( "Instruction bit pattern : 1001 0111 0010 0000" is added. )

"7.91 INT (Software Interrupt)" is changed.

( "INT#9" to "#13", "#64", "#65" → "INT#9" to "INT#13", "INT#64", "INT#65" )

"7.91 INT (Software Interrupt)" is changed. ( "Instruction bit pattern : 0001 1111 0010 0000" is added. )

"7.92 INTE (Software Interrupt for Emulator)" is changed. ( "Instruction bit pattern : 1001 1111 0011 0000" ) is added.

"7.93 RETI (Return from Interrupt)" is changed.

( D2, D1, → S, )

"7.93 RETI (Return from Interrupt)" is changed. ( "Instruction bit pattern : 1001 0111 0011 0000" is added. )

"7.94 Bcc (Branch Relative if Condition Satisfied)" is changed.

( "extension, for use as the branch destination address." → "extension" )

"7.94 Bcc (Branch Relative if Condition Satisfied)" is changed.

( "BHI 50H" →

" BHI label ... label: ; BHI instruction address + 50

" )

196

197

"7.95 JMP:D (Jump)" is changed. ( "Instruction bit pattern : 1001 1111 0000 0001" is added. )

"7.96 CALL:D (Call Subroutine)" is changed.

( "extension for use as the branch destination address" → "extension" )

xvi

Page Changes (For details, refer to main body.)

"7.96 CALL:D (Call Subroutine)" is changed. ( "CALL : D 120H

LDI : 8 #0, R2 ; Instruction placed in delay slot" →

"CALL:D label

198

LDI : 8 #0, R2 ; Instruction placed in delay slot ... label: ; CALL: D instruction address + 122

" )

"7.96 CALL:D (Call Subroutine)" is changed. ( "Instruction bit pattern : 1101 1000 1001 0000" is added. )

200

202

203

204

227

228

"7.97 CALL:D (Call Subroutine)" is changed. ( "Instruction bit pattern : 1001 1111 0001 0001" is added. )

"7.98 RET:D (Return from Subroutine)" is changed. ( "Instruction bit pattern : 1001 1111 0010 0000" is added. )

"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed.

( "extension, for use as the branch destination address" → "extension" )

"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed. ( "BHI :D 50H

LDI :8 #255, R1 ; Instruction placed in delay slot" →

"BHI:D label ... LDI :8 #255, R1 ; Instruction placed in delay slot label: ; BHI: D instruction address + 50

" )

"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed. ( "Instruction bit pattern : 1111 1111 0010 1000" is changed. )

"7.114 LDRES (Load Word Data in Memory to Resource)" is changed. ( "Instruction bit pattern : 1011 1100 1000 0010" is added. )

"7.115 STRES (Store Word Data in Resource to Memory)" is changed. ( "Instruction bit pattern : 1011 1101 1000 0010" is added. )

229

231

233

235

237

"7.116 COPOP (Coprocessor Operation)" is changed.

( "Resource" → "Coprocessor" )

"7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)" is changed.

( "Resource" → "Coprocessor" )

"7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)" is changed.

( "Resource" → "Coprocessor" )

"7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)" is changed.

( "Resource" → "Coprocessor" )

"7.120 NOP (No Operation)" is changed. ( "Instruction bit pattern : 1001 1111 1010 0000" is addded. )

xvii

Page Changes (For details, refer to main body.)

238

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243

244

245

255

257

"7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1000 0011 1111 1110" is added. )

"7.122 ORCCR (Or Condition Code Register and Immediate Data)" is changed. ( "Instruction bit pattern : 1001 0011 0001 0000" is added. )

"7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)" is changed. ( "Instruction bit pattern : 1000 0111 0001 0100" is added. )

"7.125 EXTSB (Sign Extend from Byte Data to Word Data)" is changed. ( "Instruction bit pattern : 1001 0111 1000 0001" is added. )

"7.126 EXTUB (Unsign Extend from Byte Data to Word Data)" is changed. ( "Instruction bit pattern : 1001 0111 1001 0001" is changed. )

"7.127 EXTSH (Sign Extend from Byte Data to Word Data)" is changed. ( "Instruction bit pattern : 1001 0111 1010 0001" is added. )

"7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)" is changed. ( "Instruction bit pattern : 1001 0111 1011 0001" is added. )

"7.133 ENTER (Enter Function)" is changed.

( "XXXX XXXX 0000 0011" → "0000 1111 0000 0011" )

"7.134 LEAVE (Leave Function)" is changed. ( "Instruction bit pattern : 1001 1111 1001 0000" is addded. )

258

259

"7.135 XCHB (Exchange Byte Data)" is chenged.

( "extu (Rj) → Ri" → "extu ((Rj)) → Ri" )

"7.135 XCHB (Exchange Byte Data)" is chenged. ( "Instruction bit pattern : 1000 1010 0001 0000" is added. )

xviii

Page Changes (For details, refer to main body.)

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed.

i8 .............( "128 to 255" → "0 to 255" )

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed. ( "Note: Data from -128 to -1 is handled as data from 128 to 255." is deleted. )

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed.

i20 ...........( "0x80000

to 0xFFFFFH" → "00000H to FFFFFH" )

263

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed. ( "Note: Data from -0x80000

to -1 is handled as data from 0x80000H to 0xFFFFFH." is deleted. )

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed.

i32 ...........( "0x80000000

to 0xFFFFFFFFH" → "00000000H to FFFFFFFFH" )

"A.1 Symbols Used in Instruction Lists" is chenged.

● Symbols in Mnemonic and Operation Columns is changed. ( "Note: Data from -0x80000000

to -1 is handled as data from 0x80000000H to 0xFFFFFFFFH." is deleted. )

263

264

266

"A.1 Symbols Used in Instruction Lists" is changed.

● Symbols in Mnemonic and Operation Columns is changed.

• Ri" → "• Ri, Rj" )

( "

"● Symbols in Operation Column" is changed. ( "

• ( )............. indicates indirect addressing, which values reading or loading from/to the memory address

where the registers within ( ) or the formula indicate.

• { }............ indicates the calculation priority; ( ) is used for specifying indiiirect address" is added. )

"● Cycle (CYC) Column" is changed.

( "special" → "dedicated" )

"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.

( "(Ri)&=(F0H+u4)" → "(Ri)&={F0H+u4}" )

"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.

( "(Ri)&=((u4<<4)+FH)" → "(Ri)&={{u4<<4}+FH}" )

"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.

( "(Ri) | = (u4<<4)" → "(Ri) | = {u4<<4}" )

"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.

( "(Ri) ^ = (u4<<4)" → "(Ri) ^ = {u4<<4}" )

"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.

( "(Ri) & (u4<<4)" → "(Ri) & {u4<<4}" )

xix

Page Changes (For details, refer to main body.)

"Table A.2-6 Shift Instructions (9 Instructions)" is changed.

267

( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} → Ri" )

( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" )

272

273

276

"Table A.2-13 Direct Addressing Instructions (14 Instructions)" is changed.

("disp8" → "dir8"), ("disp9" → "dir9"), ("disp10" → "dir10")

"Table A.2-16 Other Instructions (16 Instructions)" is changed.

("i8" → "u8")

"Table B.2-1 "E" Format" is changed. ( "- : Undefined" is added. )

CHAPTER 1

FR FAMILY OVERVIEW

This chapter describes the features of the FR FAMILY CPU core, and provides sample configurations.

1.1 Features of the FR Family CPU Core

1.2 Sample Configuration of an FR Family Device

1.3 Sample Configuration of the FR Family CPU

CHAPTER 1 FR FAMILY OVERVIEW

1.1 Features of the FR Family CPU Core

The FR family CPU core features proprietary Fujitsu ar chitecture and is designed for controller applications using 32-bit "RISC" based computing. The architecture is optimized for use in microcontroller CPU cores for built-in control applications where high-speed control is required.

■ Features of the FR Family CPU Core

• General-purpose register architecture

• Linear space for 32-bit (4 Gbytes) addressing

• 16-bit fixed instruction length (excluding immediate data, coprocessor instructions)

• 5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution

• 32-bit by 32-bit computation enables completion of multipl icati on instructions within five cycles

• Stepwise division instructions enable 32-bit/ 32-bit division

• Direct addressing instructions for peripheral circuit access

• Coprocessor instructions for direct designation of peripheral accelerator

• High speed interrupt processing complete within 6 cycles

CHAPTER 1 FR FAMILY OVERVIEW

1.2 Sample Configuration of an FR Family Device

FR family devices have block configuration with bus connections between individual modules. This enables module connections to be altered as necessary to accommodate a wide variety of functional configurations. Figure 1.2-1 shows an example of the configuration of an FR family device.

■ Sample Configuration of an FR Family Device

Figure 1.2-1 Sample Configuration of an FR Family Device

FR family CPU

DMAC

Data cache

RAM

Data bus

High speed

peripherals

Internal bus interface

ROM

User bus interface General-purpose port

Mandatory: Standard in all models

Instruction cache

Instruction bus

Integrated bus

Low speed peripherals

Peripheral bus

Low speed peripherals

Option: Not included in some models

CHAPTER 1 FR FAMILY OVERVIEW

1.3 Sample Configuration of the FR Family CPU

The FR family CPU core features a block configuration organized around generalpurpose registers, with dedicated registers, "ALU" units, multipliers and other features included for each specific application. Figure 1.3-1 shows a sample configuration of an FR family CPU.

■ Sample Configuration of the FR Family CPU

Figure 1.3-1 Sample Configuration of the FR Family CPU

Instruction data

Data

Data address

Instruction address

Instruction

decoder

Multiplier

32 x 8 bits

Instruction sequencer

ALU

Barrel shifter

Pipeline

control

Bypass

Bypass interlock

Wait cancel control

PC adder /inc

Internal bus

Exception processing

Internal bus Internal bus

Interrupt NMI

Wait bus control

CHAPTER 2

MEMORY ARCHITECTURE

This chapter describes memory space in the FR family CPU. Memory architecture includes the allocation of memory space as well as methods used to access memory .

2.1 FR Family Memory Space

2.2 Bit Order and Byte Order

2.3 Word Alignment

CHAPTER 2 MEMORY ARCHITECTURE

2.1 FR Family Memory Space

The FR family controls memory space in byte units, and provides linear designation of 32-bit spaces. Also, to enhance instruction efficiency, specific areas of memory are allocated for use as direct address areas and vector table areas.

■ Memory Space

Figure 2.1-1 illustrates memory space in the FR family. For a detailed description of the direct address area, see Section "2.1.1 Direct Address Area", and for the vector table area, see Section "2.1.2 Vector Table Area".

Figure 2.1-1 FR Family Memory Space

Direct address area

General addressing

0000 0000H

0000 0100H

0000 0200H

0000 0400H

000F FC00H

0010 0000H

FFFF FFFFH

■ Unused V ector Table Area

Unused vector table area is available for use as program or data area.

Byte data

Half-word data

Word data

Vector table initial area

Program or data area

000F FC00

TBR initial value

H TBR

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