FTDIChip FT232R User Manual

™

Future Technology Devices International Ltd.

FT232R USB UART I.C.

Incorporating Clock Generator Output

and FTDIChip-ID™ Security Dongle

The FT232R is the latest device to be added to FTDI’s range of USB UART interface Integrated Circuit Devices. The

FT232R is a USB to serial UART interface with optional clock generator output, and the new FTDIChip-ID™ security

dongle feature. In addition, asynchronous and synchronous bit bang interface modes are available. USB to serial

designs using the FT232R have been further simplified by fully integrating the external EEPROM, clock circuit and

USB resistors onto the device.

The FT232R adds two new functions compared with its predecessors, effectively making it a “3-in-1” chip for some

application areas. The internally generated clock (6MHz, 12MHz, 24MHz, and 48MHz) can be brought out of the

device and used to drive a microcontroller or external logic. A unique number (the FTDIChip-ID™) is burnt into the

device during manufacture and is readable over USB, thus forming the basis of a security dongle which can be used

to protect customer application software from being copied.

The FT232R is available in Pb-free (RoHS compliant) compact 28-Lead SSOP and QFN-32 packages.

Copyright © Future Technology Devices International Ltd. 2005

1. Features

1.1 Hardware Features

• Single chip USB to asynchronous serial data
transfer interface.

• Entire USB protocol handled on the chip - No
USB-specific firmware programming required.

• UART interface support for 7 or 8 data bits, 1 or 2
stop bits and odd / even / mark / space / no parity.

• Fully assisted hardware or X-On / X-Off software
handshaking.

• Data transfer rates from 300 baud to 3 Megabaud
(RS422 / RS485 and at TTL levels) and 300 baud
to 1 Megabaud (RS232).

• 256 byte receive buffer and 128 byte transmit
buffer utilising buffer smoothing technology to allow
for high data throughput.

• FTDI’s royalty-free VCP and D2XX drivers
eliminate the requirement for USB driver
development in most cases.

• In-built support for event characters and line break
condition.

• New USB FTDIChip-ID™ feature.

• New configurable CBUS I/O pins.

• Auto transmit buffer control for RS485 applications.

• Transmit and receive LED drive signals.

• New 48MHz, 24MHz,12MHz, and 6MHz clock

output signal Options for driving external MCU or
FPGA.

• FIFO receive and transmit buffers for high data
throughput.

• Adjustable receive buffer timeout.

• Synchronous and asynchronous bit bang mode

interface options with RD# and WR# strobes.

• New CBUS bit bang mode option.

Page 2

• Integrated 1024 Bit internal EEPROM for storing
USB VID, PID, serial number and product
description strings, and CBUS I/O configuration.

• Device supplied preprogrammed with unique USB
serial number.

• Support for USB suspend and resume.

• Support for bus powered, self powered, and high-

power bus powered USB configurations.

• Integrated 3.3V level converter for USB I/O .

• Integrated level converter on UART and CBUS for

interfacing to 5V - 1.8V Logic.

• True 5V / 3.3V / 2.8V / 1.8V CMOS drive output
and TTL input.

• High I/O pin output drive option.

• Integrated USB resistors.

• Integrated power-on-reset circuit.

• Fully integrated clock - no external crystal,

oscillator, or resonator required.

• Fully integrated AVCC supply filtering - No separate
AVCC pin and no external R-C filter required.

• UART signal inversion option.

• USB bulk transfer mode.

• 3.3V to 5.25V Single Supply Operation.

• Low operating and USB suspend current.

• Low USB bandwidth consumption.

• UHCI / OHCI / EHCI host controller compatible

• USB 2.0 Full Speed compatible.

• -40°C to 85°C extended operating temperature

range.

• Available in compact Pb-free 28 Pin SSOP and

QFN-32 packages (both RoHS compliant).

1.2 Driver Support

Royalty-Free VIRTUAL COM PORT
(VCP) DRIVERS for...

• Windows 98, 98SE, ME, 2000, Server 2003, XP.

• Windows Vista / Longhorn*

• Windows XP 64-bit.*

• Windows XP Embedded.

• Windows CE.NET 4.2 & 5.0

• MAC OS 8 / 9, OS-X

• Linux 2.4 and greater

The drivers listed above are all available to download for free from the FTDI website. Various 3rd Party Drivers are
also available for various other operating systems - see the FTDI website for details.

* Currently Under Development. Contact FTDI for availability.

Royalty-Free D2XX Direct Drivers
(USB Drivers + DLL S/W Interface)

• Windows 98, 98SE, ME, 2000, Server 2003, XP.

• Windows Vista / Longhorn*

• Windows XP 64-bit.*

• Windows XP Embedded.

• Windows CE.NET 4.2 & 5.0

• Linux 2.4 and greater

1.3 Typical Applications

• USB to RS232 / RS422 / RS485 Converters

• Upgrading Legacy Peripherals to USB

• Cellular and Cordless Phone USB data transfer

cables and interfaces

• Interfacing MCU / PLD / FPGA based designs to
USB

• USB Audio and Low Bandwidth Video data transfer

• PDA to USB data transfer

• USB Smart Card Readers

• USB Instrumentation

• USB Industrial Control

• USB MP3 Player Interface

• USB FLASH Card Reader / Writers

• Set Top Box PC - USB interface

• USB Digital Camera Interface

• USB Hardware Modems

• USB Wireless Modems

• USB Bar Code Readers

• USB Software / Hardware Encryption Dongles

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 3

2. Enhancements

2.1 Device Enhancements and Key Features

This section summarises the enhancements and the key features of the FT232R device. For further details, consult
the device pin-out description and functional description sections.

Integrated Clock Circuit - Previous generations of FTDI’s USB UART devices required an external crystal or ceramic
resonator. The clock circuit has now been integrated onto the device meaning that no crystal or ceramic resonator is
required. However, if required, an external 12MHz crystal can be used as the clock source.

Integrated EEPROM - Previous generations of FTDI’s USB UART devices required an external EEPROM if the
device were to use USB Vendor ID (VID), Product ID (PID), serial number and product description strings other than
the default values in the device itself. This external EEPROM has now been integrated onto the FT232R chip meaning
that all designs have the option to change the product description strings. A user area of the internal EEPROM is
available for storing additional data. The internal EEPROM is programmable in circuit, over USB without any additional
voltage requirement.

Preprogrammed EEPROM - The FT232R is supplied with its internal EEPROM preprogrammed with a serial number
which is unique to each individual device. This, in most cases, will remove the need to program the device EEPROM.

Integrated USB Resistors - Previous generations of FTDI’s USB UART devices required two external series resistors
on the USBDP and USBDM lines, and a 1.5 kΩ pull up resistor on USBDP. These three resistors have now been
integrated onto the device.

Integrated AVCC Filtering - Previous generations of FTDI’s USB UART devices had a separate AVCC pin - the
supply to the internal PLL. This pin required an external R-C filter. The separate AVCC pin is now connected internally
to VCC, and the filter has now been integrated onto the chip.

Less External Components - Integration of the crystal, EEPROM, USB resistors, and AVCC filter will substantially
reduce the bill of materials cost for USB interface designs using the FT232R compared to its FT232BM predecessor.

Transmit and Receive Buffer Smoothing - The FT232R’s 256 byte receive buffer and 128 byte transmit buffer utilise
new buffer smoothing technology to allow for high data throughput.

Configurable CBUS I/O Pin Options - There are now 5 configurable Control Bus (CBUS) lines. Options are TXDEN

- transmit enable for RS485 designs, PWREN# - Power control for high power, bus powered designs, TXLED# - for

pulsing an LED upon transmission of data, RXLED# - for pulsing an LED upon receiving data, TX&RXLED# - which
will pulse an LED upon transmission OR reception of data, SLEEP# - indicates that the device going into USB
suspend mode, CLK48 / CLK24 / CLK12 / CLK6 - 48MHz, 24MHz,12MHz, and 6MHz clock output signal options.
There is also the option to bring out bit bang mode read and write strobes (see below). The CBUS lines can be
configured with any one of these output options by setting bits in the internal EEPROM. The device is supplied with
the most commonly used pin definitions preprogrammed - see Section 10 for details.

Enhanced Asynchronous Bit Bang Mode with RD# and WR# Strobes - The FT232R supports FTDI’s BM chip
bit bang mode. In bit bang mode, the eight UART lines can be switched from the regular interface mode to an 8-bit
general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface
at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the FT232R device this mode
has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used
to allow external logic to be clocked by accesses to the bit bang I/O bus. This option will be described more fully in a
separate application note.

Synchronous Bit Bang Mode - Synchronous bit bang mode differs from asynchronous bit bang mode in that the
interface pins are only read when the device is written to. Thus making it easier for the controlling program to measure
the response to an output stimulus as the data returned is synchronous to the output data. The feature was previously
seen in FTDI’s FT2232C device. This option will be described more fully in a separate application note.

CBUS Bit Bang Mode - This mode allows four of the CBUS pins to be individually configured as GPIO pins, similar
to Asynchronous bit bang mode. It is possible to use this mode while the UART interface is being used, thus providing
up to four general purpose I/O pins which are available during normal operation. An application note describing this
feature is available separately from the FTDI website.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 4

Lower Supply Voltage - Previous generations of the chip required 5V supply on the VCC pin. The FT232R will work
with a Vcc supply in the range 3.3V - 5.25V. Bus powered designs would still take their supply from the 5V on the USB
bus, but for self powered designs where only 3.3V is available and there is no 5V supply there is no longer any need
for an additional external regulator.

Integrated Level Converter on UART Interface and Control Signals - VCCIO pin supply can be from 1.8V to 5V.
Connecting the VCCIO pin to 1.8V, 2.8V, or 3.3V allows the device to directly interface to 1.8V, 2.8V or 3.3V and other
logic families without the need for external level converter I.C. devices.

5V / 3.3V / 2.8V / 1.8V Logic Interface - The FT232R provides true CMOS Drive Outputs and TTL level Inputs.

Integrated Power-On-Reset (POR) Circuit- The device incorporates an internal POR function. A RESET# pin is

available in order to allow external logic to reset the FT232R where required. However, for many applications the
RESET# pin can be left unconnected, or pulled up to VCCIO.

Lower Operating and Suspend Current - The device operating supply current has been further reduced to 15mA,
and the suspend current has been reduced to around 70μA. This allows greater margin for peripheral designs to meet
the USB suspend current limit of 500μA.

Low USB Bandwidth Consumption - The operation of the USB interface to the FT232R has been designed to use
as little as possible of the total USB bandwidth available from the USB host controller.

High Output Drive Option - The UART interface and CBUS I/O pins can be made to drive out at three times the
standard signal drive level thus allowing multiple devices to be driven, or devices that require a greater signal drive
strength to be interfaced to the FT232R. This option is enabled in the internal EEPROM.

Power Management Control for USB Bus Powered, High Current Designs- The PWREN# signal can be used to
directly drive a transistor or P-Channel MOSFET in applications where power switching of external circuitry is required.
An option in the internal EEPROM makes the device gently pull down on its UART interface lines when the power
is shut off (PWREN# is high). In this mode any residual voltage on external circuitry is bled to GND when power is
removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored.

UART Pin Signal Inversion - The sense of each of the eight UART signals can be individually inverted by setting
options in the internal EEPROM. Thus, CTS# (active low) can be changed to CTS (active high), or TXD can be
changed to TXD#.

FTDIChip-ID™ - Each FT232R is assigned a unique number which is burnt into the device at manufacture. This ID
number cannot be reprogrammed by product manufacturers or end-users. This allows the possibility of using FT232R
based dongles for software licensing. Further to this, a renewable license scheme can be implemented based on the
FTDIChip-ID™ number when encrypted with other information. This encrypted number can be stored in the user area
of the FT232R internal EEPROM, and can be decrypted, then compared with the protected FTDIChip-ID™ to verify
that a license is valid. Web based applications can be used to maintain product licensing this way. An application note
describing this feature is available separately from the FTDI website.

Improved EMI Performance - The reduced operating current and improved on-chip VCC decoupling significantly
improves the ease of PCB design requirements in order to meet FCC, CE and other EMI related specifications.

Programmable Receive Buffer Timeout - The receive buffer timeout is used to flush remaining data from the
receive buffer. This time defaults to 16ms, but is programmable over USB in 1ms increments from 1ms to 255ms, thus
allowing the device to be optimised for protocols that require fast response times from short data packets.

Extended Operating Temperature Range - The FT232R operates over an extended temperature range of -40º to
+85º C thus allowing the device to be used in automotive and industrial applications.

New Package Options - The FT232R is available in two packages - a compact 28 pin SSOP ( FT232RL) and an
ultra-compact 5mm x 5mm pinless QFN-32 package ( FT232RQ). Both packages are lead ( Pb ) free, and use a
‘green’ compound. Both packages are fully compliant with European Union directive 2002/95/EC.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

3. Block Diagram

Clock

Multiplier /

Divider

UART

FIFO Controller

Serial Interface

Engine

( SIE )

USB

Protocol Engine

Baud Rate
Generator

UART Controller

with

Programmable

Signal Inversion

and High Drive

3.3 Volt
LDO

Regulator

USB

Transceiver

with

Integrated

Series

Resistors

and 1.5K

Pull-up

USB DPLL

Internal

12MHz

Oscillator

48MHz

48MHz

OCSI

(optional)

OSCO

(optional)

USBDP

USBDM

3V3OUT

VCC

TXD
RXD
RTS#
CTS#
DTR#
DSR#
DCD#
RI#

CBUS0

CBUS2
CBUS3

RESET#

TEST

GND

RESET

GENERATOR

3V3OUT

CBUS1

FIFO TX Buffer

128 bytes

FIFO RX Buffer

256 bytes

Internal

EEPROM

To USB Transceiver Cell

CBUS4

24 MHz

12 MHz

6 MHz

To USB

Transceiver

Cell

VCCIO

3.1 Block Diagram (Simplified)

Page 5

Figure 1 - FT232R Block Diagram

3.2 Functional Block Descriptions

3.3V LDO Regulator - The 3.3V LDO Regulator generates the 3.3V reference voltage for driving the USB transceiver

cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It
also provides 3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of this block is to power
the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry
requiring a 3.3V nominal supply at a current of around than 50mA could also draw its power from the 3V3OUT pin, if
required.

USB Transceiver - The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB
cable. The output drivers provide 3.3V level slew rate control signalling, whilst a differential receiver and two single
ended receivers provide USB data in, SEO and USB Reset condition detection. This Cell also incorporates internal
USB series resistors on the USB data lines, and a 1.5kΩ pull up resistor on USBDP.

USB DPLL - The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and
data signals to the SIE block.

Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock input to the x4
Clock multiplier. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and
UART FIFO controller blocks

Clock Multiplier / Divider - The Clock Multiplier / Divider takes the 12MHz input from the Oscillator Cell and
generates the 48MHz, 24MHz, 12MHz, and 6MHz reference clock signals. The 48Mz clock reference is used for the
USB DPLL and the Baud Rate Generator blocks.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 6

Serial Interface Engine (SIE) - The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to
Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / un-stuffing
and CRC5 / CRC16 generation / checking on the USB data stream.

USB Protocol Engine - The USB Protocol Engine manages the data stream from the device USB control endpoint. It
handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for
controlling the functional parameters of the UART.

FIFO TX Buffer (128 bytes) - Data from the USB data out endpoint is stored in the FIFO TX buffer and removed from
the buffer to the UART transmit register under control of the UART FIFO controller.

FIFO RX Buffer (256 bytes) - Data from the UART receive register is stored in the FIFO RX buffer prior to being
removed by the SIE on a USB request for data from the device data in endpoint.

UART FIFO Controller - The UART FIFO controller handles the transfer of data between the FIFO RX and TX buffers
and the UART transmit and receive registers.

UART Controller with Programmable Signal Inversion and High Drive - Together with the UART FIFO Controller
the UART Controller handles the transfer of data between the FIFO RX and FIFO TX buffers and the UART transmit
and receive registers. It performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the
data on the RS232 (RS422 and RS485) interface. Control signals supported by UART mode include RTS, CTS,
DSR , DTR, DCD and RI. The UART Controller also provides a transmitter enable control signal pin option (TXDEN)
to assist with interfacing to RS485 transceivers. RTS / CTS, DSR / DTR and X-On / X-Off handshaking options are
also supported. Handshaking, where required, is handled in hardware to ensure fast response times. The UART also
supports the RS232 BREAK setting and detection conditions. A new feature, programmable in the internal EEPROM
allows the UART signals to each be individually inverted. Another new EEPROM programmable feature allows a high

signal drive strength to be enabled on the UART interface and CBUS pins.

Baud Rate Generator - The Baud Rate Generator provides a x16 clock input to the UART Controller from the 48MHz
reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate
(used to divide by a number plus a fraction or “sub-integer”). This determines the Baud Rate of the UART, which is
programmable from 183 baud to 3 million baud.

The FT232R supports all standard baud rates and non-standard baud rates from 300 Baud up to 3 Megabaud.
Achievable non-standard baud rates are calculated as follows -

Baud Rate = 3000000 / (n + x)

where n can be any integer between 2 and 16,384 ( = 214 ) and x can be a sub-integer of the value 0, 0.125, 0.25,

0.375, 0.5, 0.625, 0.75, or 0.875. When n = 1, x = 0, i.e. baud rate divisors with values between 1 and 2 are not
possible.

This gives achievable baud rates in the range 183.1 baud to 3,000,000 baud. When a non-standard baud rate is
required simply pass the required baud rate value to the driver as normal, and the FTDI driver will calculate the
required divisor, and set the baud rate. See FTDI application note AN232B-05 for more details.

RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal
circuitry on power up. A RESET# input pin is provided to allow other devices to reset the FT232R. RESET# can be
tied to VCCIO or left unconnected, unless it is a requirement to reset the device from external logic or an external
reset generator I.C.

Internal EEPROM - The internal EEPROM in the FT232R can be used to store USB Vendor ID (VID), Product ID
(PID), device serial number, product description string, and various other USB configuration descriptors. The internal
EEPROM is also used to configure the CBUS pin functions. The device is supplied with the internal EEPROM settings
preprogrammed as described in Section 10.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

4. Device Pin Out and Signal Descriptions

USBDP

USBDM

3V3OUT

GND

RESET#

VCC

GND

NC

AGND

TEST

OSCI

OSCO

CBUS1

CBUS0

TXD

RTS#

RXD

DTR#

VCCIO

RI#

GND

NC

DSR#

DCD#

CTS#

CBUS4

CBUS2

CBUS3

FT232RL

YYXX-A

1

14

15

28

FTDI

FT232RL

A
G
N
D

G
N
D

G
N
D

G
N
D

T
E
S
T

25

7 18 21 26

3V3OUT

VCCIO

4

17

NC

RESET#

NC

24

19

8

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

1

5

3

11

2

9

10

6

CBUS0

CBUS3

CBUS2

CBUS1

23

22

13

14

20

16

15

USBDP

USBDM

VCC

OSCI

27

OSCO

28

CBUS4

12

4.1 28-LD SSOP Package

Page 7

Figure 2 - 28 Pin SSOP Package Pin Out

Figure 3 - 28 Pin SSOP Package Pin Out (Schematic Symbol)

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

Page 8

4.2 SSOP-28 Package Signal Descriptions

Table 1 - SSOP Package Pin Out Description

Pin No. Name Type Description

USB Interface Group

15 USBDP I/O USB Data Signal Plus, incorporating internal series resistor and 1.5kΩ pull up resistor to 3.3V

16 USBDM I/O USB Data Signal Minus, incorporating internal series resistor.

Power and Ground Group

4 VCCIO PWR +1.8V to +5.25V supply to the UART Interface and CBUS group pins (1...3, 5, 6, 9...14, 22, 23). In USB bus

powered designs connect to 3V3OUT to drive out at 3.3V levels, or connect to VCC to drive out at 5V CMOS
level. This pin can also be supplied with an external 1.8V - 2.8V supply in order to drive out at lower levels. It
should be noted that in this case this supply should originate from the same source as the supply to Vcc. This
means that in bus powered designs a regulator which is supplied by the 5V on the USB bus should be used.

7, 18, 21 GND PWR Device ground supply pins

17 3V3OUT Output 3.3V output from integrated L.D.O. regulator. This pin should be decoupled to ground using a 100nF capacitor.

The prime purpose of this pin is to provide the internal 3.3V supply to the USB transceiver cell and the internal

1.5kΩ pull up resistor on USBDP. Up to 50mA can be drawn from this pin to power external logic if required.
This pin can also be used to supply the FT232R’s VCCIO pin.

20 VCC PWR 3.3V to 5.25V supply to the device core.

25 AGND PWR Device analog ground supply for internal clock multiplier

Miscellaneous Signal Group

8, 24 NC NC No internal connection.

19 RESET# Input Can be used by an external device to reset the FT232R. If not required can be left unconnected, or pulled up

to VCCIO.

26 TEST Input Puts the device into I.C. test mode. Must be tied to GND for normal operation.

27 OSCI Input Input to 12MHz Oscillator Cell. Optional - Can be left unconnected for normal operation. *

28 OSCO Output Output from 12MHz Oscillator Cell. Optional - Can be left unconnected for normal operation if internal oscilla-

tor is used. *

UART Interface and CBUS Group **

1 TXD Output Transmit Asynchronous Data Output.

2 DTR# Output Data Terminal Ready Control Output / Handshake signal.

3 RTS# Output Request To Send Control Output / Handshake signal.

5 RXD Input Receive Asynchronous Data Input.

6 RI# Input Ring Indicator Control Input. When remote wake up is enabled in the internal EEPROM taking RI# low can be

used to resume the PC USB host controller from suspend.

9 DSR# Input Data Set Ready Control Input / Handshake signal.

10 DCD# Input Data Carrier Detect Control input.

11 CTS# Input Clear to Send Control input / Handshake signal.

12 CBUS4 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory Default

function is SLEEP#. See CBUS Signal Options, Table 3.

13 CBUS2 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory Default

function is TXDEN. See CBUS Signal Options, Table 3.

14 CBUS3 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory Default

function is PWREN#. See CBUS Signal Options, Table 3.

22 CBUS1 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory Default

function is RXLED#. See CBUS Signal Options, Table 3.

23 CBUS0 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device internal EEPROM. Factory Default

function is TXLED#. See CBUS Signal Options, Table 3.

* Contact FTDI technical support for details on how to use an external crystal, ceramic resonator, or oscillator with the
FT232R.

** When used in Input Mode, these pins are pulled to VCCIO via internal 200kΩ resistors. These pins can be

programmed to gently pull low during USB suspend ( PWREN# = “1” ) by setting an option in the internal EEPROM.

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005

4.3 QFN-32 Package

FT232RQ

A
G
N
D

G
N
D

G
N
D

G

N
D

T
E
S
T

24

4 17 20 26

3V3OUT

VCCIO

1

16

NC

RESET#

NC

23

18

13

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

30

2

32

8

31

6

7

3

CBUS0

CBUS3

CBUS2

CBUS1

22

21

10

11

19

15

14

USBDP

USBDM

VCC

OSCI

27

OSCO

28

CBUS4

9

NC

12

NC

5

NC

29

NC

25

FT232RQ

32

25

24

17

16

9

8

1

YYXX-A

18

9

1

2

3

4

5

6

7

8

10111213141516

17

19

20

21

22

23

24

25 26 27 28 29 30 31 32

USBDP

USBDM

3V3OUT

RESET#

VCC

NC

AGND

TEST

OSCI

OSCO

CBUS1

CBUS0

TXD

RTS#

RXD

DTR#

VCCIO

RI#

GND

NC

DSR#

DCD#

CTS#

CBUS4

CBUS2

CBUS3

GND

GND

NC

NC

NC

NC

FTDI

TOP

BOTTOM

Page 9

Figure 4 - QFN-32 Package Pin Out

Figure 5 - QFN-32 Package Pin Out (Schematic Symbol)

FT232R USB UART I.C. Datasheet Version 1.04 © Future Technology Devices International Ltd. 2005