FTDIChip FT232BM User Manual

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The FT232BM is the 2nd generation of FTDI’s popular USB UART i.c. This device not only adds extra functionality

to it’s FT8U232AM predecessor and reduces external component count, but also maintains a high degree of pin

compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the

potential for using the device in new application areas.

Single Chip USB óAsynchronous Serial Data

Transfer

• Full Handshaking & Modem Interface Signals

• UART I/F Supports 7 / 8 Bit Data, 1 / 2 Stop Bits

and Odd/Even/Mark/Space/No Parity

• Data rate 300 => 3M Baud ( TLL )

• Data rate 300 => 1M Baud ( RS232 )

• Data rate 300 => 3M Baud ( RS422/RS485 )

• 384 Byte Receive Buffer / 128 Byte Transmit Buffer

for high data throughput

• Adjustable RX buffer timeout

• Full hardware assisted hardware or X-On / X-Off

handshaking

• In-built support for event characters and line break

condition

• Auto Transmit Buffer control for RS485

• Support for USB Suspend / Resume through

SLEEP# and RI# pins

• Support for high power USB Bus powered devices

through PWREN# pin

• Integrated level converter on UART and control

signals for interfacing to 5v and 3.3v logic

• Integrated 3.3v regulator for USB IO

• Integrated Power-On-Reset circuit

• Integrated 6MHz – 48Mhz clock multiplier PLL

• USB Bulk or Isocronous data transfer modes

• 4.4v to 5.25v single supply operation

• UHCI / OHCI / EHCI host controller compatible

• USB 1.1 and USB 2.0 compatible

• USB VID, PID , Serial Number and Product

Description strings in external EEPROM

• EEPROM programmable on-board via USB

VIRTUAL COM PORT ( VCP ) DRIVERS for

- Windows 98 and Windows 98 SE

- Windows 2000 / ME / XP

- Windows CE **

- MAC OS-8 and OS-9

- MAC OS-X **

- Linux 2.40 and greater

D2XX ( USB Direct Drivers + DLL S/W Interface )

- Windows 98 and Windows 98 SE

- Windows 2000 / ME / XP

APPLICATION AREAS

- USB óRS232 Converters

- USB ó RS422 / RS485 Converters

- Upgrading RS232 Legacy Peripherals to USB

- Cellular and Cordless Phone USB data transfer

cables and interfaces

- Interfacing MCU based designs to USB

- USB Audio and Low Bandwidth Video data transfer

- PDA ó USB data transfer

- USB Smart Card Readers

- Set Top Box ( S.T.B. ) PC - USB interface

- USB Hardware Modems

- USB Wireless Modems

- USB Instrumentation

- USB Bar Code Readers

[ ** = In planning or under development ]

1.0 Features

HARDWARE FEATURES

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2.0 Enhancements

This section summarises the enhancements of the 2nd generation device compared to it’s FT8U232AM predecessor.

For further details, consult the device pin-out description and functional descriptions.

• Integrated Power-On-Reset ( POR ) Circuit

The device now incorporates an internal POR

function. The existing RESET# pin is maintained

in order to allow external logic to reset the device

where required, however for many applications

this pin can now be either left N/C or hard wired to

VCC. In addition, a new reset output pin ( RSTO#

) is provided in order to allow the new POR circuit

to provide a stable reset to external MCU and other

devices. RSTO# was the TEST pin on the previous

generation of devices.

• Integrated RCCLK Circuit

In the previous devices, an external RC circuit

was required to ensure that the oscillator and

clock multiplier PLL frequency was stable prior

to enabling the clock internal to the device. This

circuit is now embedded on-chip – the pin assigned

to this function is now designated as the TEST pin

and should be tied to GND for normal operation.

• Integrated Level Converter on UART interface

and control signals

The previous devices would drive the UART and

control signals at 5v CMOS logic levels. The

new device has a separate VCC-IO pin allowing

the device to directly interface to 3.3v and other

logic families without the need for external level

converter i.c.’s

• Improved Power Management control for USB

Bus Powered, high current devices

The previous devices had a USBEN pin, which

became active when the device was enumerated

by USB. To provide power control, this signal had

to be externally gated with SLEEP# and RESET#.

This gating is now done on-chip - USBEN has

now been replaced with the new PWREN# signal

which can be used to directly drive a transistor or

P-Channel MOSFET in applications where power

switching of external circuitry is required. A new

EEPROM based option makes the device pull

gently down it’s UART interface lines when the

power is shut off ( PWREN# is High ). In this mode,

any residual voltage on external circuitry is bled to

GND when power is removed thus ensuring that

external circuitry controlled by PWREN# resets

reliably when power is restored.

• Lower Suspend Current

Integration of RCCLK within the device and internal

design improvements reduce the suspend current

of the FT232BM to under 200uA ( excluding the

1.5k pull-up on USB DP ) in USB suspend mode.

This allows greater margin for peripherals to meet

the USB Suspend current limit of 500uA.

• Support for USB Isocronous Transfers

Whilst USB Bulk transfer is usually the best

choice for data transfer, the scheduling time of the

data is not guaranteed. For applications where

scheduling latency takes priority over data integrity

such as transferring audio and low bandwidth

video data, the new device now offers an option

of USB Isocronous transfer via an option bit in the

EEPROM.

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• Programmable Receive Buffer Timeout

In the previous device, the receive buffer timeout

used to  ush remaining data from the receive

buffer was  xed at 16ms timeout. This timeout is

now programmable over USB in 1ms increments

from 1ms to 255ms, thus allowing the device to

be better optimised for protocols requiring faster

response times from short data packets.

• TXDEN Timing  x

TXDEN timing has now been  xed to remove the

external delay that was previously required for

RS485 applications at high baud rates. TXDEN

now works correctly during a transmit send-break

condition.

• Relaxed VCC Decoupling

The 2nd generation devices now incorporate a level

of on-chip VCC decoupling. Though this does

not eliminate the need for external decoupling

capacitors, it signi cantly improves the ease of pcb

design requirements to meet FCC,CE and other

EMI related speci cations.

• Improved PreScaler Granularity

The previous version of the Prescaler supported

division by ( n + 0 ), ( n + 0.125 ), ( n + 0.25 ) and

( n + 0.5 ) where n is an integer between 2 and

16,384 ( 214 ). To this we have added ( n + 0.375

), ( n + 0.625 ), ( n + 0.75 ) and ( n+ 0.875 ) which

can be used to improve the accuracy of some baud

rates and generate new baud rates which were

previously impossible ( especially with higher baud

rates ).

• Bit Bang Mode

The 2nd generation device has a new option

referred to as “Bit Bang” mode. In Bit Bang mode,

the eight UART interface control lines can be

switched between UART interface mode and an

8-bit Parallel IO port. Data packets can be sent

to the device and they will be sequentially sent to

the interface at a rate controlled by the prescaler

setting. As well as allowing the device to be used

stand-alone as a general purpose IO controller for

example controlling lights, relays and switches,

some other interesting possibilities exist. For

instance, it may be possible to connect the device

to an SRAM con gurable FPGA as supplied by

vendors such as Altera and Xilinx. The FPGA

device would normally be un-con gured ( i.e. have

no de ned function ) at power-up. Application

software on the PC could use Bit Bang Mode to

download con guration data to the FPGA which

would de ne it’s hardware function, then after

the FPGA device is con gured the FT232BM can

switch back into UART interface mode to allow

the programmed FPGA device to communicate

with the PC over USB. This approach allows a

customer to create a “generic” USB peripheral

who’s hardware function can be de ned under

control of the application software. The FPGA

based hardware can be easily upgraded or

totally changed simply by changing the FPGA

con guration data  le. Application notes, software

and development modules for this application area

will be available from FTDI and other 3rd parties.

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• PreScaler Divide By 1 Fix

The previous device had a problem when the

integer part of the divisor was set to 1. In the 2nd

generation device setting the prescaler value to 1

gives a baud rate of 2 million baud and setting it

to zero gives a baud rate of 3 million baud. Non-

integer division is not supported with divisor values

of 0 and 1.

• Less External Support Components

As well as eliminating the RCCLK RC network, and

for most applications the need for an external reset

circuit, we have also eliminated the requirement for

a 100k pull-up on EECS to select 6MHz operation.

When the FT232BM is being used without the

con guration EEPROM, EECS, EESK and

EEDATA can now be left n/c. For circuits requiring

a long reset time ( where the device is reset

externally using a reset generator i.c., or reset is

controlled by the IO port of a MCU, FPGA or ASIC

device ) an external transistor circuit is no longer

required as the 1k5 pull-up resistor on USB DP can

be wired to the RESETO# pin instead of to 3.3v.

Note : RESETO# drives out at 3.3v level, not at 5v

VCC level. This is the preferred con guration for

new designs. In some other con gurations, RSTO#

can be used to reset external logic / MCU circuitry.

• Extended EEROM Support

The previous generation of devices only supported

EEPROM of type 93C46 ( 128 x 16 bit ). The new

devices will also work with EEPROM type 93C56

( 256 x 16 bit ) and 93C66 ( 512 x 16 bit ). The

extra space is not used by the device, however it

is available for use by other external MCU / logic

whilst the FT232BM is being held in reset.

• USB 2.0 ( full speed option )

A new EEPROM based option allows the FT232BM

to return a USB 2.0 device descriptor as opposed

to USB 1.1. Note : The device would be a USB 2.0

Full Speed device ( 12Mb/s ) as opposed to a USB

2.0 High Speed device ( 480Mb/s ).

• Multiple Device Support without EEPROM

When no EEPROM ( or a blank or invalid

EEPROM ) is attached to the device, the FT232BM

no longer gives a serial number as part of it’s

USB descriptor. This allows multiple devices to

be simultaneously connected to the same PC.

However, we still highly recommend that EEPROM

is used, as without serial numbers a device can

only be identi ed by which hub port in the USB tree

it is connected to which can change if the end user

re-plugs the device into a different port.

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x8 Clock

Multiplier

UART

FIFO Controller

Serial Interface

Engine

( SIE )

USB

Protocol Engine

Baud Rate

Generator

UART

Dual Port RX

Buffer

384 Bytes

Dual Port TX

Buffer

128 bytes

3.3 Volt LDO

Regulator

USB

Transceiver

USB DPLL

6MHZ

Oscillator

48MHz

12MHzXTIN

XTOUT

USBDP

USBDM

3V3OUT

VCC

TXD

RXD

RTS# CTS#

DTR#

DSR# DCD# RI#

EEPROM Interface

TXDEN

PWREN#

PWRCTL

TXLED# RXLED#

EECS

EESK

EEDATA

SLEEP#

RESET#

TEST

GND

RESET

GENERATOR

RSTOUT#

3V3OUT

3.0 Block Diagram ( simpli ed )

3.1 Functional Block Descriptions

• 3.3V LDO Regulator

The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output

buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also

provides 3.3v power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and

the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3v nominal

at a current of not greater than 5mA could also draw it’s power from the 3V3OUT pin if required.

• USB Transceiver

The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The

output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single

ended receivers provide USB data in, SEO and USB Reset condition detection.

• USB DPLL

The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data

signals to the SIE block.

• 6MHz Oscillator

The 6MHz Oscillator cell generates a 6MHz reference clock input to the X8 Clock multiplier from an external

6MHz crystal or ceramic resonator.

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• x8 Clock Multiplier

The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for

the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz reference clock for

the USB DPPL and the Baud Rate Generator blocks.

• Serial Interface Engine ( SIE )

The Serial Interface Engine ( SIE ) block performs the Parallel to Serial and Serial to Parallel conversion of the

USB data. In accordance to the USB 1.1 speci cation, it performs bit stuf ng / un-stuf ng and CRC5 / CRC16

generation / checking on the USB data stream.

• USB Protocol Engine

The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the

low level USB protocol ( Chapter 9 ) requests generated by the USB host controller and the commands for

controlling the functional parameters of the UART.

• Dual Port TX Buffer ( 128 bytes )

Data from the USB data out endpoint is stored in the Dual Port TX buffer and removed from the buffer to the

UART transmit register under control of the UART FIFO controller.

• Dual Port RX Buffer ( 384 bytes )

Data from the UART receive register is stored in the Dual Port RX buffer prior to being removed by the SIE on a

USB request for data from the device data in endpoint.

• UART FIFO Controller

The UART FIFO controller handles the transfer of data between the Dual Port RX and TX buffers and the UART

transmit and receive registers.

• UART

The UART performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion of the data on

the RS232 ( RS422 and RS485 ) interface. Control signals supported by the UART include RTS, CTS, DSR ,

DTR, DCD and RI. The UART provides a transmitter enable control signal ( TXDEN ) to assist with interfacing

to RS485 transceivers. The UART supports RTS/CTS, DSR/DTR and X-On/X-Off handshaking options.

Handshaking, where required, is handled in hardware to ensure fast response times. The UART also supports

the RS232 BREAK setting and detection conditions.

• Baud Rate Generator

The Baud Rate Generator provides a x16 clock input to the UART from the 48MHz reference clock and consists

of a 14 bit prescaler and 3 register bits which provide  ne tuning of the baud rate ( used to divide by a number

plus a fraction ). This determines the Baud Rate of the UART which is programmable from 183 baud to 3 million

baud.

• RESET Generator

The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An

additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT232BM or the

FT232BM to reset other devices respectively. During reset, RSTOUT# is high-impedance otherwise it drives

out at the 3.3v provided by the onboard regulator. RSTOUT# can be used to control the 1k5 pull-up on USB

DP directly where delayed USB enumeration is required. It can also be used to reset other devices. RSTOUT#

will stay high-impedance for approximately 5ms after VCC has risen above 3.5v AND the device oscillator is

running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device

from external logic or an external reset generator i.c.

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• EEPROM Interface

Though the FT232BM will work without the optional EEPROM, an external 93C46 ( 93C56 or 93C66 ) EEPROM

can be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor

value of the FT232BM for OEM applications. The EEPROM is also required for applications where multiple

FT232BM’s are connected to a single PC as the drivers rely on a unique serial number for each device to bind

a unique virtual COM port to each individual device. Other parameters controlled by the EEPROM include

Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes.

The EEPROM should be a 16 bit wide con guration such as a MicroChip 93LC46B or equivalent capable of

a 1Mb/s clock rate at VCC = 4.4v to 5.25v. The EEPROM is programmable-on board over USB using a utility

available from FTDI’s web site ( http://www.ftdichip.com ). This allows a blank part to be soldered onto the PCB

and programmed as part of the manufacturing and test process.

If no EEPROM is connected ( or the EEPROM is blank ), the FT232BM will use it’s built-in default VID, PID

Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part

of the USB descriptor.

4.0 Device Pin-Out

Figure 1

Pin-Out (LQFP-32 Package )

EESK

EEDATA

VCC

RESET#

RSTOUT#

3V3OUT

USBDP

USBDM

GND

SLEEP#

RXLED#

TXLED#

PWRCTL

PWREN#

TXDEN

VCCIO

GND

RI#

DCD#

DSR#

DTR#

CTS#

RTS#

RXD

TXD

VCC

XTOUT

XTIN

AGND

AVCC

TEST

EECS

FTDI

FT232BM

XXYY

29179

3V3OUT

USBDP

USBDM

RSTOUT#

XTIN

XTOUT

RESET#

EECS

EESK

EEDATA

TEST

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

TXDEN

PWREN#

PWRCTL

TXLED#

RXLED#

SLEEP#

G N D

A G N D

A V V C

V C C

Figure 2

Pin-Out (Schematic Symbol )

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4.1 Signal Descriptions

Table 1 - FT232BM - PINOUT DESCRIPTION

UART INTERFACE GROUP

Pin# Signal Type Description

from suspend.

USB INTERFACE GROUP

Pin# Signal Type Description

EEPROM INTERFACE GROUP

Pin# Signal Type Description

VCC via a 10k resistor for correct operation. Tri-State during device reset.

POWER CONTROL GROUP

Pin# Signal Type Description

the PWREN# pin in this way.

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MISCELLANEOUS SIGNAL GROUP

Pin# Signal Type Description

VCC.

VCC > 3.5v and the internal clock starts up, then clamps it’s output to the 3.3v

XTOUT

POWER AND GND GROUP

Pin# Signal Type Description

to GND using a 33nF ceramic capacitor in close proximity to the device pin. It’s

this pin to power external 3.3v logic if required.

VCC

VCCIO

When interfacing with 3.3v external logic connect VCCIO to the 3.3v supply of

the external logic, otherwise connect to VCC to drive out at 5v CMOS level.

AVCC

AGND

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5.0 Package Outline

Figure 3 – 32 LD LQFP Package Dimensions

Pin # 1

0.25

1.60 MAX

12o +/- 1

1.4 +/- 0.05

0.2 Min

0.6 +/- 0.15

0.05 Min

0.15 Max

0.37 +/- 0.07

0.35 +/- 0.05

0.09 Min

0.2 Max

0.09 Min

0.16 Max

7 9

0.8

FT232BM

FTDI

XXYY

The FT232BM is supplied in a 32 LD LQFP package as standard. This package has a 7mm x 7mm body ( 9mm

x 9mm including leads ) with leads on a 0.8mm pitch. An alternative 5mm x 5mm leadless chip scale package is

available on special request for projects where package area is critical.

The above drawing shows the LQFP-32 package – all dimensions are in millimetres.

XXYY = Date Code ( XX = 2 digit year number, YY = 2 digit week number.

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6.0 Absolute Maximum Ratings

These are the absolute maximum ratings for the FT232BM device in accordance with the Absolute Maximum Rating System

(IEC 60134). Exceeding these may cause permanent damage to the device.

• Storage Temperature ……………………………………………………. –65oC to + 150oC

• Ambient Temperature ( Power Applied )……………………………….. 0oC to + 70oC

• VCC Supply Voltage ……………………………………………….…….. -0.5v to +6.00v

• DC Input Voltage - Inputs ……………………………………………….. -0.5v to VCC + 0.5v

• DC Input Voltage - High Impedance Bidirectionals …………………… -0.5v to VCC + 0.5v

• DC Output Current – Outputs …………………………………………… 24mA

• DC Output Current – Low Impedance Bidirectionals …………………. 24mA

• Power Dissipation ( VCC = 5.25v ) .……………………………………… 500mW

• Electrostatic Discharge Voltage ( I < 1uA ) ……………………………… +/- 2000v

• Latch Up Current ( Vi < 0 or Vi > Vcc ) ………………………………….. 100mA

6.1 D.C. Characteristics

DC Characteristics ( Ambient Temperature = 0 .. 70oC )

Operating Voltage and Current