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CD4021BC
8-Stage Static Shift Register
CD4021BC 8-Stage Static Shift Register
October 1987
Revised January 1999
General Description
The CD4021BC is an 8-stage parallel input/serial output
shift register. A parallel/serial cont rol input enabl es individual JAM inputs to each of 8 stages. Q outputs are available
from the sixth, seventh, and eighth stages. All outputs have
equal source and sink current capabilities and conform to
standard “B” series output drive.
When the parallel/serial control input is in the logical “0”
state, data is serially shifted into the register synchronously
with the positive transition of the clock. When the parallel/
serial control is in the logical “1” state, data is jammed into
each stage of the register asynchronously with the clock.
All inputs are protected against static discharge with diodes
to V
and VSS.
DD
Features
■ Wide supply voltage range: 3.0V to 15V
■ High noise immunity: 0.45 V
■ Low power TTL compatibility:
Fan out of 2 driving 74L or 1 driving 74LS
■ 5V–10V–15V parametric ratings
■ Symmetrical output characteristics
■ Maximum input leakage 1 µA at 15V over full tempera-
ture range
DD
(typ.)
Ordering Code:
Order Number Order Code Package Description
CD4021BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
CD4021BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Connection Diagram
Pin Assignments for DIP and SOIC
Truth Table
CL
(Note 1)
XX1000 0
XX1010 1
XX1101 0
XX1111 1
X = Don't care case
Note 1: Level change
Note 2: No change
Parallel/
Serial
Serial
Input
Control
00XX0Q
10XX1Q
X0XXQ1Q
PI 1 PI n
Q1
(Internal)
(Note 2)
Q
n
n−1
n−1
n
Top View
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Logic Diagram
CD4021BC
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Absolute Maximum Ratings(Note 3)
(Note 4)
Supply Voltage (VDD) −0.5V to +18V
Input Voltage (V
Storage Temperature Range (T
Power Dissipation (P
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
(Soldering, 10 seconds ) 260°C
) −0.5V to VDD +0.5V
IN
)
D
)
L
) −65°C to +150°C
S
Recommended Operating
Conditions
Supply Voltage (V
Input Voltage (V
Operating Temperature Range (TA)
CD4021BCN −40°C to +85°C
Note 3: “Absolute Maximum Rat ings” are tho se values beyond which the
safety of the device cannot be guaranteed. E x c ept for “ Operating Temperature Range” they are not mea nt to imply that the devices sh ould be operated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device o peration.
= 0V unless otherw is e s pecified.
Note 4: V
SS
(Note 4)
) 3V to 15V
DD
) 0 to V
IN
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
I
Quiescent Device VDD = 5V, VIN = VDD or V
DD
Current VDD = 10V, VIN = VDD or V
V
LOW Level VDD = 5V 0.05 0 0.05 0.05 V
OL
Output Voltage VDD = 10V |IO| < 1 µA 0.05 0 0.05 0.05 V
V
HIGH Level VDD = 5V 4.95 4.95 5 4.95 V
OH
Output Voltage VDD = 10V |IO|< 1 µA 9.95 9.95 10 9.95 V
V
LOW Level VDD = 5V, VO = 0.5V or 4.5V 1.5 2 1.5 1.5 V
IL
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 3.0 4 3.0 3.0 V
V
HIGH Level VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3 3.5 V
IH
Input Voltage VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 6 7.0 V
I
LOW Level Output VDD = 5V, VO = 0.4V 0.52 0.44 0.88 0.36 mA
OL
Current (Note 5) VDD = 10V, VO = 0.5V 1.3 1.1 2.2 0.90 mA
I
HIGH Level Output VDD = 5V, VO = 4.6V −0.52 −0.44 −0.88 −0.36 mA
OH
Current (Note 5) VDD = 10V, VO = 9.5V −1.3 −1.1 −2.2 −0.90 mA
I
Input Current VDD = 15V, VIN = 0V −0.3 −10−5−0.3 −1.0 µA
IN
Note 5: IOH and IOL are tested one output at a ti m e.
VDD = 15V, VIN = VDD or V
VDD = 15V 0.05 0 0.05 0.05 V
VDD = 15V 14.95 14.95 15 14.95 V
VDD = 15V, VO = 1.5V or 13.5V 4.0 6 4.0 4.0 V
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 9 11.0 V
VDD = 15V, VO = 1.5V 3.6 3.0 8 2.4 mA
VDD = 15V, VO = 13.5V −3.6 −3.0 −8 −2.4 mA
VDD = 15V, VIN = 15V 0.3 10−50.3 1.0 µA
SS
SS
SS
−40°C +25°C +85°C
Min Max Min Typ Max Min Max
20 0.1 20 150 µA
40 0.2 40 300 µA
80 0.3 80 600 µA
CD4021BC
DD
Units
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AC Electrical Charac teristics (Note 6)
T
= 25°C, input tr, tf = 20 ns, CL = 50 pF, R
A
Symbol Parameter Conditions Min Typ Max Units
t
PLH
CD4021BC
t
THL
f
CL
, t
, t
Propagation Delay Time VDD = 5V 240 350 ns
PHL
Transition Time VDD = 5V 100 200 ns
TLH
Maximum Clock VDD = 5V 2.5 3.5 MHz
Input Frequency VDD = 10V 5 10 MHz
t
W
Minimum Clock VDD = 5V 100 200 ns
Pulse Width VDD = 10V 50 100 ns
trCL, tfCL Clock Rise and VDD = 5V 15 µs
Fall Time (Note 6) VDD = 10V 15 µs
t
s
Minimum Set-Up Time
Serial Input VDD = 5V 60 120 ns
tH ≥ 200 ns VDD = 10V 40 80 ns
(Ref. to CL) VDD = 15V 30 60 ns
Parallel Inputs VDD = 5V 25 50 ns
tH ≥ 200 ns VDD = 10V 15 30 ns
(Ref. to P/S) VDD = 15V 10 20 ns
t
H
Minimum Hold Time VDD = 5V 0 ns
Serial In, Parallel In, ts ≥ 400 ns VDD = 10V 10 ns
Parallel/Serial Control VDD = 15V 15 ns
t
WH
Minimum P/S VDD = 5V 150 250 ns
Pulse Width VDD = 10V 75 125 ns
t
REM
Minimum P/S Removal VDD = 5V 100 200 ns
Time (Ref. to CL) VDD = 10V 50 100 ns
C
I
C
PD
Average Input Capacitance Any Input 5 7.5 pF
Power Dissipation 100 pF
Capacitance (Note 8)
Note 6: AC Parameters are guara nt eed by DC correlated testing.
Note 7: If more than one unit is cascaded t
mated capacitive load.
Note 8: C
AN-90.
determines the n o load AC power consumption of any CMOS device. For complete exp lanation, see 74C family characteristics application note
PD
CL should be made less than or equal to the fixed propagation delay of the output of the driving stage for the esti-
r
= 200 kΩ
L
VDD = 10V 100 175 ns
VDD = 15V 70 140 ns
VDD = 10V 50 100 ns
VDD = 15V 40 80 ns
VDD = 15V 8 16 MHz
VDD = 15V 40 80 ns
VDD = 15V 15 µs
VDD = 15V 50 100 ns
VDD = 15V 40 80 ns
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Typical Performance Characteristics
CD4021BC
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Physical Dimensions in ches (millimeters) unless otherwise noted
CD4021BC
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Package Number M16A
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
CD4021BC 8-Stage Static Shift Register
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
Package Number N16E
2. A critical component i n any compon ent of a life suppo r t
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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