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LS 166
Datasheet
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FREI LS 166 Datasheet

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Page 1
HD74LS166A
8-bit Shift Register
REJ03D0450-0400
Rev.4.00
May 10, 2006
The parallel-in or serial-in modes are established by the shift / load input.
When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data inputs are enabled and synchronous loading occurs on the next clock pulse, during parallel loading, serial data flow is inhibited.
This, of course, allows the system clock to be free running and the register can be stopped on command with the other clock input. The clock-inhibit input should be changed to the high level only while the clock input is high. A buffered, direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero.
Features
• Ordering Information
Part Name Package Type
HD74LS166AP DILP-16 pin
Pin Arrangement
Serial
Input
A
Parallel
Inputs
B
C
D
Clock
Inhibit
Clock
Package Code (Previous Code)
PRDP0016AE-B (DP-16FV)
2
3
4
5
6
7
Package Abbreviation
P —
161
V
CC
Shift/
15
Load Parallel
14
Input H
13
Output Q
12
G
11
F
10
E
Taping Abbreviation (Quantity)
H
Parallel Inputs
GND
Rev.4.00, May 10, 2006, page 1 of 7
8
(Top view)
9
Clear
Page 2
HD74LS166A
Function Table
Clear
Shift
Load
Clock
Inhibit
Inputs
Clock Serial
Parallel
A…H QA Q
Internal outputs
Output
B
QH
L X X X X X L L L
H X L L X X QA0 Q
Q
B0
H0
H L L ↑ X a…h a b h H H L ↑ H X H QAn Q H H L ↑ L X L QAn Q H X H ↑ X X QA0 Q
Q
B0
Gn Gn H0
Notes: 1. H; high level, L; low level, X; irreleva nt
2. ↑; transition from low to high level
3. a to h; the level of steady-state input at inputs A to H respectively
4. QA0 to QH0; the level of QA to QH, respectively, before the indicated steady-state input conditions were established.
5. Q
to QGn; the level of QA to QG, respectively, before the most recent ↑ transition of the clock.
An
Rev.4.00, May 10, 2006, page 2 of 7
Page 3
HD74LS166A
Block Diagram
Serial Input
Clear
Shift/Load
A
R
CK
S
Q
A
B
R
CK
S
Q
B
C
R
CK
S
Q
C
D
R
CK
S
Q
D
E
R
CK
S
Q
E
F
R
CK
S
Q
F
G
R
CK
H
Clock
R
CK
Clock Inhibit
Absolute Maximum Ratings
Item Symbol Ratings Unit
V
Supply voltage Input voltage Power dissipation Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
CC
V
IN
P
T
Tstg
7 V 7 V
400 mW
–65 to +150 °C
S
Q
G
S
Q
H
Rev.4.00, May 10, 2006, page 3 of 7
Page 4
HD74LS166A
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
V
T
ƒ
CC
IOH IOL
opr
clock
t
w
t
su
t
su
t
h
4.75 5.00 5.25 V — — –400 µA — — 8 mA
–20 25 75 °C
0 — 25 MHz 20 — — ns 30 — — ns 20 — — ns
0 — — ns
Supply voltage Output current Operating temperature
Clock frequency Clock and clear pulse width Mode control setup time Data setup time Hold time
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
Input voltage
Output voltage
Input current
Short-circuit output current
Supply current** ICC — 20 32 mA VCC = 5.25 V
Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With the outputs open, 4.5 V applied to the serial input and all other inputs except the clock grounded, I
measured after a momentary ground, then 4.5 V, is applied to clock.
VIH 2.0 — — V VIL — — 0.8 V
VOH 2.7 — — V
V
OL
— — 0.4 IOL = 4 mA — — 0.5
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
= –400 µA
I
OH
V
IOL = 8 mA
VCC = 4.75 V, VIH = 2 V,
= 0.8 V
V
IL
IIH — — 20 µA VCC = 5.25 V, VI = 2.7 V IIL — — –0.4 mA VCC = 5.25 V, VI = 0.4 V
— — 0.1 mA VCC = 5.25 V, VI = 7 V
I
I
IOS –20 — –100 mA VCC = 5.25 V
CC
is
Switching Characteristics
Item Symbol Inputs min. typ. max. Unit Condition
Maximum clock frequency ƒ
Propagation delay time
Rev.4.00, May 10, 2006, page 4 of 7
max
t
Clear — 19 30 ns
PHL
t
7 14 25 ns
PHL
t
PLH
(VCC = 5 V, Ta = 25°C)
25 35 — MHz
C
= 15 pF, RL = 2 kΩ
L
Clock
5 11 20 ns
Page 5
HD74LS166A
Testing Method
Test Circuit
Z
out
P.G.
= 50Ω
4.5V
Input
V
CC
Clear
Serial Input
Shift/Load
A
B
C
D
E
F
See Testing Table
G
H
Clock
Clock Inhibit
R
L
Output
Q
H
C
L
Notes: 1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Testing table
Data inputs Shift / Load Output Bit time
Data H 0 V QH t
Serial-in 4.5 V QH t
n + 1 n + 8
Rev.4.00, May 10, 2006, page 5 of 7
Page 6
HD74LS166A
Waveform
t
w (Clear)
Clear Input
Clock Input
Data Input
Output Q
Notes: 1. Input pulse; ≤ 15 ns, t
1.3V 1.3V
1.3V 1.3V
t
w (Clock)
t
PHL
H
1.3V 1.3V 1.3V
t
n
t
su
1.3V
≤ 6 ns, PRR = 1 MHz, duty cycle 50%
THL
Clock input; tw ≥ 20 ns Clear inpu; tw ≥ 20 ns, th = 10 ns, when testing ƒ
2. Propagation delay time (t
at t
with a functional test.
n + 8
PLH
and t
PHL
3. tn; bit time before clocking transition.
t
; bit time after one clocking transition.
n + 1
t
; bit time after eight clocking transition.
n + 8
tn + 1 tn + 1
t
n
1.3V 1.3V
t
h
t
t
su
h
1.3V 1.3V 1.3V
t
PLH
, vary the clock PRR.
max
) are measured at t
n + 1
t
. Proper shifting of data is verified
PHL
3V
0V
3V
0V
3V
0V
V
V
OH
OL
Typical Clear, Shift, Load, Inhibit, and Shift Sequences
Clock
Clock Inhibit
Clear
Serial Input Shift / Load
H L
H L
H L
H
H
Parallel
Inputs
Output Q
A
B
C
D
E
F
G
H
H
HHHHH
LLLL
Clear
Rev.4.00, May 10, 2006, page 6 of 7
Serial Shift Serial Shift
Load
Inhibit
Page 7
HD74LS166A
Package Dimensions
P-DIP16-6.3x19.2-2.54 1.05g
RENESAS CodeJEITA Package Code Previous Code
16 9
1 8
0.89
Z
e c
DP-16FVPRDP0016AE-B
D
b
3
b
p
MASS[Typ.]
E
A
1
A
L
θ
e
1
( Ni/Pd/Au plating )
Dimension in Millimeters
Reference
Symbol
e
1
D E A A
0.51
1
b
0.40 0.48
p
b
3
c
0.19 0.25 0.31
θ
e
2.29 2.54 2.79 Z L
2.54
MaxNomMin
7.62
19.2
20.32
6.3
7.4
5.06
0.56
1.30
0° 15°
1.12
Rev.4.00, May 10, 2006, page 7 of 7
Page 8
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