TWR-P1025 Tower Module
Hardware User Guide
TWR-P1025HUG
Rev. 0, 3/2012
How to Reach Us:
Home Page:
www.freescale.com
Web Support:
http://www.freescale.com/support
USA/Europe or Locations Not Listed:
Freescale Semiconductor, Inc.
Technical Information Center, EL516
2100 East Elliot Road
Tempe, Arizona 85284
+1-800-521-6274 or
+1-480-768-2130
www.freescale.com/support
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
www.freescale.com/support
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku
Tokyo 153-0064
Japan
0120 191014 or
+81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor China Ltd.
Exchange Building 23F
No. 118 Jianguo Road
Chaoyang District
Beijing 100022
China
+86 010 5879 8000
support.asia@freescale.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
Freescale and the Freescale logo are trademarks of Freescale
Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine is trademarks
of Freescale Semiconductor, Inc. All other product or service names are the
property of their respective owners.
© Freescale Semiconductor, Inc., 2012
Document Number: TWR-P1025HUG
Rev. 0, 3/2012
Contents
Paragraph
Number Title
Page
Number
Chapter 1
TWR-P1025 Overview
1.1 Introduction...................................................................................................................... 1-1
1.2 Contents ........................................................................................................................... 1-2
1.3 Features............................................................................................................................ 1-2
1.4 Getting Started ................................................................................................................. 1-4
1.5 Reference Documents ...................................................................................................... 1-4
Chapter 2
Power Requirements
2.1 Overview.......................................................................................................................... 2-1
Chapter 3
Hardware Description
3.1 P1025 Microprocessor ..................................................................................................... 3-1
3.2 Clocking........................................................................................................................... 3-2
3.3 System Power .................................................................................................................. 3-5
3.4 Debug Interface................................................................................................................ 3-5
3.5 Accelerometer.................................................................................................................. 3-5
3.6 Pushbutton and LEDs ...................................................................................................... 3-5
3.7 Ethernet............................................................................................................................ 3-5
3.8 USB.................................................................................................................................. 3-7
3.9 Micro Secure Digital Card Slot (micro SDHC)............................................................... 3-8
3.10 Local Bus Interface .......................................................................................................... 3-8
3.11 UART ............................................................................................................................... 3-8
3.12 I2C ................................................................................................................................... 3-9
3.13 SPI.................................................................................................................................... 3-9
3.14 DDR3 ............................................................................................................................... 3-9
3.15 GPIO & Interrupts ......................................................................................................... 3-12
4.1 P1025 Jumper Table......................................................................................................... 4-1
Freescale Semiconductor iii
Chapter 4
Switch Table
TWR-P1025 Hardware User Guide, Rev. 0
Contents
Paragraph
Number Title
Page
Number
Chapter 5
Input/Output Connectors and Pin Usage Table
5.1 LED Usage....................................................................................................................... 5-1
5.2 I/O Connectors and Pin Usage Table ............................................................................... 5-1
Chapter 6
Tower Elevator Connections
6.1 Overview.......................................................................................................................... 6-1
Appendix A
Revision History
A.1 Version Number 0 ............................................................................................................ 7-1
iv Freescale Semiconductor
TWR-P1025 Hardware User Guide, Rev. 0
Figures
Figure
Number Title
Page
Number
1-1 Freescale Tower System.......................................................................................................... 1-1
1-2 Callouts on front side of the TWR-P1025 .............................................................................. 1-3
1-3 Callouts on back side of the TWR-P1025............................................................................... 1-3
2-1 Power Supply Barrel Connector (J2) Polarity......................................................................... 2-1
3-1 TWR-P1025 Block Diagram................................................................................................... 3-1
3-2 P1025 Clocking Scheme ......................................................................................................... 3-3
3-3 eTSEC connection to AR8035 PHY....................................................................................... 3-6
3-4 NOR Local Bus Connection ................................................................................................... 3-8
Freescale Semiconductor v
TWR-P1025 Hardware User Guide, Rev. 0
Tables
Table
Number Title
Tables
Page
Number
2-1 Power Distribution Summary.................................................................................................. 2-1
3-1 P1025 CCB to SYSCLK Ratio Selection ............................................................................... 3-4
3-2 P1025 e500 Core 0 & 1 to CCB Clock Ratio Selection.......................................................... 3-4
3-3 P1025 DDR Clock PLL Ratio................................................................................................. 3-4
3-4 CPU Speed Selection .............................................................................................................. 3-5
3-5 eTSEC1 PHY Connectivity .................................................................................................... 3-6
3-6 eTSEC1 PHY Connectivity .................................................................................................... 3-7
3-7 I2C1 Connectivity ................................................................................................................... 3-9
3-8 I2C2 Connectivity ................................................................................................................... 3-9
3-9 DDR3 Signals ....................................................................................................................... 3-10
3-10 P1025 Interrupt Usage .......................................................................................................... 3-13
3-11 P1025 GPIO Usage ............................................................................................................... 3-13
4-1 P1025 Jumper Table................................................................................................................ 4-1
5-1 LED Usage Table .................................................................................................................... 5-1
5-2 I/O Connectors and Pin Usage Table ...................................................................................... 5-1
6-1 TWR-P1025 Primary Connector Pinout ................................................................................. 6-1
6-2 TWR-P1025 Primary Connector Pinout ................................................................................. 6-4
Freescale Semiconductor vii
TWR-P1025 Hardware User Guide, Rev. 0
Chapter 1
TWR-P1025 Overview
1.1 Introduction
The TWR-P1025 is a Tower Controller Module compatible with the Freescale Tower System. It can
function as a stand-alone, low-cost platform for the evaluation of the QorIQ P1xxx family of
microprocessor (MPU) devices. The TWR-P1025 features the QorIQ P1025 dual core processor based on
the PowerPC® e500 core architecture.
The TWR-P1025 is available as a stand-alone product or can be combined with the Tower Elevator
Modules (TWR-ELEV) and other Tower eco-system components to create development platforms for a
wide variety of applications. Figure 1-1 shows an overview of the Freescale Tower System.
Freescale Semiconductor 1
Figure 1-1. Freescale Tower System
TWR-P1025 Hardware User Guide, Rev. 0
TWR-P1025 Overview
1.2 Contents
The TWR-P1025 contents include:
• TWR-P1025 board
• Quick Start Guide
1.3 Features
The features of the TWR-P1025 Tower MPU Module:
• Tower compatible microprocessor module
• Dual core P1025 in a 561 TEPBGA package operating up to 533 MHz
• P1025 JTAG
•CPLD JTAG
• Three axis accelerometer (MMA8451Q)
• Two (2) user-controllable LEDs
• One (1) reset pushbutton switch
• Ten-way DIP Switch for configuration
• microSD card slot
• mini-PCIe slot
• Two (2) 10/100/1000Mbps Ethernet RJ45
• Two (2) USB2.0 Type A
• One (1) mini-USB TypeB dual UART
• 512 MB DDR3@667 MHz
• 64 MB Flash
• IEEE1588 pinned to header + DAC and VXCO (DNP option)
Figure 1-2 and Figure 1-3 show the TWR-P1025 with some of the key features.
2 Freescale Semiconductor
TWR-P1025 Hardware User Guide, Rev. 0
TWR-P1025 Overview
Figure 1-2. Callouts on front side of the TWR-P1025
Figure 1-3. Callouts on back side of the TWR-P1025
TWR-P1025 Hardware User Guide, Rev. 0
Freescale Semiconductor 3
TWR-P1025 Overview
1.4 Getting Started
Follow the printed Quick Start Guide or the interactive DVD contained in the TWR-P1025 box for
recommended get started steps.
1.5 Reference Documents
For more information on the QorIQ family, Tower System, and MPU Modules refer following documents:
• TWR-P1025-QSG: Quick Start Guide
• TWR-P1025-SCH: Schematics
• TWR-P1025-PWA: Design Package
• P1025 Reference Manual
4 Freescale Semiconductor
TWR-P1025 Hardware User Guide, Rev. 0
Chapter 2
Power Requirements
2.1 Overview
The TWR-P1025 is designed to be externally powered through barrel connector J2 from a 5V@5A DC
supply. The barrel connector is manufactured by SWITCHCRAFT with part number RAPC722X. The
mating plug should have an inner diameter of 2.1mm and outer diameter of 5.5mm. Figure 2-1 shows the
polarity of the barrel connector.
Figure 2-1. Power Supply Barrel Connector (J2) Polarity
The 5V input is used to generate all voltages on the board. Additionally when used with TWR elevators
and other TWR peripherals, the TWR-P1025 provides 5V and 3.3V supplies.
There are several expansion options on the board that allow external boards to interface to the
TWR-P1025, such as the mini PCIe connector, USB ports and elevator expansion. As these plug in cards
have variable power requirements as well as numerous population combinations the Power capability of
the different expansion interfaces and the core board are listed in Ta bl e 2-1 . Consideration of total available
power from the external supply should be considered when adding plug-in devices or using the elevator
expansion.
Main Board 5 2.5A
MiniPCIe 3.3 1A
USB Port 1 5 0.5
USB Port 2 5 0.5
ELEVATORS 5 0.5
Freescale Semiconductor 1
Table 2-1. Power Distribution Summary
Voltage (V) Current (A) Comment
1.5 0.5
3.3 0.5
TWR-P1025 Hardware User Guide, Rev. 0
Chapter 3
Hardware Description
The TWR-P1025 is a Tower Controller Module featuring the P1025-a dual core e500v2 based
microprocessor in a 561 TEPBGA package with a maximum core operating frequency of 533MHz. It is
intended to be used stand-alone or in the Freescale Tower System. Power is supplied through a 5V barrel
connector. Figure 3-1 shows a block diagram of the TWR-P1025. The following sections describe the
hardware in more detail.
3.1 P1025 Microprocessor
The TWR-P1025 module features the P1025, the key features are:
• 533 MHz maximum core operating frequency
• 561 TEPBGA, 23mm x 23mm, 1.0mm pitch package
Freescale Semiconductor 1
Figure 3-1. TWR-P1025 Block Diagram
TWR-P1025 Hardware User Guide, Rev. 0
Hardware Description
• Dual high-performance 32-bit cores, built on Power Architecture® technology:
— 32-bit e500v2 PowerPC core
— 36-bit physical addressing
— Double-precision floating-point support
— 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache for each core
— 400 MHz to 533 MHz clock frequency
• 256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory.
• Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
— TCP/IP acceleration, quality of service, and classification capabilities
— IEEE® 1588 support
— Lossless flow control
— MII, RMII, RGMII, SGMII
• High-speed interfaces supporting various multiplexing options:
— Four SerDes upto 2.5 GHz/lane multiplexed across controllers
— Two PCI Express interfaces
— Two SGMII interfaces
• High-speed USB controller (USB 2.0)
— Host and device support
— Enhanced host controller interface (EHCI)
— ULPI interface to PHY
• Enhanced secure digital host controller (SD/MMC)
• Enhanced serial peripheral interface (eSPI)
• Integrated security engine
— Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS
— XOR acceleration
• 32-bit DDR3 SDRAM memory controller with ECC support
• Programmable interrupt controller (PIC) compliant with OpenPIC standard
• One four-channel DMA controller
• Two I2C controllers, DUART, timers
• Enhanced local bus controller (eLBC)
• QUICC Engine block
3.2 Clocking
The P1025 takes a single input clock, SYSCLK, as its primary clock source for the e500 cores and all of
the devices and interfaces that operate synchronously with the core. As shown in Figure 3-1, the SYSCLK
input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB)
clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system
logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB
2 Freescale Semiconductor
TWR-P1025 Hardware User Guide, Rev. 0
Loading...