Freescale Semiconductor PowerQUICC MPC8313E User Manual

Freescale Semiconductor

User’s Guide

Document Number: MPC8313ERDBUG

Rev. 4, 02/2009

PowerQUICC™ MPC8313E Reference
Design Board (RDB)

The MPC8313E reference design board (RDB) is a system
featuring the PowerQUICC™ II Pro processor, which
includes a built-in security accelerator. This low-cost,
high-performance system solution consists of a printed
circuit board (PCB) assembly plus a s oft ware board support
package (BSP) distributed in a CD image. This BSP enables
the fastest possible time-to-market for development or
integration of applications including printer engines,
broadband gateways, no-new-wires home adapters/access
points, and home automation boxes.

This document describes the hardware features of the board
including specifications, block diagram, connectors,
interfaces, and hardware straps. It also describes the board
settings and physical connections needed to boot the
MPC8313E RDB. Finally, it considers the software shipped
with the platform.

When you finish reading this document, you should:

• Be familiar with the board layout

• Understand the default board configuration and your
board configuration options

• Know how to get started and boot the board

Contents

1. MPC8313E RDB Hardware . . . . . . . . . . . . . . . . . . . . 2

2. Board-Level Functions . . . . . . . . . . . . . . . . . . . . . . . . 7

3. Connectors, Jumpers, Switches, and LEDs . . . . . . . 19

4. Micro-Jumper/Resistor Options for eTSEC1 . . . . . . 27

5. MPC8313E RDB Board Configuration . . . . . . . . . . 38

6. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

7. MPC8313E RDB Software . . . . . . . . . . . . . . . . . . . . 46

8. Frequently Asked Questions (FAQs) . . . . . . . . . . . . 47

9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

WARNING

This is a class A product. In a domestic
environment this product may cause radio
interference, in which case the user may
be required to take adequate measures.

• Know about the software and further documentation
that supports the board

© Freescale Semiconductor, Inc., 2008. All rights reserved.

MPC8313E RDB Hardware

Use this manual in conjunction with the following documents:

• MPC8313E PowerQUICC™ II Pro Integrated Communications Processor Family Reference
Manual (MPC8313ERM)

• MPC8313E PowerQUICC II Pro Processor Hardw are Specifications (MPC8313EEC)

• “Hardware and Layout Design Considerations for DDR Memory Interfaces” (AN2582)

NOTE

The normal function of the product may be disturbed by strong
electromagnetic interference. If so, simply reset the product to resume
normal operation by following the instructions in the manual. If normal
function does not resume, use the product in another location.

This equipment has been tested and found to comply with the limits for a
Class A digital device, pursuant to Part 15 of the FCC Rules. These limits
are designed to provide reasonable protection against harmful interference
when the equipment is operated in a commercial environment. This
equipment generates, uses, and can radiate radio frequency energy. If it is
not installed and used in accordance with the instruction manual, it may
cause harmful interference to radio communications. Operation of this
equipment in a residential area is likely to cause harmful interference, in
which case the user will be require d to co rr ect the interference at his or her
own expense.

1 MPC8313E RDB Hardware

This section covers the features, block diagram, specifications, and mechanical data of the MPC8313E
RDB.

1.1 Features

The board features are as follows:

• CPU: Freescale MPC8313E running at 333/166 MHz; CPU/coherent system bus (CSB)

• Memory subsystem:
— 128 Mbyte unbuffered DDR2 SDRAM discrete devices
— 8 Mbyte flash single-chip memory
— 32 Mbyte NAND flash memory
— 256 Kbit M24256 serial EEPROM
— SD connector to interface with the SD memory card in SPI mode

• Interfaces:
— 10/100/1000 BaseT Ethernet ports:

™

– eTSEC1, RGMII: five 10/100/1000 BaseT RJ-45 interfaces using Vitesse

switch, or selectable one 10/100/1000 BaseT RJ-45 interface using Marvell
in REVC board

VSC7385 L2

™

88E1111 PHY

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

2 Freescale Semiconductor

MPC8313E RDB Hardware

– eTSEC2, selectable RGMII or SGMII: one 10/100/1000 BaseT RJ-45 interface using

Marvell 88E1111 PHY
— USB 2.0 port: high-speed host/device
— USB interface: selectable on-chip PHY or external ULPI PHY interface by SMSC USB3300

USB PHY

— PCI: 32-bit PCI interface running at up to 66 MHz

– One 32-bit 3.3 V PCI slot connected to PCI bus
– One 32-bit 3.3 V miniPCI slot connected to PCI bus

— Dual UAR T ports:

– DUART interface: supports two UARTs up to 115200 bps for console display

• Board connectors:
— LCD connectors by GPIO
— ATX power supply connector
— JTAG/COP for debugging

• IEEE Std. 1588™ signals for test and measurement

• Real-time clock and thermal sensor on I2C bus

• Programmable LEDs for debug use

• 6-layer PCB routing (4-layer signals, 2-layer power and ground)

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Freescale Semiconductor 3

MPC8313E RDB Hardware

MPC8313E

eTSEC1

Vitesse
L2 Switch

RGMII/

ULPI/

SMSC
USB PHY

IEEE1588

eTSEC2

Marvell
PHY

RGMII/SGMII

Clock, pulse, etc.

On-Chip
USB

Dual
UART

USB
mini-AB

USB
mini-AB

SPI

SD card

33/66 MHz

3.3 V 32-Bit
PCI Slot

3.3 V 32-Bit
miniPCI Slot

PCI Bus

System Clock
and USB Clock

128 Mbyte

DDR2

8 Mbyte NOR

Flash Memory

32-Bit DDR2
Bus

32 Mbyte NAND

Flash Memory

LEDs/status

Buffers

16-Bit Local
Bus

DAC for
IEEE1588
Clock (optional)

I2C Bus

Real-Time

Clock

Thermal

Sensor

GPIO

LCD
Connectors

JTAG/COP
Header

JTAG/COP

Power Su pp ly

with Low Power

Mode

Te st
Points

: selected by resistor options

---NOTE---

EEPROM

Marvell
PHY

RGMII/SGMII

Figure 1 shows the MPC8313E RDB block diagram.

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

4 Freescale Semiconductor

Figure 1. MPC8313E RDB Block Diagram

1.2 Specifications

Table 1 lists the specifications of the MPC8313E RDB.

Table 1. MPC8313E-RDB Specifications

Characteristics Specifications

Power requirements (without add-on card): Typical Maximum

12 V DC 0A 0 A

5.0 V DC1 mA1.5 A

Communication processor MPC8313E running at 266 MHz

MPC8313E RDB Hardware

Addressing: Total address range
Flash memory (local bus)
DDR2 SDRAM

Operating temperature 0

Storage temperature –25

Relative humidity 5% to 90% (noncondensing)

PCB dimensions:
Length
Width
Thickness

4 Gbyte (32 address lines)
8 Mbyte with one chip-select
128 Mbyte DDR2 SDRAM

o

C to 70o C (room temperature)

o

C to 85oC

6693 mil (REVA and REVB) or 7692 mil (REVC)
6693 mil
62 mil

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Freescale Semiconductor 5

MPC8313E RDB Hardware

1.3 Mechanical Data

Figure 2 shows the MPC8313E RDB REVAx and REVB dimensions (in mil and [mm]). The board

measures 170 mm × 170 mm (6693 mil × 6693 mil) for integration in a mini-ITX chassis.

Figure 2. Dimensions of the MPC8313E RDB (REVAx and REVB)

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

6 Freescale Semiconductor

Board-Level Functions

Figure 3 shows the MPC8313E RDB Rev C dimensions (in mil and [mm]). The board measures

195 mm × 170 mm (7692 mil × 6693 mil).

Figure 3. Dimensions of the MPC8313E RDB (REVC)

2 Board-Level Functions

The board-level functions are reset, external interrupts, clock distribution, DDR SDRAM controller, local
bus controller, I2C interfaces, SD memory card interface, USB interface, eTSEC1 10/100/1000 BaseT
interface, dual RS-232 ports, PCI bus, and COP/JTAG.

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Freescale Semiconductor 7

Board-Level Functions

MAX811

3.3 V

MR

Push Button

GND

HRESET from COP

SRESET

from COP

TRST

from COP

SRESET

to MPC8313E

TRST

to MPC8313E

PORESET

to MPC8313E

NOR FLASH

L2 Switch

MPC8313E

Reset config logic

Marvell PHY

2.1 Reset and Reset Configurations

The MPC8313E RDB reset module generates a single reset to the MPC8313E and other peripherals on the
board. The reset unit provides power-on reset, hard reset, and soft reset signals in compliance with the
MPC8313E hardware specification.

Figure 4 shows the reset circuitry. Note the following:

• Hard reset is generated either by the COP/JTAG port or the MPC8313E.

• Power-on reset is generated by the Maxim MAX811 device. When MR is deasserted and 3.3 V is
ready , the MAX81 1 internal timeout guarantees a minimum reset active time of 150 ms before
PORESET is deasserted. This circuitry guarantees a 150 ms PORESET pulse width after 3.3 V
reaches the right voltage level, which meets the specification of the PORESET input of
MPC8313E.

• COP/JTAG port reset provides convenient hard-reset capability for a COP/JT AG controller. The
RESET line is available at the COP/JT AG port connector. The COP/JTAG controller can directly
generate the hard-reset signal by asserting this line low.

• Push button reset interfaces using the MR signal with debounce capability to produce a manual
master reset of the RDB.

• Soft reset is generated by the COP/JT AG port. Assertion of SRESET causes the MPC8313E to
abort all current internal and external transactions and set most registers to their default values.

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

8 Freescale Semiconductor

Figure 4. Reset Circuitry of the MPC8313E

2.2 External Interrupts

IRQ0

IRQ2

IRQ3

IRQ4

MPC8313E

SD Card

IRQ1

PCI slot (AD15) INTA

Mini PCI (AD14) INTA and PCI slot (AD15) INTB

L2 Switch and ULPI external USB PHY (optional)

Marvell PHY, RTC (optional) and LM75 (optional)

Figure 5 shows the external interrupts to the MPC8313E.

Figure 5. MPC8313E Interrupts

The following are descriptions of the interrupt signals shown in Figure 5:

• All external interrupt signals are pulled up by 4.7 KΩ resistors.

•IRQ0 is connected to SD Card

Board-Level Functions

•IRQ1 is connected to PCI slot INTA.

•IRQ2 is connected to and shared by the PCI slot’s INTB and the mini PCI slot INTA.

•IRQ3 is connected to the L2 switch as well as to an external USB PHY (by an optional resistor).

•IRQ4 is connected to the Marvell GBE PHY as well as to RTC and LM75 (by an optional resistors).

Freescale Semiconductor 9

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Board-Level Functions

MPC8313E

LCLKx (NC)

local bus

PLL

DDR
PLL

PCI
DIV

66.666 MHz

OSC

CLKIN

33/66 MHz

33/66 MHz

Mini PCI Slot

PCI Slot

OCCR

2

PCI_SYNC_OUT

PCI_SYNC_IN

System

PLL

M66EN

33/66 MHz

CFG_CLKIN_DIV

NC

48 MHz
OSC

25 MHz
OSC

USB
CLKIN

L2 Switch

GBE PHY

GTX_CLK125

SD_REF_CLK

50 MHz OSC/
50 MHz VCXO

IEEE1588
TMR CLK

0

1

2

ULPI USB

GND GND

24 MHz

Crystal

PHY

Real-Time

GND GND

32.768 KHz

Crystal

Clock

DDR2 SDRAM

CLK

MCK

MCK#

133 MHz

PLL

125 MHz
LVD S
OSC

125MHz

2.3 Clock Distribution

Figure 6 and Table 2 show the clock distribution on the MPC8313E RDB.

Figure 6. MPC8313E-RDB Clock Scheme

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

10 Freescale Semiconductor

Board-Level Functions

Table 2. Clock Distribution

Clock Frequency Module Generated by Description

66.666 MHz MPC8313E CLKIN 66.666 MHz oscillator The MPC8313E uses CLKIN to generate the
PCI_SYNC_OUT clock signal, which is fed back
on the board through the PCI_SYNC_IN signal
to the internal system PLL. From the power-on
reset configuration, the CSB clock is generated
by the internal PLL and is fed to the e300 core
PLL for generating the e300 core clock. The
CFG_CLKIN_DIV
whether CLKIN or CLKIN/2 is driven on the
PCI_SYNC_OUT signal. The CFG_CLKIN_DIV
is tied to the M66EN input pin.

133 MHz DDR2 SDRAM MPC8313E The DDR memory controller is configured to use

the 2:1 mode CSB to DDR for the DDR interface
(DDR266). The local bus clock uses 1:1 local to
CSB clock, which is configured by hard reset
configuration or SPMR register.

configuration input selects

33/66 MHz PCI 32-bit slot and MiniPCI

slot

25 MHz L2 Switch and GBE PHY 25 MHz oscillator The 25 MHz oscillator provides the clock for the

125 MHz eTSEC clock GBE PHY with PLL

48 MHz USB clock 48 MHz oscillator 48 MHz is provided for on-chip USB PHY of

50 MHz IEEE1588 Clock (TMR_CLK) 50 MHz oscillator/50

24 MHz ULPI external USB PHY 24 MHz crystal 24 MHz crystal is used by the ULPI external

32.768 KHz Real-time clock 32.768 KHz crystal 32.768 KHz crystal is used by the real-time clock

MPC8313E The PCI module uses the PCI_SYNC_IN as its

clock source. The trace length of the
PCI_SYNC_IN to PCI_SYNC_OUT signal is
matched with all PCI clocks on the RDB.

L2 switch and the GBE PHY

The GTX_CLK125 and SERDES (SGMII) clocks

(REVC), or
125 MHz oscillators
(REVB), or
GBE PHY (REVAx)

MHz VCXO

are provided by external oscillators (or by GBE
PHY in REVAx and REVC boards).

MPC8313E

50 MHz is used by the IEEE 1588 module. It can
be an ordinary oscillator or VCXO controlled by
SPI DAC.

USB PHY

2.4 DDR2 SDRAM Controller

The MPC8313E processor uses DDR2 SDRAM as the system memory. The DDR2 interface uses the
SSTL2 driver/receiver and 1.8 V power. A Vref 1.8 V/2 is needed for all SSTL2 receivers in the DDR2
interface. For details on DDR2 timing design and termination, refer to the Freescale application note
entitled “Hardware and Layout Design Considerations for DDR Memory Interfaces” (AN2582). Signal
integrity test results show this design does not require terminating resistors (series resistor (R
termination resistor (R

)) for the discrete DDR2 devices used. DDR2 supports on-die termination; the

T

DDR2 chips and MPC8313E are connected directly. The interface is 1.8 V provided by an on-board

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Freescale Semiconductor 11

) and

S

Board-Level Functions

DDR2 Device (512 Mbit, 16-Bit)

MPC8313E

DDR2
Controller

DDR2 Device (512 Mbit, 16-Bit)

MCS0

MCK, MCK, MCKE

MRAS

, MCAS, MWE

MDM[0:3], MDQS[0:3]

A[0:14], BA[0:2]

MDQ[0:31]

ODT

VREF

1.8 V Reg

VREF

voltage regulator. VREF, which is half the interface voltage, or 0.9 V, is provided by a voltage divider of

1.8 V for voltage tracking and low cost. The MPC8313E provides a pair of clock pins, which are connected
and shared by the two DDR2 devices.

Figure 7 shows the DDR2 SDRAM controller connection.

2.5 Local Bus Controller

The MPC8313E local bus controller has a 26-bit LAD[0–15] and LA[16–25] address that consists of
16-bit data multiplex bus and control signals. The local bus speed is up to 133 MHz. T o interface with the
standard memory device, an address latch must provide the address signals. The LALE is used as the
latching signal. To reduce loading of the high speed local bus interface, a data buffer for all low-speed
devices is attached to the memory controller. The followings modules are connected to the local bus:

2.5.1 NOR Flash Memory

Through the general-purpose chip-select machine (GPCM), the MPC8313E RDB provides 8 Mbyte of
flash memory using a chip-select signal. The flash memory is used with the 16-bit port size. Figure 8

Figure 7. DDR2 SDRAM Connection

• 8 Mbyte NOR flash memory

• 32 Mbyte NAND flash memory

• LED/status buffer s

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

12 Freescale Semiconductor

Board-Level Functions

MPC8313E

eLBC
Controller

NOR
Flash 16-Bit

NOR_CS

*NOTE: NOR_CS

can be either CS0 or CS1

by DIP switch option, default is CS0

Latch

Buffer

LA[24:16]

A[0:8]

A[9:21]

LBA[15:3]

LAD[15:0]

DQ[0:15]

LBD[15:0]

WE

OE

WE0

GPL2

MPC8313E

eLBC
Controller

NAND
Flash 8-Bit

NAND_CS

*NOTE: NAND_CS

can be either CS0 or CS1

by DIP switch option; the default is CS1

CLE
ALE
WE
RE
R/B
WP

GPL0
GPL1

WE0
GPL2
GPL4
GPL3

LAD[0:7] IO[7:0]

*Buffer

LBD0-7

shows the hardware connections for the flash memory . The starting address for the 8 M byte flash memory
is 0xFE00_0000 to 0xFE7F_FFFF.

2.5.2 NAND Flash Memory

The MPC8313E has native support for NAND Flash memory through its NAND Flash control machine
(FCM). The MPC8313E RDB implements an 8-bit NAND Flash with 32 Mbyte in size. Figure 9 shows
the NAND Flash connection.

Freescale Semiconductor 13

Figure 8. NOR Flash Connection

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Figure 9. NAND Flash Connection

Board-Level Functions

MPC8313E

eLBC
Controller

WE0

GPL2

LAD[0:7]

Buffer

LCS3

LCX373

LCX245

8x LEDs

Write Buffer

Read Buffer

SD_INSERT
SD_PROTECT
RSVD0
BOOT0
RSVD1
M66EN
REV0
REV1

LBD[0:7]

OE

2.5.3 LED/Status Buffers

The MPC8313E RDB has an 8-bit read/write buffer . The read buffer returns information on M66EN, board
revision, boot device (NOR or NAND), and SD card status. The write buffer controls eight LEDs on the
board for status or debug indication. Figure 10 shows the hardware connection of the buffers.

2.6 I2C Interfaces

The MPC8313E has two I2C interfaces. On the MPC8313E RDB, I2C1 is used as master mode. It is
connected to the following three devices as shown in Figure 11.

It may also be connected to the DAC AD5301 at addres s 0x0C, whose optional nature is represented in

Figure 11 by the dashed line.

The connection of the I
the reset configuration word of the MPC8313E, as well as to store the configuration registers’ values and
user program if the MPC8313E boot sequencer is enabled. By default, the EEPROM is not used and the
hard reset configuration words are loaded from local bus flash memory. For details about how to program

Figure 10. LED/Status Buffers

• Serial EEPROM M24256 at address 0x50.

• Real-time clock DS1339U at address 0x68.

• Thermal sensor LM75 at address 0x48.

2

C bus is shown in Figure 11. The M24256 serial EEPROM can be used to store

14 Freescale Semiconductor

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Board-Level Functions

I2C1-SCL

I2C EEROM

M24256

MPC8313E

SCL

SDA

I2C1-SDA

I

2

C Address = 0x50

I2C RTC

DS1339U

SCL

SDA

I

2

C Address = 0x68

I2C Sensor

LM75

SCL

SDA

I

2

C Address = 0x48

3.3 V

I2C DAC (Optional)

AD5301

SCL

SDA

I

2

C Address = 0x0C

the reset configuration word value i n I2C EEPROM and the boot se quencer mode, refer to the MPC8313E
reference manual.

Figure 11. I2C Connection

2.7 SD Memory Card Interface

An SD memory card interface connects directly to the SPI bus of the MPC8313E. SD data mode and SDIO
mode are not supported. The SPI mode is the only SD operating mode supported by this connection. Hot
insertion and removal is not supported. See Figure 12 for the hardware connection.

For REVB boards, the SD card chip select signal is changed from GPIO31(SPISEL) to GPIO13(LA8)
because when using SPI as master mode, SPISEL
device select signal). In this case, another GPIO pin should be used. GPIO13 is implemented on this board
as an example.

cannot be set as GPIO (which is supposed to be used for

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4

Freescale Semiconductor 15

Board-Level Functions

MPC8313E

CS
DIN
DOUT
SCLK

INSERT

CONTACT

PROTECT

SD_CS
SPIMOSI

SPIMISO

SPICLK

SD_INSERT

SD_CONTACT

SD_PROTECT

LA8 (GPIO13)

SPIMOSI
SPIMISO

SPICLK

SD Memory Card Socket

Status Read
Buffer

Local Bus

MPC8313E

USB-DP
USB-DM

USB mini-AB

On-Chip
USB PHY

ULPI external
USB PHY Interface

USB3300
USB PHY

USB VBUS
Power Supply

USB mini-AB

USB-VBUS

Control

Control

**ULPI

IRQ3

**NOTE: Because ULPI is multiplexed with eTSEC1 RGMII, by default
on-chip PHY is used. A change of resistor option is needed to use
the external USB PHY interface.

OR

Power down before inserting or removing the SD memory card.

2.8 USB Interface

CAUTION

Figure 12. SD Memory Card Connection

MPC8313E supports a USB 2.0 high speed host/device i nterface through its on-chip USB PHY or external
ULPI USB PHY. The MPC8313E R DB s upports both options. By default, the on- chip USB PHY is used.

Figure 13 shows the USB connections.

Figure 13. USB Connections

16 Freescale Semiconductor

PowerQUICC™ MPC8313E Reference Design Board (RDB), Rev. 4