Freescale Semiconductor PowerPC e500 Core Reference Manual

PowerPC™ e500 Core

Family Reference Manual

Supports

e500v1
e500v2

E500CORERM

Rev. 1, 4/2005

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

Document Number: E500CORERM
Rev. 1, 4/2005

Part I—e500 Core I

Core Complex Overview 1

Register Model 2

Instruction Model 3

Execution Timing 4

Interrupts and Exceptions 5

Power Management 6

Performance Monitor 7

Debug Support 8

Part II—e500 Core Complex II

Timer Facilities 9

Auxiliary Processing Units (APUs) 10

L1 Caches 11

Memory Management Units 12

Core Complex Bus (CCB) 13

Appendix A—Programming Examples A

Appendix B—Guidelines for 32-Bit Book E B

Appendix C—Simplified Mnemonics for PowerPC Instructions C

Appendix D—Opcode Listings D

Appendix E—Revision History E

Index IND

I Part I—e500 Core

1 Core Complex Overview

2 Register Model

3 Instruction Model

41Execution Timing

5 Interrupts and Exceptions

6 Power Management

7 Performance Monitor

8 Debug Support

II Part II—e500 Core Complex

9 Timer Facilities

10 Auxiliary Processing Units (APUs)

11 L1 Caches

12 Memory Management Units

13 Core Complex Bus (CCB)

A Appendix A—Programming Examples

B Appendix B—Guidelines for 32-Bit Book E

C Appendix C—Simplified Mnemonics for PowerPC Instructions

D Appendix D—Opcode Listings

E Appendix E—Revision History

IND Index

Contents

Paragraph
Number Title

Cont ents

Page

Number

About This Book

Audience .......................................................................................................................xxxii

Organization.................................................................................................................. xxxii

Suggested Reading............................................ ........................................................... xxxiii

General Information............................................................................................. xxxiii

Related Documentation .......................... ................................................. ............ xxxiv

Conventions ................................................................................................................. xxxiv

Terminology Conventions..............................................................................................xxxv

Part I

e500 Core

Chapter 1

Core Complex Overview

1.1 Overview.......................................................................................................................... 1-1

1.1.1 Upward Compatibility .................................... .......... .......... .......... .......... .......... .......... .1-3

1.1.2 Core Complex Summary ............................................................................................. 1-3

1.2 e500 Processor and System Version Numbers ............................. ........................ ............ 1-5

1.3 Features............................................................................................................................1-5

1.3.1 e500v2 Differences.................................................................................................... 1-11

1.4 Inst ru ction Set ............. .............. ........ .............. ............... ........ .............. .............. ........ .... 1-12

1.5 Inst ru ction Flow.......... ........ .............. .............. ......... .............. .............. ........ .............. ....1-14

1.5.1 Initial Instruction Fetch . ............................................................................................. 1-14

1.5.2 Branch Detection and Prediction............................................................................... 1-14

1.5.3 e500 Execution Pipeline ............................................................................................ 1-16

1.6 Programming Model...................................................................................................... 1-18

1.7 On-Chip Cache Implementation.................................................................................... 1-20

1.8 Interrupts and Exception Handling................................................................................ 1-20

1.8.1 Ex c eption Ha n d l i n g ............ .............. ........ ............... ........ .............. .............. ........ ...... 1-20

1.8.2 Interrupt Classes ........................................................................................................ 1-21

1.8.3 Interrupt Types........................................................................................................... 1-21

1.8.4 Upper Bound on Interrupt Latencies ......................................................................... 1-22

1.8.5 Interrupt Registers...................................................................................................... 1-22

1.9 Memory Management.................................................................................................... 1-24

1.9.1 Address Translation................................................................................................... 1-26

1.9.2 M MU Assist Reg ist e rs (MAS0–MAS4 and MAS6–MAS 7 ).... .............................. ... 1-27

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1.9.3 Process I D Reg isters (PID0–PID2 )..... ............... .............. .............. ........ .............. ...... 1-28

1.9.4 TLB Cohere n cy ............. ........ .............. ............... ........ .............. .............. ........ ............ 1- 28

1.10 Memory Coherency ....................................................................................................... 1-29

1.10.1 Atomic Update Memory References ......................................................................... 1-29

1.10.2 Memory Access Ordering.......................................................................................... 1-29

1.10.3 Cache Control Instructions ........................................................................................ 1-29

1.10.4 Progra m m a b l e Pag e Charact e ri stics ............. ......... .............. ........ .............. .............. .. 1-30

1.11 Core Complex Bus (CCB)............................................................................................. 1-30

1.12 Performance Mon i t oring....... .............. .............. ............... .............. .............. ........ .......... 1-3 0

1.12.1 Global Control Register............................................................................................. 1-31

1.12.2 Performance Monitor Counter Registers....................................................... .......... .. 1-31

1.12.3 Local Control Registers ............................................................................................. 1-31

1.13 Legacy Support of PowerPC Architecture..................................................................... 1-32

1.13.1 Instruction Set Compatibility.....................................................................................1-32

1.13.1 .1 User Ins t ru c t i o n Set .. ........ .............. ............... ........ .............. .............. .............. ...... 1-32

1.13.1 .2 Supervi sor Inst ru ction Se t ....... .............. ............... .............. .............. .............. ........ 1-32

1.13.2 Memory Subsystem ................................................................................................... 1-33

1.13.3 Exce p t io n Ha n d l i n g .............. .............. ............... ........ .............. .............. ........ ............ 1- 3 3

1.13.4 Memory Management................................................................................................ 1-33

1.13.5 Reset........................................................................................................................... 1-34

1.13.6 Little-Endian Mode....................................................................................................1-34

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Chapter 2

Register Model

2.1 Overview.......................................................................................................................... 2-1

2.2 e500 Register Model........................................................................................................ 2-2

2.2.1 Special-Purpose Registers (SPRs) ............................................................................... 2-5

2.3 Registers for Integer Operations ...................................................................................... 2-9

2.3.1 General-Purpose Registers (GPRs).............................................................................. 2-9

2.3.2 In t e g er Excep t ion Re g i ster (XER)................ ......... .............. .............. ........ .............. .... 2-9

2.4 Registers for Branch Operations...................................................................................... 2-9

2.4.1 Condition Register (CR).............................................................................................. 2-9

2.4.2 Li n k Re g i ster (LR)........ .............. ........ ............... ........ .............. .............. ........ ............ 2- 1 0

2.4.3 Count Register (CTR)................................................................................................2-10

2.5 Proce sso r Co n t ro l Regist e rs.... ........ ........ ............... .............. ........ .............. .............. ...... 2-10

2.5.1 Ma chine State Reg ister (M S R) ........... ........ ............... .............. ........ .............. ............ 2- 1 0

2.5.2 Processor ID Regis t e r (P IR) ................... ......... .............. .............. .............. ........ ........ 2-12

2.5.3 Processor Version Reg i ster (PVR)................ ......... .............. .............. ........ .............. .. 2-13

2.5.4 System Versi o n Re g i st er (SVR).... .............. ............... ........ .............. .............. ........ .... 2-1 3

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2.6 Timer Registers................. ........ .............. ........ ............... .............. ........ .............. ........ ....2-14

2.6.1 Time r Co n t ro l Re g i ster (TCR ).................... ......... .............. .............. ........ .............. .... 2-1 5

2.6.2 Timer Status Register (TSR)...................................................................................... 2-16

2.6.3 Time Ba se (TBU and TBL ) .................. ........ ............... .............. ........ .............. ........ .. 2-16

2.6.4 Decrementer Register (DEC)..................................................................................... 2-16

2.6.5 D e c r e m e n t e r A u t o -Reload Regist e r (D ECAR)............... ........................................... 2-16

2.6.6 Alternate Time Base Registers (ATBL and A TBU)................................................... 2-16

2.6.6.1 Alternate Time Base Upper (ATBU) ..................................................................... 2-17

2.7 Interrupt Registers..........................................................................................................2-17

2.7.1 Interrupt Registers Defined by Book E...................................................................... 2-18

2.7.1.1 Save/Rest o re Register 0/1 (SRR0 and SRR1) ......... ........ ........ .............. ........ ........ 2- 1 8

2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1).....................................2-18

2.7.1.3 Data Excep ti o n Ad d ress Regis t e r (DEAR).............. ........ .............. .............. ........ .. 2-18

2.7.1.4 Interrupt Vector Prefix Register (IVPR)................................................................ 2-19

2.7.1.5 Interrupt Vector Offset Registers (IVORs) ............................................................ 2-19

2.7.1.6 Exception Syndrome Register (ESR).................................................................... 2-20

2.7.2 e500-Specific Interrupt Registers.............................................................................. 2-22

2.7.2.1 Machine C h eck S a v e/Restore Reg i ster 0 (MCSRR0)...... .................... .................2-22

2.7.2.2 Machine C h eck S a v e/Restore Reg i ster 1 (MCSRR1)...... .................... .................2-22

2.7.2.3 Machine Check Address Register (MCAR) .......................................................... 2-22

2.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 2-23

2.8 Softwar e -Use SPRs ( SP RG 0 – SPRG7 and U SP RG0) ......... .............. ........ .............. ...... 2-2 4

2.9 Branch Target Buffer (BTB) Registers .......................................................................... 2-24

2.9.1 Branch Buffer Entry Address Register (BBEAR)..................................................... 2-25

2.9.2 B ranch Buff e r Targ e t A d d r e ss Register (B BTAR) ....... .......... ................................... 2-25

2.9.3 Branch Unit Control and Status Register (BUCSR) .................................................. 2-26

2.10 Hardware Implementation-Dependent Registers........................................................... 2-27

2.10.1 Hardwa r e Im p l e m e n t a t i o n -Dependent Register 0 (HI D 0 )...................... ...................2-27

2.10.2 Hardwa r e Im p l e m e n t a t i o n -Dependent Register 1 (HI D 1 )...................... ...................2-29

2.11 L1 Cache Configuration Registers................................................................................. 2-31

2.11.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 2-31

2.11.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 2-33

2.11.3 L1 Cache Co n fi g u ra t i o n Register 0 (L1CFG0) .................................... .....................2-34

2.11.4 L1 Cache Co n fi g u ra t i o n Register 1 (L1CFG1) .................................... .....................2-35

2.12 MMU Registers.............................................................................................................. 2-35

2.12.1 Proce ss I D Re g i st e rs (PID0– P ID 2 )..... ............... .............. .............. ........ .............. ...... 2-36

2.12.2 MMU Control and Sta t u s Register 0 (MMUCSR0)......................... ......................... 2-36

2.12.3 MMU Configuration Register (MMUCFG) .............................................................. 2-37

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2.12.4 TLB Configuration Registers (TLBnCFG) ..................... .............. ........ .............. ...... 2-37

2.12.4 .1 TLB0 Configurati o n Re g i st e r (TLB0CF G) ........... ........ .............. .............. ........ .... 2-38

2.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................2-39

2.12.5 MMU Assist Registers (MAS0–MAS4, MAS6–MAS7) .......................................... 2-39

2.12.5 .1 MAS Regist e r 0 (MA S 0 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-40

2.12.5 .2 MAS Regist e r 1 (MA S 1 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-41

2.12.5 .3 MAS Regist e r 2 (MA S 2 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-42

2.12.5 .4 MAS Regist e r 3 (MA S 3 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-43

2.12.5 .5 MAS Regist e r 4 (MA S 4 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-43

2.12.5 .6 MAS Regist e r 6 (MA S 6 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-44

2.12.5.7 MAS Register 7 (MAS7)—e500v2 Only.............................................................. 2-45

2.13 Debug Registers.............................................................................................................2-45

2.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................ 2-46

2.13.1.1 Debug Control Register 0 (DBCR0)...................................................................... 2-46

2.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 2-46

2.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 2-47

2.13.2 Debug Status Register (DBSR).................................................................................. 2-47

2.13.3 Instruction Address Compare Registers (IAC1–IAC4).............................................2-48

2.13.4 D a t a Ad d ress Compar e Reg isters (D A C1 – D AC2) ........ ........ ........ .............. ........ ...... 2-48

2.14 SPE and SPFP APU Registers ....................................................................................... 2-49

2.14.1 Signal Processing and Embedded Floating-Point Status and Control

Register (SPEFSCR).............................................................................................. 2-49

2.14.2 Accumulator (ACC)................................................................................................... 2-52

2.15 Perfor mance Moni t o r Re g i sters (PMRs) ..................... ........ .............. .............. ........ ...... 2-52

2.15.1 Global Co n tr o l Reg ister 0 (PM GC0 ) ...... ............... ........ .............. ........ .............. ........ 2-53

2.15.2 User Global Control Register 0 (UPMGC0).............................................................. 2-54

2.15.3 Local Control A Registers (PMLCa0–PMLCa3) ...................................................... 2-55

2.15.4 User Local Control A Registers (UPMLCa0–UPMLCa3)........................................2-56

2.15.5 Local Control B Registers (PMLCb0–PMLCb3)...................................................... 2-56

2.15.6 User Local Control B Registers (UPMLCb0–UPMLCb3)........................................ 2- 57

2.15.7 Performance Monitor Counter Registers (PMC0–PMC3)......................................... 2-57

2.15.8 User Performance Monitor Counter Registers (UPMC0–UPMC3) .......................... 2-58

2.16 Synchro n i zation Requ irement s for SPRs.. ........ ............... .............. ........ .............. .......... 2-58

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3.1 Operand Conventions ...................................................................................................... 3-1

3.1.1 Data Organization in Memory and Data Transfers......................................................3-1

3.1.2 Alignment and Misaligned Accesses........................................................................... 3-2

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Chapter 3

Instruction Model

Contents

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Number Title

3.1.3 e500 Floating-Point Implementation........................................................................... 3-2

3.1.4 Unsupported Book E Instructions................................................................................ 3-3

3.2 Instruction Set Su m m a r y .............. ........ ............... .............. ........ .............. ........ .............. .. 3-5

3.2.1 Classes of Instructions ................................................................................................. 3-6

3.2.2 Definition of Boundedly Undefined............................................................................ 3-6

3.2.3 Synchroni z ation Requ i rements. ........ ............... ........ .............. ........ .............. .............. .. 3-6

3.2.3.1 Synchronization Requirements for e500-Specific SPRs. ...................... .................. 3-8

3.2.3.2 Synchronization with tlbwe and tlbivax Instructions ...........................................3-10

3.2.3.3 Context Sync h ronizat i o n ........ ........ ............... .............. ........ .............. .............. ...... 3-11

3.2.3.4 Execution Synchronizati o n........... ........ ............... .............. ........ .............. .............. 3-11

3.2.3.5 Instruction-Related Interrupts................................................................................ 3-12

3.3 Instruction Set Ove r v iew .......... .............. ........ ............... .............. ........ .............. ............ 3- 1 3

3.3.1 Book E User-Level Instructions .................................... ............ ............ .............. ...... 3-13

3.3.1.1 Integer Instructi o n s ... .............. ..................... ........ .............. .............. .............. ........ 3-13

3.3.1.1 .1 In t e g er Arithm e t i c In struct ions ............. ............... ........ .............. .............. .......... 3-1 3

3.3.1.1 .2 In t e g er Compar e In structio n s ... ........ ............... .............. ........ .............. ........ ...... 3-15

3.3.1.1 .3 In t e g er Logical Instru c t i o n s...... ............... ........ .............. .............. ........ .............. 3-15

3.3.1.1 .4 In t e g er Rotate an d Sh i ft Instru ctions.. ............... ........ .............. ........ .............. .... 3-1 6

3.3.1.2 Load and Store In structi o n s .... .............. ............... .............. ........ .............. .............. 3-17

3.3.1.2.1 Self-Modifying Code......................................................................................... 3-17

3.3.1.2.2 Integer Load and Store Address Generation......................................................3-18

3.3.1.2 .3 In t e g er Load In st ruction s...... .............. ......... .............. .............. ........ .............. .... 3-2 0

3.3.1.2 .4 In t e g er Store Inst ru ctions.......... ............... .............. ........ .............. .............. ........ 3-21

3.3.1.2 .5 In t e g er Load and Stor e w i t h Byt e-Reverse Instru c t i o n s............ ........ .............. .. 3-22

3.3.1.2.6 Integer Load and Store Multiple Instructions.................................................... 3-22

3.3.1.3 Branch and Flow Control Instructions................................................................... 3-23

3.3.1.3.1 Conditional Branch Control............................................................................... 3-23

3.3.1.3 .2 B r a n c h In structi o n s..... .............. ............... .............. ........ .............. .............. ........ 3-24

3.3.1.3.3 Condition Register Logical Instructions............................................................ 3-25

3.3.1.3 .4 Trap Instruc t ion s. .............. .............. ............... .............. ........ .............. .............. .. 3-25

3.3.1.4 System Linkage Instruction ................................................................................... 3-26

3.3.1.5 Processor Co n trol Instruction s........ ............... ........ .............. .............. .............. ...... 3-26

3.3.1.5.1 Move to/from Condition Register Instructions..................................................3-26

3.3.1.5 .2 Mo v e t o / from Special-Purpo se Regist er Instru ct ions.... ........ ........ .............. ...... 3-26

3.3.1.6 Memory Synchronization Instructions .................................................................. 3-30

3.3.1.6.1 mbar (MO = 1). ........ .............. .............. ......... .............. .............. ........ .............. .. 3-31

3.3.1.7 Atomic Update Primitives Using lwarx and stwcx. .............................................. 3-32

3.3.1.7.1 Reservations....................................................................................................... 3-34

3.3.1.7 .2 Forward Pr o g ress...... ........ .............. ............... ........ .............. ........ .............. ........ 3-36

3.3.1.7 .3 R eservat i o n Lo ss D u e t o Gr a n u l arity .............. .............. ........ .............. .............. 3 -36

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3.3.1.8 Memory Control Instructions ................................................................................ 3-37

3.3.1.8.1 User-Level Cache Instructions .......................................................................... 3-37

3.3.2 Supervisor-Level Instructions.................................................................................... 3-39

3.3.2.1 System Linkage Instructions.................................................................................. 3-39

3.3.2.2 Supervisor-Level Memory Control Instructions.................................................... 3-40

3.3.2.2.1 Supervisor-Level Cache Instruction .................................................................. 3-40

3.3.2.2.2 Supervisor-Level TL B Ma n a g ement Instru ctions.................... .........................3-41

3.3.3 Recommended Simplified Mnemonics...................................................................... 3-42

3.3.4 Book E Instructions with Implementation- Specific Features.................................... 3-43

3.3.5 e500 Instructions........................................................................................................3-43

3.3.6 C o n t ex t Synchro n i za t i o n ............. .............. ......... .............. .............. ........ .............. ...... 3-44

3.4 Memory Access Alignment Support.............................................................................. 3-44

3.5 Using msync and mbar to Orde r Me m o ry Accesses..... ........................................ .......3-45

3.5.1 Lo c k Ac q u i sition an d Im p o rt Barriers........ ......... .............. ........ .............. ........ .......... 3-45

3.5.1.1 Acquire Lock and Import Shared Memory............................................................ 3-45

3.5.1.2 Obtain Pointer and Import Shared Memory .......................................................... 3-45

3.5.1.3 Lock Release and Export Barriers......................................................................... 3-46

3.5.1.3.1 Export Shared Memory and Release Lock........................................................ 3-46

3.5.1.3.2 Export Shared Memory and Release Lock using mbar (MO = 0).................... 3-47

3.5.2 Safe Fetch ..................................................................................................................3-47

3.6 Update In structi o n s ........... .................... ............... .............. .............. ........ .............. ........ 3-47

3.7 Memory Synchronization .............................................................................................. 3-48

3.8 EIS-Defined Instructions and APUs Implem ented on the e500 .. .............. .................... 3-48

3.8.1 SPE and Embedded Floating-Point APUs................................................................. 3-49

3.8.1.1 SPE Operands: Signed Fractions ........................................................................... 3-51

3.8.1.2 SPE Integer and Fractional Operations.................................................................. 3-52

3.8.1.3 SPE APU Instructions............................................................................................ 3-52

3.8.1.4 Embedded Fl o ating-Poin t A P U In st ructions........ .......... .......................................3-58

3.8.2 Integer Select (isel) APU.... .............. ........ ............... .............. ........ .............. .............. 3-60

3.8.3 Perform a n ce Mo n i t o r A PU... .............. ........ ............... .............. .............. ........ ............ 3-60

3.8.4 Cache Locking APU.................................................................................................. 3-61

3.8.5 Machine Check APU ................................................................................................. 3-63

3.9 e500-Specific Instructions ............................................................................................. 3-63

3.9.1 Branch Target Buffer (BTB) Locking Instructions.................................................... 3-63

3.10 Instruction Listing. .............. .............. ........ ............... .............. .............. ........ .............. .... 3-66

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Chapter 4

Execution Timing

4.1 Terminology and Conventions......................................................................................... 4-1

4.2 Instruction Timing Ov e rview.......... .............. ............... ........ .............. .............. ........ ........ 4-4

4.3 General Timing Considerations ..................................................................................... 4-10

4.3.1 General Instruction Flow ........................................................................................... 4-11

4.3.2 Instruction Fetch Timing Considerations................................................................... 4-12

4.3.2.1 L1 and L2 TLB Access Times............................................................................... 4-12

4.3.2.2 Interrup t s A ssociate d wit h In structi o n Fetchin g.............. ........ .............. .............. .. 4-12

4.3.2.3 Cache-Related Latency.......................................................................................... 4-13

4.3.3 Dispatch, Issue, and Completion Considerations ...................................................... 4-14

4.3.3.1 GPR and CR Rename Register Operation............................................................. 4-15

4.3.3.2 LR and CTR Shadow (Speculative) Registers....................................................... 4-15

4.3.3.3 Instructi o n S e ri alizat ion.................. ........ . ........ ........ .............. .............. .............. .... 4-1 5

4.3.4 Interrupt Latency........................................................................................................ 4-16

4.3.5 M emory Synchr o ni zation T i m in g Co n sideration s.................................... .................4-17

4.3.5.1 msync Instruction Timing Considerations ............................................................ 4-17

4.3.5.2 mbar Instruction Timing Con siderati o n s. ............... .............. ........ .............. .......... 4-17

4.4 Execution ....................................................................................................................... 4-18

4.4.1 B r a n ch U n i t Ex ecutio n ........ ........ .............. ............... ........ .............. .............. ........ ...... 4-18

4.4.1.1 Branch Ins t ru c t i o n s and Compl e t i o n ............... .............. .............. .............. ........ .... 4-1 8

4.4.1.2 BTB Branch Prediction and Resolution ................................................................ 4-20

4.4.1.3 BTB Operations..................................................................................................... 4-21

4.4.1.3.1 BTB Locking ..................................................................................................... 4-23

4.4.1.3.2 BTB Locking APU Programming Model..........................................................4-24

4.4.1.3.3 BTB Operati o n s Con trolled by BU CS R......................................... ...................4-24

4.4.1.3.4 BTB Special Cases—Phantom Branches and Multiple Matches...................... 4-25

4.4.2 Load/Store Unit Execution ........................................................................................ 4-25

4.4.2.1 Load/Store U n it Qu e u e i n g Stru c t u res... ......... .............. .............. ........ .............. ...... 4-25

4.4.3 Simple and Multiple Unit Execution ......................................................................... 4-27

4.4.3.1 MU Divide Exe c u t i o n............. ........ ............... .............. ........ .............. .............. ...... 4-28

4.4.3.2 MU Floating-Point Ex e cu t ion... ........ ............... .............. ........ .............. .............. .... 4-2 9

4.4.4 Load/Store Execution ................................................................................................ 4-29

4.4.4.1 Effect of Operand Placement on Performance ...................................................... 4-30

4.5 Memory Performance Considerations ........................................................................... 4-30

4.6 Instruction La te n c y Summary... ........ .............. ............... ........ .............. .............. ........ .... 4-3 1

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4.7 Instruction Sch e d u l i n g Gui d e l i n e s.... ........ ............... ........ .............. .............. ........ .......... 4-44

4.7.1 Fetch/Branch Considerati o n s.... .............. ............... ........ .............. .............. ........ ........ 4-45

4.7.1.1 Dynamic Prediction versus No Branch Prediction................................................ 4-45

4.7.1.1 .1 Positio n -I n d e p en d e n t Co d e........... ............... .............. ........ .............. .............. .... 4-4 5

4.7.2 D i sp a t c h Un it Resour ce Req u irement s....... ......... .............. ........ .............. ........ .......... 4-45

4.7.2.1 Dispatch Groupings............................................................................................... 4-46

4.7.3 Issue Queu e Re source Re q u i rements.......... ............... ........ .............. ........ .............. .... 4-4 6

4.7.3.1 General Is su e Q u eu e (G I Q ) ...... ........ ............... .............. ........ .............. .............. .... 4-4 6

4.7.3.2 Branch Issu e Q u eu e (BIQ).............. ............... .............. .............. .............. .............. 4-46

4.7.4 Completion Unit Resource Requirements ................................................................. 4-46

4.7.4.1 Completion Groupings...........................................................................................4-47

4.7.5 Serialization Effe c t s.. .............. .............. ........ ............... .............. .............. ........ .......... 4-47

4.7.6 Ex e cution Un i t C o n si d e r a t i o n s ........... ............... ........ .............. .............. ........ ............ 4- 4 7

4.7.6.1 SU Considerations ................................................................................................. 4-47

4.7.6.2 MU Conside rat i o n s... .............. .............. ......... .............. .............. ........ .............. ...... 4-48

4.7.6.3 LSU Consider a t i o n s............ ........ .............. ............... ........ .............. .............. ........ .. 4-48

4.7.6.3.1 Load/Store Interaction ....................................................................................... 4-48

4.7.6.3 .2 Misalignm ent Effect s...... ........ . . . . . . . . . . . . . . ............... .............. .............. ........ .......... 4-4 9

4.7.6.3 .3 Lo a d Mi ss Pipelin e ............... ........ ............... .............. ........ .............. ........ .......... 4-50

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Chapter 5

Interrupts and Exceptions

5.1 Overview.......................................................................................................................... 5-1

5.2 e500 Interrupt Definitions................................................................................................ 5-2

5.2.1 Recoverability from Interrupts.....................................................................................5-4

5.3 Interrupt Registers............................................................................................................ 5-5

5.4 Exceptions........................................................................................................................ 5-8

5.5 Interrupt Classes .............................................................................................................. 5-9

5.5.1 R eq u i rements for System Reset Gene r a t i o n .... ........ .............. .............. ........ .............. 5-10

5.6 Interrupt Processing....................................................................................................... 5-10

5.7 Interrupt Definitions ...................................................................................................... 5-12

5.7.1 Critical Input Interrupt...............................................................................................5-13

5.7.2 Machine Check Interrupt ........................................................................................... 5-14

5.7.2.1 Core Complex Bus (CCB) a n d L1 Ca che Machine Che c k Erro rs........ .................5-16

5.7.2.2 Cache Parity Error Injection .................................................................................. 5-18

5.7.3 D a t a Stor ag e Interru p t............... .............. ............... .............. ........ .............. .............. .. 5-19

5.7.4 In structio n St o rag e Interr u p t............... ........ . ........ ........ .............. .............. .............. .... 5-2 0

5.7.5 External Input Interrupt ............................................................................................. 5-21

5.7.6 Alignment Interrupt ................................................................................................... 5-22

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5.7.7 Program Interrupt....................................................................................................... 5-24

5.7.8 System Call Interrupt................................................................................................. 5-25

5.7.9 Decrementer Interrupt................................................................................................ 5-25

5.7.10 Fixed-Interval Timer Interrupt................................................................................... 5-26

5.7.11 Watchdog Timer Interrupt.......................................................................................... 5-27

5.7.12 Data TLB Error Interrupt............ ........ ............... .............. ........ .............. ........ ............ 5-27

5.7.13 Instru ction TLB Error Inte r rupt........ ............... .............. .............. .............. .............. .. 5-29

5.7.14 Debug Interrupt.......................................................................................................... 5-30

5.7.15 EIS-Defined Int errupt s.......... .................... ............... .............. .............. .............. ........ 5-31

5.7.15.1 SPE/Embedded Floating-Point APU Unavailable Interrupt.................................. 5-31

5.7.15.2 Embedded Floating-Point Data Interrupt .............................................................. 5-32

5.7.15.3 Embedded Floating-Point Round Interrupt ...........................................................5-32

5.8 Perfor m a n c e Mo n itor Interrupt... .............. ............... .............. .............. .............. ............ 5- 3 3

5.9 Partial l y Ex e cuted Inst ruction s ......... .............. ............... ........ .............. .............. ........ .... 5-3 3

5.10 Interrupt Ordering and Masking .................................................................................... 5-35

5.10.1 Guidel i n e s fo r System Software ............... ............... .............. .............. .............. ........ 5-36

5.10.2 Interrupt Order...........................................................................................................5-37

5.11 Exception Priorities........................................................................................................5-37

5.11.1 e500 Exception Priorities........................................................................................... 5-39

5.12 e500 Interrupt Latency................................................................................................... 5-39

5.13 Guarded Load and Cache-Inhibited stwcx. Inst ruction s .... ........ .............. .............. ...... 5-40

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Chapter 6

Power Management

6.1 Overview.......................................................................................................................... 6-1

6.2 Power Ma n a g em e n t Si g n als.. .............. ........ ............... .............. ........ .............. ........ .......... 6-1

6.3 Core and Integrated Device Power Management States.................................................. 6-2

6.4 Power Ma n a g em e n t C o n t ro l Bi t s........ .............. ......... .............. .............. ........ .............. .... 6-3

6.4.1 Software Considerations for Power Management.......................................................6-4

6.5 Power Ma n a g em e n t Pr o tocol.............. ........ ............... ........ .............. .............. ........ .......... 6-5

6.6 Interrupts and Power Management.................................................................................. 6-6

Chapter 7

Performance Monitor

7.1 Overview.......................................................................................................................... 7-1

7.2 Perfor m a n ce Mo n i t o r A PU Registe r s ........... ............... .............. ........ .............. .............. .. 7-2

7.2.1 G l o b a l Co n tr o l Re g i st e r 0 (PM G C0 ) ...... ............... ........ ........ .............. ........ .............. .. 7-4

7.2.2 User Global Control Register 0 (UPMGC0)................................................................ 7-5

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7.2.3 Local Control A Registers (PMLCa0–PMLCa3) ........................................................ 7-5

7.2.4 User Local Control A Registers (UPMLCa0–UPMLCa3)..........................................7-6

7.2.5 Local Control B Registers (PMLCb0–PMLCb3)........................................................ 7-6

7.2.6 User Local Control B Register s (UPMLCb0–UPMLCb3)..........................................7- 7

7.2.7 Performance Monitor Counter Registers (PMC0–PMC3)........................................... 7-8

7.2.8 User Performance Monitor Counter Registers (UPMC0–UPMC3) ............................ 7-9

7.3 Perfor m a n ce Mo n i t o r A PU Instruc t i o n s ........... ............... .............. ........ .............. ............ 7- 9

7.4 Perfor m a n c e Mo n itor Interrupt... .............. ............... .............. .............. .............. ............ 7- 1 0

7.5 Event Cou n t i n g ........... .............. ........ .............. ............... ........ .............. .............. ........ .... 7-10

7.5.1 Processor Context Configurability.............................................................................7-10

7.6 Examples........................................................................................................................ 7-11

7.6.1 Chaining Counters ..................................................................................................... 7-11

7.6.2 Thresholding .............................................................................................................. 7-12

7.7 Event Se l ec t i o n ................. ........ .............. ............... ........ .............. .............. ........ ............7-12

Chapter 8

Debug Support

8.1 Overview.......................................................................................................................... 8-1

8.2 Programming Model........................................................................................................ 8-1

8.2.1 R eg i ster Set............. ........ .............. .............. ............... ........ .............. .............. .............. 8-1

8.2.2 In structio n Set................. ........ .............. ............... ........ .............. .............. ........ ............8-2

8.2.3 Debug Interrupt Model ................................................................................................ 8-2

8.2.4 Deviations from the Book E Debug Model ................................................................. 8-3

8.2.5 Hardware Facilities............................................................... ........ .......... ........ .......... ...8-4

8.3 TAP Con t roller and Re g i st e r Model ............... ......... .............. .............. ........ .............. ...... 8-4

8.3.1 TAP Interface Signals ................................. ................. ...... ........ ........ ........ ........ ........ .. 8-5

8.4 Book E Debug Events...................................................................................................... 8-6

8.4.1 Instruction Address Compare Debug Event ................................................................ 8- 7

8.4.1.1 Instructio n A d d r e ss Compare Use r and Super v i so r Modes......... ........ .............. ...... 8-7

8.4.1.2 Effective Ad d re ss Mode . .............. ........ ............... .............. ........ .............. .............. .. 8-8

8.4.1.3 Instructio n A d d ress Compar e Mo d e......... ......... .............. ........ .............. ........ .......... 8-8

8.4.2 Data Address Compare Debug Event...................................... ........ ........ ........ ........ .... 8- 9

8.4.2.1 Data Address Compare Read/Write Enable.............................................................8-9

8.4.2.2 Data Address Compare User/Supervisor Mode.....................................................8-10

8.4.2.3 Effective Ad d re ss Mode . .............. ........ ............... .............. ........ .............. .............. 8-10

8.4.2.4 Data Addre ss Co m p a re (DAC) Mod e.................. .............. ........ .............. .............. 8 -10

8.4.3 Trap Debug Event.................................................................................... .................. 8-11

8.4.4 Branch Taken Debug Event....................................................................................... 8-12

8.4.5 Instruction Complete Debug Event............................................................................8-12

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8.4.6 Interrupt T a ken Debug Event.....................................................................................8-13

8.4.7 Return Debug Event................................................................................................... 8-13

8.4.8 Unconditional Debug Event....................................................................................... 8-14

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Part II

e500 Core Complex

Chapter 9

Timer Facilities

9.1 Timer Facil iti e s ..... ........ ........ .............. .............. ......... .............. .............. ........ .............. .... 9-1

9.2 Timer Registers................. ........ .............. ........ ............... .............. ........ .............. ........ ......9-2

9.3 The e500 Timer Implementation......................................................................................9- 3

9.3.1 Alternate Time Base APU ........................................................................................... 9-4

9.3.2 Perform a n ce Mo n i t o r Time Ba se Ev e n t ....... ............... .............. ........ .............. ............ 9- 4

Chapter 10

Auxiliary Processing Units (APUs)

10.1 Overview........................................................................................................................10-1

10.2 Branch Target Buffer (BTB) Locking APU................................................................... 10-2

10.2.1 BTB Locki n g A PU Programm ing Model............ .............. .............. ........ .............. .... 10- 2

10.2.1 .1 BTB Locki n g A PU Instruc t i o n s ..... ........ ............... .............. ........ .............. ............ 10 - 2

10.2.1 .2 BTB Locki n g A PU Reg ister s ................... ......... .............. ........ .............. .............. .. 10-3

10.3 Alternate Time Base APU.............................................................................................. 10-3

10.3.1 Programming Model.................................................................................................. 10-3

10.4 Double-Precision Floating-Point APU (e500 v2 Only)................................................. 10-4

10.4.1 Programming Model.................................................................................................. 10-4

10.4.2 Double-Precision Floating-Point APU Operations.................................................... 10-4

10.4.2.1 Operational Modes................................................................................................. 10-4

10.4.2.2 Floating-Point Data Formats.................................................................................. 10-5

10.4.2 .3 Overflo w an d U nderflow................ ............... ........ .............. .............. ........ ............ 10 -6

10.4.3 Instruction Descriptio n s.......... .............. ........ ............... .............. .............. ........ .......... 10-6

10.4.4 Embedded Floating-Point Results Summary........................................................... 10-22

10.4.5 Floating-Point Conversion Models..........................................................................10-22

10.4.5.1 Common Functions.............................................................................................. 10-22

10.4.5.2 Convert from Double-Precision Floating-Point to Integer Word

with Saturation................................................................................................. 10-23

10.4.5.3 Convert to Double-Precision Floating-Point from Integer Word

with Saturation................................................................................................. 10-25

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Chapter 11

L1 Caches

11.1 Overview........................................................................................................................11-1

11.1.1 Block Di ag ram.. ........ .............. .............. ........ ............... .............. ........ .............. .......... 11-3

11.1.1.1 Load/Store Unit (LSU) .......................................................................................... 11-3

11.1.1.1.1 Caching-Allowe d Lo a d s and the LSU............. .............. ........ .............. .............. 11-4

11.1.1.1.2 Store Queue ........ ........ .............. ............... ........ .............. .............. ........ .............. 11-4

11.1.1.1.3 L1 Load Miss Queue (L MQ ).... ............... .............. ........ .............. .............. ........ 11-4

11.1.1.1.4 Data Line Fill Buffer (D LFB)............... ............... .............. ........ .............. .......... 11-4

11.1.1.1.5 Data Write Buffe r ( D W B) ................ ............... ........ .............. ........ .............. ...... 11-5

11.1.1.2 Instru ction Un i t................. .................... ............... .............. ........ .............. .............. 11-5

11.1.1.3 Core Interface Unit ................................................................................................ 11-5

11.2 L1 Cache Organ i z at ion ... ........ ........ .............. ......... .............. .............. ........ .............. ...... 11-6

11.2.1 L1 Data Cach e Organizat i o n... ........ ........ ............... .............. ........ .............. .............. .. 11-6

11.2.2 L1 Instru ction Cache Organiza t i o n.................. .............. ........ .............. .............. ........ 11-7

11.2.3 L1 Cache Parity ...... .............. ........ .............. ............... ........ .............. .............. ........ .... 11-8

11.2.4 Cache Parity Error Injection...................................................................................... 11-9

11.3 Cache Coherency Support ............................................................................................. 11-9

11.3.1 Data Cache Coherency Model .................. ......... .............. ........ .............. ........ ............ 11-9

11.3.2 Instruction Cache Coherency Model ........................................................................11-11

11.3.3 Snoop Signaling............................................................ .............. .............. .............. . 11-12

11.3.4 WIMGE Settings and Effect on L1 Caches............................................................. 11-13

11.3.4.1 Write-Back Stores................................................................................................ 11-13

11.3.4.2 Write-Through Stores................. ............ ....................... .......... ............ .......... ...... 11-13

11.3.4.3 Caching -Inhibited Load s a n d Stor e s. ............... ........ .............. .............. ........ ........ 11-13

11.3.4.4 Misaligned Accesses and the Endian (E) Bit....................................................... 11-13

11.3.4.5 Speculative Accesses to Guarded Memory ......................................................... 11-13

11.3.5 Load/Store Operations ............................................................................................. 11-14

11.3.5.1 Perfo r med Loads an d Stor e s. ........ ............... .............. .............. ........ .............. ...... 11-14

11.3.5.2 Sequential Consistency of Memory Accesses..................................................... 11-15

11 .3.5.3 Enforcing Store Orderin g w i t h Re spect to Loads........................... .....................11-15

11.3.5.4 Atomic Memory References................................................................................ 11-15

11.4 L1 Cache Cont rol................ ........ .............. ........ ............... .............. ........ .............. ........ 11-16

11.4.1 Cache Control Instructions ...................................................................................... 11-16

11.4.2 L1 Instruction and Data Cache Enabling/Disabling ................................................ 11-18

11.4.3 L1 Instruction and Data Cache Flash Invalidation .................................................. 11-18

11.4.4 L1 Instruction and Data Cache Line Locking/Unlocking........................................ 11-19

11.4.4.1 Effects of Other Cache Instructions on Locked Lines......................................... 11-21

11.4.4.2 Flash Clearing of Lock Bits................................................................................. 11-21

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11.5 L1 Data Cach e Flushin g ....... .............. .............. ......... .............. .............. ........ .............. 11-22

11.6 L1 Cache Operation ............ .............. ........ ............... .............. ........ .............. .............. .. 11-22

11.6.1 Cache Mis s a n d Reload Operations.. ........ ............... .............. ........ .............. ........ .... 11-23

11.6.1.1 Data Cach e Fills.... ........ .............. ........ ............... .............. ........ .............. ........ ...... 11-23

11.6.1.2 Instruction Cache Fills.........................................................................................11-23

11.6.1.3 Cache Allocation on Misses ................................................................................ 11-24

11.6.1.4 Store Mis s Me rg i n g ........ .............. ........ ............... .............. ........ .............. ........ .... 11-24

11.6.1.5 Store Hit to a Data Cache Block Marked Shared ................................................ 11-24

11.6.1.6 Data Cach e Block Push O p e ration .................. ........ .............. ........ .............. ........ 11-24

11.6.2 L1 Cache Block Replacement.................................................................................. 11-25

11.6.2.1 PLRU Replacement ............................................................................................. 11-25

11.6.2.2 PLRU Bit Updates............................................................................................... 11-26

11.6.2.3 Cache Locking and PLRU................................................................................... 11-27

11.7 L2 Cache Support ........................................................................................................ 11-27

11.7.1 Invalid ating th e L2 Ca c h e a fter a Cache Tag Parity Error... .............. .................... .. 11-27

11.7.2 L2 Lockin g................ .............. .............. ............... ........ .............. .............. .............. .. 11-27

11.7.2.1 L2 Unlo ck ing.................. ........ .............. ............... ........ .............. .............. ........ .... 11-28

11.7.2.2 L1 Over l o c k........ .............. ........ .............. ............... ........ .............. .............. ........ .. 11-28

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Chapter 12

Memory Management Units

12.1 e500 MMU Overview....................................................................................................12-1

12.1.1 MMU Features........................................................................................................... 12-1

12.1.2 TLB Entr y Ma i n t e n an c e F e at u res..... ............... .............. ........ .............. .............. ........ 12-3

12.2 Effective-to-Real Address Translation........................................................................... 12-4

12.2.1 Virtual Addresses with Three PID Registers............................................................. 12-5

12.2.2 Variable-Sized Pages.................................................................................................. 12-6

12.2.3 Checkin g fo r TLB Entry Hit... ........ .............. ......... .............. .............. ........ .............. .. 12-7

12.2.4 Checking for Access Permissions.......................... ...... ...... ...... .... ...... ...... ...... ...... .... .. 12-7

12.3 Translation Lookaside Buffers (TLBs).......................................................................... 12-8

12.3.1 L1 TLB Arra y s...... ........ .............. .............. ......... .............. .............. ........ .............. ...... 12-9

12.3.2 L2 TLB Arra y s...... ........ .............. .............. ......... .............. .............. ........ .............. .... 12-11

12.3.2 .1 IPROT Inv a l i d a t i o n Pr o t e ction in TLB1 ........... .............. .............. ........ .............. 12-12

12.3.2.2 Replacement Algorithms for L2 MMU............................................................... 12-13

12.3.2.2.1 Round-Robin Replacement for TLB0—e500v1.......... .................... ................ 12- 14

12.3.2.2.2 Round-Robin Replacement for TLB0—e500v2.......... .................... ................ 12- 14

12.3.3 Consis t en c y Be t w ee n L1 an d L2 TLBs.. ......... ........ .............. .............. ........ ............ 12-15

12.3.4 L1 and L2 TLB Access Times................................................................................. 12-16

12.3.5 The G Bit (of W IMGE) .................. ........ ............... .............. ........ .............. .............. 1 2 -16

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12.3.6 TLB Entry Field Definitions.................................................................................... 12-17

12.4 TLB Instruction s—Implementati o n.............. ............... .............. .............. .............. ...... 12 -17

12.4.1 TLB Read Entry (tlbre) Inst ruction.... ........ ............... .............. ........ .............. .......... 12-1 8

12.4.1 .1 Reading En t ries from th e TLB1 Array.......... ........ .............. .............. .............. .... 12- 1 8

12.4.1 .2 Reading En t ries from th e TLB0 Array.......... ........ .............. .............. .............. .... 12- 1 8

12.4.2 TLB Write Entry (tlbwe) Instruction.... ............... .............. .............. .............. ........ .. 12-19

12.4.2 .1 Writing to the TLB1 Array ... .............. ............... ........ .............. .............. ........ ...... 12 -19

12.4.2 .2 Writing to the TLB0 Array ... .............. ............... ........ .............. .............. ........ ...... 12 -19

12.4.3 TLB Search (tlbsx) Instruction—Searching the TLB1 and TLB0 Arrays .............. 12-19

12.4.4 TLB Invalidate (tlbivax) Instructi o n .... ........ ............... .............. .............. ........ ........ 12-20

12.4.4.1 TLB Selection for tlbivax Instructio n ................. .............. .............. ........ ............ 12 -21

12.4.4.2 Invalidate All Address Encoding for tlbivax Instru c t i o n..... .......... .....................12-22

12.4.4.3 TLB Invalidate Broadcast Enabling .................................................................... 12-22

12.4.5 TLB Synchronize (tlbsync) Instruction................................................................... 12-22

12.5 TLB Entr y Ma i n t e n an c e— D etails ............ ............... .............. ........ .............. .............. .. 12-22

12.5.1 Automa t i c Updates—T LB Mi ss Excepti o n s ..... ........ .............. .............. ........ .......... 12-2 3

12.5.2 TLB Interrupt Rout i n e s... .............. .............. ......... .............. .............. ........ .............. .. 12-24

12.5.2 .1 Permission s Viola t i o n s (ISI, DSI) Interrupt Handlers....... ................................. 12-24

12.6 TLB States a ft er Reset ........ ........ .............. ............... ........ .............. .............. ........ ........ 12-24

12.7 Core Complex MMU Registers ................................................................................... 12-25

12.7.1 e500 MAS Registers................................................................................................ 12-26

12.7.1 .1 MAS Regist e r 7 (MA S 7 ) ...... .............. ............... ........ .............. ........ .............. ...... 12 -31

12.7.2 MAS Regist e r U p d a t e s ................... .............. ......... .............. ........ .............. ........ ...... 12 -32

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Chapter 13

Core Complex Bus (CCB)

13.1 Overview........................................................................................................................13-1

13.2 Signal Summary............................................................................................................. 13-2

13.3 Core Interface Behavior................................................................................................. 13-5

13.3.1 Parity Sp ecifica tion........... ........ .............. ............... ........ .............. .............. ........ ........ 13-5

13.3.2 msync Operation and the Bus.................................................................................... 13-6

13.3.3 mbar Operati o n and t h e B u s .... .............. ............... ........ .............. .............. ........ ........ 13-6

13.4 Address Streaming Mode............................................................................................... 13-7

13.5 L2 Cache Support . .............. ................................................................... ........................ 13-7

13.5.1 L2 Lockin g.......... .............. .............. ........ ............... .............. ........ .............. .............. .. 13-7

13.5.2 L2 Unloc k i n g .................. ........ .............. ............... ........ .............. .............. ........ .......... 13-8

13.5.3 L1 Overl o c k .................. .............. ........ ............... ........ .............. .............. ........ ............ 13-8

13.6 Reserv a t i o n Managemen t ............. ........ ............... .............. ........ .............. .............. ........ 13-8

13.7 Remote A t o m ic Status Monit o ring....... ........ ............... .............. ........ .............. .............. 1 3 -9

13.8 Proper Reporting of Bus Faults ..................................................................................... 13-9

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Contents

Paragraph
Number Title

Appendix A

Programming Examples

A.1 Synchronization ..............................................................................................................A-1

A.1.1 Synchronization Primitives......................................................................................... A-2

A.1.1.1 Fetch and No-op ..................................................................................................... A-2

A.1.1.2 Fetch and Store ....................................................................................................... A-3

A.1.1.3 Fetch and Add......................................................................................................... A-3

A.1.1.4 Fetch and AND....................................................................................................... A-3

A.1.1.5 Test and Set............... ........ .............. ............... ........ .............. ........ .............. .............A-4

A.1.1.6 Compare and Swap................................................................................................. A-4

A.1.1.7 Notes.......................................................................................................................A-4

A.1.2 Lock Acqui sition and R elease .............. ............... ........ .............. .............. ........ ........... A-5

A.1.3 List Insertion............................................................................................................... A-6

A.1.3.1 Notes.......................................................................................................................A-7

Appendix B

Guidelines for 32-Bit Book E

Page

Number

B.1 64-Bit–Specific Book E Instructions...............................................................................B-1

B.2 Registers on 32-Bit Book E Implementations .................................................................B-2

B.3 Addressing on 32-Bit Book E Implementations..............................................................B-2

B.4 TLB Fields on 32-bit Book E Implementations............................................................... B-2

B.5 32-Bit Book E Software Guidelines................. ...............................................................B-3

B.5.1 32-Bit Instruction Selection.........................................................................................B-3

B.5.2 32-Bit Addressing........................................................................................................B-3

Appendix C

Simplified Mnemonics for PowerPC Instructions

C.1 Overview..........................................................................................................................C-1

C.2 Sub tr a ct Simplified Mnem o n i cs ... ........ ............... ........ .............. ........ .............. ........ ........C-2

C.2.1 Su b tr a ct Immediat e. .............. .............. ........ ............... ........ .............. ........ .............. ......C-2

C.2.2 Subtract ........................................................................................................................C-2

C.3 Rotate and Shift Simplified Mnemonics..........................................................................C-2

C.3.1 Op erations o n Words ...... ........ .............. ........ ......... .............. ........ .............. ........ ..........C- 3

C.4 Bra n ch In structi o n Simplified Mnemon i c s..... ............... .............. ........ .............. ........ ......C-4

C.4.1 Key Facts about Simplified Branch Mnemonics ....................................... .............. ....C-5

C.4.2 Eliminating the BO Operand .......................................................................................C-5

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C.4.3 Incorporat ing the BO Bra n ch Pr e d i ction .... ............... ........ .............. ........ ........ ............ C-7

C.4.4 The BI Operan d —C R Bi t and F i e l d Re p resentati o n s.... ........ .............. ........ ........ ........C-8

C.4.4. 1 BI Ope ra n d In structio n En coding... ........ ......... .............. .............. ........ .............. ......C-8

C.4.4. 1 .1 Specify i n g a C R Bi t................ ........ ......... .............. ........ .............. ........ .............. ..C-9

C.4.4.1.2 The crS Op e rand .................... ........ ............... ........ .............. ........ .............. ........C-10

C.4.5 Simplified Mnemonics that Incorporate the BO Operand.........................................C-11

C.4.5.1 Examples that Eliminate the BO Operand.............................................................C-12

C.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO

and Replaces BI with crS).....................................................................................C-15

C.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions: Examples.........C-17

C.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions: Listings............C-17

C.5 Compare Word Simplified Mnemonics .........................................................................C-20

C.6 Condition Register Logical Simplified Mnemonics......................................................C-20

C.7 Trap Inst ru ctions Si m p l i fi e d Mn em o n ics .................... .............. ........ .............. ..............C-21

C.8 Simplified Mnemonics for Accessing SPRs. .... ..... .... .. .... .. .... .. .... .. .... .. .... .. .... .. .... .. .... .. ..C-23

C.9 Recommended Simplified Mnemonics..........................................................................C-24

C.9.1 No-Op (nop) ..............................................................................................................C-24

C.9.2 Load Immediate (li)...................................................................................................C-24

C.9.3 Load Address (la) ......................................................................................................C-24

C.9.4 Move Register (mr)...................................................................................................C-25

C.9.5 Complement Register (not) .......................................................................................C-25

C.9.6 Move to Condition Register (mtcr)...........................................................................C-25

C.10 EIS-Spe cific Simp l i fied Mnem o n i c s ...... ........ ............... ........ .............. ........ .............. ....C- 2 6

C.10.1 Integer Select (isel)....................................................................................................C-26

C.10.2 SPE Mnemonics.........................................................................................................C-26

C.11 Comprehensive List of Simplified Mnemonics .............................................................C-26

Page

Number

D.1 Instructions (Binary) by Mnemonic................................................................................ D-1

D.2 Instructions (Decimal and Hexadecimal) by Opcode................................................... D-22

D.3 Instructions by Form..................................................................................................... D-35

E.1 Major Changes From Revision 0 to Revision 1.............................................................. A-1

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Appendix D

Opcode Listings

Appendix E

Revision History

Index

Figures

Figure
Number Title

Figures

Page

Number

1-1 e500 Core Complex Block Diagram....................................................................................... 1-2

1-2 Vect o r an d Fl o a t i n g -Point AP U s...... .............. ............... .............. ........ .............. .............. ........ 1-6

1-3 Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 1-8

1-4 Thre e - St a g e Lo a d / St o r e Uni t ......... .............. ........ ............... .............. ........ .............. .............. ..1-9

1-5 Ins t ru ction Pipeline Flo w....... .............. .............. ......... .............. .............. ........ .............. ........ 1-16

1-6 GPR Issue Queu e (G IQ) .... ........ .............. ........ ............... .............. .............. .............. ........ .... 1-17

1-7 e500 Core Programming Model............................................................................................1-19

1-8 MMU Structure ..................................................................................................................... 1-25

1-9 Effec t i v e - to-Real Add r e ss Translation F low.. ........ ............... .............. ........ .............. ............ 1- 2 6

1-10 Effective-to-Real Address Translation Flow (e500v2) ......................................................... 1-27

2-1 e500 Register Model ............................................................................................................... 2-3

2-2 Mac h ine State Register (MS R) .................. .............. ......... .............. .............. ........ .............. .. 2-10

2-3 Proc essor Versi o n Reg i ster (PVR)............... ........ ............... .............. ........ .............. ........ ...... 2-13

2-4 System Version Reg ister (SV R)............... .............. ......... .............. .............. ........ .............. .... 2-1 3

2-5 Relationship of Timer Facilities to the Time Base................................................................ 2-14

2-6 Timer Control Register (TCR ) ..... ........ .............. ......... .............. ........ .............. ........ .............. 2-15

2-7 Alternate Time Base Register Lower (ATBL) ...................................................................... 2-17

2-8 Alternate Time Base Register Upper (ATBU) ...................................................................... 2-17

2-9 Interrupt Vector Offset Registers (IVORs) ........................................................................... 2-19

2-10 Exception Syndrome Register (ESR).................................................................................... 2-20

2-1 1 Ma ch ine Check Save/Restore Reg i ster 0 (MCSRR0).. ........................................ .................2-22

2-12 M a ch ine Check Save/Restore Reg i ster 1 (MCSRR1).. ........................................ .................2-22

2-13 Machine Check Address Register (MCAR).......................................................................... 2-22

2-14 Machine Check Syndrome Register (MCSR)....................................................................... 2-23

2-15 Branch Buffer Entry Address Register (BBEAR) ................................................................ 2-25

2-16 Branch Buffer Target Address Register (BBTAR)................................................................ 2-25

2-17 Bra n c h Un i t Co n t r o l and Status Register (B U CS R ) ............... .............. ........ .............. ........ .. 2-26

2-18 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-27

2-19 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-29

2-20 L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 2-31

2-21 L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 2-33

2-22 L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 2-34

2-23 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 2-35

2-24 Pro cess ID Reg i st e r s (PID0–P ID 2 ).... ........ ........ ............... ........ .............. .............. ........ ........ 2-36

2-25 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-36

2-26 MMU Configuration Register (MMUCFG) ......................................................................... 2-37

2-27 TL B Co n f i guration Re g i st e r 0 (TLB0CFG) .... ............... ........ ........ .............. ........ .............. .. 2-38

2-28 TL B Co n f i guration Re g i st e r 1 (TLB1CFG) .... ............... ........ ........ .............. ........ .............. .. 2-39

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Figures

Figure
Number Title

2-29 MAS Re g i st er 0 (MAS0) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-40

2-30 MAS Re g i st er 1 (MAS1) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-41

2-31 MAS Re g i st er 2 (MAS2) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-42

2-32 MAS Re g i st er 3 (MAS3) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-43

2-33 MAS Re g i st er 4 (MAS4) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-43

2-34 MAS Re g i st er 6 (MAS6) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-44

2-35 MAS Re g i st er 7 (MAS7) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-45

2-36 Debug Control Register 2 (DBCR2)..................................................................................... 2- 47

2-37 Debug Status Register (DBSR)............................................................................................. 2-48

2-38 Signal Processing and Embedded Floating-Point Status and Control

Regist e r (S P EFSCR) ......... ........ .............. ........ ............... ........ .............. .............. ........ ...... 2-50

2-39 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 2-53

2-40 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 2-55

2-41 Local Control B Registers (PMLCb0–PMLCb3)/

User Local Control B Registers (UPMLCb0–UPMLCb3) .............................................. 2-56

2-42 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................. 2-57

3-1 Register Indirect with Immediate Index Addressing for Integer Loads/Stores. .......... .......... 3- 18

3-2 Re g i ste r Indirect with In d e x A d d ressing for Integ er Loads/St o res....................................... 3-19

3-3 Register Indirect Addressing for Integer Loads/Stores.........................................................3-20

3-4 SPE and Floating-Point APU GPR Usage ............................................................................ 3-50

3-5 Integ er and Frac t i o n a l O p erations............ .............. ......... .............. .............. ........ .............. .... 3-52

4-1 Ins t ru ction Flow Pipeli n e Diagram Showing Pi p el ine Stages .................... .............. .............. 4-4

4-2 e500 Instruction Flow Diagram—Details............................................................................... 4-5

4-3 GPR Issue Queu e (G IQ) .... ........ .............. ........ ............... .............. .............. .............. ........ ...... 4-7

4-4 Execution Pipeline Stages and Events .................................................................................... 4-9

4-5 Execution Stag e s .... .............. ........ .............. .............. ......... .............. .............. ........ ................ 4-10

4-6 Branch Completion (LR/CTR Write-Back).......................................................................... 4-19

4-7 Updating Branch History ......................................................................................................4-20

4-8 Fetch Groups and Cache Line Alignment.... ............ ....................... .......... ............ .......... ...... 4-21

4-9 Fetch Group Addresses ......................................................................................................... 4-22

4-10 Cache/Core Interface Unit Integration.................................................................................. 4-26

4-1 1 MU Div i d e By p ass Path (Showing an 11 -Cycle Divide )..................... .............................. ... 4-28

6-1 Core Power Management State Diagram................................................................................ 6-2

6-2 Exam p l e Co re Power Man agemen t Hand shakin g ........ ........ .............. .............. ........ .............. 6-5

7-1 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) .................................. 7-4

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Figures

Figure
Number Title

7-2 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) ................................................7-5

7-3 Local Control B Registers (PMLCb0–PMLCb3)/

User Local Control B Registers (UPMLCb0–UPMLCb3) ................................................ 7-7

7-4 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................... 7-8

8-1 TAP Controller with Supported Registers...............................................................................8-4

9-1 Relationship of Timer Facilities to Time Base........................................................................9-2

10-1 Vec t o r an d Fl o a t i n g -Point AP U s...... .............. ............... ........ .............. .............. .............. ...... 10 -2

10-2 Floating-Point Data Format .................................................................................................. 10-5

11-1 Cache/Core Interface Unit Integration.................................................................................. 11-3

11-2 L1 D at a Ca ch e Organizat i o n................ ........ ............... .............. ........ .............. .............. ........ 11-6

11-3 L1 In structi o n Cache Organiz ation ............ .............. ............... .............. ........ .............. .......... 11-7

11-4 PLRU Replacement Algorithm........................................................................................... 11-26

12-1 Effective-to-Real Address Translation Flow (e500v1) ......................................................... 12-4

12-2 Effective-to-Real Address Translation Flow (e500v2) ......................................................... 12-5

12-3 Virtual Address and TLB-Entry Compare Process............................................................... 12-7

12-4 Two-Level MMU Structure.......... ........ .............. ............... ........ .............. .............. ........ ........ 12-8

12-5 L1 MMU TLB Organization............................................................................................... 12-10

12-6 L2 MMU TLB Organization—e500v1............................................................................... 12-11

12-7 L2 MMU TLB Organization—e500v2............................................................................... 12-12

12-8 Round Robin Replacement for TLB0—e500v1 ................................................................. 12-14

12-9 Round Robin Replacement for TLB0—e500v2 ................................................................. 12-14

12-10 L1 MMU TLB Relationships with L2 TLBs ...................................................................... 12-15

12-11 MAS Regist e r 0 (MA S 0 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-26

12-12 MAS Regist e r 1 (MA S 1 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-27

12-13 MAS Regist e r 2 (MA S 2 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-28

12-14 MAS Regist e r 3 (MA S 3 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-29

12-15 MAS Regist e r 4 (MA S 4 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-30

12-16 MAS Regist e r 6 (MA S 6 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-31

12-17 MAS Regist e r 7 (MA S 7 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-31

13-1 CCB Interface Signals...........................................................................................................13-2

C-1 Branch Conditional (bc) Instructio n F o rm a t..................... .............. ........ .............. .............. ....C- 4

C-2 BO Field (Bits 6–10 of the Instruction Encoding). .................................................................C-6

C-3 BI Field (Bits 11–14 of the Instruction Encoding)..................................................................C-9

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Figures

Figure
Number Title

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Tables

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Number Title

Tabl e s

Page

Number

1-1 Revi sion Leve l -t o - D e v i c e Marking Cross-Re ference..... ........ .............. .............. ........ ............ 1-5

1-2 Perf o rmance Mon itor APU In st ruction s ...... ........ ............... .............. ........ .............. .............. 1-12

1-3 Cache Locking APU Instructions ......................................................................................... 1-12

1-4 Scalar and Vector Embedded Floating-Point APU Instructions ...........................................1-13

1-5 BTB Lo c k i n g A PU Instruc t i o n s......... ........ .............. ............... ........ .............. ........ .............. .. 1-14

1-6 Interrupt Registers................................................................................................................. 1-22

1-7 Interrupt Vector Registers and Exception Conditions........................................................... 1-23

2-1 Book E Special-Purpose Registers (by SPR Abbreviation).................................................... 2-6

2-2 Im p l e m e n t a t i o n -S p e cific SPRs (by SP R Abbreviat io n ).......... .......... .....................................2-8

2-3 MSR F ield Descr iptions....... .............. ........ .............. ............... ........ .............. ........ .............. .. 2-11

2-4 PVR Field Descriptions ........................................................................................................ 2-13

2-5 TCR Implementation-Specific Field Descriptions................................................................ 2-15

2-6 ATBL Field Descriptions ......................................................................................................2-17

2-7 ATBU F ield Descr ipt ions............... .............. ........ ............... .............. ........ .............. ..............2-17

2-8 IVOR Assignments ............................................................................................................... 2-19

2-9 ESR F i e l d Des c riptions.. ........ .............. ........ ............... .............. ........ .............. .............. ........ 2-21

2-10 MCSR Field Descriptions.....................................................................................................2-23

2-11 BBE AR F i e l d Descriptio n s.. ........ .............. ........ ............... ........ .............. .............. ........ ........ 2-25

2-12 BBTAR Field Des criptions ...... ........ ........ .............. ......... .............. ........ .............. .............. .... 2-25

2-13 BUCSR Field Descriptions................................................................................................... 2-26

2-14 HID0 Field Descriptions ....................................................................................................... 2-27

2-15 HID1 Field Descriptions ....................................................................................................... 2-29

2-16 L1CSR0 Field Descriptions .................................................................................................. 2-32

2-17 L1CSR1 Field Descriptions .................................................................................................. 2-33

2-18 L1CFG0 Fiel d Descript ion s ........... ........ .............. ............... ........ .............. ........ .............. ...... 2-34

2-19 L1CFG1 Fiel d Descript ion s ........... ........ .............. ............... ........ .............. ........ .............. ...... 2-35

2-20 MM U CS R 0 Field Desc ri p t i o n s........ ........ .............. ............... ........ .............. .............. ........ .... 2-3 6

2-21 MMUCFG Field Descriptions .............................................................................................. 2-37

2-22 TL B0 CF G F i e l d Descriptio n s.. .............. ........ ............... ........ .............. ........ .............. ............ 2-38

2-23 TL B1 CF G F i e l d Descriptio n s.. ........ .............. ............... ........ .............. ........ .............. ........ .... 2-39

2-24 MAS0 Field Descriptions—MMU Rea d /Write and Replacement Control .................... .... .. 2- 40

2-25 MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 2-41

2-26 MAS2 Field Descriptions—EPN and Page Attributes .........................................................2-42

2-27 MAS3 Field Descriptions—RPN and Access Contr ol . .... .... .... .... .... .... .... .... .... .... .... .... .... .... 2-43

2-28 MAS4 Field Descriptions—Hardware Replacement Assist Configuration..........................2-44

2-29 MAS 6 Fi el d D e scriptio n s........... .............. ........ ............... .............. ........ .............. .............. .... 2-45

2-30 MAS 7 Fi el d D e scriptio n s— H i g h -Order RPN ......... ......... .............. .............. ........ .............. .. 2-45

2-31 DBCR0 Field Descriptions ................................................................................................... 2-46

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2-32 DBCR1 Implementation-Specific Field Descriptions...........................................................2-46

2-33 DBCR2 Implementation-Specific Field Descriptions...........................................................2-47

2-34 DBSR Implementation-Specific Field Descriptions............................................................. 2-48

2-35 SPEFSCR Field D e scripti o n s..... ........ .............. ............... ........ .............. .............. ........ .......... 2-50

2-36 Pe rforman ce Mo n i t o r Re g i sters—Supervisor Leve l................... ........ .............. .............. ...... 2-52

2-37 Performance Monitor Registers—User Level (Read-Only) .................................................2-53

2-38 PMG C0 Field Des criptions.. .............. ........ .............. ............... ........ .............. .............. ........ .. 2-54

2-39 PMLCa0–PMLCa3 Fiel d Des c riptions.. ........ ............... ........ .............. ........ .............. ........ .... 2-5 5

2-40 PMLCb0–PMLCb3 Field Descriptions ................................................................................2-56

2-41 PMC0–PMC3 Field Descriptions ......................................................................................... 2-57

2-42 Sy n c h ron ization Req u i rements for SPRs... ........ ......... .............. ........ .............. .............. ........ 2-58

3-1 Add ress Characteris t ics of Aligne d Ope r a n d s ..... ......... .............. ........ .............. .............. ........ 3-2

3-2 Unsupported Book E Instructions (32-Bit) .............................................................................3-4

3-3 Data Access Synchronization Requirements ............................ .... ...... .... ...... .... ...... .... ...... .... .. 3- 8

3-4 Synchronization Requirements for e500-Specific SPRs......................................................... 3-8

3-5 Ins t ruction Fe t c h an d /or Executi o n Syn chroniz at ion Requi rements... ........ .............. ........ ...... 3-9

3-6 Integ er Arithm e t i c In structi o n s .. .............. .............. ............... ........ .............. .............. ............ 3-14

3-7 Integ er 32-Bi t Compare Instructi o n s (L = 0) ......... ......... .............. .............. .............. ........ .... 3-1 5

3-8 Integ er Logical Instr u ct ions ... ........ ........ .............. ............... ........ .............. .............. ........ ...... 3-15

3-9 Integ er Rotate In structi o n s ..... .............. .............. ............... ........ .............. .............. ................ 3-16

3-10 Int e g er Shift In structio n s........ .............. .............. ............... ........ .............. .............. ................ 3-16

3-11 Int e g er Load In st ructio n s . .............. .............. ............... .............. .............. .............. ................ 3-20

3-12 Int e g er Store In st ru ctions ................. .................... ............... .............. .............. .............. ........3-21

3-13 Integer Load and Store with Byte-Reverse Instructions.......................................................3-22

3-14 Integer Load and Store Multiple Instructions....................................................................... 3-23

3-15 BO Bi t De sc r iptions ........... ........ .............. ........ ........ ............... ........ .............. ........ ................3-23

3-16 BO Op e rand Encod i n g s . ........ .............. ........ ............... ........ .............. .............. ........ ..............3-23

3-17 Br an c h In structi o n s ...... ........ ........ .............. .............. ............... ........ .............. .............. ..........3-24

3-18 Condition Register Logical Instructions ............................................................................... 3-25

3-19 Trap Ins t ru ctions .......... ........ .............. .............. ............... ........ .............. .............. .................. 3-25

3-20 System Linkage Instruction ..................................................................................................3-26

3-21 Move to/from Condition Register Instructions .....................................................................3-26

3-22 Move to/from Special-Purpose Register Instructions...........................................................3-26

3-23 Book E Special-Purpose Registers (by SPR Abbreviation).................................................. 3-27

3-24 I m p l e m e n t ation-Speci fic SPRs (by SPR Abb reviation ).......... ........................................ .....3-29

3-25 Memory Synchronization Instructions.................................................................................. 3-30

3-26 User-Level Cache Instructions.............................................................................................. 3-38

3-27 System Linkage Instructions—Supervisor-Level ................................................................. 3-40

3-28 Move to/from Machine State Register Instructions .............................................................. 3-40

3-29 Supervisor-Level Cache Management Instruction................................................................ 3-41

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3-30 TL B Man a g ement Instructi o n s .... ........ ........ ............... ........ .............. ........ .............. ........ ...... 3-41

3-31 Implementation-Specific Instructions Summary .................................................................. 3-43

3-32 e500-Specific Instructions (E xcept SPE and SPFP Instructions ).........................................3-43

3-33 Natural Alignment Boundaries for Extended Vector Instructions ........................................ 3-44

3-34 SPE APU Vector Multiply Instruction Mnemonic Structure ................................................3-52

3-35 Mnemonic Ext e n sions for Mu ltiply-A c cu mulate I n structi o n s...... .............. .............. ........ .... 3-5 3

3-36 SPE APU Vector In structio n s ........ .............. ........ ............... .............. .............. ........ .............. 3-53

3-37 Vector and Scalar Floating-Point APU Instructions ............................................................. 3-59

3-38 Int e g er Select APU Instru ction .................... ............... .............. .............. .............. .............. .. 3-60

3-39 Pe rforman ce Mo n i t o r A P U In st ruction s ...... ............... .............. ........ .............. .............. ........ 3-60

3-40 e500-Defined PMR Encodings ............................................................................................. 3-61

3-41 Cache Locking APU Instructions ......................................................................................... 3-61

3-42 Machine Check APU Instruction .......................................................................................... 3-63

3-43 Branch Target Buffer (BTB) Instructions ............................................................................. 3-63

3-44 List of Instructions ................................................................................................................ 3-66

4-1 Load a n d Stor e Q u eu e s .... ........ .............. ........ ............... .............. ........ .............. ........ ............ 4-26

4-2 The E ffec t o f O p erand Size o n Div i d e Latency....... ............... .............. ........ .............. .......... 4-27

4-3 Bran c h O p eration Executio n Lat e n cies........ ............... ........ .............. .............. ........ .............. 4-31

4-4 System Operation Ins t ru ction Execution Latencie s ............ .............. .............. ........ .............. 4-31

4-5 Condition Register Logical Execution Latencies.................................................................. 4-33

4-6 SU and MU PowerPC Instruction Execution Latencies ....................................................... 4-33

4-7 LSU In structi o n Latencie s . ........ .............. .............. ......... .............. .............. .............. ........ ....4-35

4-8 SPE and Embedded Floating-Point APU Instruction Latencies ...........................................4-38

4-9 Natural Alignment Boundaries for Extended Vector Instructions........................................4-49

4-10 Dat a Ca ch e Mi ss, L2 Cach e H i t Timing .............. ......... .............. .............. ........ .............. ...... 4-50

5-1 SPE APU Unavailable Interrupt Generation When MSR[SPE] = 0.......................................5-3

5-2 Interrupt Registers Defined by the PowerPC Architecture..................................................... 5-5

5-3 Exception Syndrome Register (ESR) Definition .................................................................... 5-6

5-4 Machine Check Syndrome Register (MCSR) Field Descriptions ..........................................5-7

5-5 Asynchronous and Synchronous Interrupts. ........................................................................... 5- 9

5-6 Interrupt and Ex c eption Types ..... ........ .............. ............... ........ .............. .............. ........ ........ 5-12

5-7 Critical Input Interrupt Register Settings..............................................................................5-14

5-8 e500 Machine Check Exception Sources................. ......................................... .................... 5- 15

5-9 Machine Check Interrupt Settings......................................................................................... 5-16

5-10 Pa ri t y Error Excep tion Sce n arios..... ........ .............. ............... .............. ........ .............. ............ 5-17

5-11 Data Storage Interrupt Exception Conditions .......... ................................. ................ ............ 5- 19

5-12 Dat a Stor a g e I n terrupt R eg i ster Setti n g s...... ............... ........ .............. ........ .............. .............. 5-20

5-13 Instruction Storage Interrupt Exception Conditions ............................................................. 5-20

5-14 Instruction Storage Interrupt Register Settings..................................................................... 5-21

5-15 External Input Interrupt Register Settings ............................................................................ 5-22

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5-16 Alignment Interrupt Register Settings .................................................................................. 5-23

5-17 Pro g ram Inter ru p t Ex c eption Con d i t ions............. ......... .............. .............. ........ .............. ...... 5-24

5-18 Pro g r a m In t e r ru p t Re g i ster Sett ing s....... ........ ............... ........ .............. .............. ........ ............ 5- 24

5-19 System Call Interrupt Register Settings................................................................................ 5-25

5-20 Dec r e m e n t e r In t e r ru p t Re g i ster Sett in g s.... ........ ......... .............. .............. ........ .............. ........ 5-25

5-21 Fixed-Interval Timer Interrupt Register Settings.................................................................. 5-26

5-22 Watchdog Timer Interrupt Register Settings......................................................................... 5-27

5-23 Dat a TLB Error Interrupt Ex ception Co n d i tions ..... ......... .............. .............. ........ .............. .. 5-27

5-24 Data TLB Error Interrupt Register Settings..........................................................................5-28

5-25 M MU A ssist Register Field Updates fo r TLB Error Inter ru p t s............... .. .......... .................5-28

5-26 Instruction TLB Error Interrupt Exception Conditions .........................................................5-29

5-27 Instructi o n TLB Error In t errupt Re g is ter Setti n g s .......... .............. .............. .............. ............ 5- 2 9

5-28 Debug Interrupt Register Settings......................................................................................... 5-30

5-29 SPE/Embedded Floating-Point APU Unavailable Interrupt Regi st er Settings.....................5-31

5-30 Embedded Floating-Point Data Interrupt Register Settings.................................................. 5-32

5-31 Embedded Floating-Point Round Interrupt Register Settings............................................... 5-33

5-32 Op erations to Avoid ............. ........ .............. .............. ......... .............. ........ .............. ................5-36

6-1 Power Management Signals of Core Complex....................................................................... 6-1

6-2 Core Power States ................................................................................................................... 6-3

6-3 Core Power Management Control Bits ................................................................................... 6-3

7-1 Perf o rmance Mon itor Registers–Supervisor Level..... ........ .............. ........ .............. .............. .. 7-2

7-2 Performance Monitor Registers–User Level (Read-Only).....................................................7-3

7-3 PMGC0 F ield Descr iptions.......... ........ .............. ......... .............. .............. ........ .............. ........ ..7-4

7-4 PML Ca 0 – P MLCa3 Fiel d Descriptio n s.. ........ ............... ........ ........ .............. ........ .............. ...... 7-6

7-5 PMLCb0–PMLCb3 Field Descriptions ..................................................................................7-7

7-6 PMC0–PMC3 Field Descriptions ........................................................................................... 7-8

7-7 Perf o rmance Mon itor APU In st ruction s ...... ........ ............... .............. ........ .............. ........ ........ 7-9

7-8 Proc essor States and PMLCa0–PM LCa3 Bit Set t ing s........ .............. ........ .............. ........ ...... 7-11

7-9 Event Types ........................................................................................................................... 7-13

7-10 Pe rforman ce Mo n i t o r Ev ent Selec t i o n............... ............... ........ .............. .............. .............. .. 7-13

8-1 Debug SPRs ................................................................................................... ............ ............. 8-1

8-2 Debug Interrupt Register Settings........................................................................................... 8-3

8-3 DBCR0 and DBSR Field Differences..................................................................................... 8-4

8-4 TAP/IEEE/JTAG Inte rface Si gnal Summary ........................ ...... ...... .... ...... ...... .... ...... ...... .... .. 8-5

8-5 JTAG Signal Details................................................................................................................8-6

8-6 Debug Events.......................................................................................................................... 8-7

8-7 Ins t ruction Ad d ress Compar e Mo d es....... ........ ............... ........ .............. .............. ........ ............ 8- 8

8-8 Data A d d ress Compar e Mo d es ........ ........ ........ ............... .............. ........ .............. ........ .......... 8-10

10-1 BT B Lo c k i n g A PU Instruc t i o n s......... ........ .............. ............... ........ .............. .............. ........ .. 10-2

11-1 Cache Line State Definitions .............................................................................................. 11-10

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11-2 L1 D at a Ca ch e Coherency State Transiti o n s.......... ............... ........ .............. .............. ........ .. 11-10

11-3 L1 In structi o n Cache Cohe rency State Trans i tions......... .............. .............. .............. ...........11-11

11-4 Data Cache Snoop Coherency State Transitions....................... .......... ........ .......... .......... .... 11-12

11-5 Instruction Cache Snoop Coherency State Transitions....................................................... 11-12

11-6 Cache Instruction Comparison............................................................................................ 11-16

11-7 Failed Cache Events............................................................................................................ 11-17

11-8 L1 PLRU Replacement Way Selection ............................................................................... 11-25

11-9 PLRU Bit Update Rules...................................................................................................... 11-26

12-1 TL B Ma i n t e n an ce Programming Mod e l .................. ............... ........ .............. .............. ........ .. 12-3

12-2 Page Sizes for L1VSPs and TLB1 (L2 MMU) on the e500 Core.........................................12-6

12-3 Index of TLBs .......................................................................................................................12-9

12-4 TL B En t ry Bit Defi n it i o n s for e500... .............. ........ ............... .............. .............. ........ ........ 12-17

12-5 tlbivax EA Bit Definitions.................................................................................................. 12-21

12-6 TLB1 Entry 0 Values after Reset ........................................................................................ 12-25

12-7 Registers Used for MMU Functions ................................................................................... 12-25

12-8 MAS0 Field Descriptions—MMU Read/Write and Replacement Control ........................ 12-26

12-9 MAS1 Field Descriptions—Descriptor Context and Configuration Control...................... 12-27

12-10 MAS2 Field Descriptions—EPN and Page Attributes ....................................................... 12-28

12-11 MAS3 Field Descriptions–RPN and Access Control ............... .... .... .... .... .... .... .... .... .... .... .. 12-29

12-12 MAS4 Field Descriptions—Hardware Replacement Assist Configuration ................ ........ 12-30

12-13 MAS6—TLB Search Context Register 0............................................................................ 12-31

12-14 MAS7 Fiel d De scripti o n s— High Ord er RPN ..... ......... ........ .............. ........ .............. .......... 12-3 1

12-15 MMU Assist Re g i ster Fiel d Upd ates ... .............. ......... .............. ........ .............. ........ ............ 12 - 3 2

13-1 Su mm ary of Sele c t ed In ternal Si g n a l s ..... .............. ............... .............. .............. ........ ............ 13 -2

C-1 Sub tr ac t Im mediate Simplified Mnemon i c s ........ ......... ........ .............. ........ .............. ........ ......C-2

C-2 Sub tr ac t Simplified Mnemon ics......... ........ .............. ......... .............. ........ .............. ........ ..........C-2

C-3 Word Rotate and Shift Simplified Mnemonics.......................................................................C-3

C-4 Bran c h In structi o n s ...... ........ .............. ........ .............. ............... .............. ........ .............. ............C-4

C-5 BO Bit En c o d i n g s .... ........ ........ .............. ........ ............... ........ .............. .............. ........ ..............C-6

C-6 BO Op erand Encod i n g s . .............. ........ .............. ......... .............. ........ .............. ........ .............. ..C-6

C-7 CR0 and CR1 Fields as Updated by Integer Instructions .......................................................C-9

C-8 BI O p e ra n d Set t ings for CR Field s for Branch Comparisons........ .......................................C-1 0

C-9 CR Fie l d Id en t i fi c ation Symbols........ ........ .............. ......... ........ .............. ........ ........ ..............C-11

C-10 Branch Sim p lified Mn em o n ics .. ........ .............. ........ ............... ........ .............. ........ .............. ..C-11

C-11 Branch In structi o n s .................... .............. ........ ............... .............. ........ .............. ..................C-12

C-12 Si mplifie d Mnemonic s for bc and bca without LR Update..................................................C-13

C-13 Si mplifie d Mnemonic s for bclr and bcctr without LR Update............................................C-13

C-14 Si mplifie d Mnemonic s for bcl and bcla with LR U p d at e .......... ........ .............. .............. ...... C-14

C-15 Si mplifie d Mnemonic s for bclrl and bcctrl with LR Upd ate...... ........................................ .C -1 4

C-16 Standard Coding for Branch Conditions...............................................................................C-15

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C-17 Branch Instructions and Simplified Mnemonics that Incorporate CR Conditions ...............C-16

C-18 Simpl i fi e d Mn emonics with Compariso n Con d i t i o n s...... .......... .............................. .............C-16

C-19 Simplified Mnemonics for bc and bca without Comparison Conditions or

LR Updating.....................................................................................................................C-17

C-20 Simplified Mnemonics for bclr and bcctr without Comparison Conditions

and LR Updating..............................................................................................................C-18

C-21 Simplified Mnemonics for bcl and bcla with Comparison Conditions

and LR Updating..............................................................................................................C-18

C-22 Simplified Mnemonics for bclrl and bcctrl with Comparison Conditions

and LR Updating..............................................................................................................C-19

C-23 Word Compare Simplified Mnemonics ................................................................................C-20

C-24 Condition Register Logical Simplified Mnemonics .............................................................C-20

C-25 Standard Codes for Trap Instructions....................................................................................C-21

C-26 Trap Simplif i e d Mn emonics ........ ........ .............. ......... .............. ........ .............. .............. ........C-22

C-27 TO Operand Bi t Encodin g ... .............. ........ .............. ......... .............. ........ .............. .............. ..C-23

C-28 Additional Simplified Mnemonics for Accessing SPRGs....................................................C-24

C-29 Simplified Mnemonics..........................................................................................................C-26

D-1 Instructions (Binary) by Mnemonic....................................................................................... D-1

D-2 Instr u ctions (Decim a l and Hexadecima l) b y Opc o d e................ .............................. ............D-22

D-3 Instructions (Binary) by Form.............................................................................................. D-35

E-1 Revision History .................................................................................................................... A-1

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