Freescale Semiconductor PowerPC e500 Core Reference Manual

PowerPC™ e500 Core

Family Reference Manual

Supports

e500v1
e500v2

E500CORERM

Rev. 1, 4/2005

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© Freescale Semiconductor, Inc. 2005. All rights reserved.

Document Number: E500CORERM
Rev. 1, 4/2005

Part I—e500 Core I

Core Complex Overview 1

Register Model 2

Instruction Model 3

Execution Timing 4

Interrupts and Exceptions 5

Power Management 6

Performance Monitor 7

Debug Support 8

Part II—e500 Core Complex II

Timer Facilities 9

Auxiliary Processing Units (APUs) 10

L1 Caches 11

Memory Management Units 12

Core Complex Bus (CCB) 13

Appendix A—Programming Examples A

Appendix B—Guidelines for 32-Bit Book E B

Appendix C—Simplified Mnemonics for PowerPC Instructions C

Appendix D—Opcode Listings D

Appendix E—Revision History E

Index IND

I Part I—e500 Core

1 Core Complex Overview

2 Register Model

3 Instruction Model

41Execution Timing

5 Interrupts and Exceptions

6 Power Management

7 Performance Monitor

8 Debug Support

II Part II—e500 Core Complex

9 Timer Facilities

10 Auxiliary Processing Units (APUs)

11 L1 Caches

12 Memory Management Units

13 Core Complex Bus (CCB)

A Appendix A—Programming Examples

B Appendix B—Guidelines for 32-Bit Book E

C Appendix C—Simplified Mnemonics for PowerPC Instructions

D Appendix D—Opcode Listings

E Appendix E—Revision History

IND Index

Contents

Paragraph
Number Title

Cont ents

Page

Number

About This Book

Audience .......................................................................................................................xxxii

Organization.................................................................................................................. xxxii

Suggested Reading............................................ ........................................................... xxxiii

General Information............................................................................................. xxxiii

Related Documentation .......................... ................................................. ............ xxxiv

Conventions ................................................................................................................. xxxiv

Terminology Conventions..............................................................................................xxxv

Part I

e500 Core

Chapter 1

Core Complex Overview

1.1 Overview.......................................................................................................................... 1-1

1.1.1 Upward Compatibility .................................... .......... .......... .......... .......... .......... .......... .1-3

1.1.2 Core Complex Summary ............................................................................................. 1-3

1.2 e500 Processor and System Version Numbers ............................. ........................ ............ 1-5

1.3 Features............................................................................................................................1-5

1.3.1 e500v2 Differences.................................................................................................... 1-11

1.4 Inst ru ction Set ............. .............. ........ .............. ............... ........ .............. .............. ........ .... 1-12

1.5 Inst ru ction Flow.......... ........ .............. .............. ......... .............. .............. ........ .............. ....1-14

1.5.1 Initial Instruction Fetch . ............................................................................................. 1-14

1.5.2 Branch Detection and Prediction............................................................................... 1-14

1.5.3 e500 Execution Pipeline ............................................................................................ 1-16

1.6 Programming Model...................................................................................................... 1-18

1.7 On-Chip Cache Implementation.................................................................................... 1-20

1.8 Interrupts and Exception Handling................................................................................ 1-20

1.8.1 Ex c eption Ha n d l i n g ............ .............. ........ ............... ........ .............. .............. ........ ...... 1-20

1.8.2 Interrupt Classes ........................................................................................................ 1-21

1.8.3 Interrupt Types........................................................................................................... 1-21

1.8.4 Upper Bound on Interrupt Latencies ......................................................................... 1-22

1.8.5 Interrupt Registers...................................................................................................... 1-22

1.9 Memory Management.................................................................................................... 1-24

1.9.1 Address Translation................................................................................................... 1-26

1.9.2 M MU Assist Reg ist e rs (MAS0–MAS4 and MAS6–MAS 7 ).... .............................. ... 1-27

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1.9.3 Process I D Reg isters (PID0–PID2 )..... ............... .............. .............. ........ .............. ...... 1-28

1.9.4 TLB Cohere n cy ............. ........ .............. ............... ........ .............. .............. ........ ............ 1- 28

1.10 Memory Coherency ....................................................................................................... 1-29

1.10.1 Atomic Update Memory References ......................................................................... 1-29

1.10.2 Memory Access Ordering.......................................................................................... 1-29

1.10.3 Cache Control Instructions ........................................................................................ 1-29

1.10.4 Progra m m a b l e Pag e Charact e ri stics ............. ......... .............. ........ .............. .............. .. 1-30

1.11 Core Complex Bus (CCB)............................................................................................. 1-30

1.12 Performance Mon i t oring....... .............. .............. ............... .............. .............. ........ .......... 1-3 0

1.12.1 Global Control Register............................................................................................. 1-31

1.12.2 Performance Monitor Counter Registers....................................................... .......... .. 1-31

1.12.3 Local Control Registers ............................................................................................. 1-31

1.13 Legacy Support of PowerPC Architecture..................................................................... 1-32

1.13.1 Instruction Set Compatibility.....................................................................................1-32

1.13.1 .1 User Ins t ru c t i o n Set .. ........ .............. ............... ........ .............. .............. .............. ...... 1-32

1.13.1 .2 Supervi sor Inst ru ction Se t ....... .............. ............... .............. .............. .............. ........ 1-32

1.13.2 Memory Subsystem ................................................................................................... 1-33

1.13.3 Exce p t io n Ha n d l i n g .............. .............. ............... ........ .............. .............. ........ ............ 1- 3 3

1.13.4 Memory Management................................................................................................ 1-33

1.13.5 Reset........................................................................................................................... 1-34

1.13.6 Little-Endian Mode....................................................................................................1-34

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Chapter 2

Register Model

2.1 Overview.......................................................................................................................... 2-1

2.2 e500 Register Model........................................................................................................ 2-2

2.2.1 Special-Purpose Registers (SPRs) ............................................................................... 2-5

2.3 Registers for Integer Operations ...................................................................................... 2-9

2.3.1 General-Purpose Registers (GPRs).............................................................................. 2-9

2.3.2 In t e g er Excep t ion Re g i ster (XER)................ ......... .............. .............. ........ .............. .... 2-9

2.4 Registers for Branch Operations...................................................................................... 2-9

2.4.1 Condition Register (CR).............................................................................................. 2-9

2.4.2 Li n k Re g i ster (LR)........ .............. ........ ............... ........ .............. .............. ........ ............ 2- 1 0

2.4.3 Count Register (CTR)................................................................................................2-10

2.5 Proce sso r Co n t ro l Regist e rs.... ........ ........ ............... .............. ........ .............. .............. ...... 2-10

2.5.1 Ma chine State Reg ister (M S R) ........... ........ ............... .............. ........ .............. ............ 2- 1 0

2.5.2 Processor ID Regis t e r (P IR) ................... ......... .............. .............. .............. ........ ........ 2-12

2.5.3 Processor Version Reg i ster (PVR)................ ......... .............. .............. ........ .............. .. 2-13

2.5.4 System Versi o n Re g i st er (SVR).... .............. ............... ........ .............. .............. ........ .... 2-1 3

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2.6 Timer Registers................. ........ .............. ........ ............... .............. ........ .............. ........ ....2-14

2.6.1 Time r Co n t ro l Re g i ster (TCR ).................... ......... .............. .............. ........ .............. .... 2-1 5

2.6.2 Timer Status Register (TSR)...................................................................................... 2-16

2.6.3 Time Ba se (TBU and TBL ) .................. ........ ............... .............. ........ .............. ........ .. 2-16

2.6.4 Decrementer Register (DEC)..................................................................................... 2-16

2.6.5 D e c r e m e n t e r A u t o -Reload Regist e r (D ECAR)............... ........................................... 2-16

2.6.6 Alternate Time Base Registers (ATBL and A TBU)................................................... 2-16

2.6.6.1 Alternate Time Base Upper (ATBU) ..................................................................... 2-17

2.7 Interrupt Registers..........................................................................................................2-17

2.7.1 Interrupt Registers Defined by Book E...................................................................... 2-18

2.7.1.1 Save/Rest o re Register 0/1 (SRR0 and SRR1) ......... ........ ........ .............. ........ ........ 2- 1 8

2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1).....................................2-18

2.7.1.3 Data Excep ti o n Ad d ress Regis t e r (DEAR).............. ........ .............. .............. ........ .. 2-18

2.7.1.4 Interrupt Vector Prefix Register (IVPR)................................................................ 2-19

2.7.1.5 Interrupt Vector Offset Registers (IVORs) ............................................................ 2-19

2.7.1.6 Exception Syndrome Register (ESR).................................................................... 2-20

2.7.2 e500-Specific Interrupt Registers.............................................................................. 2-22

2.7.2.1 Machine C h eck S a v e/Restore Reg i ster 0 (MCSRR0)...... .................... .................2-22

2.7.2.2 Machine C h eck S a v e/Restore Reg i ster 1 (MCSRR1)...... .................... .................2-22

2.7.2.3 Machine Check Address Register (MCAR) .......................................................... 2-22

2.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 2-23

2.8 Softwar e -Use SPRs ( SP RG 0 – SPRG7 and U SP RG0) ......... .............. ........ .............. ...... 2-2 4

2.9 Branch Target Buffer (BTB) Registers .......................................................................... 2-24

2.9.1 Branch Buffer Entry Address Register (BBEAR)..................................................... 2-25

2.9.2 B ranch Buff e r Targ e t A d d r e ss Register (B BTAR) ....... .......... ................................... 2-25

2.9.3 Branch Unit Control and Status Register (BUCSR) .................................................. 2-26

2.10 Hardware Implementation-Dependent Registers........................................................... 2-27

2.10.1 Hardwa r e Im p l e m e n t a t i o n -Dependent Register 0 (HI D 0 )...................... ...................2-27

2.10.2 Hardwa r e Im p l e m e n t a t i o n -Dependent Register 1 (HI D 1 )...................... ...................2-29

2.11 L1 Cache Configuration Registers................................................................................. 2-31

2.11.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 2-31

2.11.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 2-33

2.11.3 L1 Cache Co n fi g u ra t i o n Register 0 (L1CFG0) .................................... .....................2-34

2.11.4 L1 Cache Co n fi g u ra t i o n Register 1 (L1CFG1) .................................... .....................2-35

2.12 MMU Registers.............................................................................................................. 2-35

2.12.1 Proce ss I D Re g i st e rs (PID0– P ID 2 )..... ............... .............. .............. ........ .............. ...... 2-36

2.12.2 MMU Control and Sta t u s Register 0 (MMUCSR0)......................... ......................... 2-36

2.12.3 MMU Configuration Register (MMUCFG) .............................................................. 2-37

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2.12.4 TLB Configuration Registers (TLBnCFG) ..................... .............. ........ .............. ...... 2-37

2.12.4 .1 TLB0 Configurati o n Re g i st e r (TLB0CF G) ........... ........ .............. .............. ........ .... 2-38

2.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................2-39

2.12.5 MMU Assist Registers (MAS0–MAS4, MAS6–MAS7) .......................................... 2-39

2.12.5 .1 MAS Regist e r 0 (MA S 0 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-40

2.12.5 .2 MAS Regist e r 1 (MA S 1 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-41

2.12.5 .3 MAS Regist e r 2 (MA S 2 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-42

2.12.5 .4 MAS Regist e r 3 (MA S 3 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-43

2.12.5 .5 MAS Regist e r 4 (MA S 4 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-43

2.12.5 .6 MAS Regist e r 6 (MA S 6 ) ...... .............. ......... .............. ........ .............. .............. ........ 2-44

2.12.5.7 MAS Register 7 (MAS7)—e500v2 Only.............................................................. 2-45

2.13 Debug Registers.............................................................................................................2-45

2.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................ 2-46

2.13.1.1 Debug Control Register 0 (DBCR0)...................................................................... 2-46

2.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 2-46

2.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 2-47

2.13.2 Debug Status Register (DBSR).................................................................................. 2-47

2.13.3 Instruction Address Compare Registers (IAC1–IAC4).............................................2-48

2.13.4 D a t a Ad d ress Compar e Reg isters (D A C1 – D AC2) ........ ........ ........ .............. ........ ...... 2-48

2.14 SPE and SPFP APU Registers ....................................................................................... 2-49

2.14.1 Signal Processing and Embedded Floating-Point Status and Control

Register (SPEFSCR).............................................................................................. 2-49

2.14.2 Accumulator (ACC)................................................................................................... 2-52

2.15 Perfor mance Moni t o r Re g i sters (PMRs) ..................... ........ .............. .............. ........ ...... 2-52

2.15.1 Global Co n tr o l Reg ister 0 (PM GC0 ) ...... ............... ........ .............. ........ .............. ........ 2-53

2.15.2 User Global Control Register 0 (UPMGC0).............................................................. 2-54

2.15.3 Local Control A Registers (PMLCa0–PMLCa3) ...................................................... 2-55

2.15.4 User Local Control A Registers (UPMLCa0–UPMLCa3)........................................2-56

2.15.5 Local Control B Registers (PMLCb0–PMLCb3)...................................................... 2-56

2.15.6 User Local Control B Registers (UPMLCb0–UPMLCb3)........................................ 2- 57

2.15.7 Performance Monitor Counter Registers (PMC0–PMC3)......................................... 2-57

2.15.8 User Performance Monitor Counter Registers (UPMC0–UPMC3) .......................... 2-58

2.16 Synchro n i zation Requ irement s for SPRs.. ........ ............... .............. ........ .............. .......... 2-58

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3.1 Operand Conventions ...................................................................................................... 3-1

3.1.1 Data Organization in Memory and Data Transfers......................................................3-1

3.1.2 Alignment and Misaligned Accesses........................................................................... 3-2

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Chapter 3

Instruction Model

Contents

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Number Title

3.1.3 e500 Floating-Point Implementation........................................................................... 3-2

3.1.4 Unsupported Book E Instructions................................................................................ 3-3

3.2 Instruction Set Su m m a r y .............. ........ ............... .............. ........ .............. ........ .............. .. 3-5

3.2.1 Classes of Instructions ................................................................................................. 3-6

3.2.2 Definition of Boundedly Undefined............................................................................ 3-6

3.2.3 Synchroni z ation Requ i rements. ........ ............... ........ .............. ........ .............. .............. .. 3-6

3.2.3.1 Synchronization Requirements for e500-Specific SPRs. ...................... .................. 3-8

3.2.3.2 Synchronization with tlbwe and tlbivax Instructions ...........................................3-10

3.2.3.3 Context Sync h ronizat i o n ........ ........ ............... .............. ........ .............. .............. ...... 3-11

3.2.3.4 Execution Synchronizati o n........... ........ ............... .............. ........ .............. .............. 3-11

3.2.3.5 Instruction-Related Interrupts................................................................................ 3-12

3.3 Instruction Set Ove r v iew .......... .............. ........ ............... .............. ........ .............. ............ 3- 1 3

3.3.1 Book E User-Level Instructions .................................... ............ ............ .............. ...... 3-13

3.3.1.1 Integer Instructi o n s ... .............. ..................... ........ .............. .............. .............. ........ 3-13

3.3.1.1 .1 In t e g er Arithm e t i c In struct ions ............. ............... ........ .............. .............. .......... 3-1 3

3.3.1.1 .2 In t e g er Compar e In structio n s ... ........ ............... .............. ........ .............. ........ ...... 3-15

3.3.1.1 .3 In t e g er Logical Instru c t i o n s...... ............... ........ .............. .............. ........ .............. 3-15

3.3.1.1 .4 In t e g er Rotate an d Sh i ft Instru ctions.. ............... ........ .............. ........ .............. .... 3-1 6

3.3.1.2 Load and Store In structi o n s .... .............. ............... .............. ........ .............. .............. 3-17

3.3.1.2.1 Self-Modifying Code......................................................................................... 3-17

3.3.1.2.2 Integer Load and Store Address Generation......................................................3-18

3.3.1.2 .3 In t e g er Load In st ruction s...... .............. ......... .............. .............. ........ .............. .... 3-2 0

3.3.1.2 .4 In t e g er Store Inst ru ctions.......... ............... .............. ........ .............. .............. ........ 3-21

3.3.1.2 .5 In t e g er Load and Stor e w i t h Byt e-Reverse Instru c t i o n s............ ........ .............. .. 3-22

3.3.1.2.6 Integer Load and Store Multiple Instructions.................................................... 3-22

3.3.1.3 Branch and Flow Control Instructions................................................................... 3-23

3.3.1.3.1 Conditional Branch Control............................................................................... 3-23

3.3.1.3 .2 B r a n c h In structi o n s..... .............. ............... .............. ........ .............. .............. ........ 3-24

3.3.1.3.3 Condition Register Logical Instructions............................................................ 3-25

3.3.1.3 .4 Trap Instruc t ion s. .............. .............. ............... .............. ........ .............. .............. .. 3-25

3.3.1.4 System Linkage Instruction ................................................................................... 3-26

3.3.1.5 Processor Co n trol Instruction s........ ............... ........ .............. .............. .............. ...... 3-26

3.3.1.5.1 Move to/from Condition Register Instructions..................................................3-26

3.3.1.5 .2 Mo v e t o / from Special-Purpo se Regist er Instru ct ions.... ........ ........ .............. ...... 3-26

3.3.1.6 Memory Synchronization Instructions .................................................................. 3-30

3.3.1.6.1 mbar (MO = 1). ........ .............. .............. ......... .............. .............. ........ .............. .. 3-31

3.3.1.7 Atomic Update Primitives Using lwarx and stwcx. .............................................. 3-32

3.3.1.7.1 Reservations....................................................................................................... 3-34

3.3.1.7 .2 Forward Pr o g ress...... ........ .............. ............... ........ .............. ........ .............. ........ 3-36

3.3.1.7 .3 R eservat i o n Lo ss D u e t o Gr a n u l arity .............. .............. ........ .............. .............. 3 -36

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3.3.1.8 Memory Control Instructions ................................................................................ 3-37

3.3.1.8.1 User-Level Cache Instructions .......................................................................... 3-37

3.3.2 Supervisor-Level Instructions.................................................................................... 3-39

3.3.2.1 System Linkage Instructions.................................................................................. 3-39

3.3.2.2 Supervisor-Level Memory Control Instructions.................................................... 3-40

3.3.2.2.1 Supervisor-Level Cache Instruction .................................................................. 3-40

3.3.2.2.2 Supervisor-Level TL B Ma n a g ement Instru ctions.................... .........................3-41

3.3.3 Recommended Simplified Mnemonics...................................................................... 3-42

3.3.4 Book E Instructions with Implementation- Specific Features.................................... 3-43

3.3.5 e500 Instructions........................................................................................................3-43

3.3.6 C o n t ex t Synchro n i za t i o n ............. .............. ......... .............. .............. ........ .............. ...... 3-44

3.4 Memory Access Alignment Support.............................................................................. 3-44

3.5 Using msync and mbar to Orde r Me m o ry Accesses..... ........................................ .......3-45

3.5.1 Lo c k Ac q u i sition an d Im p o rt Barriers........ ......... .............. ........ .............. ........ .......... 3-45

3.5.1.1 Acquire Lock and Import Shared Memory............................................................ 3-45

3.5.1.2 Obtain Pointer and Import Shared Memory .......................................................... 3-45

3.5.1.3 Lock Release and Export Barriers......................................................................... 3-46

3.5.1.3.1 Export Shared Memory and Release Lock........................................................ 3-46

3.5.1.3.2 Export Shared Memory and Release Lock using mbar (MO = 0).................... 3-47

3.5.2 Safe Fetch ..................................................................................................................3-47

3.6 Update In structi o n s ........... .................... ............... .............. .............. ........ .............. ........ 3-47

3.7 Memory Synchronization .............................................................................................. 3-48

3.8 EIS-Defined Instructions and APUs Implem ented on the e500 .. .............. .................... 3-48

3.8.1 SPE and Embedded Floating-Point APUs................................................................. 3-49

3.8.1.1 SPE Operands: Signed Fractions ........................................................................... 3-51

3.8.1.2 SPE Integer and Fractional Operations.................................................................. 3-52

3.8.1.3 SPE APU Instructions............................................................................................ 3-52

3.8.1.4 Embedded Fl o ating-Poin t A P U In st ructions........ .......... .......................................3-58

3.8.2 Integer Select (isel) APU.... .............. ........ ............... .............. ........ .............. .............. 3-60

3.8.3 Perform a n ce Mo n i t o r A PU... .............. ........ ............... .............. .............. ........ ............ 3-60

3.8.4 Cache Locking APU.................................................................................................. 3-61

3.8.5 Machine Check APU ................................................................................................. 3-63

3.9 e500-Specific Instructions ............................................................................................. 3-63

3.9.1 Branch Target Buffer (BTB) Locking Instructions.................................................... 3-63

3.10 Instruction Listing. .............. .............. ........ ............... .............. .............. ........ .............. .... 3-66

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Chapter 4

Execution Timing

4.1 Terminology and Conventions......................................................................................... 4-1

4.2 Instruction Timing Ov e rview.......... .............. ............... ........ .............. .............. ........ ........ 4-4

4.3 General Timing Considerations ..................................................................................... 4-10

4.3.1 General Instruction Flow ........................................................................................... 4-11

4.3.2 Instruction Fetch Timing Considerations................................................................... 4-12

4.3.2.1 L1 and L2 TLB Access Times............................................................................... 4-12

4.3.2.2 Interrup t s A ssociate d wit h In structi o n Fetchin g.............. ........ .............. .............. .. 4-12

4.3.2.3 Cache-Related Latency.......................................................................................... 4-13

4.3.3 Dispatch, Issue, and Completion Considerations ...................................................... 4-14

4.3.3.1 GPR and CR Rename Register Operation............................................................. 4-15

4.3.3.2 LR and CTR Shadow (Speculative) Registers....................................................... 4-15

4.3.3.3 Instructi o n S e ri alizat ion.................. ........ . ........ ........ .............. .............. .............. .... 4-1 5

4.3.4 Interrupt Latency........................................................................................................ 4-16

4.3.5 M emory Synchr o ni zation T i m in g Co n sideration s.................................... .................4-17

4.3.5.1 msync Instruction Timing Considerations ............................................................ 4-17

4.3.5.2 mbar Instruction Timing Con siderati o n s. ............... .............. ........ .............. .......... 4-17

4.4 Execution ....................................................................................................................... 4-18

4.4.1 B r a n ch U n i t Ex ecutio n ........ ........ .............. ............... ........ .............. .............. ........ ...... 4-18

4.4.1.1 Branch Ins t ru c t i o n s and Compl e t i o n ............... .............. .............. .............. ........ .... 4-1 8

4.4.1.2 BTB Branch Prediction and Resolution ................................................................ 4-20

4.4.1.3 BTB Operations..................................................................................................... 4-21

4.4.1.3.1 BTB Locking ..................................................................................................... 4-23

4.4.1.3.2 BTB Locking APU Programming Model..........................................................4-24

4.4.1.3.3 BTB Operati o n s Con trolled by BU CS R......................................... ...................4-24

4.4.1.3.4 BTB Special Cases—Phantom Branches and Multiple Matches...................... 4-25

4.4.2 Load/Store Unit Execution ........................................................................................ 4-25

4.4.2.1 Load/Store U n it Qu e u e i n g Stru c t u res... ......... .............. .............. ........ .............. ...... 4-25

4.4.3 Simple and Multiple Unit Execution ......................................................................... 4-27

4.4.3.1 MU Divide Exe c u t i o n............. ........ ............... .............. ........ .............. .............. ...... 4-28

4.4.3.2 MU Floating-Point Ex e cu t ion... ........ ............... .............. ........ .............. .............. .... 4-2 9

4.4.4 Load/Store Execution ................................................................................................ 4-29

4.4.4.1 Effect of Operand Placement on Performance ...................................................... 4-30

4.5 Memory Performance Considerations ........................................................................... 4-30

4.6 Instruction La te n c y Summary... ........ .............. ............... ........ .............. .............. ........ .... 4-3 1

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4.7 Instruction Sch e d u l i n g Gui d e l i n e s.... ........ ............... ........ .............. .............. ........ .......... 4-44

4.7.1 Fetch/Branch Considerati o n s.... .............. ............... ........ .............. .............. ........ ........ 4-45

4.7.1.1 Dynamic Prediction versus No Branch Prediction................................................ 4-45

4.7.1.1 .1 Positio n -I n d e p en d e n t Co d e........... ............... .............. ........ .............. .............. .... 4-4 5

4.7.2 D i sp a t c h Un it Resour ce Req u irement s....... ......... .............. ........ .............. ........ .......... 4-45

4.7.2.1 Dispatch Groupings............................................................................................... 4-46

4.7.3 Issue Queu e Re source Re q u i rements.......... ............... ........ .............. ........ .............. .... 4-4 6

4.7.3.1 General Is su e Q u eu e (G I Q ) ...... ........ ............... .............. ........ .............. .............. .... 4-4 6

4.7.3.2 Branch Issu e Q u eu e (BIQ).............. ............... .............. .............. .............. .............. 4-46

4.7.4 Completion Unit Resource Requirements ................................................................. 4-46

4.7.4.1 Completion Groupings...........................................................................................4-47

4.7.5 Serialization Effe c t s.. .............. .............. ........ ............... .............. .............. ........ .......... 4-47

4.7.6 Ex e cution Un i t C o n si d e r a t i o n s ........... ............... ........ .............. .............. ........ ............ 4- 4 7

4.7.6.1 SU Considerations ................................................................................................. 4-47

4.7.6.2 MU Conside rat i o n s... .............. .............. ......... .............. .............. ........ .............. ...... 4-48

4.7.6.3 LSU Consider a t i o n s............ ........ .............. ............... ........ .............. .............. ........ .. 4-48

4.7.6.3.1 Load/Store Interaction ....................................................................................... 4-48

4.7.6.3 .2 Misalignm ent Effect s...... ........ . . . . . . . . . . . . . . ............... .............. .............. ........ .......... 4-4 9

4.7.6.3 .3 Lo a d Mi ss Pipelin e ............... ........ ............... .............. ........ .............. ........ .......... 4-50

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Chapter 5

Interrupts and Exceptions

5.1 Overview.......................................................................................................................... 5-1

5.2 e500 Interrupt Definitions................................................................................................ 5-2

5.2.1 Recoverability from Interrupts.....................................................................................5-4

5.3 Interrupt Registers............................................................................................................ 5-5

5.4 Exceptions........................................................................................................................ 5-8

5.5 Interrupt Classes .............................................................................................................. 5-9

5.5.1 R eq u i rements for System Reset Gene r a t i o n .... ........ .............. .............. ........ .............. 5-10

5.6 Interrupt Processing....................................................................................................... 5-10

5.7 Interrupt Definitions ...................................................................................................... 5-12

5.7.1 Critical Input Interrupt...............................................................................................5-13

5.7.2 Machine Check Interrupt ........................................................................................... 5-14

5.7.2.1 Core Complex Bus (CCB) a n d L1 Ca che Machine Che c k Erro rs........ .................5-16

5.7.2.2 Cache Parity Error Injection .................................................................................. 5-18

5.7.3 D a t a Stor ag e Interru p t............... .............. ............... .............. ........ .............. .............. .. 5-19

5.7.4 In structio n St o rag e Interr u p t............... ........ . ........ ........ .............. .............. .............. .... 5-2 0

5.7.5 External Input Interrupt ............................................................................................. 5-21

5.7.6 Alignment Interrupt ................................................................................................... 5-22

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5.7.7 Program Interrupt....................................................................................................... 5-24

5.7.8 System Call Interrupt................................................................................................. 5-25

5.7.9 Decrementer Interrupt................................................................................................ 5-25

5.7.10 Fixed-Interval Timer Interrupt................................................................................... 5-26

5.7.11 Watchdog Timer Interrupt.......................................................................................... 5-27

5.7.12 Data TLB Error Interrupt............ ........ ............... .............. ........ .............. ........ ............ 5-27

5.7.13 Instru ction TLB Error Inte r rupt........ ............... .............. .............. .............. .............. .. 5-29

5.7.14 Debug Interrupt.......................................................................................................... 5-30

5.7.15 EIS-Defined Int errupt s.......... .................... ............... .............. .............. .............. ........ 5-31

5.7.15.1 SPE/Embedded Floating-Point APU Unavailable Interrupt.................................. 5-31

5.7.15.2 Embedded Floating-Point Data Interrupt .............................................................. 5-32

5.7.15.3 Embedded Floating-Point Round Interrupt ...........................................................5-32

5.8 Perfor m a n c e Mo n itor Interrupt... .............. ............... .............. .............. .............. ............ 5- 3 3

5.9 Partial l y Ex e cuted Inst ruction s ......... .............. ............... ........ .............. .............. ........ .... 5-3 3

5.10 Interrupt Ordering and Masking .................................................................................... 5-35

5.10.1 Guidel i n e s fo r System Software ............... ............... .............. .............. .............. ........ 5-36

5.10.2 Interrupt Order...........................................................................................................5-37

5.11 Exception Priorities........................................................................................................5-37

5.11.1 e500 Exception Priorities........................................................................................... 5-39

5.12 e500 Interrupt Latency................................................................................................... 5-39

5.13 Guarded Load and Cache-Inhibited stwcx. Inst ruction s .... ........ .............. .............. ...... 5-40

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Chapter 6

Power Management

6.1 Overview.......................................................................................................................... 6-1

6.2 Power Ma n a g em e n t Si g n als.. .............. ........ ............... .............. ........ .............. ........ .......... 6-1

6.3 Core and Integrated Device Power Management States.................................................. 6-2

6.4 Power Ma n a g em e n t C o n t ro l Bi t s........ .............. ......... .............. .............. ........ .............. .... 6-3

6.4.1 Software Considerations for Power Management.......................................................6-4

6.5 Power Ma n a g em e n t Pr o tocol.............. ........ ............... ........ .............. .............. ........ .......... 6-5

6.6 Interrupts and Power Management.................................................................................. 6-6

Chapter 7

Performance Monitor

7.1 Overview.......................................................................................................................... 7-1

7.2 Perfor m a n ce Mo n i t o r A PU Registe r s ........... ............... .............. ........ .............. .............. .. 7-2

7.2.1 G l o b a l Co n tr o l Re g i st e r 0 (PM G C0 ) ...... ............... ........ ........ .............. ........ .............. .. 7-4

7.2.2 User Global Control Register 0 (UPMGC0)................................................................ 7-5

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7.2.3 Local Control A Registers (PMLCa0–PMLCa3) ........................................................ 7-5

7.2.4 User Local Control A Registers (UPMLCa0–UPMLCa3)..........................................7-6

7.2.5 Local Control B Registers (PMLCb0–PMLCb3)........................................................ 7-6

7.2.6 User Local Control B Register s (UPMLCb0–UPMLCb3)..........................................7- 7

7.2.7 Performance Monitor Counter Registers (PMC0–PMC3)........................................... 7-8

7.2.8 User Performance Monitor Counter Registers (UPMC0–UPMC3) ............................ 7-9

7.3 Perfor m a n ce Mo n i t o r A PU Instruc t i o n s ........... ............... .............. ........ .............. ............ 7- 9

7.4 Perfor m a n c e Mo n itor Interrupt... .............. ............... .............. .............. .............. ............ 7- 1 0

7.5 Event Cou n t i n g ........... .............. ........ .............. ............... ........ .............. .............. ........ .... 7-10

7.5.1 Processor Context Configurability.............................................................................7-10

7.6 Examples........................................................................................................................ 7-11

7.6.1 Chaining Counters ..................................................................................................... 7-11

7.6.2 Thresholding .............................................................................................................. 7-12

7.7 Event Se l ec t i o n ................. ........ .............. ............... ........ .............. .............. ........ ............7-12

Chapter 8

Debug Support

8.1 Overview.......................................................................................................................... 8-1

8.2 Programming Model........................................................................................................ 8-1

8.2.1 R eg i ster Set............. ........ .............. .............. ............... ........ .............. .............. .............. 8-1

8.2.2 In structio n Set................. ........ .............. ............... ........ .............. .............. ........ ............8-2

8.2.3 Debug Interrupt Model ................................................................................................ 8-2

8.2.4 Deviations from the Book E Debug Model ................................................................. 8-3

8.2.5 Hardware Facilities............................................................... ........ .......... ........ .......... ...8-4

8.3 TAP Con t roller and Re g i st e r Model ............... ......... .............. .............. ........ .............. ...... 8-4

8.3.1 TAP Interface Signals ................................. ................. ...... ........ ........ ........ ........ ........ .. 8-5

8.4 Book E Debug Events...................................................................................................... 8-6

8.4.1 Instruction Address Compare Debug Event ................................................................ 8- 7

8.4.1.1 Instructio n A d d r e ss Compare Use r and Super v i so r Modes......... ........ .............. ...... 8-7

8.4.1.2 Effective Ad d re ss Mode . .............. ........ ............... .............. ........ .............. .............. .. 8-8

8.4.1.3 Instructio n A d d ress Compar e Mo d e......... ......... .............. ........ .............. ........ .......... 8-8

8.4.2 Data Address Compare Debug Event...................................... ........ ........ ........ ........ .... 8- 9

8.4.2.1 Data Address Compare Read/Write Enable.............................................................8-9

8.4.2.2 Data Address Compare User/Supervisor Mode.....................................................8-10

8.4.2.3 Effective Ad d re ss Mode . .............. ........ ............... .............. ........ .............. .............. 8-10

8.4.2.4 Data Addre ss Co m p a re (DAC) Mod e.................. .............. ........ .............. .............. 8 -10

8.4.3 Trap Debug Event.................................................................................... .................. 8-11

8.4.4 Branch Taken Debug Event....................................................................................... 8-12

8.4.5 Instruction Complete Debug Event............................................................................8-12

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8.4.6 Interrupt T a ken Debug Event.....................................................................................8-13

8.4.7 Return Debug Event................................................................................................... 8-13

8.4.8 Unconditional Debug Event....................................................................................... 8-14

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Part II

e500 Core Complex

Chapter 9

Timer Facilities

9.1 Timer Facil iti e s ..... ........ ........ .............. .............. ......... .............. .............. ........ .............. .... 9-1

9.2 Timer Registers................. ........ .............. ........ ............... .............. ........ .............. ........ ......9-2

9.3 The e500 Timer Implementation......................................................................................9- 3

9.3.1 Alternate Time Base APU ........................................................................................... 9-4

9.3.2 Perform a n ce Mo n i t o r Time Ba se Ev e n t ....... ............... .............. ........ .............. ............ 9- 4

Chapter 10

Auxiliary Processing Units (APUs)

10.1 Overview........................................................................................................................10-1

10.2 Branch Target Buffer (BTB) Locking APU................................................................... 10-2

10.2.1 BTB Locki n g A PU Programm ing Model............ .............. .............. ........ .............. .... 10- 2

10.2.1 .1 BTB Locki n g A PU Instruc t i o n s ..... ........ ............... .............. ........ .............. ............ 10 - 2

10.2.1 .2 BTB Locki n g A PU Reg ister s ................... ......... .............. ........ .............. .............. .. 10-3

10.3 Alternate Time Base APU.............................................................................................. 10-3

10.3.1 Programming Model.................................................................................................. 10-3

10.4 Double-Precision Floating-Point APU (e500 v2 Only)................................................. 10-4

10.4.1 Programming Model.................................................................................................. 10-4

10.4.2 Double-Precision Floating-Point APU Operations.................................................... 10-4

10.4.2.1 Operational Modes................................................................................................. 10-4

10.4.2.2 Floating-Point Data Formats.................................................................................. 10-5

10.4.2 .3 Overflo w an d U nderflow................ ............... ........ .............. .............. ........ ............ 10 -6

10.4.3 Instruction Descriptio n s.......... .............. ........ ............... .............. .............. ........ .......... 10-6

10.4.4 Embedded Floating-Point Results Summary........................................................... 10-22

10.4.5 Floating-Point Conversion Models..........................................................................10-22

10.4.5.1 Common Functions.............................................................................................. 10-22

10.4.5.2 Convert from Double-Precision Floating-Point to Integer Word

with Saturation................................................................................................. 10-23

10.4.5.3 Convert to Double-Precision Floating-Point from Integer Word

with Saturation................................................................................................. 10-25

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Chapter 11

L1 Caches

11.1 Overview........................................................................................................................11-1

11.1.1 Block Di ag ram.. ........ .............. .............. ........ ............... .............. ........ .............. .......... 11-3

11.1.1.1 Load/Store Unit (LSU) .......................................................................................... 11-3

11.1.1.1.1 Caching-Allowe d Lo a d s and the LSU............. .............. ........ .............. .............. 11-4

11.1.1.1.2 Store Queue ........ ........ .............. ............... ........ .............. .............. ........ .............. 11-4

11.1.1.1.3 L1 Load Miss Queue (L MQ ).... ............... .............. ........ .............. .............. ........ 11-4

11.1.1.1.4 Data Line Fill Buffer (D LFB)............... ............... .............. ........ .............. .......... 11-4

11.1.1.1.5 Data Write Buffe r ( D W B) ................ ............... ........ .............. ........ .............. ...... 11-5

11.1.1.2 Instru ction Un i t................. .................... ............... .............. ........ .............. .............. 11-5

11.1.1.3 Core Interface Unit ................................................................................................ 11-5

11.2 L1 Cache Organ i z at ion ... ........ ........ .............. ......... .............. .............. ........ .............. ...... 11-6

11.2.1 L1 Data Cach e Organizat i o n... ........ ........ ............... .............. ........ .............. .............. .. 11-6

11.2.2 L1 Instru ction Cache Organiza t i o n.................. .............. ........ .............. .............. ........ 11-7

11.2.3 L1 Cache Parity ...... .............. ........ .............. ............... ........ .............. .............. ........ .... 11-8

11.2.4 Cache Parity Error Injection...................................................................................... 11-9

11.3 Cache Coherency Support ............................................................................................. 11-9

11.3.1 Data Cache Coherency Model .................. ......... .............. ........ .............. ........ ............ 11-9

11.3.2 Instruction Cache Coherency Model ........................................................................11-11

11.3.3 Snoop Signaling............................................................ .............. .............. .............. . 11-12

11.3.4 WIMGE Settings and Effect on L1 Caches............................................................. 11-13

11.3.4.1 Write-Back Stores................................................................................................ 11-13

11.3.4.2 Write-Through Stores................. ............ ....................... .......... ............ .......... ...... 11-13

11.3.4.3 Caching -Inhibited Load s a n d Stor e s. ............... ........ .............. .............. ........ ........ 11-13

11.3.4.4 Misaligned Accesses and the Endian (E) Bit....................................................... 11-13

11.3.4.5 Speculative Accesses to Guarded Memory ......................................................... 11-13

11.3.5 Load/Store Operations ............................................................................................. 11-14

11.3.5.1 Perfo r med Loads an d Stor e s. ........ ............... .............. .............. ........ .............. ...... 11-14

11.3.5.2 Sequential Consistency of Memory Accesses..................................................... 11-15

11 .3.5.3 Enforcing Store Orderin g w i t h Re spect to Loads........................... .....................11-15

11.3.5.4 Atomic Memory References................................................................................ 11-15

11.4 L1 Cache Cont rol................ ........ .............. ........ ............... .............. ........ .............. ........ 11-16

11.4.1 Cache Control Instructions ...................................................................................... 11-16

11.4.2 L1 Instruction and Data Cache Enabling/Disabling ................................................ 11-18

11.4.3 L1 Instruction and Data Cache Flash Invalidation .................................................. 11-18

11.4.4 L1 Instruction and Data Cache Line Locking/Unlocking........................................ 11-19

11.4.4.1 Effects of Other Cache Instructions on Locked Lines......................................... 11-21

11.4.4.2 Flash Clearing of Lock Bits................................................................................. 11-21

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11.5 L1 Data Cach e Flushin g ....... .............. .............. ......... .............. .............. ........ .............. 11-22

11.6 L1 Cache Operation ............ .............. ........ ............... .............. ........ .............. .............. .. 11-22

11.6.1 Cache Mis s a n d Reload Operations.. ........ ............... .............. ........ .............. ........ .... 11-23

11.6.1.1 Data Cach e Fills.... ........ .............. ........ ............... .............. ........ .............. ........ ...... 11-23

11.6.1.2 Instruction Cache Fills.........................................................................................11-23

11.6.1.3 Cache Allocation on Misses ................................................................................ 11-24

11.6.1.4 Store Mis s Me rg i n g ........ .............. ........ ............... .............. ........ .............. ........ .... 11-24

11.6.1.5 Store Hit to a Data Cache Block Marked Shared ................................................ 11-24

11.6.1.6 Data Cach e Block Push O p e ration .................. ........ .............. ........ .............. ........ 11-24

11.6.2 L1 Cache Block Replacement.................................................................................. 11-25

11.6.2.1 PLRU Replacement ............................................................................................. 11-25

11.6.2.2 PLRU Bit Updates............................................................................................... 11-26

11.6.2.3 Cache Locking and PLRU................................................................................... 11-27

11.7 L2 Cache Support ........................................................................................................ 11-27

11.7.1 Invalid ating th e L2 Ca c h e a fter a Cache Tag Parity Error... .............. .................... .. 11-27

11.7.2 L2 Lockin g................ .............. .............. ............... ........ .............. .............. .............. .. 11-27

11.7.2.1 L2 Unlo ck ing.................. ........ .............. ............... ........ .............. .............. ........ .... 11-28

11.7.2.2 L1 Over l o c k........ .............. ........ .............. ............... ........ .............. .............. ........ .. 11-28

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Chapter 12

Memory Management Units

12.1 e500 MMU Overview....................................................................................................12-1

12.1.1 MMU Features........................................................................................................... 12-1

12.1.2 TLB Entr y Ma i n t e n an c e F e at u res..... ............... .............. ........ .............. .............. ........ 12-3

12.2 Effective-to-Real Address Translation........................................................................... 12-4

12.2.1 Virtual Addresses with Three PID Registers............................................................. 12-5

12.2.2 Variable-Sized Pages.................................................................................................. 12-6

12.2.3 Checkin g fo r TLB Entry Hit... ........ .............. ......... .............. .............. ........ .............. .. 12-7

12.2.4 Checking for Access Permissions.......................... ...... ...... ...... .... ...... ...... ...... ...... .... .. 12-7

12.3 Translation Lookaside Buffers (TLBs).......................................................................... 12-8

12.3.1 L1 TLB Arra y s...... ........ .............. .............. ......... .............. .............. ........ .............. ...... 12-9

12.3.2 L2 TLB Arra y s...... ........ .............. .............. ......... .............. .............. ........ .............. .... 12-11

12.3.2 .1 IPROT Inv a l i d a t i o n Pr o t e ction in TLB1 ........... .............. .............. ........ .............. 12-12

12.3.2.2 Replacement Algorithms for L2 MMU............................................................... 12-13

12.3.2.2.1 Round-Robin Replacement for TLB0—e500v1.......... .................... ................ 12- 14

12.3.2.2.2 Round-Robin Replacement for TLB0—e500v2.......... .................... ................ 12- 14

12.3.3 Consis t en c y Be t w ee n L1 an d L2 TLBs.. ......... ........ .............. .............. ........ ............ 12-15

12.3.4 L1 and L2 TLB Access Times................................................................................. 12-16

12.3.5 The G Bit (of W IMGE) .................. ........ ............... .............. ........ .............. .............. 1 2 -16

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12.3.6 TLB Entry Field Definitions.................................................................................... 12-17

12.4 TLB Instruction s—Implementati o n.............. ............... .............. .............. .............. ...... 12 -17

12.4.1 TLB Read Entry (tlbre) Inst ruction.... ........ ............... .............. ........ .............. .......... 12-1 8

12.4.1 .1 Reading En t ries from th e TLB1 Array.......... ........ .............. .............. .............. .... 12- 1 8

12.4.1 .2 Reading En t ries from th e TLB0 Array.......... ........ .............. .............. .............. .... 12- 1 8

12.4.2 TLB Write Entry (tlbwe) Instruction.... ............... .............. .............. .............. ........ .. 12-19

12.4.2 .1 Writing to the TLB1 Array ... .............. ............... ........ .............. .............. ........ ...... 12 -19

12.4.2 .2 Writing to the TLB0 Array ... .............. ............... ........ .............. .............. ........ ...... 12 -19

12.4.3 TLB Search (tlbsx) Instruction—Searching the TLB1 and TLB0 Arrays .............. 12-19

12.4.4 TLB Invalidate (tlbivax) Instructi o n .... ........ ............... .............. .............. ........ ........ 12-20

12.4.4.1 TLB Selection for tlbivax Instructio n ................. .............. .............. ........ ............ 12 -21

12.4.4.2 Invalidate All Address Encoding for tlbivax Instru c t i o n..... .......... .....................12-22

12.4.4.3 TLB Invalidate Broadcast Enabling .................................................................... 12-22

12.4.5 TLB Synchronize (tlbsync) Instruction................................................................... 12-22

12.5 TLB Entr y Ma i n t e n an c e— D etails ............ ............... .............. ........ .............. .............. .. 12-22

12.5.1 Automa t i c Updates—T LB Mi ss Excepti o n s ..... ........ .............. .............. ........ .......... 12-2 3

12.5.2 TLB Interrupt Rout i n e s... .............. .............. ......... .............. .............. ........ .............. .. 12-24

12.5.2 .1 Permission s Viola t i o n s (ISI, DSI) Interrupt Handlers....... ................................. 12-24

12.6 TLB States a ft er Reset ........ ........ .............. ............... ........ .............. .............. ........ ........ 12-24

12.7 Core Complex MMU Registers ................................................................................... 12-25

12.7.1 e500 MAS Registers................................................................................................ 12-26

12.7.1 .1 MAS Regist e r 7 (MA S 7 ) ...... .............. ............... ........ .............. ........ .............. ...... 12 -31

12.7.2 MAS Regist e r U p d a t e s ................... .............. ......... .............. ........ .............. ........ ...... 12 -32

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Chapter 13

Core Complex Bus (CCB)

13.1 Overview........................................................................................................................13-1

13.2 Signal Summary............................................................................................................. 13-2

13.3 Core Interface Behavior................................................................................................. 13-5

13.3.1 Parity Sp ecifica tion........... ........ .............. ............... ........ .............. .............. ........ ........ 13-5

13.3.2 msync Operation and the Bus.................................................................................... 13-6

13.3.3 mbar Operati o n and t h e B u s .... .............. ............... ........ .............. .............. ........ ........ 13-6

13.4 Address Streaming Mode............................................................................................... 13-7

13.5 L2 Cache Support . .............. ................................................................... ........................ 13-7

13.5.1 L2 Lockin g.......... .............. .............. ........ ............... .............. ........ .............. .............. .. 13-7

13.5.2 L2 Unloc k i n g .................. ........ .............. ............... ........ .............. .............. ........ .......... 13-8

13.5.3 L1 Overl o c k .................. .............. ........ ............... ........ .............. .............. ........ ............ 13-8

13.6 Reserv a t i o n Managemen t ............. ........ ............... .............. ........ .............. .............. ........ 13-8

13.7 Remote A t o m ic Status Monit o ring....... ........ ............... .............. ........ .............. .............. 1 3 -9

13.8 Proper Reporting of Bus Faults ..................................................................................... 13-9

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Contents

Paragraph
Number Title

Appendix A

Programming Examples

A.1 Synchronization ..............................................................................................................A-1

A.1.1 Synchronization Primitives......................................................................................... A-2

A.1.1.1 Fetch and No-op ..................................................................................................... A-2

A.1.1.2 Fetch and Store ....................................................................................................... A-3

A.1.1.3 Fetch and Add......................................................................................................... A-3

A.1.1.4 Fetch and AND....................................................................................................... A-3

A.1.1.5 Test and Set............... ........ .............. ............... ........ .............. ........ .............. .............A-4

A.1.1.6 Compare and Swap................................................................................................. A-4

A.1.1.7 Notes.......................................................................................................................A-4

A.1.2 Lock Acqui sition and R elease .............. ............... ........ .............. .............. ........ ........... A-5

A.1.3 List Insertion............................................................................................................... A-6

A.1.3.1 Notes.......................................................................................................................A-7

Appendix B

Guidelines for 32-Bit Book E

Page

Number

B.1 64-Bit–Specific Book E Instructions...............................................................................B-1

B.2 Registers on 32-Bit Book E Implementations .................................................................B-2

B.3 Addressing on 32-Bit Book E Implementations..............................................................B-2

B.4 TLB Fields on 32-bit Book E Implementations............................................................... B-2

B.5 32-Bit Book E Software Guidelines................. ...............................................................B-3

B.5.1 32-Bit Instruction Selection.........................................................................................B-3

B.5.2 32-Bit Addressing........................................................................................................B-3

Appendix C

Simplified Mnemonics for PowerPC Instructions

C.1 Overview..........................................................................................................................C-1

C.2 Sub tr a ct Simplified Mnem o n i cs ... ........ ............... ........ .............. ........ .............. ........ ........C-2

C.2.1 Su b tr a ct Immediat e. .............. .............. ........ ............... ........ .............. ........ .............. ......C-2

C.2.2 Subtract ........................................................................................................................C-2

C.3 Rotate and Shift Simplified Mnemonics..........................................................................C-2

C.3.1 Op erations o n Words ...... ........ .............. ........ ......... .............. ........ .............. ........ ..........C- 3

C.4 Bra n ch In structi o n Simplified Mnemon i c s..... ............... .............. ........ .............. ........ ......C-4

C.4.1 Key Facts about Simplified Branch Mnemonics ....................................... .............. ....C-5

C.4.2 Eliminating the BO Operand .......................................................................................C-5

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C.4.3 Incorporat ing the BO Bra n ch Pr e d i ction .... ............... ........ .............. ........ ........ ............ C-7

C.4.4 The BI Operan d —C R Bi t and F i e l d Re p resentati o n s.... ........ .............. ........ ........ ........C-8

C.4.4. 1 BI Ope ra n d In structio n En coding... ........ ......... .............. .............. ........ .............. ......C-8

C.4.4. 1 .1 Specify i n g a C R Bi t................ ........ ......... .............. ........ .............. ........ .............. ..C-9

C.4.4.1.2 The crS Op e rand .................... ........ ............... ........ .............. ........ .............. ........C-10

C.4.5 Simplified Mnemonics that Incorporate the BO Operand.........................................C-11

C.4.5.1 Examples that Eliminate the BO Operand.............................................................C-12

C.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO

and Replaces BI with crS).....................................................................................C-15

C.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions: Examples.........C-17

C.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions: Listings............C-17

C.5 Compare Word Simplified Mnemonics .........................................................................C-20

C.6 Condition Register Logical Simplified Mnemonics......................................................C-20

C.7 Trap Inst ru ctions Si m p l i fi e d Mn em o n ics .................... .............. ........ .............. ..............C-21

C.8 Simplified Mnemonics for Accessing SPRs. .... ..... .... .. .... .. .... .. .... .. .... .. .... .. .... .. .... .. .... .. ..C-23

C.9 Recommended Simplified Mnemonics..........................................................................C-24

C.9.1 No-Op (nop) ..............................................................................................................C-24

C.9.2 Load Immediate (li)...................................................................................................C-24

C.9.3 Load Address (la) ......................................................................................................C-24

C.9.4 Move Register (mr)...................................................................................................C-25

C.9.5 Complement Register (not) .......................................................................................C-25

C.9.6 Move to Condition Register (mtcr)...........................................................................C-25

C.10 EIS-Spe cific Simp l i fied Mnem o n i c s ...... ........ ............... ........ .............. ........ .............. ....C- 2 6

C.10.1 Integer Select (isel)....................................................................................................C-26

C.10.2 SPE Mnemonics.........................................................................................................C-26

C.11 Comprehensive List of Simplified Mnemonics .............................................................C-26

Page

Number

D.1 Instructions (Binary) by Mnemonic................................................................................ D-1

D.2 Instructions (Decimal and Hexadecimal) by Opcode................................................... D-22

D.3 Instructions by Form..................................................................................................... D-35

E.1 Major Changes From Revision 0 to Revision 1.............................................................. A-1

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Appendix D

Opcode Listings

Appendix E

Revision History

Index

Figures

Figure
Number Title

Figures

Page

Number

1-1 e500 Core Complex Block Diagram....................................................................................... 1-2

1-2 Vect o r an d Fl o a t i n g -Point AP U s...... .............. ............... .............. ........ .............. .............. ........ 1-6

1-3 Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 1-8

1-4 Thre e - St a g e Lo a d / St o r e Uni t ......... .............. ........ ............... .............. ........ .............. .............. ..1-9

1-5 Ins t ru ction Pipeline Flo w....... .............. .............. ......... .............. .............. ........ .............. ........ 1-16

1-6 GPR Issue Queu e (G IQ) .... ........ .............. ........ ............... .............. .............. .............. ........ .... 1-17

1-7 e500 Core Programming Model............................................................................................1-19

1-8 MMU Structure ..................................................................................................................... 1-25

1-9 Effec t i v e - to-Real Add r e ss Translation F low.. ........ ............... .............. ........ .............. ............ 1- 2 6

1-10 Effective-to-Real Address Translation Flow (e500v2) ......................................................... 1-27

2-1 e500 Register Model ............................................................................................................... 2-3

2-2 Mac h ine State Register (MS R) .................. .............. ......... .............. .............. ........ .............. .. 2-10

2-3 Proc essor Versi o n Reg i ster (PVR)............... ........ ............... .............. ........ .............. ........ ...... 2-13

2-4 System Version Reg ister (SV R)............... .............. ......... .............. .............. ........ .............. .... 2-1 3

2-5 Relationship of Timer Facilities to the Time Base................................................................ 2-14

2-6 Timer Control Register (TCR ) ..... ........ .............. ......... .............. ........ .............. ........ .............. 2-15

2-7 Alternate Time Base Register Lower (ATBL) ...................................................................... 2-17

2-8 Alternate Time Base Register Upper (ATBU) ...................................................................... 2-17

2-9 Interrupt Vector Offset Registers (IVORs) ........................................................................... 2-19

2-10 Exception Syndrome Register (ESR).................................................................................... 2-20

2-1 1 Ma ch ine Check Save/Restore Reg i ster 0 (MCSRR0).. ........................................ .................2-22

2-12 M a ch ine Check Save/Restore Reg i ster 1 (MCSRR1).. ........................................ .................2-22

2-13 Machine Check Address Register (MCAR).......................................................................... 2-22

2-14 Machine Check Syndrome Register (MCSR)....................................................................... 2-23

2-15 Branch Buffer Entry Address Register (BBEAR) ................................................................ 2-25

2-16 Branch Buffer Target Address Register (BBTAR)................................................................ 2-25

2-17 Bra n c h Un i t Co n t r o l and Status Register (B U CS R ) ............... .............. ........ .............. ........ .. 2-26

2-18 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-27

2-19 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-29

2-20 L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 2-31

2-21 L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 2-33

2-22 L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 2-34

2-23 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 2-35

2-24 Pro cess ID Reg i st e r s (PID0–P ID 2 ).... ........ ........ ............... ........ .............. .............. ........ ........ 2-36

2-25 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-36

2-26 MMU Configuration Register (MMUCFG) ......................................................................... 2-37

2-27 TL B Co n f i guration Re g i st e r 0 (TLB0CFG) .... ............... ........ ........ .............. ........ .............. .. 2-38

2-28 TL B Co n f i guration Re g i st e r 1 (TLB1CFG) .... ............... ........ ........ .............. ........ .............. .. 2-39

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Figures

Figure
Number Title

2-29 MAS Re g i st er 0 (MAS0) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-40

2-30 MAS Re g i st er 1 (MAS1) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-41

2-31 MAS Re g i st er 2 (MAS2) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-42

2-32 MAS Re g i st er 3 (MAS3) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-43

2-33 MAS Re g i st er 4 (MAS4) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-43

2-34 MAS Re g i st er 6 (MAS6) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-44

2-35 MAS Re g i st er 7 (MAS7) ........... .............. ........ ............... ........ .............. ........ .............. ........ .. 2-45

2-36 Debug Control Register 2 (DBCR2)..................................................................................... 2- 47

2-37 Debug Status Register (DBSR)............................................................................................. 2-48

2-38 Signal Processing and Embedded Floating-Point Status and Control

Regist e r (S P EFSCR) ......... ........ .............. ........ ............... ........ .............. .............. ........ ...... 2-50

2-39 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 2-53

2-40 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 2-55

2-41 Local Control B Registers (PMLCb0–PMLCb3)/

User Local Control B Registers (UPMLCb0–UPMLCb3) .............................................. 2-56

2-42 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................. 2-57

3-1 Register Indirect with Immediate Index Addressing for Integer Loads/Stores. .......... .......... 3- 18

3-2 Re g i ste r Indirect with In d e x A d d ressing for Integ er Loads/St o res....................................... 3-19

3-3 Register Indirect Addressing for Integer Loads/Stores.........................................................3-20

3-4 SPE and Floating-Point APU GPR Usage ............................................................................ 3-50

3-5 Integ er and Frac t i o n a l O p erations............ .............. ......... .............. .............. ........ .............. .... 3-52

4-1 Ins t ru ction Flow Pipeli n e Diagram Showing Pi p el ine Stages .................... .............. .............. 4-4

4-2 e500 Instruction Flow Diagram—Details............................................................................... 4-5

4-3 GPR Issue Queu e (G IQ) .... ........ .............. ........ ............... .............. .............. .............. ........ ...... 4-7

4-4 Execution Pipeline Stages and Events .................................................................................... 4-9

4-5 Execution Stag e s .... .............. ........ .............. .............. ......... .............. .............. ........ ................ 4-10

4-6 Branch Completion (LR/CTR Write-Back).......................................................................... 4-19

4-7 Updating Branch History ......................................................................................................4-20

4-8 Fetch Groups and Cache Line Alignment.... ............ ....................... .......... ............ .......... ...... 4-21

4-9 Fetch Group Addresses ......................................................................................................... 4-22

4-10 Cache/Core Interface Unit Integration.................................................................................. 4-26

4-1 1 MU Div i d e By p ass Path (Showing an 11 -Cycle Divide )..................... .............................. ... 4-28

6-1 Core Power Management State Diagram................................................................................ 6-2

6-2 Exam p l e Co re Power Man agemen t Hand shakin g ........ ........ .............. .............. ........ .............. 6-5

7-1 Performance Monitor Global Control Register 0 (PMGC0)/

User Performance Monitor Global Control Register 0 (UPMGC0) .................................. 7-4

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Figures

Figure
Number Title

7-2 Local Control A Registers (PMLCa0–PMLCa3)/

User Local Control A Registers (UPMLCa0–UPMLCa3) ................................................7-5

7-3 Local Control B Registers (PMLCb0–PMLCb3)/

User Local Control B Registers (UPMLCb0–UPMLCb3) ................................................ 7-7

7-4 Performance Monitor Counter Registers (PMC0–PMC3)/

User Performance Monitor Counter Registers (UPMC0–UPMC3)................................... 7-8

8-1 TAP Controller with Supported Registers...............................................................................8-4

9-1 Relationship of Timer Facilities to Time Base........................................................................9-2

10-1 Vec t o r an d Fl o a t i n g -Point AP U s...... .............. ............... ........ .............. .............. .............. ...... 10 -2

10-2 Floating-Point Data Format .................................................................................................. 10-5

11-1 Cache/Core Interface Unit Integration.................................................................................. 11-3

11-2 L1 D at a Ca ch e Organizat i o n................ ........ ............... .............. ........ .............. .............. ........ 11-6

11-3 L1 In structi o n Cache Organiz ation ............ .............. ............... .............. ........ .............. .......... 11-7

11-4 PLRU Replacement Algorithm........................................................................................... 11-26

12-1 Effective-to-Real Address Translation Flow (e500v1) ......................................................... 12-4

12-2 Effective-to-Real Address Translation Flow (e500v2) ......................................................... 12-5

12-3 Virtual Address and TLB-Entry Compare Process............................................................... 12-7

12-4 Two-Level MMU Structure.......... ........ .............. ............... ........ .............. .............. ........ ........ 12-8

12-5 L1 MMU TLB Organization............................................................................................... 12-10

12-6 L2 MMU TLB Organization—e500v1............................................................................... 12-11

12-7 L2 MMU TLB Organization—e500v2............................................................................... 12-12

12-8 Round Robin Replacement for TLB0—e500v1 ................................................................. 12-14

12-9 Round Robin Replacement for TLB0—e500v2 ................................................................. 12-14

12-10 L1 MMU TLB Relationships with L2 TLBs ...................................................................... 12-15

12-11 MAS Regist e r 0 (MA S 0 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-26

12-12 MAS Regist e r 1 (MA S 1 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-27

12-13 MAS Regist e r 2 (MA S 2 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-28

12-14 MAS Regist e r 3 (MA S 3 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-29

12-15 MAS Regist e r 4 (MA S 4 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-30

12-16 MAS Regist e r 6 (MA S 6 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-31

12-17 MAS Regist e r 7 (MA S 7 ) ... ........ ........ ........ .............. ......... ........ .............. ........ .............. ...... 12-31

13-1 CCB Interface Signals...........................................................................................................13-2

C-1 Branch Conditional (bc) Instructio n F o rm a t..................... .............. ........ .............. .............. ....C- 4

C-2 BO Field (Bits 6–10 of the Instruction Encoding). .................................................................C-6

C-3 BI Field (Bits 11–14 of the Instruction Encoding)..................................................................C-9

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Figures

Figure
Number Title

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Tables

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Number Title

Tabl e s

Page

Number

1-1 Revi sion Leve l -t o - D e v i c e Marking Cross-Re ference..... ........ .............. .............. ........ ............ 1-5

1-2 Perf o rmance Mon itor APU In st ruction s ...... ........ ............... .............. ........ .............. .............. 1-12

1-3 Cache Locking APU Instructions ......................................................................................... 1-12

1-4 Scalar and Vector Embedded Floating-Point APU Instructions ...........................................1-13

1-5 BTB Lo c k i n g A PU Instruc t i o n s......... ........ .............. ............... ........ .............. ........ .............. .. 1-14

1-6 Interrupt Registers................................................................................................................. 1-22

1-7 Interrupt Vector Registers and Exception Conditions........................................................... 1-23

2-1 Book E Special-Purpose Registers (by SPR Abbreviation).................................................... 2-6

2-2 Im p l e m e n t a t i o n -S p e cific SPRs (by SP R Abbreviat io n ).......... .......... .....................................2-8

2-3 MSR F ield Descr iptions....... .............. ........ .............. ............... ........ .............. ........ .............. .. 2-11

2-4 PVR Field Descriptions ........................................................................................................ 2-13

2-5 TCR Implementation-Specific Field Descriptions................................................................ 2-15

2-6 ATBL Field Descriptions ......................................................................................................2-17

2-7 ATBU F ield Descr ipt ions............... .............. ........ ............... .............. ........ .............. ..............2-17

2-8 IVOR Assignments ............................................................................................................... 2-19

2-9 ESR F i e l d Des c riptions.. ........ .............. ........ ............... .............. ........ .............. .............. ........ 2-21

2-10 MCSR Field Descriptions.....................................................................................................2-23

2-11 BBE AR F i e l d Descriptio n s.. ........ .............. ........ ............... ........ .............. .............. ........ ........ 2-25

2-12 BBTAR Field Des criptions ...... ........ ........ .............. ......... .............. ........ .............. .............. .... 2-25

2-13 BUCSR Field Descriptions................................................................................................... 2-26

2-14 HID0 Field Descriptions ....................................................................................................... 2-27

2-15 HID1 Field Descriptions ....................................................................................................... 2-29

2-16 L1CSR0 Field Descriptions .................................................................................................. 2-32

2-17 L1CSR1 Field Descriptions .................................................................................................. 2-33

2-18 L1CFG0 Fiel d Descript ion s ........... ........ .............. ............... ........ .............. ........ .............. ...... 2-34

2-19 L1CFG1 Fiel d Descript ion s ........... ........ .............. ............... ........ .............. ........ .............. ...... 2-35

2-20 MM U CS R 0 Field Desc ri p t i o n s........ ........ .............. ............... ........ .............. .............. ........ .... 2-3 6

2-21 MMUCFG Field Descriptions .............................................................................................. 2-37

2-22 TL B0 CF G F i e l d Descriptio n s.. .............. ........ ............... ........ .............. ........ .............. ............ 2-38

2-23 TL B1 CF G F i e l d Descriptio n s.. ........ .............. ............... ........ .............. ........ .............. ........ .... 2-39

2-24 MAS0 Field Descriptions—MMU Rea d /Write and Replacement Control .................... .... .. 2- 40

2-25 MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 2-41

2-26 MAS2 Field Descriptions—EPN and Page Attributes .........................................................2-42

2-27 MAS3 Field Descriptions—RPN and Access Contr ol . .... .... .... .... .... .... .... .... .... .... .... .... .... .... 2-43

2-28 MAS4 Field Descriptions—Hardware Replacement Assist Configuration..........................2-44

2-29 MAS 6 Fi el d D e scriptio n s........... .............. ........ ............... .............. ........ .............. .............. .... 2-45

2-30 MAS 7 Fi el d D e scriptio n s— H i g h -Order RPN ......... ......... .............. .............. ........ .............. .. 2-45

2-31 DBCR0 Field Descriptions ................................................................................................... 2-46

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2-32 DBCR1 Implementation-Specific Field Descriptions...........................................................2-46

2-33 DBCR2 Implementation-Specific Field Descriptions...........................................................2-47

2-34 DBSR Implementation-Specific Field Descriptions............................................................. 2-48

2-35 SPEFSCR Field D e scripti o n s..... ........ .............. ............... ........ .............. .............. ........ .......... 2-50

2-36 Pe rforman ce Mo n i t o r Re g i sters—Supervisor Leve l................... ........ .............. .............. ...... 2-52

2-37 Performance Monitor Registers—User Level (Read-Only) .................................................2-53

2-38 PMG C0 Field Des criptions.. .............. ........ .............. ............... ........ .............. .............. ........ .. 2-54

2-39 PMLCa0–PMLCa3 Fiel d Des c riptions.. ........ ............... ........ .............. ........ .............. ........ .... 2-5 5

2-40 PMLCb0–PMLCb3 Field Descriptions ................................................................................2-56

2-41 PMC0–PMC3 Field Descriptions ......................................................................................... 2-57

2-42 Sy n c h ron ization Req u i rements for SPRs... ........ ......... .............. ........ .............. .............. ........ 2-58

3-1 Add ress Characteris t ics of Aligne d Ope r a n d s ..... ......... .............. ........ .............. .............. ........ 3-2

3-2 Unsupported Book E Instructions (32-Bit) .............................................................................3-4

3-3 Data Access Synchronization Requirements ............................ .... ...... .... ...... .... ...... .... ...... .... .. 3- 8

3-4 Synchronization Requirements for e500-Specific SPRs......................................................... 3-8

3-5 Ins t ruction Fe t c h an d /or Executi o n Syn chroniz at ion Requi rements... ........ .............. ........ ...... 3-9

3-6 Integ er Arithm e t i c In structi o n s .. .............. .............. ............... ........ .............. .............. ............ 3-14

3-7 Integ er 32-Bi t Compare Instructi o n s (L = 0) ......... ......... .............. .............. .............. ........ .... 3-1 5

3-8 Integ er Logical Instr u ct ions ... ........ ........ .............. ............... ........ .............. .............. ........ ...... 3-15

3-9 Integ er Rotate In structi o n s ..... .............. .............. ............... ........ .............. .............. ................ 3-16

3-10 Int e g er Shift In structio n s........ .............. .............. ............... ........ .............. .............. ................ 3-16

3-11 Int e g er Load In st ructio n s . .............. .............. ............... .............. .............. .............. ................ 3-20

3-12 Int e g er Store In st ru ctions ................. .................... ............... .............. .............. .............. ........3-21

3-13 Integer Load and Store with Byte-Reverse Instructions.......................................................3-22

3-14 Integer Load and Store Multiple Instructions....................................................................... 3-23

3-15 BO Bi t De sc r iptions ........... ........ .............. ........ ........ ............... ........ .............. ........ ................3-23

3-16 BO Op e rand Encod i n g s . ........ .............. ........ ............... ........ .............. .............. ........ ..............3-23

3-17 Br an c h In structi o n s ...... ........ ........ .............. .............. ............... ........ .............. .............. ..........3-24

3-18 Condition Register Logical Instructions ............................................................................... 3-25

3-19 Trap Ins t ru ctions .......... ........ .............. .............. ............... ........ .............. .............. .................. 3-25

3-20 System Linkage Instruction ..................................................................................................3-26

3-21 Move to/from Condition Register Instructions .....................................................................3-26

3-22 Move to/from Special-Purpose Register Instructions...........................................................3-26

3-23 Book E Special-Purpose Registers (by SPR Abbreviation).................................................. 3-27

3-24 I m p l e m e n t ation-Speci fic SPRs (by SPR Abb reviation ).......... ........................................ .....3-29

3-25 Memory Synchronization Instructions.................................................................................. 3-30

3-26 User-Level Cache Instructions.............................................................................................. 3-38

3-27 System Linkage Instructions—Supervisor-Level ................................................................. 3-40

3-28 Move to/from Machine State Register Instructions .............................................................. 3-40

3-29 Supervisor-Level Cache Management Instruction................................................................ 3-41

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3-30 TL B Man a g ement Instructi o n s .... ........ ........ ............... ........ .............. ........ .............. ........ ...... 3-41

3-31 Implementation-Specific Instructions Summary .................................................................. 3-43

3-32 e500-Specific Instructions (E xcept SPE and SPFP Instructions ).........................................3-43

3-33 Natural Alignment Boundaries for Extended Vector Instructions ........................................ 3-44

3-34 SPE APU Vector Multiply Instruction Mnemonic Structure ................................................3-52

3-35 Mnemonic Ext e n sions for Mu ltiply-A c cu mulate I n structi o n s...... .............. .............. ........ .... 3-5 3

3-36 SPE APU Vector In structio n s ........ .............. ........ ............... .............. .............. ........ .............. 3-53

3-37 Vector and Scalar Floating-Point APU Instructions ............................................................. 3-59

3-38 Int e g er Select APU Instru ction .................... ............... .............. .............. .............. .............. .. 3-60

3-39 Pe rforman ce Mo n i t o r A P U In st ruction s ...... ............... .............. ........ .............. .............. ........ 3-60

3-40 e500-Defined PMR Encodings ............................................................................................. 3-61

3-41 Cache Locking APU Instructions ......................................................................................... 3-61

3-42 Machine Check APU Instruction .......................................................................................... 3-63

3-43 Branch Target Buffer (BTB) Instructions ............................................................................. 3-63

3-44 List of Instructions ................................................................................................................ 3-66

4-1 Load a n d Stor e Q u eu e s .... ........ .............. ........ ............... .............. ........ .............. ........ ............ 4-26

4-2 The E ffec t o f O p erand Size o n Div i d e Latency....... ............... .............. ........ .............. .......... 4-27

4-3 Bran c h O p eration Executio n Lat e n cies........ ............... ........ .............. .............. ........ .............. 4-31

4-4 System Operation Ins t ru ction Execution Latencie s ............ .............. .............. ........ .............. 4-31

4-5 Condition Register Logical Execution Latencies.................................................................. 4-33

4-6 SU and MU PowerPC Instruction Execution Latencies ....................................................... 4-33

4-7 LSU In structi o n Latencie s . ........ .............. .............. ......... .............. .............. .............. ........ ....4-35

4-8 SPE and Embedded Floating-Point APU Instruction Latencies ...........................................4-38

4-9 Natural Alignment Boundaries for Extended Vector Instructions........................................4-49

4-10 Dat a Ca ch e Mi ss, L2 Cach e H i t Timing .............. ......... .............. .............. ........ .............. ...... 4-50

5-1 SPE APU Unavailable Interrupt Generation When MSR[SPE] = 0.......................................5-3

5-2 Interrupt Registers Defined by the PowerPC Architecture..................................................... 5-5

5-3 Exception Syndrome Register (ESR) Definition .................................................................... 5-6

5-4 Machine Check Syndrome Register (MCSR) Field Descriptions ..........................................5-7

5-5 Asynchronous and Synchronous Interrupts. ........................................................................... 5- 9

5-6 Interrupt and Ex c eption Types ..... ........ .............. ............... ........ .............. .............. ........ ........ 5-12

5-7 Critical Input Interrupt Register Settings..............................................................................5-14

5-8 e500 Machine Check Exception Sources................. ......................................... .................... 5- 15

5-9 Machine Check Interrupt Settings......................................................................................... 5-16

5-10 Pa ri t y Error Excep tion Sce n arios..... ........ .............. ............... .............. ........ .............. ............ 5-17

5-11 Data Storage Interrupt Exception Conditions .......... ................................. ................ ............ 5- 19

5-12 Dat a Stor a g e I n terrupt R eg i ster Setti n g s...... ............... ........ .............. ........ .............. .............. 5-20

5-13 Instruction Storage Interrupt Exception Conditions ............................................................. 5-20

5-14 Instruction Storage Interrupt Register Settings..................................................................... 5-21

5-15 External Input Interrupt Register Settings ............................................................................ 5-22

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Number Title

5-16 Alignment Interrupt Register Settings .................................................................................. 5-23

5-17 Pro g ram Inter ru p t Ex c eption Con d i t ions............. ......... .............. .............. ........ .............. ...... 5-24

5-18 Pro g r a m In t e r ru p t Re g i ster Sett ing s....... ........ ............... ........ .............. .............. ........ ............ 5- 24

5-19 System Call Interrupt Register Settings................................................................................ 5-25

5-20 Dec r e m e n t e r In t e r ru p t Re g i ster Sett in g s.... ........ ......... .............. .............. ........ .............. ........ 5-25

5-21 Fixed-Interval Timer Interrupt Register Settings.................................................................. 5-26

5-22 Watchdog Timer Interrupt Register Settings......................................................................... 5-27

5-23 Dat a TLB Error Interrupt Ex ception Co n d i tions ..... ......... .............. .............. ........ .............. .. 5-27

5-24 Data TLB Error Interrupt Register Settings..........................................................................5-28

5-25 M MU A ssist Register Field Updates fo r TLB Error Inter ru p t s............... .. .......... .................5-28

5-26 Instruction TLB Error Interrupt Exception Conditions .........................................................5-29

5-27 Instructi o n TLB Error In t errupt Re g is ter Setti n g s .......... .............. .............. .............. ............ 5- 2 9

5-28 Debug Interrupt Register Settings......................................................................................... 5-30

5-29 SPE/Embedded Floating-Point APU Unavailable Interrupt Regi st er Settings.....................5-31

5-30 Embedded Floating-Point Data Interrupt Register Settings.................................................. 5-32

5-31 Embedded Floating-Point Round Interrupt Register Settings............................................... 5-33

5-32 Op erations to Avoid ............. ........ .............. .............. ......... .............. ........ .............. ................5-36

6-1 Power Management Signals of Core Complex....................................................................... 6-1

6-2 Core Power States ................................................................................................................... 6-3

6-3 Core Power Management Control Bits ................................................................................... 6-3

7-1 Perf o rmance Mon itor Registers–Supervisor Level..... ........ .............. ........ .............. .............. .. 7-2

7-2 Performance Monitor Registers–User Level (Read-Only).....................................................7-3

7-3 PMGC0 F ield Descr iptions.......... ........ .............. ......... .............. .............. ........ .............. ........ ..7-4

7-4 PML Ca 0 – P MLCa3 Fiel d Descriptio n s.. ........ ............... ........ ........ .............. ........ .............. ...... 7-6

7-5 PMLCb0–PMLCb3 Field Descriptions ..................................................................................7-7

7-6 PMC0–PMC3 Field Descriptions ........................................................................................... 7-8

7-7 Perf o rmance Mon itor APU In st ruction s ...... ........ ............... .............. ........ .............. ........ ........ 7-9

7-8 Proc essor States and PMLCa0–PM LCa3 Bit Set t ing s........ .............. ........ .............. ........ ...... 7-11

7-9 Event Types ........................................................................................................................... 7-13

7-10 Pe rforman ce Mo n i t o r Ev ent Selec t i o n............... ............... ........ .............. .............. .............. .. 7-13

8-1 Debug SPRs ................................................................................................... ............ ............. 8-1

8-2 Debug Interrupt Register Settings........................................................................................... 8-3

8-3 DBCR0 and DBSR Field Differences..................................................................................... 8-4

8-4 TAP/IEEE/JTAG Inte rface Si gnal Summary ........................ ...... ...... .... ...... ...... .... ...... ...... .... .. 8-5

8-5 JTAG Signal Details................................................................................................................8-6

8-6 Debug Events.......................................................................................................................... 8-7

8-7 Ins t ruction Ad d ress Compar e Mo d es....... ........ ............... ........ .............. .............. ........ ............ 8- 8

8-8 Data A d d ress Compar e Mo d es ........ ........ ........ ............... .............. ........ .............. ........ .......... 8-10

10-1 BT B Lo c k i n g A PU Instruc t i o n s......... ........ .............. ............... ........ .............. .............. ........ .. 10-2

11-1 Cache Line State Definitions .............................................................................................. 11-10

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Tabl e
Number Title

11-2 L1 D at a Ca ch e Coherency State Transiti o n s.......... ............... ........ .............. .............. ........ .. 11-10

11-3 L1 In structi o n Cache Cohe rency State Trans i tions......... .............. .............. .............. ...........11-11

11-4 Data Cache Snoop Coherency State Transitions....................... .......... ........ .......... .......... .... 11-12

11-5 Instruction Cache Snoop Coherency State Transitions....................................................... 11-12

11-6 Cache Instruction Comparison............................................................................................ 11-16

11-7 Failed Cache Events............................................................................................................ 11-17

11-8 L1 PLRU Replacement Way Selection ............................................................................... 11-25

11-9 PLRU Bit Update Rules...................................................................................................... 11-26

12-1 TL B Ma i n t e n an ce Programming Mod e l .................. ............... ........ .............. .............. ........ .. 12-3

12-2 Page Sizes for L1VSPs and TLB1 (L2 MMU) on the e500 Core.........................................12-6

12-3 Index of TLBs .......................................................................................................................12-9

12-4 TL B En t ry Bit Defi n it i o n s for e500... .............. ........ ............... .............. .............. ........ ........ 12-17

12-5 tlbivax EA Bit Definitions.................................................................................................. 12-21

12-6 TLB1 Entry 0 Values after Reset ........................................................................................ 12-25

12-7 Registers Used for MMU Functions ................................................................................... 12-25

12-8 MAS0 Field Descriptions—MMU Read/Write and Replacement Control ........................ 12-26

12-9 MAS1 Field Descriptions—Descriptor Context and Configuration Control...................... 12-27

12-10 MAS2 Field Descriptions—EPN and Page Attributes ....................................................... 12-28

12-11 MAS3 Field Descriptions–RPN and Access Control ............... .... .... .... .... .... .... .... .... .... .... .. 12-29

12-12 MAS4 Field Descriptions—Hardware Replacement Assist Configuration ................ ........ 12-30

12-13 MAS6—TLB Search Context Register 0............................................................................ 12-31

12-14 MAS7 Fiel d De scripti o n s— High Ord er RPN ..... ......... ........ .............. ........ .............. .......... 12-3 1

12-15 MMU Assist Re g i ster Fiel d Upd ates ... .............. ......... .............. ........ .............. ........ ............ 12 - 3 2

13-1 Su mm ary of Sele c t ed In ternal Si g n a l s ..... .............. ............... .............. .............. ........ ............ 13 -2

C-1 Sub tr ac t Im mediate Simplified Mnemon i c s ........ ......... ........ .............. ........ .............. ........ ......C-2

C-2 Sub tr ac t Simplified Mnemon ics......... ........ .............. ......... .............. ........ .............. ........ ..........C-2

C-3 Word Rotate and Shift Simplified Mnemonics.......................................................................C-3

C-4 Bran c h In structi o n s ...... ........ .............. ........ .............. ............... .............. ........ .............. ............C-4

C-5 BO Bit En c o d i n g s .... ........ ........ .............. ........ ............... ........ .............. .............. ........ ..............C-6

C-6 BO Op erand Encod i n g s . .............. ........ .............. ......... .............. ........ .............. ........ .............. ..C-6

C-7 CR0 and CR1 Fields as Updated by Integer Instructions .......................................................C-9

C-8 BI O p e ra n d Set t ings for CR Field s for Branch Comparisons........ .......................................C-1 0

C-9 CR Fie l d Id en t i fi c ation Symbols........ ........ .............. ......... ........ .............. ........ ........ ..............C-11

C-10 Branch Sim p lified Mn em o n ics .. ........ .............. ........ ............... ........ .............. ........ .............. ..C-11

C-11 Branch In structi o n s .................... .............. ........ ............... .............. ........ .............. ..................C-12

C-12 Si mplifie d Mnemonic s for bc and bca without LR Update..................................................C-13

C-13 Si mplifie d Mnemonic s for bclr and bcctr without LR Update............................................C-13

C-14 Si mplifie d Mnemonic s for bcl and bcla with LR U p d at e .......... ........ .............. .............. ...... C-14

C-15 Si mplifie d Mnemonic s for bclrl and bcctrl with LR Upd ate...... ........................................ .C -1 4

C-16 Standard Coding for Branch Conditions...............................................................................C-15

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Tabl e
Number Title

C-17 Branch Instructions and Simplified Mnemonics that Incorporate CR Conditions ...............C-16

C-18 Simpl i fi e d Mn emonics with Compariso n Con d i t i o n s...... .......... .............................. .............C-16

C-19 Simplified Mnemonics for bc and bca without Comparison Conditions or

LR Updating.....................................................................................................................C-17

C-20 Simplified Mnemonics for bclr and bcctr without Comparison Conditions

and LR Updating..............................................................................................................C-18

C-21 Simplified Mnemonics for bcl and bcla with Comparison Conditions

and LR Updating..............................................................................................................C-18

C-22 Simplified Mnemonics for bclrl and bcctrl with Comparison Conditions

and LR Updating..............................................................................................................C-19

C-23 Word Compare Simplified Mnemonics ................................................................................C-20

C-24 Condition Register Logical Simplified Mnemonics .............................................................C-20

C-25 Standard Codes for Trap Instructions....................................................................................C-21

C-26 Trap Simplif i e d Mn emonics ........ ........ .............. ......... .............. ........ .............. .............. ........C-22

C-27 TO Operand Bi t Encodin g ... .............. ........ .............. ......... .............. ........ .............. .............. ..C-23

C-28 Additional Simplified Mnemonics for Accessing SPRGs....................................................C-24

C-29 Simplified Mnemonics..........................................................................................................C-26

D-1 Instructions (Binary) by Mnemonic....................................................................................... D-1

D-2 Instr u ctions (Decim a l and Hexadecima l) b y Opc o d e................ .............................. ............D-22

D-3 Instructions (Binary) by Form.............................................................................................. D-35

E-1 Revision History .................................................................................................................... A-1

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About This Book

The primary objective of this user’s manual is to describe the functionality of the e500 embedded
microprocessor core for software and hardware developers. This book is intended as a companion
to the EREF: A Reference for Freescale Book E and the e500 Core (hereafter referred to as EREF).
The e500 is a PowerPC™ processor.

Note that, while previous versions of this manual covered only the e500v1 core (and referred to it
simply as the e500 core), this version includes coverage of both the e500v1 and e500v2 cores.
Where the two cores diverge, the differences are clearly delineated.

Book E is a PowerPC architecture definition for embedded processors that ensures binary
compatibility with the user-instruction set architecture (UISA) portion of the PowerPC
architecture as it was jointly developed by Apple, IBM, and Motorola. The version of the
architecture jointly developed by Apple, IBM, and Motorola is referred to as the AIM version of
the PowerPC architecture.

This document distinguishes between the three levels of the architectural and implementation
definition, as follows:

• The Book E architecture. Book E defines a set of user-level instructions and registers that
are drawn from the user instruction set architecture (UISA) portion of the AIM definition
PowerPC architecture. Book E also include numerous other supervisor-level registers and
instructions as they were defined in the AIM version of the PowerPC architecture for the
virtual environment architecture (VEA) and the operating environment architecture (OEA).

Because Book E defines a much different model for operating system resources (such as
the MMU and interrupts), it defines many new registers and instructions.

• Freescale Book E implementation standards. In many cases, the Book E architecture
definition provides a very general framework, leaving many higher-level details up to the
implementation. To ensure consistency among its Book E implementations, Freescale has
defined implementation standards that provide an additional layer of architecture between
Book E and the actual devices.

• e500 implementation details. Each processor typically defines instructions, registers, bits
within registers, and other aspects that are more detailed than either the Book E definition
or the Freescale Book E implementation standards.

This book describes all of the instructions and registers implemented on the e500, including
those defined by Book E and those that are e500-specific.

PowerPC e500 Core Family Reference Manual, Rev. 1

Freescale Semiconductor xxxi

Information in this book is subject to change without notice, as described in the disclaimers on the
title page of this book. As with any technical documentation, it is the readers’ responsibility to be
sure they are using the most recent version of the documentation.

Audience

It is assumed that the reader understands operating systems, microprocessor system design, and
the basic principles of RISC processing.

Organization

Following is a summary and a brief description of the major sections of this manual:

• Chapter 1, “Core Complex Overview,” provides a general description of e500
functionality.

• Chapter 2, “Register Model,” is useful for software engineers who need to understand the
programming model for the three programming environments and the functionality of each
register.

• Chapter 3, “Instruction Model,” provides an overview of the addressing modes and a
description of the instructions. Instructions are organized by function.

• Chapter 4, “Execution Timing,” describes how instructions are fetched, decoded, issues,
executed, and completed and how instruction results are presented to the processor and
memory system. Tables are provided that indicate latency and throughput for each of the
instructions supported by the e500.

• Chapter 5, “Interrupts and Exceptions,” describes how the e500 implements the interrupt
model as it is defined by the Book E architecture.

• Chapter 6, “Power Management,” describes the power management facilities as they are
defined by Book E and implemented in the e500 core.

• Chapter 7, “Performance Monitor,” describes the e500 implementation of the performance
monitor APU that is defined by the Freescale Book E implementation standards.

• Chapter 8, “Debug Support,” describes the debug facilities as they are defined by Book E
and implemented in the e500 core.

• Chapter 9, “Timer Facilities,” describes the Book E-defined timer facilities implemented in
the e500 core. These resources include the time base (TB), decrementer (DEC),
fixed-interval timer (FIT), and watchdog timer.

• Chapter 10, “Auxiliary Processing Units (APUs),” lists the extensions to the
Book E–defined programming model that are supported on the e500 and describes the
e500-specific branch target buffer locking APU.

• Chapter 11, “L1 Caches,” provides specific hardware and software details regarding the
e500 cache implementation.

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xxxii Freescale Semiconductor

• Chapter 12, “Memory Management Units,” provides specific hardware and software
details regarding the e500 MMU implementation.

• Chapter 13, “Core Complex Bus (CCB),” describes those aspects of the CCB that are
configurable or that provide status information through the programming interface. It
provides a glossary of those signals that are mentioned in other chapters to offer a clearer
understanding of how the core is integrated as part of a larger device.

• Appendix A, “Programming Examples,” provides example code for use of creating atomic
primitives with load and store with reservation instructions and for programming
multiple-precision shifts.

• Appendix B, “Guidelines for 32-Bit Book E,” provides a set of guidelines for software
developers. Application software written to these guidelines can be labelled 32-bit Book E
applications and can expect to execute properly on all implementations of Book E, both
32-bit and 64-bit implementations.

• Appendix C, “Simplified Mnemonics for PowerPC Instructions,” provides a set of
simplified mnemonic examples and symbols.

• Appendix D, “Opcode Listings,” lists opcodes by mnemonic and by opcode. It includes an
alphabetical listing that includes simplified mnemonics and the architecturally defined
instructions (with syntax) to which they map.

• Appendix E, “Revision History,” contains a revision history for this manual.

• This book also includes an index.

Suggested Reading

This section lists additional reading that provides background for the information in this manual
as well as general information about the architecture.

General Information

The following documentation, published by Morgan-Kaufmann Publishers, 340 Pine Street, Sixth
Floor, San Francisco, CA, provides useful information about the PowerPC architecture and
computer architecture in general:

• The PowerPC Architectur e: A Specification for a New Family of RISC Pr ocessors, Second
Edition, by International Business Machines, Inc.

For updates to the specification, see http://www.austin.ibm.com/tech/ppc-chg.html

• Computer Architectur e: A Quantitative Approach, Third Edition, by John L. Hennessy and
David A. Patterson.

• Computer Organization and Design: Th e Hardware/Software Interface, Second Edition,
David A. Patterson and John L. Hennessy.

PowerPC e500 Core Family Reference Manual, Rev. 1

Freescale Semiconductor xxxiii

Related Documentation

Freescale documentation is available from the sources listed on the back cover of this manual; the
document order numbers are included in parentheses for ease in ordering:

• EREF: A Refer ence for Fr eescale Book E and the e500 Core (EREF)—This book provides
a higher-level view of the programming model as it is defined by Book E, the Freescale
Book E implementation standards, and the e500 microprocessor.

• e500 Software Optimization Guide (eSOG) (AN2665)—This manual provides information
to programmers so that they may write optimal code for the e500.

• Reference manuals—These books provide details about individual implementations and
are intended for use with the EREF.

• Addenda/errata to reference manuals—Because some processors have follow-on parts, an
addendum is provided that describes the additional features and functionality changes.
These addenda are intended for use with the cor responding reference manuals.

• Hardware specifications—Hardware specifications provide specific data regarding bus
timing, signal behavior, and AC, DC, and thermal characteristics, as well as other design
considerations.

• Product briefs—Each device has a product brief that provides an overvie w of its features.
This document is roughly the equivalent to the overview (Chapter 1) of an
implementation’ s reference manual.

• Application notes—These short documents address specific design issues useful to
programmers and engineers working with Freescale processors.

Additional literature is published as new processors become available. For a current list of
documentation, refer to http://www.freescale.com

Conventions

This document uses the following notational conventions:
cleared/set When a bit takes the value zero, it is said to be cleared; when it takes a value

of one, it is said to be set.

mnemonics Instruction mnemonics are shown in lowercase bold.
italics Italics indicate variable command parameters, for example, bcctrx.

Book titles in text are set in i talics.

Internal signals are set in italics, for example, qual BG
0x0 Prefix to denote hexadecimal number
0b0 Prefix to denote binary number

.

rA, rB Instruction syntax used to identify a source GPR

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xxxiv Freescale Semiconductor

rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations for registers are shown in uppercase text. Specific bits, fields,

or ranges appear in brackets. For example, MSR[LE] refers to the

little-endian mode enable bit in the machine state register.
x In some contexts, such as signal encodings, an unitalicized x indicates a

don’t care.

x An italicized x indicates an alphanumeric variable.
n An italicized n indicates an numeric variable.

¬ NOT logical operator
& AND logical operator
| OR logical operator

0 0 0 0

Indicates reserved bits or bit fields in a register. Although these bits can be

written to as ones or zeros, they are always read as zeros.

Terminology Conventions

Table i lists certain terms used in this manual that differ from the architecture terminology

conventions.

Table i. Terminology Conventions

Architecture Specification This Manual

Change bit Changed bit

Extended mnemonics Simplified mnemonics

Out of order memory accesses Speculative memory accesses

Privileged mode (or privileged state) Supervisor level

Problem mode (or problem state) User level

Reference bit Referenced bit

Relocation Translation

Storage (locations) Memory

Storage (the act of) Access

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xxxvi Freescale Semiconductor

Part I
e500 Core

Part I specifically describes the e500 core, excluding details abo ut cache memories and MMU
features. It contains chapters that apply to the entire core, as follows:

• Chapter 1, “Core Complex Overview,” summarizes the e500 core. This a 32-bit
implementation of the Book E PowerPC architecture, including a recognition that different
processor implementations may require extensions or deviations from the architectural
descriptions.

• Chapter 2, “Register Model,” describes the e500 core register model as defined in Book E
and the additional implementation-specific registers unique to the e500 core, including a
Book E SPR model.

• Chapter 3, “Instruction Model,” provides information about the Book E architecture as it
relates specifically to the e500 core complex. The e500 core complex also implements
several APUs, which define additional instructions, registers, and interrupts. The chapter
also features operand conventions, branch prediction, memory access alignment support,
and memory synchronization sections.

• Chapter 4, “Execution Timing,” describes the e500 core’s operations performance as
defined by instructions and how it reports the results of instruction execution. It gives
detailed descriptions of how the core execution units work and how these units interact with
other parts of the processor , such as the instruction fetching mechanism, register files, and
caches. Included are examples of instruction sequences and tables that provide information
useful to assembly language programmers for optimizing performance.

• Chapter 5, “Interrupts and Exceptions,” is a general description of the Book E interrupt and
exception model and gives details of the additions and changes to that model that are
implemented in the e500 core complex.

• Chapter 6, “Power Management,” describes the hardware and software resources the
system uses to minimize its power consumption. This chapter regards the power
management facilities as they are defined by Book E and implemented in devices that
contain the e500 core, but its scope is limited to features of the core only.

• Chapter 7, “Performance Monitor,” describes the e500 implementation of the performance
monitor APU that is defined by the Freescale Book E implementation standards.

• Chapter 8, “Debug Support,” describes the e500 core complex internal debug capabilities
and associated features. Included are important deviations to the Book E debug mode.

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Par t I-2 Freescale Semiconductor

Chapter 1
Core Complex Overview

This chapter provides an overview of the PowerPC™ e500 microprocessor core.
References to e500 are true for both the e500v1 and e500v2.
This chapter includes the following:

• An overview of the Book E version of the PowerPC architecture features as implemented
in this core and a summary of the core feature set

• A summary of the instruction pipeline and flow

• An overview of the programming model

• An overview of interrupts and exception handling

• A description of the memory management architecture

• High-level details of the e500 core memory and coherency m odel

• A brief description of the core complex bus (C CB)

• A summary of the Book E architecture compatibility and migration from the original
version of the PowerPC architecture as it is defined by Apple, IBM, and Motorola (referred
to as the AIM version of the PowerPC architecture)

The e500 core provides features that the integrated device may not implement or may implement
in a more specific way.

1.1 Overview

The e500 processor core is a low-power implementation of the family of reduced instruction set
computing (RISC) embedded processors that implement the Book E definition of the Pow erPC
architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words
in the 64-bit general-purpose registers (GPRs).

Figure 1-1 is a block diagram of the processor core complex that shows how the functional units

operate independently and in parallel. Note that this conceptual diagram does not attempt to show
how these features are physically implemented.

PowerPC e500 Core Family Reference Manual, Rev. 1

Freescale Semiconductor 1-1

Core Complex Overview

Memory Unit

(12 instructions)

Instruction Queue

32-Kbyte I Cache

Tags

128-Bit

(TLB0)

64-Entry

I-L1TLB4K

L2 MMUs

L1 Instruction MMU

4-Entry

I-L1VSP

TLB Array

256/512-Entry

Unified

(TLB1)

16-Entry

TLB Array

MAS

Registers

(4 Instructions)

Queue (GIQ)

General Issue

64-Entry

D-L1TLB4K

Tags

Fill Buffer

Instruction Line

L1 Data MMU

4-Entry

D-L1VSP

Station

Reservation

GPR File

instruction per cycle.

(64/32 bit)

Load/Store Unit

Rename

Buffers (14)

32-Kbyte D Cache

e500v2 (9 entry)

e500v1 (4 entry)

Data Line

Buffer

Fill Buffer Data Write

e500v1 (3 entry)

Load Miss

Queue Queue

L1 Store

32-/

64-Bit

Core Interface Unit

Core Complex Bus

e500v2 (5 entry)

Instruction Unit

Additional Features

Fetch Stages

• Time Base Counter/Decrementer

GPR

Operand Bus

BTB

Each execution unit can accept one

Station

Reservation

512 Entry

(1 BIQ, 2 GIQ)

(64/32 bit)

Multiple Unit

Two Instruction Dispatch

LR

CTR

Branch Prediction Unit

• Clock Multiplier

• JTAG/COP Interface

• Power Management

• Performance Monitor

from the IQ to the CQ at dispatch.

Program order is maintained by passing instructions

Branch Issue

Two instruction issue to GIQ per clock

Station

Reservation

Queue (BIQ)

Station

Reservation

Condition

Station

One instruction issue to BIQ per clock

Reservation

(32 bit)

Simple Unit 2

(32/64 bit)

Simple Unit 1

Register

Rename

CR Field

Buffers (14)

Unit

Branch

Completion Bus

CRF Bus

Maximum

Two Instructions

Retire per Cycle

Completion Queue (14 Entry)

Figure 1-1. e500 Core Complex Block Diagram

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Book E allows processors to provide auxiliary processing units (APUs), which are extensions to
the architecture that can perform computational or system management functions. One of these on
the e500 is the signal processing engine APU (SPE APU), which includes a suite of vector
instructions that use the upper and lower halves of the GPRs as a single two-element operand.
Most APUs implemented on the e500 are defined by the Freescale Semiconductor Book E
implementation standards (EIS).

1.1.1 Upward Compatibility

The e500 provides 32-bit effective addresses and integer data types of 8, 16, and 32 bits, as defined
by Book E. It also provides two-element, 64-bit data types for the SPE APU and the embedded
vector floating-point APU, which include instructions that operate on operands comprised of two
32-bit elements. For detailed information regarding the e500 instruction set, see Chapter 3,

“Instruction Model.”

The embedded single-precision scalar floating-point APU provides 32-bit single-precision
instructions.

NOTE

The SPE APU and embedded floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these
instructions will not be supported in devices subsequent to
PowerQUICC III. Freescale Semiconductor strongly recommends
that use of these instructions be confined to libraries and device
drivers. Customer software that uses SPE or embedded floating-point
APU instructions at the assembly level or that uses SPE intrinsics will
require rewriting for upward compatibility with next-generation
PowerQUICC devices.

Freescale Semiconductor offers a libmoto_e500 library that uses SPE
instructions. Freescale will also provide libraries to support
next-generation PowerQUICC devices.

1.1.2 Core Complex Summary

The core complex is a superscalar processor that can issue two instructions and complete two
instructions per clock cycle. Instructions complete in order, but can execute out of order . Execution
results are available to subsequent instructions through the rename buffers, but those results are
recorded into architected registers in program order, maintaining a precise exception model. All
arithmetic instructions that execute in the core operate on data in the GPRs. Although the GPRs
are 64 bits wide, only SPE APU, DPFP (e500v2 only), and embedded vector floating-point
instructions operate on the upper word of the GPRs; the upper 32 bits are not affected by other
32-bit instructions.

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The processor core integrates two simple instruction units (SU1, SU2), a multiple-cycle
instruction unit (MU), a branch unit (BU), and a load/store unit (LSU).

The LSU and SU2 support 64- and 32-bit instructions.
The ability to execute five instructions in parallel and the use of simple instructions with short

execution times yield high efficiency and throughput. Most integer instructions execute in 1 clock
cycle. A series of independent vector floating-point add instructions can be issued and completed
with a throughput of one instruction per cycle.

The core complex includes independent on-chip, 32-Kbyte, eight-way set-associative, physically
addressed caches for instructions and data. It also includes on-chip first-level instruction and data
memory management units (MMUs) and an on-chip second-level unified MMU.

• The first-level MMUs contain two four-entry, fully-associative instruction and data
translation lookaside buffer (TLB) arrays that provide sup port for demand-paged virtual
memory address translation and variable-sized pages. They also contain two 64-entry,
4-way set-associative instruction and data TLB arrays that support 4-Kbyte pages. These
arrays are maintained entirely by the hardware with a true least-recently-used (LRU)
algorithm.

• The second-level MMU contains a 16-entry , fully-associative unified (instruction and data)
TLB array that provides support for variable-sized pages. It also contains a unified TLB for
4-Kbyte page size support, as follows:

— a 256-entry, 2-way set-associative unified TLB for the e500v1
— a 512-entry, 4-way set-associative unified TLB for the e500v2
These second-level TLBs are maintained completely by the software.

The core complex allo ws cache -line-based u ser-mode locks on th e conten ts in eithe r the instru ction
or data cache. This provides embedded applications with the capability fo r locking interrupt
routines or other im porta nt (time- sens itive) in struc tion sequ ence s into the inst ruction c ache . It al so
allows data to be locked into the data cache, which supp orts deterministic executi on time.

The core complex supports a high-speed on-chip internal bus with data tagging called the core
complex bus (CCB). The CCB has two general-purpose read data buses, one write data bus, data
parity bits, data tag bits, an address bus, and address attribute bits. The processor core complex
supports out-of-order reads, in-order writes, and one level of pipelining for addresses with
address-retry responses. It can also support single-beat and burst data transfers for memory
accesses and memory-mapped I/O operations.

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1.2 e500 Processor and System Version Numbers

Table 1-1 matches the revision code in the processor version register (PVR) and the system version

register (SVR). These registers can be accessed as SPRs through the e500 core (see Chapter 2,

“Register Model”) or as memory-mapped registers defined by the integrated device (s ee the

reference manual for the device).

Table 1-1. Revision Level-to-Device Marking Cross-Reference

SoC Revision

1.0 1.0 0x8020_0010 SoC-dependent value

1.1 2.0 0x8020_0020 SoC-dependent value

2.0 2.0 0x8021_0010 SoC-dependent value

e500v2 Core

Revision

Processor Version Register (PVR) System Version Register (SVR)

1.3 Features

Key features of the e500 are summarized as follows:

• Implements Book E 32-bit architecture

• Auxiliary processing units
The branch target buffer (BTB) locking APU is specific to the e500. The BTB locking APU

gives the user the ability to lock, unlock, and invalidate BTB entries; further information is
provided in Table 1-5 and Section 10.2, “Branch Tar get Buf fer (BTB) Locking APU.” The
EIS defines the following APUs:

— Integer select. This APU consists of the Integer Select instruction, isel, which is a

conditional register move that helps eliminate conditional branches, decreases latency,
and reduces the code footprint.

— Performance monitor. The performance monitor facility provides the ability to monitor

and count predefined events such as processor clocks, misses in the instruction cache or
data cache, types of instructions decoded, or mispredicted branches. The count of such
events can be used to trigger the performance monitor exception. Additional
performance monitor registers (PMRs) similar to SPRs are used to configure and track
performance monitor operations. These registers are accessed with the Move to PMR
and Move from PMR instructions (mtpmr and mfpmr). See Section 1.12,

“Performance Monitoring.”

— Cache locking. This APU allows instructions and data to be locked into their respective

caches on a cache block basis. Locking is performed by a set of touch and lock set
instructions. This functionality can be enabled for user mode by setting MSR[UCLE].
The APU also provides resources for detecting and handling overlocking conditions.

— Machine check. The machine check interrupt is treated as a separate level of interrupt.

It uses its own save and restore registers (MCSRR0 and MCSRR1) and Return from

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Machine Check Interrupt (rfmci) instruction. See Section 1.8, “Interrupts and

Exception Handling.”

— Single-precision embedded scalar and vector floating-point APUs. These instructions

are listed in Table 1-4.

— Signal processin g engine APU (SPE APU). Note th at the SPE is not a separate u nit; SPE

computation al and logical instructions are executed in the simple and multip le-cycle
units used by all oth er computational and logic al instructions, and 64 -bit loads and stores
are executed in the common LSU. Figure 1-1 shows how execution logic for SU 1, the
MU, and the LSU is replicated to support operations on the upper halves of the GPRs.

Note that the SPE APU and the two single-precision floating-point APUs were combined in the
original implementation of the e500 v1, as shown in Figure 1-2.

Vector and Floating-Point APUs e500 v1 e500 v2

Original SPE

Definition

SPE vector instructions ev…

Vector single-precision floating-point evfs…

Scalar single-precision floating-point efs…

Scalar double-precision floating-point efd…

√√

√√

√√

√

Figure 1-2. Vector and Floating-Point APUs

The e500 register set is modified as follows:
– GPRs are widened to 64 bits to support 64-bit load, store, and merge operations. Note

that the upper 32 bits are affected only by 64-bit instructions.
– A 64-bit accumulator (ACC) has been added.
– The signal processing and embedded floating-point status and control register

(SPEFSCR) provides interrupt control and status for SPE and embedded

floating-point instructions.
These registers are shown in Figure 1-7. SPE instructions are grouped as follows:
– Single-cycle integer add and subtract with the same latencies for SPE APU

operations as for the 32-bit equivalent
– Single-cycle logical operations
– Single-cycle shift and rotates
– Four-cycle integer pipelined multiplies
– 4-, 11-, 19-, and 35-cycle integer divides
–If rA or rB is zero, a floating-point divide take s 4 cycles; al l other ca ses take 29 cy cles.
– 4-cycle SIMD pipelined multiply-accumulate (MAC)
– 64-bit accumulator for no-stall MAC operations

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– 64-bit loads and stores
– 64-bit merge instructions

• Cache structure—Separate 32-Kbyte, 32-byte line, 8-way set-associative level 1 instruction
and data caches

— 1.5-cycle cache array access, 3-cycle load-to-use latency
— Pseudo-LRU (PLRU) replacement algorithm
— Copy-back data cache that can fu nction as a write-t hrough cache on a page-by-page basis
— Supports all Book E memory coherency modes
— Supports EIS-defined cache-locking instructions, as listed in Table 1-3

• Dual-issue superscalar control
— T wo-instructions-per-clock peak issue rate
— Precise exception handling

• Decode unit
— 12-entry instruction queue (IQ)
— Full hardware detection of interlocks
— Decodes as many as two instructions per cycle
— Decode serialization control
— Register dependency resolution and renaming

• Branch prediction unit (BPU)
— Dynamic branch prediction using a 512-entry, 4-way set-associative branch target

buffer (BTB) supported by the e500 BTB instructions listed in Table 1-5.

— Branch prediction is handled in the fetch stages.

• Completion unit
— As many as 14 instructions allowed in 14-entry completion queue (CQ)
— In-order retirement of as many as two instructions per cycle
— Completion and refetch serialization control
— Synchronization for all instruction flow changes—interrupts, mispredicted branches,

and context-synchronizing instructions

• Issue queues
— Two-entry branch instruction issue queue (BIQ)
— Four-entry general instruction issue queue (GIQ)

• Branch unit—The branch unit (BU) is an execution unit and is distinct from the BPU. It
executes (resolves) all branch and CR logical instructions.

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• Two simple units (SU1 and SU2)
— Add and subtract
— Shift and rotate
— Logical operations
— Support for 64-bit SPE APU instructions in SU1

• Multiple-cycle unit (MU)—The MU is shown in Figure 1-3.

From GIQ0 or GIQ1

Reservation

Station

Upper Lower

MU-1

MU-2

MU-3

MU-4

Divide Bypass Path

Divide

Postdivide

Figure 1-3. Four-Stage MU Pipeline, Showing Divide Bypass

The MU has the following features:
— Four-cycle latency for all multiplication, including SPE integer and fractional multiply

instructions and embedded scalar and vector floating-point multiply instructions

— V ariable-latency divide: 4, 11, 19, and 35 cycles for all integer divide instructions. If rA

or rB is zero, floating-point divide instructions take 4 cycles; all others take 29. Note
that although most divide instructions take more than 4 cycles to execute, the MU
allows subsequent multiply instructions to execute through all four MU stages in
parallel with the divide.

— 4-cycle floating-point add and subtract

• The load/store unit (LSU) is shown in Figure 1-4.
The LSU has the following features:
— 3-cycle load latency
— Fully pipelined
— Load miss queue allows up to four load misses before stalling (up to nine load misses

in the e500v2).
— Load hits can continue to be serviced when the load miss queue is full.
— The seven-entry L1 store queue allows full pipelining of stores.

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To completion queue

To GPR operand bus

To G P R s

Reservation

Station

Load/Store Unit

(64-/32-Bit)

Three-Stage Pipeline

Queues and Buffers

L1 Store

Queue Miss

Load

Queue

Core Complex Overview

To data cache

e500v1 (4 entry)

e500v2 (9 entr y)

e500v1 (3 entry)
e500v2 (5 entry)

Data Line

Fill Buffer

To core interface unit

Data Write

Buffer

Figure 1-4. Three-Stage Load/Store Unit

— The three-entry data line fill buffer (five-entry on the e500v2) is used for loads and

cacheable stores. Stores are allocated here so loads can access data from the store

immediately.
— The data write buffer contains three entries: one dedicated for snoop pushes, one

dedicated for castouts, and one that can be used for snoop pushes or cast outs.

• Cache coherency
— Supports four-state cache coherency: modified-exclusive, exclusive, shared, and invalid

(MESI). Note, however that shared state may not be accessible in some
implementations.

— Bus support for hardware-enforced coherency (bus snooping)

• Core complex bus (CCB)—internal bus
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— Address protocol with address pipelining and retry/copyback derived from bus used by

previous generations of PowerPC processors (referred to as the 60x bus)

— Two general-purpose read data buses and one write data bus

• Extended exception handling
— Supports Book E interrupt model

– Less than 10-cycle interrupt latency
– Interrupt vector prefix register (IVPR)

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– Interrupt vector offset registers (IVORs) 0–15 as defined in Book E, plus

e500-defined IVORs 32–35
– Exception syndrome register (ESR)
– Book E-defined preempting critical interrupt, including critical interrupt status

registers (CSRR0 and CSRR1) and an rfci instruction

— e500-specific interrupts not defined in Book E architecture

– Machine-check APU
– SPE APU unavailable exception
– Floating-point data exception
– Floating-point round exception
– Performance monitor

• Memory management unit (MMU)
— 32-bit effective address translated to 32-bit real address (using a 41-bit interim virtual

address) for the e500v1core and 36-bit real addressing for th e e500v2 core

— TLB entries for variable- (4-Kbyte–256-Mbyte pages for the e500v1 and

4-Kbyte–4-Gbyte pages for the e500v2) and fixed-size (4-Kbyte) pages

— Data L1 MMU

– 4-entry, fully associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages

— Instruction L1 MMU

– 4-entry, fully associative TLB array for variable-sized pages
– 64-entry, 4-way set-associative TLB for 4-Kbyte pages

— Unified L2 MMU

– 16-entry, fully associative TLB array for variable-sized pages
– e500v1—A 256-entry, 2-way set-associative unified (for instruction and data

accesses) L2 TLB array (TLB0) supports only 4-Kbyte pages

– e500v2—A 512-entry, 4-way set-associative unified (for instruction and data

accesses) L2 TLB array (TLB0) supports only 4-Kbyte pages

— Software reload for TLBs

32

— Virtual memory support for as much as 4 Gbytes (2
— Real memory support for as much as 4 Gbytes (2

36

and 64 Gbytes (2

) on the e500v2

) of effective address space

32

) of physical memory on the e500v1

— Support for big-endian and true little-endian memory on a per-page basis

• Power management

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— Low-power design
— Power-saving modes: core-halted and core-stopped
— Internal clock multipliers ranging from 1 to 8 times the bus clock, including integer and

half-mode multipliers.
— Dynamic power management of execution units, caches, and MMUs
— NAP, DOZE, and SLEEP bits in HID0 can be used to assert nap, doze, and sleep output

signals to initiate power-saving modes at th e integrated device level.

• Testability
— LSSD scan design
— JT AG interface
— ESP support
— Nexus debug support

• Reliability and serviceability
— Parity checking on caches
— Parity checking on e500 local bus

1.3.1 e500v2 Differences

The e500v2 provides the following additional features not supported by the e500v1:

• The e500v2 uses 36-bit physical addressing, which is supported by the following:
— MMU assist register 7 (MAS7)
— HID0[EN_MAS7_UPDATE]
— Programmable jumper options to specify the upper bits of the reset vector.

• The e500v2 has a 512-entry, 4-way set-associative unified TLB for TLB1.

• The maximum variable page size is extended to 4 Gbytes.

• Embedded double-precision floating-point APU has been added. These instructions use the
64-bit GPRs as single, 64-bit double-precision operands. This APU is enabled through
MSR[SPE].

• Slightly different functionality of HID1[RFXE] bit.

• The data line fill buffer in the LSU is expanded from three to five entries.

• The load miss queue in the LSU is expanded from four to nine entries.

• TBSEL and TBEE bits have been added to the performance monitor global control
register 0 (PMGC0) to support monitoring of time base events.

• Minor modifications to the SPE APU.

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• Data cache flush assist capability , supported through HID0[DCFA]. When DCF A is set, the
cache miss replacement algorithm ignores invalid entries and follows the replacement
sequence defined by the PLRU bits. This reduces the series of uniquely addressed load or
dcbz instructions required to flush the cache.

Detailed descriptions of these differences are pr ovided in their respective chapters.

NOTE

Unless otherwise indicated, references to e500 apply to both e500v1
and e500v2.

1.4 Instruction Set

The e500 implements the following instructions:

• The Book E instruction set for 32-bit implementations. This is composed primarily of the
user-level instructions defined by the PowerPC user instru ction set architecture (UISA).
The e500 does not include Book E floating-point, load string, or store string instructions.

• The e500 supports the following implementation-specific instructions:
— Integer select APU. This APU consists of the Integer Select instruction (isel), which

functions as an if

-then-else statement that selects between two source registers by

comparison to a CR bit. This instruction eliminates conditional branches, decreases
latency, and reduces the code footprint.

— Performance monitor APU. Table 1-2 lists performance monitor APU instructions.

Table 1-2. Performance Monitor APU Instructions

Name Mnemonic Syntax

Move from Performance Monitor Register mfpmr rD,PMRN

Move to Performance Monitor Register mtpmr PMRN,rS

— Cache locking APU. This APU consists of the instructions described in Table 1-3.

Table 1-3. Cache Locking APU Instructions

Name Mnemonic Syntax

Data Cache Block Lock Clear dcblc CT, rA, rB

Data Cache Block Touch and Lock Set dcbtls CT, rA, rB

Data Cache Block Touch for Store and Lock Set dcbtstls CT, rA, rB

Instruction Cache Block Lock Clear icblc CT, rA, rB

Instruction Cache Block Touch and Lock Set icbtls CT, rA, rB

— Machine check APU. This APU defines the Return from Machine Check Interrupt

instruction (rfmci).

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— SPE APU vector instructions. V ector instructions are defined that view the 64-bit GPRs

as composed of a vector of two 32-bit elements (some instructions also read or write
16-bit elements). Some scalar instructions produce a 64-bit scalar result.

Sectio n 3.8.1.3, “SPE APU Instructio n s ,” lists SPE APU vector instructions.

— The embedded floating-point APUs provide scalar and vector floating-point

instructions. Scalar single-precision floating-point instructions use only the lower 32
bits of the GPRs; double-precision operands (e500v2 only) use all 64 bits. Table 1-4
lists embedded floating-point instructions.

Table 1-4. Scalar and Vector Embedded Floating-Point APU Instructions

Instruction

Scalar SP Scalar DP Vector

Convert Floating-Point Single- from Double-Precision —efscfd — rD,rB

Convert Floating-Point Double- from Single-Precision —efdcfs — rD,rB

Convert Floating-Point from Signed Fraction efscfsf efdcfsf evfscfsf rD,rB

Convert Floating-Point from Signed Fraction efscfsf efdcfsf evfscfsf rD,rB

Convert Floating-Point from Signed Integer efscfsi efdcfsi evfscfsi rD,rB

Convert Floating-Point from Unsigned Fraction efscfuf efdcfuf evfscfuf rD,rB

Convert Floating-Point from Unsigned Integer efscfui efdcfui evfscfui rD,rB

Convert Floating-Point to Signed Fraction efsctsf efdctsf evfsctsf rD,rB

Convert Floating-Point to Signed Integer efsctsi efdctsi evfsctsi rD,rB

Convert Floating-Point to Signed Integer with Round toward Zero efsctsiz efdctsiz evfsctsiz rD,rB

Convert Floating-Point to Unsigned Fraction efsctuf efdctuf evfsctuf rD,rB

Convert Floating-Point to Unsigned Integer efsctui efdctui evfsctui rD,rB

Convert Floating-Point to Unsigned Integer with Round toward Zero efsctuiz efdctuiz evfsctuiz rD,rB

Floating-Point Absolute Value efsabs efdabs evfsabs rD,rA

Floating-Point Add efsadd efdadd evfsadd rD,rA,rB

Floating-Point Compare Equal efscmpeq efdcmpeq evfscmpeq crD,rA,rB

Floating-Point Compare Greater Than efscmpgt efdcmpgt evfscmpgt crD,rA,rB

Floating-Point Compare Less Than efscmplt efdcmplt evfscmplt crD,rA,r

Floating-Point Divide efsdiv efddiv evfsdiv rD,rA,rB

Floating-Point Multiply efsmul efdmul evfsmul rD,rA,rB

Floating-Point Negate efsneg efdneg evfsneg rD,rA

Floating-Point Negative Absolute Value efsnabs efdnabs evfsnabs rD,rA

Floating-Point Subtract efssub efdsub evfssub rD,rA,rB

Floating-Point Test Equal efststeq efdtsteq evfststeq crD,rA,rB

Floating-Point Test Greater Than efststgt efdtstgt evfststgt crD,rA,rB

Floating-Point Test Less Than efststlt efdtstlt evfststlt crD,rA,rB

Mnemonic

Syntax

B

— BTB locking APU instructions. The core complex provides a 512-entry BTB for

efficient processing of branch instructions. The BTB is a branch target address cache,

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organized as 128 rows with 4-w ay set associativity, that holds the address and target
instruction of the 512 most-recently taken branches. Table 1-5 lists BTB instructions.

Table 1-5. BTB Locking APU Instructions

Name Mnemonic Syntax

Branch Buffer Load Entry and Lock Set bblels —

Branch Buffer Entry Lock Reset bbelr —

1.5 Instruction Flow

The e500 core is a pipelined, superscalar processor with parallel execution units that allow
instructions to execute out of order but record their results in order. Pipelining breaks instruction
processing into discrete stages, so multiple instructions in an instruction sequence can occupy the
successive stages: as an instruction completes one stage, it passes to the next, leaving the previous
stage available to a subsequent instruction. So, even though it may take multiple cycles for an
instruction to pass through all of the pipeline stages, once a pipeline is full, instruction throughput
is much shorter than the latency.

A superscalar processor is one that issues multiple independent instructions into separate
execution units, allowing parallel execution. The e500 core has five execution units, one each for
branch (BU), load/store (LSU), and multiple-cycle operations (MU), and two for simple arithmetic
operations (SU1 and SU2). The MU and SU1 arithmetic execution units also execute 64-bit SPE
vector instructions, using both the lower and upper halves of the 64-bit GPRs.

The parallel execution units allow multiple instructions to execute in parallel and out of order. For
example, a low-latency addition instruction that is issued to an SU after an integer divide is issued
to the MU should finish executing before the higher latency divide instruction. The add instruction
can make its results available to a subsequent instruction, but it cannot update the architected GPR
specified as its target operand ahead of the multiple-cycle divide instruction.

1.5.1 Initial Instruction Fetch

The e500 core begins execution at fixed virtual address 0xFFFF_FFFC. The MMU has a default
page translation which maps this to the identical physical address. So, the instruction at physical
address 0xFFFF_FFFC must be a branch to another address within the 4-Kby te boot page.

1.5.2 Branch Detection and Prediction

To improve branch performance, the e500 provides implementation-specific dynamic branch
prediction using the BTB to resolve branch instructions and improve the accuracy of branch
predictions. Each of the 512 entries in the 4-way set associative address cache of branch target
addresses includes a 2-bit saturating branch history counter, whose value is incremented or
decremented depending on whether the branch was taken. These bits can take on four values

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indicating strongly taken, weakly taken, weakly not taken, and strongly not taken. The BTB is used
not only to predict branches, but to detect branches during the fetch stage, offering an efficient way
to access instruction streams for branches predicted as taken.

In the e500, all branch instructions are assigned positions in the completion queue at dispatch.
Speculative instructions in branch target streams are allo wed to execute and proceed through the
completion queue, although they can complete only after the branch prediction is resolved as
correct and after the branch instruction itself completes.

If a branch resolves as correct, instructions in the target stream are marked nonspeculative and are
allowed to complete. If the branch history bits in the BTB indicated weakly taken or weakly not
taken, the prediction is upgraded to strongly taken or strongly not taken.

If a br anch resolves as incorr ect, instru ctions in the target s tream are flushed from the executio n
pipel ine, the bran ch history b its are updated in the BTB entry, and nonspeculative fetching begins
from t he correct path.

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1.5.3 e500 Execution Pipeline

The seven stages of the e500 execution pipeline—fetch1, fetch2/predecode, decode/dispatch,
issue, execute, complete, and write back—are highlighted in grey in Figure 1-5.

Indicates stages

At dispatch, instructions are deallocated from the

IQ and assigned sequential positions in the CQ.

Issue Stage

Branch Issue Queue (BIQ)

Execute Stage

LSU Stage 1

BU

Execute

BU

Finish

Stage 2

Stage 3

General Issue Queue (GIQ)

MU Stage 1

Stage 2

Stage 3

Stage 4

Fetch Stage 1

Fetch Stage 2

Decode Stage

Maximum two-instruction per cycle dispatch
to the issue queues. BIQ can accept one
per cycle; GIQ can accept at most two.

Divide Bypass

Divide

Postdivide

Instruction Cache

Maximum four-instruction
fetch per clock cycle

SU1

SU2

Completion Stage

Write-Back Stage

Maximum two-instruction
completion per clock cycle

Figure 1-5. Instruction Pipeline Flow

The common pipeline stages are as follows:

• Instr ucti on fetch —I nclu de s the cl oc k cycl es neces sa ry to re que st an in st ruct io n and th e ti me
the mem ory syste m take s to respo nd to th e reques t. Instr ucti ons retr ieved ar e latc hed into the
instr uction queu e (IQ) for subsequent consideratio n by the dispatcher.

Instructio n fetch timi ng dep ends on many vari ables, s uch as wheth er an instructio n is in the
on-chip inst ruction cache or an L2 cache ( if implemented) . Those facto rs increas e when it is
necessary to fetch i nstr uctions f rom s ystem mem ory a nd includ e the process or -to-bus clo ck
ratio, the amount of bus traffic, and wheth er any cache coherency operations are required.

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Core Complex Overview

Because there are so many variables, unless otherwise specified, the instruction timing
examples in this chapter assume optimal performance and show the po rtion of the fetch
stage in which the instruction is in the instruction queue. The fetch1 and fetch2 stages are
primarily involved in retrieving instructions.

• The decode/dispatch stage fully decodes each instruction; most instructions are dispatched
to the issue queues (however, isync, rfi, sc, nops, and some other instructions do not go to
issue queues).

• The two issue queues, BIQ and GIQ, can accep t as many as one and two instructions,
respectively , in a cycle. The behavior of instruction dispatch is covered in significant detail
in the e500 Software Optimization Guide. The following simplification covers most cases:

— Instructions dispatch only from the two lowest IQ entries—IQ0 and IQ1.
— A total of two instructions can be dispatched to the issue queues per clock cycle.
— Space mu st be av aila ble in t he CQ for an i nstr uction to de code a nd di spatch (thi s inclu des

instructions that are assigned a space in the CQ but not in an issue queue).

Dispatch is treated as an event at the end of the decode stage. The issue stage reads source
operands from rename registers and register files and determines when instructions are
latched into the execution unit reservation stations. Note that the e500 has 14 rename
registers, one for each completion queue entry , so instructions cannot stall because of a
shortage of rename registers.

The general behavior of the two issue queues is described as follows:
— The GIQ accepts as many as two instructions from the dispatch unit per cycle. SU1,

SU2, MU, and all LSU instructions (including 64-bit loads and stores) are dispatched to
the GIQ, shown in Figure 1-6.

From IQ0/IQ1

GIQ3

GIQ2

GIQ1

GIQ0

To SU2, MU, or LSU

To SU1, MU, or LSU

Figure 1-6. GPR Issue Queue (GIQ)

Instructions can be issued out-of-order from the bottom two GIQ entries (GIQ1–GIQ0).
GIQ0 can issue to SU1, MU, and LSU. GIQ1 can issue to SU2, MU, and LSU.

Note that SU2 executes a subset of the instructions that can be executed in SU1. The
ability to identify and dispatch instructions to SU2 increases the availability of SU1 to
execute more computational-intensive instructions.

An instruction in GIQ1 destined for SU2 or the LSU need not wait for an MU
instruction in GIQ0 that is stalled behind a long-latency divide.

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Core Complex Overview

• The execute stage accepts instructions from its issue queue when the appropriate
reservation stations are not busy . In this stage, the operands assigned to the execution stage
from the issue stage are latched.

The execution unit executes the instruction (perhaps over multiple cycles), writes results on
its result bus, and notifies the CQ when the instruction finishes. The execution unit reports
any exceptions to the completion stage. Instruction-generated exceptions are not taken until
the excepting instruction is next to retire.

Most integer instructions have a 1-cycle latency, so results of these instructions are
available 1 clock cycle after an instruction enters the execution unit. The MU and LSU are
pipelined, as shown in Figure 1-5.

Branches resolve in execute stage. If a branch is mispredicted, it takes 5 cycles for the next
instruction to reach the execute stage.

• The complete and write-back stages maintain the correct architectural machine state and
commit results to the architecture-defined registers in the proper order. If completion logic
detects an instruction containing an exception status or a mispredicted branch, all following
instructions are cancelled, their execution results in rename registers are discarded, and the
correct instruction stream is fetched.

The complete stage ends when the instruction is retired. T wo instructions can be retired per
clock cycle. If no dependencies exist, as many as two instructions are retired in program
order. Section 4.7.4, “Completion Unit Resource Requirements,” describes completion
dependencies.

The write-back stage occurs in the clock cycle after the instruction is retired.

The e500 co re also provides new instructi ons that perform s ingle-instruc tion, multiple-d ata (SIMD)
operations . These signal proce ssing instructions co nsist of paralle l operations on both the upper and
lower 32 bits of tw o 64-bit GPR values and produce two 32-bit results written to a 64-bit GPR.

As shown in Figure 1-5, the LSU, MU, and SU1 replicate logic to support 64-bit operations.
Although a vector instruction generates separate, discrete results in the upper and lower halves of
the target GPR, latency and throughput for vector instructions are the same as those for their scalar
equivalents.

1.6 Programming Model

The following section describes the e500 core registers defined in Book E, the Freescale
Semiconductor Book E implementation standards (EIS), and registers that are specific to the e500.

Figure 1-7 shows the e500 register set.

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Core Complex Overview

User-Level Registers

General-Purpose Registers Instruction-Accessible Registers User General SPR (Read/Write)

0 31 32 63 0 31 32 63 32 63

(upper) GPR0 (lower)

GPR1

GPR2

General­purpose
registers

GPR31 spr 260 SPRG4

Performance Monitor PMRs (Read-Only)

pmr 384

pmr 0–3 UPMCs

pmr 128–131

pmr 256–259 UPMLCbs

UPMGC0

UPMLCas

L1 Cache (Read-Only)

spr 515

L1CFG0

L1CFG1

1

Global control register

1

Counter
registers 0–3

1

Local control registers

1

a0–a3, b0–b3

1

L1 cache
configuration reg isters

1

0–1spr 516

CR Cond ition register

spr 9

CTR

Count register

spr 8 LR Link register spr 259 SPRG3

spr 1 XER Integer exception

spr 512 SPEFSCR

1

ACC

register

1

SPE FP status/control
register

Accumulator

Miscellaneous Registers

spr 513

spr 514

BBEAR

BBTAR

3

Branch buffer entry
address register

3

Branch buffer target
address register

spr 256 USPRG0

General SPRs (Read-Only)

• • •

spr 263 SPRG7

Time-Base Registers (Read-Only)

spr 268

spr 269

spr 526

spr 527

TBL

TBU

AT B L

AT BU

Supervisor-Level Registers

32 63 32 63 32 63

spr 63 IVPR

spr 26 SRR0

spr 27

SRR1

spr 58 CSRR0

spr 59 CSRR1

spr 570

MCSRR0

spr 571

MCSRR1

spr 62

ESR

spr 572 MCSR

spr 573

spr 61

MCAR

DEAR

Interrupt vector
prefix

Save/restore
registers 0/1

Critical SRR 0/1 Processor version spr 528

1

Machine check

1

SRR 0/1

Exception syndrome
register

1

Machine check
syndrome register

Machine check
address register

Data exception
address register

Debug Registers

spr 308 DBCR0

spr 309 DBCR1 spr 944 MAS7

spr 310 DBCR2 spr 1009 HID1

spr 304

DBSR

spr 312 IAC1

spr 313 IAC2

spr 316 DAC1

spr 317 DAC2

1

These registers are defined by the EIS

2

e500v2 only

3

These registers are e500-specific

Debug control
registers 0–2

Debug status register spr 633

Instruction ad dress
compare
registers 1 and 2

Data address
compare
registers 1 and 2

Interrupt Registers Configuration Registers

spr 400 IVOR0

spr 401 IVOR1

• • •

Interrupt vector offset
registers 0–15

spr 415 IVOR15

1

IVOR32

1

spr 529

spr 530 IVOR34

spr 531 IVOR35

IVOR33

Interrupt vector offset
registers 32–35

1

1

MMU Control and Status (Read/Write)

1

spr 1012 MMUCSR0

spr 624 MAS0

spr 625 MAS1

spr 626

spr 627

spr 628

spr 630

MAS2

MAS3

MAS4

MAS6

spr 48 PI D0

PID1

spr 634 PID2

MMU control a nd status
register 0

1

1

1

1

MMU assist
registers

1

1

1. 2

1

Process ID
registers 0–2

1

MMU Control and Status (Read Only)

spr 1015 MMUCFG

TLB0CFG

spr 688

spr 689 TLB1CFG

1

MMU configuration

1

TLB configuration 0/1 pmr 16–19 PMC0–3 1Counter registers 0–3

1

L1 Cache (Read/Write)

1

spr 1010

spr 1011 L1CSR1

L1CSR0

L1 Cache

1

Control/Status 0/1

spr 1023 SVR System version

spr 286 P IR Processor ID

spr 287 PVR

Timer/Decrementer Registers

spr 22 DEC Decrementer

spr 54 DECAR

spr 284 TBL

spr 285 TBU

spr 340 TCR Timer control

spr 336 TSR Timer status

spr 1008 HID0

spr 1013

spr 272–279

Performance Monitor Registers

pmr 400

pmr 144–147 PMLCa0–3 1Local control a0–a3

pmr 272–275

MSR Machine state

Miscellaneous Registers

BUCSR

SPRG0–7

PMGC0

PMLCb0–3

Figure 1-7. e500 Core Programming Model

User SPR
general 0

SPR general
registers 3–7

Time base
lower/upper

1, 2

Alternate time b ase

1, 2

lower/upper

Decrementer
auto-reload

Time base
lower/upper

1

Hardware
implementation

1

dependent 0–1

3

Branch control and
status register

General SPRs 0–7

1

Global control register

1

Local control b0–b3

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Core Complex Overview

1.7 On-Chip Cache Implementation

The core complex contains separate 32-Kbyte, eight-way set-associative, level 1 (L1) instruction
and data caches to give rapid access to instructions and data.

The data cache supports four-state MESI memory coherency protocol. The core complex
broadcasts all cache management functions based on the setting of the address broadcast enable
bit, HID1[ABE], allowing management of other caches in the system.

The caches implement a pseudo-least-recently-used (PLRU) replacement algorithm.
Parity generation and checking may be enabled for both caches, and each cache can be

independently invalidated through L1CSR1 and L1CSR0. Additionally, instructions are provided
to perform cache locking and unlocking on both data and instruction caches on a cache-block
granularity . These are listed in Section 1.10.3, “Cache Control Instructions.”

Individual instruction cache blocks and data cache blocks can be invalid ated using the icbi and
dcbi instructions, respectively. The entire data cache can be invalidated by setting L1CSR0[CFI];
the entire instruction cache can be invalidated by setting L1CSR1[ICFI].

1.8 Interrupts and Exception Handling

The e500 core supports an extended exception handling model, with nested interrupt capability
and extensive interrupt vector programmability. The following sections define the exception
model, including an overview of exception handling as implemented on the e500 core, a brief
description of the exception classes, and an overview of the registers involved in the processes.

1.8.1 Exception Handling

In general, interrupt processing begins with an exception that occurs due to external conditions,
errors, or program execution problems. When the exception occurs, the processor checks to verify
interrupt processing is enabled for that particular exception. If enabled, the interrupt causes the
state of the processor to be saved in the appropriate registers and prepares to begin execution of
the handler located at the associated vector address for that particular exception.

Once the handler is executing, the implementation may need to check one or more bits in the
exception syndrome register (ESR) or the SPEFSCR, depending on the exception, to verify the
specific cause of the exception and take appropriate action.

The core complex provides the interrupts described in Section 1.8.5, “Interrupt Registers.”

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Core Complex Overview

1.8.2 Interrupt Classes

All interrupts may be categorized as asynchronous/synchronous and critical/noncritical.

• Asynchronous interrupts (such as machine check, critical input, and external interrupts) are
caused by events that are independent of instruction execution. For asynchronous
interrupts, the address reported in a save/restore register is the address of the instruction that
would have executed next had the asynchronous interrupt not occurred.

• Synchronous interrupts are those that are caused directly by the execution or attempted
execution of instructions. Synchronous inputs may be either precise or imprecise, which are
described as follows:

— Synchronous precise interrupts are those that precisely indicate the address of the

instruction causing the exception that generated the interrupt or, in some cases, the
address of the immediately following instruction. The interrupt type and status bits
indicate which instruction is addressed in the appropriate save/restore register.

— Synchronous impre cise interrupts are those that may indicate the address of the

instructio n causing the exception th at generated th e interrupt or some instru ction after the
instructio n causing the interrupt. If the inter rupt was caused by either the cont ext
synchroniz ing mechanism or the execution syn chronizi ng mechanism, the addre ss in th e
appropriat e save/restore register is the address o f th e interrupt forcing instruction. If the
interrupt wa s not caused by either of those mechanisms, the address in the save/restore
register is th e last instruction to start execution and may not have completed. No
instructio n following the instruction in the save/restore register has ex ecuted.

1.8.3 Interrupt Types

The e500 core processes all interrupts as either machine check , critical, or noncritical types.
Separate control and status register sets are provided for each interrupt type. The core handles
interrupts from these three types in the following priority order:

1. Machine check interrupt (highest priority)—The e500 defines a separate set of resources
for the machine check interrupt. They use the machine check save and restore registers
(MCSRR0/MCSRR1) to save state when they are taken, and they use the rfmci instruction
to restore state. These interrupts can be masked by the machine check enable bit,
MSR[ME].

2. Noncritical interrupts—First-level interrupts that allow the processor to change program
flow to handle conditions generated by external signals, errors, or unusual conditions
arising from program execution or from programmable timer-related events. These
interrupts are largely identical to those previously defined by the OEA portion of the
Power PC architecture. They use save and restore registers (SRR0/SRR1) to save state
when they are taken and they use the rfi instruction to restore state. Asynchronous
noncritical interrupts can be masked by the external interrupt enable bit , MSR[EE].

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Core Complex Overview

3. Critical interrupts—Critical interrupts can be taken during a noncritical interrupt or during
regular program flow. They use the critical save and restore registers (CSRR0/CSRR1) to
save state when they are taken and they use the rfci instruction to restore state. These
interrupts can be masked by the critical enable bit, MSR[CE]. Book E defines the critical
input, watchdog timer, and machine check interrupts as critical interrupts, but the e500
defines a third set of resources for the machine check interrupt, as described in Table 1-6.

All inter rupts except ma chine check are ordered within the two categories of noncritic al and critica l,
such that only on e interrupt of each category is reported, and when it is processed (ta ken), no
program st ate is lost. Because sav e/restore register pa irs are s erially reusa ble, progr am state may be
lost when an unor dered interrupt is taken (see Section 5.10, “Interrupt Ordering and Masking”).

1.8.4 Upper Bound on Interrupt Latencies

Core complex interrupt latency is defined as the number of core clocks between the sampling of
the interrupt signal as asserted and the initiation of the IVOR fetch (that is, the fetch of the first
instruction in the handler). Core complex interrupt latency is determinate unless a guarded load or
a cache-inhibited stwcx. is being executed, in which case the latency is indeterminate. The
minimum latency is 3 core clocks and the maximum is 8, not including the 2 bus clock cycles
required to synchronize the interrupt signal from the pad.

When an interrupt is taken, all instructions in the IQ are thrown away unless the oldest instruction
is a load/store instruction. That is, if an asynchronous interrupt is being serviced and the oldest
instruction is not a load/store instruction, the core complex goes straight from sampling the
interrupt to ensuring a recoverable state and issuing an exce ption. If a load/store instruction is
oldest, the core complex waits 4 clocks before ensuring a recoverable state. During this time, any
instruction finished by the LSU is deallocated.

1.8.5 Interrupt Registers

The registers associated with interrupt and exception handling are described in Table 1-6.

Table 1-6. Interrupt Registers

Register Description

Noncritical Interrupt Registers

SRR0 Save/restore register 0—Holds the address of the instruction causing the exception or the address of the

instruction that will execute after the rfi instruction.

SRR1 Save/restore register 1—Holds machine state on noncritical interrupts and restores machine state after an

rfi instruction is executed.

Critical Interrupt Registers

CSRR0 Critical save/restore register 0—On critical interrupts, holds either the address of the instruction causing the

exception or the address of the instruction that will execute after the rfci instruction.

CSRR1 Critical save/restore register 1—Holds machine state on critical interrupts and restores machine state after

an rfci instruction is executed.

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Core Complex Overview

Table 1-6. Interrupt Registers (continued)

Register Description

Machine Check Interrupt Registers

MCSRR0 Machine check save/restore register 0—Used to store the address of the instruction that will execute after

an rfmci instruction is executed.

MCSRR1 Machine check save/restore register 1—Holds machine state on machine check interrupts and restores

machine state (if recoverable) after an rfmci instruction is executed.

MCAR Machine check address register—Holds the address of the data or instruction that caused the machine

check interrupt. MCAR contents are not meaningful if a signal triggered the machine check interrupt.

Syndrome Registers

MCSR Machine check syndrome register—Holds machine state information on machine check interrupts and

restores machine state after an rfmci instruction is executed.

ESR Exception syndrome register—Provides a syndrome to differentiate between the different kinds of

exceptions that generate the same interrupt type. Upon generation of a specific exception type, the
associated bit is set and all other bits are cleared.

SPE APU Interrupt Registers

SPEFSCR Signal processing and embedded floating-point status and control register—Provides interrupt control and

status as well as various condition bits associated with the operations performed by the SPE APU.

Other Interrupt Registers

DEAR Data exception address register—Holds the address that was referenced by a load, store, or cache

management instruction that caused an alignment, data TLB miss, or data storage interrupt.

IVPR

IVORs

Together, IVPR[32–47] || IVOR
See Ta bl e 1 -7 and the EREF for more information.

n

[48–59] || 0b0000 define the address of an interrupt-processing routine.

Each interr upt has an associat ed interrupt vector address, obtained by concate nating the IVP R value
with the addres s index in the associated IVOR (that is, IVPR[32–47] || IVORn[48–59] || 0b0000).
The resulti ng addre ss is that of the i nstructi on to be execu ted w hen that inte rrupt occ urs. I VPR a nd
IVOR values are indeterminate on reset, and must be in itialized by the system softwa re using
mtspr. Table 1-7 lists IVOR registe rs implemented on the e500 and the associated interrupts. For
more informat ion, see Chapter 5, “Interrupts and Exceptions.”

Table 1-7. Interrupt Vector Registers and Exception Conditions

Register Interrupt

Book E–Defined IVORs

IVOR0 Critical input

IVOR1 Machine check interrupt offset

IVOR2 Data storage interrupt offset

IVOR3 Instruction storage interrupt offset

IVOR4 External input interrupt offset

IVOR5 Alignment interrupt offset

IVOR6 Program interrupt offset

IVOR7 Floating-point unavailable interrupt offset (not supported on the e500)

IVOR8 System call interrupt offset

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Core Complex Overview

Table 1-7. Interrupt Vector Registers and Exception Conditions (continued)

Register Interrupt

IVOR9 Auxiliary processor unavailable interrupt offset (not supported on the e500)

IVOR10 Decrementer interrupt offset

IVOR11 Fixed-interval timer interrupt offset

IVOR12 Watchdog timer interrupt offset

IVOR13 Data TLB error interrupt offset

IVOR14 Instruction TLB error interrupt offset

IVOR15 Debug interrupt offset

e500-Specific IVORs

IVOR32 SPE APU unavailable interrupt offset

IVOR33 SPE floating-point data exception interrupt offset

IVOR34 SPE floating-point round exception interrupt offset

IVOR35 Performance monitor

1.9 Memory Management

The e500 core complex supports demand-paged virtual memory as well other mem ory
management schemes that depend on precise control of effective-to-physical address translation
and flexible memory protection as defined by Book E. The mapping mechanism consists of
software-managed TLBs that support variable-sized pages with per-page properties and
permissions. The following properties can be configured for each TLB:

• User-mode page execute access

• User-mode page read access

• User-mode page write access

• Supervisor-mode page execute access

• Supervisor-mode page read access

• Supervisor-mode page write access

• Write-through required ( W)

• Caching inhibited (I)

• Memory coherency required (M)

• Guarded (G)

• Endianness (E)

• User-definable (U0–U3), a 4-bit implementation-specific field

The core complex employs a two-level memory management unit (MMU) architecture. There are
separate instruction and data level-1 (L1) MMUs backed up by a unified level-2 (L2) MMU,

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This two-level structure is shown in Figure 1-8.

Core Complex Overview

To instruction unit

MAS

Registers

To load/store unit

Memory Unit

32-Kbyte I-Cache

Ta g s

L1 Instruction MMU

4-Entry

I-L1VSP

L2 MMUs

Unified

16-Entry

TLB Array

(TLB1)

4-Entry

D-L1VSP

32-Kbyte D-Cache

256/512-Entry

L1 Data MMU

D-L1TLB4K

Ta g s

64-Entry

I-L1TLB4K

TLB Array

(TLB0)

64-Entry

Core Interface

Data Line
FIll Buffer

Instruction Line

FIll Buffer

Figure 1-8. MMU Structure

Level-1 MMUs have the following features:

• Four-entry, fully associative TLB array that supports all nine page sizes

• 64-entry , 4-way set-associative TLB 4-Kbyte array that supports 4-Kbyte pages only

• Hardware partially managed by L2 MMU

• Supports snooping of TLBs by both internal and external tlbivax instructions

The level-2 MMU has the following features:

• A 16-entry , fully associative L2 TLB array (TLB1) that supports all nine variable page sizes

• TLB array (TLB0) that supports only 4-Kbyte pages, as follows:
— e500v1—256-entry, 2-way set-associative TLB array
— e500v2—512-entry, 4-way set-associative TLB array

• Hardware assist for TLB miss exceptions

• Software managed by tlbre, tlbwe, tlbsx, tlbsync, tlbivax, and mtspr instructions

• Supports snooping of TLB by both internal and external tlbivax instructions

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Core Complex Overview

1.9.1 Address Translation

The core complex fetch and load/store units generate 32-bit effective addresses. The MMU
translates these addresses to real addresses (32-bit real addresses for the e500v1 core, 36-bit for
the e500v2) (which are used for memory bus accesses) using an interim 41-bit virtual address.

Figure 1-9 shows the translation flow for the e500v1 core.

••• IS DS •••

Instruction Access

L2 MMU (unified)

16-Entry Fully-Assoc. VSP Array (TLB1)

256-Entry 2-Way Set Assoc. Array (TLB0)

* Number of bits depends on page size

(4 Kbytes–256 Mbytes)

MSR

Data Access

AS

32-bit Real Address

8 bits

PID0

PID1

PID2

32-bit Effective Address (EA)

4–20 bits* 12–28 bits*

Effective Page Number Byte Address

Three 41-bit Virtual Addresses (VAs)

L1 MMUs

Instruction L1 MMU

2 TLBs 2 TLBs

4–20 bits* 12–28 bits*

Real Page Number Byte Address

Data L1 MMU

Figure 1-9. Effective-to-Real Address Translation Flow

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Figure 1-10 shows the same translation flow for the e500v2 core.

Core Complex Overview

••• IS DS •••

Instruction Access

L2 MMU (unified)

16-Entry Fully-Assoc. VSP Array (TLB1)

512-Entry 4-Way Set Assoc. Array (TLB0)

* Number of bits depends on page size

(4 Kbytes–4 Gbytes)

MSR

Data Access

AS

36-bit Real Address

8 bits

PID0

PID1

PID2

32-bit Effective Address (EA)

0–20 bits*

Effective Page Number Byte Address

Three 41-bit Virtual Addresses (VAs)

L1 MMUs

Instruction L1 MMU

2 TLBs 2 TLBs

4–24 bits* 12–32 bits*

Real Page Number Byte Address

Data L1 MMU

12–32 bits*

Figure 1-10. Effective-to-Real Address Translation Flow (e500v2)

The appropriate L1 MMU (instruction or data) is checked for a matching address translation. The
instruction L1 MMU and data L1 MMU operate independently and can be accessed in parallel, so
that hits for instruction accesses and data accesses can occur in the same clock. If an L1 MMU
misses, the request for translation is forwarded to the unified (instruction and data) L2 MMU. If
found, the contents of the TLB entry are concatenated with the byte address to obtain the physical
address of the requested access. On misses, the L1 TLB entries are replaced from their L2 TLB
counterparts using a true LRU algorithm.

1.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)

Book E defines SPR numbers for the MMU assist regi sters, which are used to hold values either
read from or to be written to the TLBs and information required to identify the TLB to be accessed.
To ensure consistency among Freescale Semiconductor Book E processors, certain aspects of the
implementation are defined by the Freescale Semiconductor Book E standard, whereas more
specific details are left to individual implementations. MAS3 implements the real page number

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Core Complex Overview

(RPN), the user attribute bits (U0–U3), and permission bits (UX, SX, UW, SW, UR, SR) that
specify user and supervisor read, write, and execute permissions.

The e500 does not implement MAS5.
MAS registers are affected by the following instructions (see Section 12.4, “TLB

Instructions—Implementation,” for more detailed information):

• MAS registers are accessed with the mtspr and mfspr instructions.

• The TLB Read Entry instruction (tlbre) causes the contents of a single TLB entry from the
L2 MMU to be placed in defined locations in MAS0–MAS3 (and optionally MAS7 on the
e500v2). The TLB entry to be extracted is determined by information written to MAS0 and
MAS2 before the tlbre instruction is execut ed.

• The TLB Write Entry instruction (tlbwe) causes the information stored in certain locations
of MAS0–MAS3 (and MAS7 on the e500v2) to be written to the TLB specified in MAS0.

• The TLB Search Indexed instruction (tlbsx) updates MAS registers conditionally , based on
success or failure of a lookup in the L2 MMU. The lookup is specified by the instruction
encoding and specific search fields in MAS6. The values placed in the MAS registers may
differ, depending on a successful or unsuccessful search.

For TLB miss and certain MMU-related DSI/ISI exceptions, MAS4 provides default values for
updating MAS0–MAS2.

1.9.3 Process ID Registers (PID0–PID2)

The e500 core complex also implements three process ID (PID) registers that hold the values used
to construct the three virtual addresses for each access. These process IDs provide an extended
page sharing capability. Which of these three virtual addresses is used is controlled by the TID
field of a matching TLB entry, and when TID = 0x00 (identifying a page as globally shared), the
PID values are ignored.

A hit to multiple TLB entries in the L1 MMU (even if they are in separate arrays) or a hit to
multiple entries in the L2 MMU is considered to be a programming error.

1.9.4 TLB Coherency

The core complex provides the ability to invalidate a TLB entry, as defined in the Book E
architecture. The tlbivax instruction invalidates a matching local TLB entry. Execution of this
instruction is also broadcast on the core complex bus (C CB) if HID1[ABE] is set. The core
complex also snoops TLB invalidate transactions on the CCB from other bus masters.

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Core Complex Overview

1.10 Memory Coherency

The core complex supports four-state memory coherency . Memory coherency is
hardware-supported on the system bus through bus snooping and the retry/copyback bus protocol,
and through broadcasting of cache management instructions. Translation coherency is also
hardware-supported through broadcasting and bus snooping of TLB invalidate transactions. The
four-state MESI protocol supports efficient large-scale real-time data sharing between multiple
caching bus masters.

1.10.1 Atomic Update Memory References

The e500 core supports atomic update memory references for both aligned word forms of data
using the load and reserve and store conditional instruction pair, lwarx and stwcx.. Typically, a
load and reserve instruction establishes a reservation and is paired with a store conditional
instruction to achieve the atomic operation. However, there are restrictions and requirements for
this functionality . The processor revokes reservations during a context switch, so the programmer
must reacquire the reservation after a context switch occurs.

1.10.2 Memory Access Ordering

The core complex supports weakly ordered references to memory. Thus the e500 manages the
order and synchronization of instructions to ensure proper execution when memory is shared
between multiple processes or programs. The cache and data memory control attributes, along
with msync and mbar, provide the required access control; msync and mbar are also broadcast
on the CCB to provide the appropriate control in the case of multiprocessor or shared memory
systems.

1.10.3 Cache Control Instructions

The core complex supports Book E instructions for performing a full range of cache control
functions, including cache locking by line. The core complex supports broadcasting and snooping
of these cache control instructions on the CCB. The e500 core also supports the following
e500-specific cache locking instructions:

• Data Cache Block Lock Clear (dcblc)

• Data Cache Block Touch and Lock Set (dcbtls)

• Data Cache Block Touch for Store and Lock Set (dcbtstls)

• Instruction Cache Block Lock Clear (icblc)

• Instruction Cache Block Touch and Lock Set (icbtls)

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Core Complex Overview

1.10.4 Programmable Page Characteristics

Cache and memory attributes are programmable on a per-page basis. In addition to the
write-through, caching-inhibited, memory coherency enforced, and guarded characteristics
defined by the WIMG bits, Book E defines an endianness bit, E, that allows selection of big- or
little-endian byte ordering on a per-page basis.

In addition to the WIMGE bits, the Book E MMU model defines user-definable page attribute bits
(U0–U3).

1.11 Core Complex Bus (CCB)

The core complex defines a versatile local bus interface that allows a wide range of system
performance and system-complexity trade-offs. The interface defines the following buses.

• An address-out bus for mastering bus transactions

• An address-in bus for snooping internal resources

• Three tagged data buses

Two of the data buses are general-purpose data-in buses for reads, and the third is a data-out bus
for writes. The two data-in buses feature support for out-of-order read transactions from two
different sources simultaneously, and all three data buses may be operated concurrently. The
address-in bus supports snooping for external management of the L1 caches and TLBs by other
bus masters. The core complex broadcasts and snoops the cache and TLB management
instructions accordingly. It is envisioned that a wide range of system implementations can be
constructed from the defined interface.

1.12 Performance Monitoring

The e500 core provides a performance monitoring capability that allows counting of events such
as processor clocks, instruction cache misses, data cache misses, mispredicted branches, and
others. The count of these events may be configured to trigger a performance monitor exception
following the e500 interrupt model. This interrupt is assigned to vector offset register IVOR35.

The register set associated with the performance monitoring function consists of counter registers,
a global control register, and local control registers. These registers are read/write from supervisor
mode, and each register is reflected to a corresponding read-only register for user mode. Two
instructions, mtpmr and mfpmr, are provided for moving data to and from these registers. An
overview of the performance monitoring registers is provided in the fo llowing sections.

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Core Complex Overview

1.12.1 Global Control Register

The PMGC0 register provides global control of the performance monitoring facility from
supervisor mode. From this register all counters may be frozen, unfrozen, or configured to freeze
on an enabled condition or event. Additionally, the performance monitoring facility may be
disabled or enabled from this register. The contents of PMGC0 are reflected to UPMGC0, which
may be read from user mode using the mfpmr instruction.

1.12.2 Performance Monitor Counter Registers

There are four counter registers (PCM0–PCM3) provided in the performance monitoring facility.
These 32-bit registers hold the current count for software-selectable events and can be
programmed to generate an exception on overflow. These registers may be written or read from
supervisor mode using the mtpmr and mfpmr instructions. The contents of these registers are
reflected to UPCM0–UPCM3, which can be read from user mode with mfpmr.

Performance monitor exceptions occur only if all of the fo llowing conditions are met:

• A counter is in the overflow state.

• The counter's overflow signaling is enabled.

• Overflow exception generation is enabled in PMGC0.

• MSR[EE] is set.

1.12.3 Local Control Registers

For each of the counter registers, there are two corresponding local control registers. These two
registers specify which of the 128 available events is to be counted, what specific action is to be
taken on overflow, and various options for freezing a counter value under given modes or
conditions.

• PMLCa0–PMLCa3 provide fields that allow freezing of the corresponding counter in user
mode, supervisor mode, or under software control. Additionally, the overflow condition
may be enabled or disabled from this register. The contents of these registers are reflected
to UPMLCa0–UPMLCa3, which can be read from user mode with mfpmr.

• PMLCb0–PMLCb3 provide count scaling for each counter register using configurable
threshold and multiplier values. The threshold is a 6-bit value and the multiplier is a 3-bit
encoded value, allowing eight multiplier values in the range of 1 to 128. Any counter may
be configured to increment only when an event occurs mor e than [threshold × multiplier]
times. The contents of these registers are reflected to UPMLCb0–UPMLCb3, which can be
read from user mode with mfpmr.

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Core Complex Overview

1.13 Legacy Support of PowerPC Architecture

This section provides an overview of the architectural differences and compatibilities of the e500
core compared with the AIM PowerPC architecture. The two levels of the e500 programming
environment are as follows:

• User level—This defines the base user-level instruction set, user-level registers, data types,
memory conventions, and the memory and programming models seen by application
programmers.

• Supervisor level—This defines supervisor-level resources typically required by an
operating system, the memory management model, supervisor level registers, and the
exception model.

In general, the e500 core supports the user-level architecture from the existing AIM architecture.
The following subsections are intended to highlight the main differences. For specific
implementation details refer to the relevant chapter.

1.13.1 Instruction Set Compatibility

The following sections generally describe the user and supervisor instruction sets.

1.13.1.1 User Instruction Set

The e500 core executes legacy user-mode binaries and object files except for the following:

• The e500 supports vector and scalar single-precision floating-point operations as APUs.
The e500v2 supports scalar double-precision floating-point instructions. These instructions
have different encoding than the AIM definition of the PowerPC architecture. Additionally ,
the e500 core uses GPRs for floating-point operations, rather than the FPRs defined by the
UISA. Most porting of floating-point operations can be handled by recompiling.

• String instructions are not implemented on the e500; therefore, trap emulation must be
provided to ensure backward compatibility.

1.13.1.2 Supervisor Instruction Set

The supervisor mode instruction set defined by the AIM version of the PowerPC architecture is
compatible with the e500 with the following exceptions:

• The MMU architecture is different, so some TLB manipulation instructions have different
semantics.

• Instructions that support the BATs and segment registers are not implemented.

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Core Complex Overview

1.13.2 Memory Subsystem

Both Book E and the AIM version of the PowerPC architecture provide separate instruction and
data memory resources. The e500 provides additional cache control features, including cache
locking.

1.13.3 Exception Handling

Exception handling is generally the same as that defined in the AIM version of the PowerPC
architecture for the e500, with the following differences:

• Book E defines a new critical interrupt, providing an extra level of interrupt nesting. The
critical interrupt includes external critical and watchdog timer time-out inputs.

• The machine check exception differs from the Book E and from the AIM definition. It
defines the Return from Machine Check Interrupt instruction, rfmci, and two machine
check save/restore registers, MCSRR0 and MCSRR1.

• Book E processors can use IVPR and IVORs to set exception vectors individually, but they
can be set to the address offsets defined in the OEA to provide compatibility.

• Unlike the AIM version of the PowerPC architecture, Book E does not define a reset vector;
execution begins at a fixed virtual address, 0xFFFF_FFFC.

• Some Book E and e500-specific SPRs are different from those defined in the AIM version
of the PowerPC architecture, particularly those related to the MMU functions. Much of this
information has been moved to a new exception syndrome register (ES R).

• Timer services are generally compatible, although Book E defines a new decrementer auto
reload feature, the fixed-interval timer critical interrupt, and the watchdog timer interrupt,
which are implemented in the e500 core.

An overview of the interrupt and exception handling capabilities of the e500 core can be found in

Section 1.8, “Interrupts and Exception Handling.”

1.13.4 Memory Management

The e500 core implements a straightforward virtual address space that complies with the Book E
MMU definition, which eliminates segment registers and block address translation resources.
Book E defines resources for fixed 4-Kbyte pages and multiple, variable page sizes that can be
configured in a single implementation. TLB management is provided with new instructions and
SPRs.

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Core Complex Overview

1.13.5 Reset

Book E–compliant cores do not share a common reset ve ctor with the AIM version of the
PowerPC architecture. Instead, at reset fetching begins at address 0xFFFF_FFFC. In addition to
the Book E reset definition, the EIS and the e500 define specific aspects of the MMU page
translation and protection mechanisms. Unlike the AIM version of the PowerPC core, as soon as
instruction fetching begins, the e500 core is in virtual mode with a hardware-initialized TLB entry.

EIS–defined aspects of the MMU are described in the ERE F. Specific details of how the e500 is
initialized are provided in Section 12.6, “TLB States after Reset.”

1.13.6 Little-Endian Mode

Unlike the AIM version of the PowerPC architecture, where little-endian mode is controlled on a
system basis, Book E allows control of byte ordering on a memory page basis. In addition, the
little-endian mode used in Book E is true little endian .

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Chapter 2
Register Model

This chapter describes implementation-specific details of the register model as it is implemented
on the e500 core processors. It identifies all registers that are implemented on the e500 cores, but,
with a few exceptions, does not include full descriptions of those registers and register fields that
are implemented exactly as they are defined by the Book E architecture and by the Freescale
Book E implementation standards (EIS). A full description of these registers is provided in the
EREF: A Reference for Freescale Book E and the e500 Core (EREF).

It is important to note that a device that integrates the e500 core may not implement all of the fields
and registers that are defined here, and may interpret some fields more specifically than can be
defined here. For specific details, refer to the “Register Summary” chapter in the reference manual
for the device that incorporates the e500 core. The register summary chapter fully describes all
registers and register fields as they are implemented on the device.

2.1 Overview

Although this chapter organizes registers according to their functionality, they can be
differentiated according to how they are accessed , as follows:

• General-purpose registers (GPRs)—Used as source and destination operands for most
operations. The e500 implements 64-bit GPRs. Book E–defined instructions access only
the lower word; SPE vector instructions and embedded vector single-precision and
double-precision floating-point APUs (e500v2 only) use all 64 bits. See Section 2.3.1,

“General-Purpose Registers (GPRs).”

• Special-purpose registers (SPRs)—Accessed by using the Book E–defined Move to
Special-Purpose Register (mtspr) and Move from Special-Purpose Register (mfspr)
instructions. Section 2. 2.1, “Special-Purpose Registers (SPRs),” lists SPRs.

• System-level registers that are not SPRs. These are as follows:
— Machine state register (MSR). MSR is accessed with the Move to Machine State

Register (mtmsr) and Move from Machine State Register (mfmsr) instructions. See

Section 2.5.1, “Machine State Register (MSR).”

— Condition register (CR) bits are grouped into eight 4-bit fields, CR0–CR7, which are set

as follows:
– Specified CR fields can be set by a move to the CR from a GPR (mtcrf).
– A specified CR field can be set by a move to the CR from another CR field (mcrf),

or from the XER (mcrxr).

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Register Model

– CR0 can be set as the implicit result of an integer instruction.
– A specified CR field can be set as the result of an integer or floating-point compare

instruction (including SPE and SPFP compare instructions).

See Section 2.4.1, “Condition Register (CR).”

— The EIS-defined accumulator, used by the SPE APU. See Section 2.14.2, “Accumulator

(ACC).”

• Performance monitor registers (PMRs). Similar to SPRs, PMRs are accessed by using the
EIS-defined Move to Performance Monitor Register (mtpmr) and Move from Performance
Monitor Register (mfspr) instructions. See Section 2.15, “Performance Monitor Registers

(PMRs).”

2.2 e500 Register Model

The following sections describe the e500 core register model as defined in Book E and the
additional implementation-specific registers unique to the e500 core. Figure 2-1 shows the e500
register set and identifies which are defined by Book E, which are defined by the EIS, and which
are e500-specific.

Book E processors implement the following types of software-accessible registers:

• Book E–defined registers that are accessed as part of instruction execution. These include
the following:

— Registers used for integer operations:

– General-purpose registers (GPRs)—Book E defines a set of 32 GPRs used to hold

source and destination operands for load, store, arithmetic, and computational
instructions, and to read and write to other registers.

– Integer exception register (XER)—Bits in this register are set based on the operation

of an instruction considered as a whole, not on intermediate results. (For example,
the Subtract from Carrying instruction (subfc), the result of which is specified as the
sum of three values, sets bits in the XER based on the entire operation, not on an

intermediate sum.)
These registers are described in Section 2.3, “Registers for Integer Operations.”
— Condition register (CR)—Used to record conditions such as overflows and carries that

occur as a result of executing arithmetic instructions (including those implemented by
the SPE and SPFP APUs). The CR is described in Section 2.4, “Registers for Branch

Operations.”

— Machine state register (MSR)—Used by the operating system to configure parameters

such as user/supervisor mode, address space, and enabling of asynchronous interrupts.
MSR is described in Section 2.5.1, “Machine State Register (MSR).”

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User-Level Registers

General-Purpose Registers Instruction-Accessible Registers User General SPR (Read/Write)

0 31 32 63 0 31 32 63 32 63

(upper) GPR0 (lower)

GPR1

GPR2

General­purpose
registers

GPR31 spr 260 SPRG4

Performance Monitor PMRs (Read-Only)

pmr 384

pmr 0–3

pmr 128–131

pmr 256–259 UPMLCbs

UPMGC0

UPMLCas

L1 Cache (Read-Only)

spr 515

UPMCs

L1CFG0

L1CFG1

1

Global control register

1

Counter
registers 0–3

1

Local control registers

1

a0–a3, b0–b3

1

L1 cache
configuration reg isters

1

0–1spr 516

CR Cond ition register

spr 9

CTR

Count register

spr 8 LR Link register spr 259 SPRG3

spr 1 XER Integer exception

spr 512 SPEFSCR

1

ACC

register

1

SPE FP status/control
register

Accumulator

Miscellaneous Registers

spr 513

spr 514

BBEAR

BBTAR

3

Branch buffer entry
address register

3

Branch buffer target
address register

spr 256 USPRG0

General SPRs (Read-Only)

• • •

spr 263 SPRG7

Time-Base Registers (Read-Only)

spr 268

spr 269

spr 526

spr 527

TBL

TBU

AT B L

AT BU

Supervisor-Level Registers

32 63 32 63 32 63

spr 63 IVPR

spr 26 SRR0

spr 27

SRR1

spr 58 CSRR0

spr 59 CSRR1

spr 570

MCSRR0

spr 571

MCSRR1

spr 62

ESR

spr 572 MCSR

spr 573 MCAR Machine check

spr 61 DEAR Da ta exception

Interrupt vector
prefix

Save/restore
registers 0/1

Critical SRR 0/1 Processor version spr 528 IVOR32

1

Machine check

1

SRR 0/1

Exception syndrome
register

1

Machine check
syndrome register

address register

address register

Debug Registers

spr 308 DBCR0

spr 309 DBCR1

spr 310

spr 304

DBCR2

DBSR

spr 312 IAC1

spr 313 IAC2

spr 316 DAC1 pmr 400 PMGC0

spr 317 DAC2 spr 688 TLB0CFG

1

These registers are defined by the EIS

2

e500v2 only

3

These registers are e500-specific

Debug control
registers 0–2

Debug status register spr 633

Instruction ad dress
compare
registers 1 and 2

Data address
compare
registers 1 and 2

Interrupt Registers Configuration Registers

spr 400 IVOR0

spr 401 IVOR1

• • •

Interrupt vector offset
registers 0–15

spr 1023 SVR System version

spr 415 IVOR15 spr 286 PIR Processor ID

1

1

spr 529

spr 530 IVOR34

spr 531 IVOR35

IVOR33

Interrupt vector offset
registers 32–35

1

1

MMU Control and Status (Read/Write)

1

spr 1012 MMUCSR0

spr 624 MAS0

spr 625 MAS1

spr 626

MAS2

spr 627 MAS3

spr 628

spr 630

spr 944

spr 48

MAS4

MAS6

MAS7

PID0

PID1

spr 634 PID2

MMU control a nd status
register 0

1

1

1

1

MMU assist
registers

1

1

1. 2

Process ID

1

registers 0–2

1

MMU Control and Status (Read Only)

1

spr 1015 MMUCFG

spr 689 TLB1CFG

MMU configuration

1

TLB configuration 0/1 pmr 16–19

L1 Cache (Read/Write)

1

spr 1010

spr 1011 L1CSR1

L1CSR0

L1 Cache

1

Control/Status 0/1

spr 287 PVR

Timer/Decrementer Registers

spr 22 DEC Decrementer

spr 54 DECAR

spr 284 TBL

spr 285 TBU

spr 340 TCR Timer control

spr 336 TSR Timer status

spr 1008

spr 1009

spr 1013

spr 272–279

Performance Monitor Registers

pmr 144–147

pmr 272–275

MSR Machine state

Miscellaneous Registers

HID0

HID1

BUCSR

SPRG0–7

PMC0–3

PMLCa0–3

PMLCb0–3

Figure 2-1. e500 Register Model

Register Model

User SPR
general 0

SPR general
registers 3–7

Time base
lower/upper

1, 2

Alternate time b ase

1, 2

lower/upper

Decrementer
auto-reload

Time base
lower/upper

1

Hardware
implementation

1

dependent 0–1

3

Branch control and
status register

General SPRs 0–7

1

Global control register

1

Counter registers 0–3

1

Local control a0–a3

1

Local control b0–b3

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Register Model

• Book E–defined special-purpose registers (SPRs) that are accessed explicitly using mtspr
and mfspr instructions. These registers are listed in Table 2-1 in Section 2.2.1,

“Special-Purpose Registers (SPRs).”

• Freescale EIS–defined SPRs and e500-defined SPRs that are accessed explicitly using the
mtspr and mfspr instructions. These registers are listed in Table 2-2 in Section 2.2.1,

“Special-Purpose Registers (SPRs).”

• Freescale EIS–defined performance monitor registers (PMRs). These registers are similar
to SPRs, but are accessed with EIS–defined move to and move from PMR instructions
(mtpmr and mfpmr).

Book E– and e500-defined SPRs are grouped by function as follows :

• Section 2.4, “Registers for Branch Operations.” This section includes descriptions of the
count register (CTR) and the link register (LR).

• Section 2.5, “Processor Control Registers”

• Section 2.6, “Timer Registers”

• Section 2.7, “Interrupt Registers”

• Section 2.8, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0)”

• Section 2.9, “Branch Target Buffer (BTB) Registers”

• Section 2.10, “Hardware Implementation-Dependent Registers”

• Section 2.11, “L1 Cache Configuration Registers”

• Section 2.12, “MMU Registers”

• Section 2.13, “Debug Registers”

• Section 2.14, “SPE and SPFP APU Registers”

Book E defines 32- and 64-bit registers. All 32-bit registers are supported as defined in Book E.
However, except for the 64-bit FPRs, which are not implemented on the e500, only bits 32–63 of
Book E’s 64-bit registers (such as LR, CTR, the GPRs, SRR0, and CSRR0) are required to be
implemented in hardware in a 32-bit Book E implementation. The e500 implements 64-bit GPRs,
the upper 32 bits of which are used only with the e500-specific signal processing engine (SPE)
APU, embedded vector single-precision floating-point APU, and the e500v2 embedded scalar
double-precision floating-point APU instructions.

Likewise, all Book E integer instructions defined to return a 64-bit result return only bits 32–63 of
the result on a 32-bit Book E implementation. SPE APU vector instructions return 64-bit values,
as do DPFP APU instructions on the e500v2; SPFP APU ins tructions return single-precision
32-bit values.

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Register Model

NOTE

The SPE APU and embedded floating-point APU functionality is
implemented in all PowerQUICC III devices. However, these
instructions will not be supported in devices subsequent to
PowerQUICC III. Freescale Semiconductor strongly recommends
that use of these instructions be confined to libraries and device
drivers. Customer software that uses SPE or embedded floating-point
APU instructions at the assembly level or that uses SPE intrinsics will
require rewriting for upward compatibility with next-generation
PowerQUICC devices.

Freescale Semiconductor offers a libmoto_e500 library that uses SPE
instructions. Freescale will also provide libraries to support
next-generation PowerQUICC devices.

This chapter describes how the e500 implements registers defined by Book E. As with the
instructio n set and o ther asp ects of the archite cture, Boo k E defines some fe atures very specific ally ,
for example, resources that ensure compatibility with implementatio ns of the PowerPC ISA.
However , because a principal goal of the Book E architecture is to of fer flexibility among embe dded
processors and families of embedded processors, some resources are either defi ned as optional or
are defined in a very general way, leaving specific details up to the implementation.

2.2.1 Special-Purpose Registers (SPRs)

SPRs are on-chip registers that are architecturally part of the processor core. They control the use
of the debug facilities, timers, interrupts, memory management unit, and other arc hitected
processor resources and are accessed with the mtspr and mfspr instructions. Unlisted encodings
are reserved for future use.

Table 2-1 summarizes SPRs defined in Book E. The SPR numbers are used in the instruction

mnemonics. Bit 5 in an SPR number indicates whether an SPR is accessible from user or
supervisor software. An mtspr or mfspr instruction that specifies an unsupported SPR number is
considered an invalid instruction. The e500 treats such invalid instructions as follows:

• If the invalid SPR falls within the range specified as user mode (SPR[5] = 0), an illegal
exception is taken.

• If supervisor software attempts to access an invalid supervisor-level SPR (SPR[5] = 1),
results are undefined.

• If user software attempts to access an invalid supervisor-level SPR, a privilege exception is
taken.

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Register Model

Table 2-1. Book E Special-Purpose Registers (by SPR Abbreviation)

SPR

Abbreviation

Name

Defined SPR Number

Decimal Binary

Access

Supervisor

Only

Section/

Page

ATBL Alternate time base register lower 526 10000 01110 Read-only No 2.6.6/2-16

ATBU Alternate time base register upper 527 10000 01111 Read-only No 2.6.6/2-16

CSRR0 Critical save/restore register 0 58 00001 11010 Read/Write Yes 2.7.1.1/2-18

CSRR1 Critical save/restore register 1 59 00001 11011 Read/Write Yes 2.7.1.1/2-18

CTR Count register 9 00000 01001 Read/Write No 2.4.3/2-10

DAC1 Data address compare 1 316 01001 11100 Read/Write Yes 2.13.4/2-48

DAC2 Data address compare 2 317 01001 11101 Read/Write Yes 2.13.4/2-48

DBCR0 Debug control register 0

DBCR1 Debug control register 1

DBCR2 Debug control register 2

DBSR Debug status register 304 01001 10000 Read/Clear

1

1

1

308 01001 10100 Read/Write Yes 2.13.1/2-46

309 01001 10101 Read/Write Yes 2.13.1/2-46

310 01001 10110 Read/Write Yes 2.13.1/2-46

2

Ye s 2.13.2/2-47

DEAR Data exception address register 61 00001 11101 Read/Write Yes 2.6.5/2-16

DEC Decrementer 22 00000 10110 Read/Write Yes 2.6.4/2-16

DECAR Decrementer auto-reload 54 00001 10110 Write-only Yes 2.6.4/2-16

ESR Exception syndrome register 62 00001 11110 Read/Write Yes 2.7.1.6/2-20

IAC1 Instruction address compare 1 312 01001 11000 Read/Write Yes 2.13.3/2-48

IAC2 Instruction address compare 2 313 01001 11001 Read/Write Yes 2.13.3/2-48

IVOR0 Critical input 400 01100 10000 Read/Write Yes 2.7.1.5/2-19

IVOR1 Machine check interrupt offset 401 01100 10001 Read/Write Yes 2.7.1.5/2-19

IVOR2 Data storage interrupt offset 402 01100 10010 Read/Write Yes 2.7.1.5/2-19

IVOR3 Instruction storage interrupt offset 403 01100 10011 Read/Write Yes 2.7.1.5/2-19

IVOR4 External input interrupt offset 404 01100 10100 Read/Write Yes 2.7.1.5/2-19

IVOR5 Alignment interrupt offset 405 01100 10101 Read/Write Yes 2.7.1.5/2-19

IVOR6 Program interrupt offset 406 01100 10110 Read/Write Yes 2.7.1.5/2-19

IVOR8 System call interrupt offset 408 01100 11000 Read/Write Yes 2.7.1.5/2-19

IVOR10 Decrementer interrupt offset 410 01100 11010 Read/Write Yes 2.7.1.5/2-19

IVOR11 Fixed-interval timer interrupt offset 411 01100 11011 Read/Write Yes 2.7.1.5/2-19

IVOR12 Watchdog timer interrupt offset 412 01100 11100 Read/Write Yes 2.7.1.5/2-19

IVOR13 Data TLB error interrupt offset 413 01100 11101 Read/Write Yes 2.7.1.5/2-19

IVOR14 Instruction TLB error interrupt offset 414 01100 11110 Read/Write Yes 2.7.1.5/2-19

IVOR15 Debug interrupt offset 415 01100 11111 Read/Write Yes 2.7.1.5/2-19

IVPR Interrupt vector 63 00001 11111 Read/Write Yes 2.7.1.4/2-19

LR Link register 8 00000 01000 Read/Write No 2.4.2/2-10

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Register Model

Table 2-1. Book E Special-Purpose Registers (by SPR Abbreviation) (continued)

SPR

Abbreviation

PID Process ID register

Name

3

Defined SPR Number

Access

Decimal Binary

Supervisor

Only

Section/

48 00001 10000 Read/Write Yes 2.12.1/2-36

PIR Processor ID register 286 01000 11110 Read-only Yes 2.5.2/2-12

PVR Processor version register 287 01000 11111 Read-only Yes 2.5.3/2-13

SPRG0 SPR general 0 272 01000 10000 Read/Write Yes 2.8/2-24

SPRG1 SPR general 1 273 01000 10001 Read/Write Yes 2.8/2-24

SPRG2 SPR general 2 274 01000 10010 Read/Write Yes 2.8/2-24

SPRG3 SPR general 3 259 01000 00011 Read-only No

4

2.8/2-24

275 01000 10011 Read/Write Yes

SPRG4 SPR general 4 260 01000 00100 Read-only No 2.8/2-24

276 01000 10100 Read/Write Yes

SPRG5 SPR general 5 261 01000 00101 Read-only No 2.8/2-24

277 01000 10101 Read/Write Yes

SPRG6 SPR general 6 262 01000 00110 Read-only No 2.8/2-24

278 01000 10110 Read/Write Yes

SPRG7 SPR general 7 263 01000 00111 Read-only No 2.8/2-24

Page

279 01000 10111 Read/Write Yes

SRR0 Save/restore register 0 26 00000 11010 Read/Write Yes 2.7.1.1/2-18

SRR1 Save/restore register 1 27 00000 11011 Read/Write Yes 2.7.1.1/2-18

TBL Time base lower 268 01000 01100 Read-only No 2.6.3/2-16

284 01000 11100 Write-only Yes 2.6.3/2-16

TBU Time base upper 269 01000 01101 Read-only No 2.6.3/2-16

285 01000 11101 Write-only Yes 2.6.3/2-16

TCR Timer control register 340 01010 10100 Read/Write Yes 2.6.1/2-15

TSR Timer status register 336 01010 10000 Read/Clear

USPRG0 User SPR general 0

6

256 01000 00000 Read/Write No 2.8/2-24

5

Ye s 2.6.2/2-16

XER Integer exception register 1 00000 00001 Read/Write No 2.3.2/2-9

1

Writing to these registers requires synchronization, as described in Section 2.16, “Synchronization Requirements for SPRs.”

2

The DBSR is read using mfspr. It cannot be directly written to. Instead, DBSR bits corresponding to 1 bits in the GPR can be
cleared using mtspr.

3

Implementations may support more than one PID. The e500 implements the Book E–defined PID as PID0.

4

User-mode read access to SPRG3 is implementation-dependent.

5

The TSR is read using mfspr. It cannot be directly written to. Instead, TSR bits corresponding to 1 bits in the GPR can be cleared
using mtspr.

6

USPRG0 is a separate physical register from SPRG0.

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Register Model

Table 2-2 describes the implementation-specific SPRs of the core complex. Compilers should

recognize the mnemonic name given in Table 2-2 when parsing instructions.

Table 2-2. Implementation-Specific SPRs (by SPR Abbreviation)

SPR

Abbreviation

BBEAR Branch buffer entry address register

BBTAR Branch buffer target address register

BUCSR Branch unit control and status register

HID0 Hardware implementation dependent register 0

HID1 Hardware implementation dependent register 1

IVOR32 SPE/embedded floating-point APU unavailable

Name SPR Number Access Supervisor Only Section/Page

1

1

1

1

1

513 Read/Write No 2.9.1/2-25

514 Read/Write No 2.9.2/2-25

1013 Read/Write Yes 2.9.3/2-26

1008 Read/Write Yes 2.10.1/2-27

1009 Read/Write Yes 2.10.1/2-27

528 Read/Write Yes 2.7.1.5/2-19

interrupt offset

IVOR33 Embedded floating-point data exception interrupt

529 Read/Write Yes 2.7.1.5/2-19

offset

IVOR34 Embedded floating-point round exception interrupt

530 Read/Write Yes 2.7.1.5/2-19

offset

IVOR35 Performance monitor 531 Read/Write Yes 2.7.1.5/2-19

L1CFG0 L1 cache configuration register 0 515 Read-only No 2.11.3/2-34

L1CFG1 L1 cache configuration register 1 516 Read-only No 2.11.4/2-35

L1CSR0 L1 cache control and status register 0

L1CSR1 L1 cache control and status register 1

MAS0 MMU assist register 0

MAS1 MMU assist register 1

MAS2 MMU assist register 2

MAS3 MMU assist register 3

MAS4 MMU assist register 4

MAS6 MMU assist register 6

MAS7 MMU assist register 7

1

1

1

1

1

1

1

1

1

1010 Read/Write Yes 2.11.1/2-31

1011 Read/Write Yes 2.11.2/2-33

624 Read/Write Yes 2.12.5.1/2-40

625 Read/Write Yes 2.12.5.2/2-41

626 Read/Write Yes 2.12.5.3/2-42

627 Read/Write Yes 2.12.5.4/2-43

628 Read/Write Yes 2.12.5.5/2-43

630 Read/Write Yes 2.12.5.6/2-44

944 Read/Write Yes 2.12.5.7/2-45

MCAR Machine check address register 573 Read-only Yes 2.7.2.3/2-22

MCSR Machine check syndrome register 572 Read/Write Yes 2.7.2.4/2-23

MCSRR0 Machine-check save/restore register 0 570 Read/Write Yes 2.7.2.1/2-22

MCSRR1 Machine-check save/restore register 1 571 Read/Write Yes 2.7.2.2/2-22

MMUCFG MMU configuration register 1015 Read-only Yes 2.12.3/2-37

MMUCSR0 MMU control and status register 0

PID0 Process ID register 0. Book E defines only this PID

register and refers to as PID, not PID0.

PID1 Process ID register 1

PID2 Process ID register 2

SPEFSCR Signal processing and embedded floating-point

status and control register

1

1

1

1

1

1012 Read/Write Yes 2.12.2/2-36

48 Read/Write Yes 2.12.1/2-36

633 Read/Write Yes 2.12.1/2-36

634 Read/Write Yes 2.12.1/2-36

512 Read/Write No 2.14.1/2-49

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Register Model

Table 2-2. Implementation-Specific SPRs (by SPR Abbreviation) (continued)

SPR

Abbreviation

SVR System version register 1023 Read-only Yes 2.5.4/2-13

TLB0CFG TLB configuration register 0 688 Read-only Yes 2.12.4/2-37

TLB1CFG TLB configuration register 1 689 Read-only Yes 2.12.4.2/2-39

1

Writing to these registers requires synchronization, as described in Section 2.16, “Synchronization Requirements for SPRs.”

Name SPR Number Access Supervisor Only Section/Page

2.3 Registers for Integer Operations

The following sections describe registers defined for integer computational instructions.

2.3.1 General-Purpose Registers (GPRs)

Book E implementations provide 32 GPRs (GPR0–GPR31) for integer operations. The instruction
formats provide 5-bit fields for specifying the GPRs to be used in the execution of the instruction.
Each GPR is a 64-bit register and can be used to contain address and integer data, although all
instructions except SPE APU instructions, double-precision embedded floating-point instructions
(e500v2 only), and single-precision embedded vector floating-point instructions use and return
32-bit values in GPR bits 32–63.

2.3.2 Integer Exception Register (XER)

Bits in the integer exception register (XER) are set based on the operation of an instruction
considered as a whole, not on intermediate results. (For example, the Subtract from Carrying
instruction (subfc), the result of which is specified as the sum of three values, sets bits in the XER
based on the entire operation, not on an intermediate sum.)

The e500 implements the XER as it is defined by Book E.

2.4 Registers for Branch Operations

This section describes registers used by Book E branch and CR operations.

2.4.1 Condition Register (CR)

The e500 implements the CR as it is defin ed by Book E for integer instructions. Note that the
embedded floating-point instructions do not use the CR.

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Register Model

2.4.2 Link Register (LR)

The e500 implements the LR as it is defined by Book E.
The link register can be used to provide the branch target address for a Branch Conditional to LR

instruction, and it holds the return address after branch and link instructions.

2.4.3 Count Register (CTR)

The e500 implements the CTR as it is defined by Book E. The CTR can be used to hold a loop
count that can be decremented and tested during execution of branch instructions that contain an
appropriately encoded BO field. If the CTR value is 0 before being decremented, it is –1 afterward.
The entire CTR can be used to hold the branch target address for a Branch Conditional to CTR
(bcctrx) instruction.

2.5 Processor Control Registers

This section addresses machine state, processor ID, and processor version registers.

2.5.1 Machine State Register (MSR)

The machine state register (MSR), shown in Figure 2-2, defines the state of the processor (that is,
enabling and disabling of interrupts and debugging exceptions, enabling and disabling of address
translation for instruction and data memory accesses, enabling and disabling some APUs, and
specifying whether the processor is in supervisor or user m ode).

Access: Supervisor-only

32 36 37 38 39 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 60 61 62 63

R

W

Reset All zeros

MSR contents are automatically saved, altered, and restored by the interrupt-handling mechanism.
If a non-critical interrupt is taken, MSR contents are automatically copied into SRR1. If a critical
interrupt is taken, MSR contents are automatically copied into CSRR1. When an rfi or rfci is
executed, MSR contents are restored from SRR1 or CSRR1. The e500 implements the machine
check interrupt differently than it is defined in Book E. When a machine check interrupt is taken,
MCSRR0 and MCSRR1 hold the return address and MSR information. The EIS defines the Return
from Machine Check Interrupt instruction, rfmci, which restores MSR contents from MCSRR1
when it is executed.

— UCLE SPE — WE CE — EE PR FP ME —UBLE DE — IS DS —PMM —

Figure 2-2. Machine State Register (MSR)

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Register Model

MSR contents are read into a GPR using mfmsr. The contents of a GPR can be written to MSR
using mtmsr. The write MSR external enable instructions (wrtee and wrteei) can be used to set
or clear MSR[EE] without affecting other M SR bits.

Table 2-3 describes e500-specific MSR fields. Note that other registers in this chapter describe

only fields that are either e500-specific or that differ from the Book E definition.

Table 2-3. MSR Field Descriptions

Bits Name Description

32–36 — Reserved, should be cleared.

37 UCLE User-mode cache lock enable. (e500-specific). Used to restrict user-mode cache-line locking by the operating

system.
0 Any cache lock instruction executed in user-mode takes a cache-locking DSI exception and sets either

ESR[DLK] or ESR[ILK]. This allows the operating system to manage and track the locking/unlocking of cache
blocks by user-mode tasks.

1 Cache-locking instructions can be executed in user-mode and they do not take a DSI for cache-locking. (They

may still take a DSI for access violations, though.)

38 SPE SPE enable. (e500-specific).

0 If software attempts to execute an instruction that accesses the upper word of a GPR, the SPE APU

unavailable exception is taken.

1 Software can execute the following instructions:

On the e500v1, these instructions include the SPE instructions and both vector and scalar single-precision
floating-point instructions.
On the e500v2, these instructions include the SPE instructions, embedded double-precision, and
single-precision vector floating-point instructions. (That is, all instructions that access the upper half of the
64-bit GPRs.)

39–44 — Reserved, should be cleared.

45 WE Wait state enable. On the e500, this allows the core complex to signal a request for power management,

according to the states of HID0[DOZE], HID0[NAP], and HID0[SLEEP].
0 The processor is not in wait state and continues processing. On the e500, no power management request is

signaled to external logic.

1 The processor enters wait state by ceasing to execute instructions and entering low-power mode. Details of

how wait state is entered and exited and how the processor behaves in the wait state are implementation
dependent. On the e500, MSR[WE] gates the DOZE, NAP, and SLEEP outputs from the core complex; as a
result, these outputs negate to the external power management logic on entry to the interrupt and then return
to their previous state on return from the interrupt. WE is cleared on entry to any interrupt and restored to its
previous state upon return.

46 CE Critical enable. Book E defines this bit as an enable for the critical input, watchdog timer, and machine check

interrupts. On the e500, this bit does not affect machine check interrupts.
0 Critical input and watchdog timer interrupts are disabled.
1 Critical input and watchdog timer interrupts are enabled.

47 — Reserved, should be cleared.

48 EE External enable

0 External input, decrementer, fixed-interval timer, and performance monitor interrupts are disabled.
1 External input, decrementer, fixed-interval timer, and performance monitor interrupts are enabled.

49 PR User mode (problem state)

0 The processor is in supervisor mode, can execute any instruction, and can access any resource (for example,

GPRs, SPRs, and the MSR).

1 The processor is in user mode, cannot execute any privileged instruction, and cannot access any privileged

resource.

PR also affects memory access control.

1

1

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Register Model

Table 2-3. MSR Field Descriptions (continued)

Bits Name Description

50 FP Floating-point available. Book E defines the operation of FP as follows:

0 The processor cannot execute floating-point instructions, including floating-point loads, stores, and moves.
1 The processor can execute floating-point instructions.
On the e500, this bit is reserved and permanently cleared, indicating that it does not implement a Book E
floating-point unit (FPU). Setting it has no effect.

51 ME Machine check enable.

0 Machine check interrupts are disabled. On e500 cores, a machine check condition causes a checkstop.
1 Machine check interrupts are enabled.

52 FE0 Floating-point exception mode 0. On the e500, this bit is reserved and permanently cleared, indicating that the

e500 does not implement a Book E FPU. Setting it has no effect.

53 UBLE Allocated for implementation-dependent use. On the e500, it is the user BTB lock enable bit.

0 Execution of the BTB lock instructions for user mode is disabled; a privileged instruction exception is taken

instead.

1 Execution of the BTB lock instructions for user mode is enabled.

54 DE Debug interrupt enable

0 Debug interrupts are disabled.
1 Debug interrupts are enabled if DBCR0[IDM] = 1.
For the e500, see the description of the DBSR[UDE] in Section 2.13.2, “Debug Status Register (DBSR).”

55 FE1 Floating-point exception mode 1. On the e500, this bit is reserved and permanently cleared, indicating that the

e500 does not implement a Book E FPU. Setting it has no effect.

56–57 — Reserved, should be cleared.

58 IS Instruction address space

0 The processor directs all instruction fetches to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs all instruction fetches to address space 1 (TS = 1 in the relevant TLB entry).

59 DS Data address space

0 The processor directs data memory accesses to address space 0 (TS = 0 in the relevant TLB entry).
1 The processor directs data memory accesses to address space 1 (TS = 1 in the relevant TLB entry).

60 — Reserved, should be cleared.

61 PMM Performance monitor mark bit. System software can set PMM when a marked process is running to enable

statistics to be gathered only during the execution of the marked process. MSR[PR] and MSR[PMM] together
define a state that the processor (supervisor or user) and the process (marked or unmarked) may be in at any
tim e. If this state matches an individual state specified in the PMLCa
counting is enabled.

62–63 — Reserved, should be cleared.

1

An MSR bit that is reserved may be altered by return from interrupt instructions.

1

1

n

, the state for which monitoring is enabled,

1

2.5.2 Processor ID Register (PIR)

The e500 implements the processor ID register (PIR) as defined by the Book E architecture. The
PIR contains a value that can be used to distinguish the processor from other processors in the
system.

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Register Model

2.5.3 Processor Version Register (PVR)

The e500 implements the processor version register (PVR) as defined by the Book E architecture.
The read-only PVR, shown in Figure 2-3, contains a value identifying the version and revision
level of the processor. The PVR distinguishes between processors that differ in attributes that may
affect software.

SPR 287 Access: Supervisor read-only

32 47 48 63

R Version Revision

W

Reset(e500v1) 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Reset (e500v2) 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

Figure 2-3. Processor Version Register (PVR)

Table 2-4 describes the PVR fields.

Table 2-4. PVR Field Descriptions

Bits Name Description

32–47 Version A 16-bit number that identifies the version of the processor. Different version numbers indicate major

differences between processors, such as which optional facilities and instructions are supported.

48–63 Revision A 16-bit number that distinguishes between implementations of the version. Different revision numbers

indicate minor differences between processors having the same version number, such as clock rate and
engineering change level.

2.5.4 System Version Register (SVR)

The system version register (SVR), shown in Figure 2-4, contains a read-only SoC-dependent
value; consult the documentation for the implementation.

SPR 1023 Access: Supervisor read-only

32 63

R System version

W

Reset SoC-dependent value (determined by

Figure 2-4. System Version Register (SVR)

svr

[0:31]. See Section 13.2, “Signal Summary.”)

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Register Model

2.6 Timer Registers

The time base (TB), decrementer (DEC), fixed-interval timer (FIT), and watchdog timer provide
timing functions for the system. The e500 provides the ability to select any of the TB bits to trigger
watchdog and fixed-interval timer events, as shown in Figure 2-5.

Time Base (incrementer)

6332

TBU

Watchdog timer events based on one of the TB bits
selected by the EIS–defined TCR[WPEXT] concatenated
with the Book E–defined TCR[WP] (WPEXT || WP).

Fixed-interval timer events based on one of TB bits
selected by the EIS–defined TCR[FPEXT] concatenated
with the Book E–defined TCR[FP] (FPEXT || FP).

Decrementer event = 0/1 detect

32

TBL

DEC

DECAR

6332

Timer Clock
(Time Base Clock)

tbclk

Auto-reload

63

Figure 2-5. Relationship of Timer Facilities to the Time Base

e500 registers involved in timing are described as follows:

• The TB is a long-period counter driven at an implementation-dependent frequency.

• The decrementer, updated at the same rate as the TB, provides a way to signal an exception
after a specified period unless one of the following occurs:

— DEC is altered by software in the interim.
— The TB update frequency changes.
DEC is typically used as a general-purpose software timer.

• The time base for the TB and DE C is selected by the time base enable (TBEN) and select
time base clock (SEL_TBCLK) bits in HID0, as follows:

— If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 0, the time base is updated every 8 bus

clocks.

— If HID0[TBEN] = 1 and HID0[SEL_TBCLK] = 1, the time base is updated on the

rising edge of tbclk (or an implementation-specific clock input).

• Software can select one from of four TB bits to signal a fixed-interval interrupt whenever
the bit transitions from 0 to 1. It is typically used to trigger periodic system maintenance
functions. Bits that may be selected are implementation-dependent.

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Register Model

• The watchdog timer, also a selected TB bit, provides a way to signal a critical exception
when the selected bit transitions from 0 to 1. It is typically used for system error recovery.
If software does not respond in time to the initial interrupt by clearing the associated status
bits in the TSR before the next expiration o f the watchdog timer interval, a watchdog
timer-generated processor reset may result, if so enabled.

All timer facilities must be initialized during start-up.

2.6.1 Timer Control Register (TCR)

The e500 implements the TCR, shown in Figure 2-6, as defined by the Book E architecture except
as follows:

• TCR[WPEXT] and TCR[FPEXT], not specified in Book E, are concatenated with
TCR[WP] and TCR[FP] to select a bit that triggers the watchpoint timer and fixed-interval
timer events.

• The value programmed into WRC is reflected on the e500 wrs signals.

SPR 340 Access: Supervisor-only

32 33 34 35 36 37 38 39 40 41 42 43 46 47 50 51 63

R

WP WRC WIE DIE FP FIE ARE — WPEXT FPEXT —

W

Reset All zeros

Figure 2-6. Timer Control Register (TCR)

Table 2-5 describes the e500 TCR fields that differ from the Book E definiti on.

Bits Name Description

32–33 WP Watchdog timer period. When concatenated with WPEXT, specifies one of 64-bit locations of the time base

34–35 WRC Watchdog timer reset control. When a watchdog reset event occurs, the value programmed into WRC is

38–39 FP Fixed interval timer period. When concatenated with FPEXT, FP specifies one of 64 bit locations of the time

Table 2-5. TCR Implementation-Specific Field Descriptions

used to signal a watchdog timer exception on a transition from 0 to 1.
WPEXT,WP = 0000_00 selects TBU[32] (the msb of the TB)
WPEXT,WP = 1111_11 selects TBL[63] (the lsb of the TB)

reflected on
WRC. Although WRC can be set by software, it cannot be cleared by software (except by a software-induced
reset). Once written to a non-zero value, WRC may no longer be altered by software.
00 No watchdog timer reset will occur.
01 Force processor checkstop on second timeout of watchdog timer
10 Assert processor reset output (
11 Reserved

base used to signal a fixed-interval timer exception on a transition from 0 to 1.
FPEXT || FP = 0000_00 selects TBU[32] (the msb of the TB)
FPEXT || FP = 1111_11 selects TBL[63] (the lsb of the TB)

wrs

and into TSR[WRS], but the WRC bits are reset to 00. At this point, software can reprogram

p_resetout_b

) on second timeout of watchdog timer

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Register Model

Table 2-5. TCR Implementation-Specific Field Descriptions (continued)

Bits Name Description

43–46 WPEXT Watchdog timer period extension (see the description for WP)

47–50 FPEXT Fixed-interval timer period extension (see the description for FP)

2.6.2 Timer Status Register (TSR)

The e500 implements the TSR as it is defined by the Book E architecture. The 32-bit TSR contains
status on timer events and the most recent watchdog timer-initiated processor reset. All TSR bits
function as write-1-to-clear.

2.6.3 Time Base (TBU and TBL)

The e500 implements the time base registers as they are defined by the Book E architecture. The
time base (TB) is composed of two 32-bit registers, the time base upper (TBU) concatenated on
the right with the time base lower (TBL). TB provides timing functions for the system. TB is a
volatile resource and must be initialized during start-up.

2.6.4 Decrementer Register (DEC)

The e500 implements the DEC as it is defined by the Book E architecture. DEC is a 32-bit
decrementing counter that is updated at the same rate as the TB. It provides a way to signal a
decrementer interrupt after a specified period unless one of the following occurs:

• DEC is altered by software in the interim.

• The TB update frequency changes.

DEC is typically used as a general-purpose software timer. The decrementer auto-reload register
is used to automatically reload a programmed value into DEC, as described in Section 2.6.5,

“Decrementer Auto-Reload Register (DECAR).”

2.6.5 Decrementer Auto-Reload Register (DECAR)

The e500 implements the DECAR as it is defined by the Book E architecture. If the auto-reload
function is enabled (TCR[ARE] = 1), the auto-reload value in DECAR is written to DEC when
DEC decrements from 0x0000_0001 to 0x0000_0000. Note that writing DEC with zeros by using
an mtspr[DEC] does not automatically generate a decrementer exception.

2.6.6 Alternate Time Base Registers (ATBL and ATBU)

The alternate time base counter (ATB), shown in Figure 2-7, is formed by concatenating the upper
and lower alternate time base registers (ATBU and ATBL). ATBL (SPR 526) provides read-only

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Register Model

access to the 64-bit alternate time base counter, which is incremented at an
implementation-defined frequency. On the e500v2, this frequency is the core frequency. The ATB
register is accessible in both user and supervisor mode.

Like the TB implementation, the ATBL register is an aliased name for ATB.

SPR 526 Access: User read-only

32 63

R ATBL U

W

Reset All zeros

Figure 2-7. Alternate Time Base Register Lower (ATBL)

Table 2-6 describes the ATB fields.

Table 2-6. ATBL Field Descriptions

Bits Name Description

32–63 ATBCL Alternate time base counter lower

Lower 32 bits of the alternate time base counter

2.6.6.1 Alternate Time Base Upper (ATBU)

The ATBU register, shown in Figure 2-8, provides read-only access to the upper 32 bits of the
alternate time base counter. It is accessible in both user and supervisor mode.

SPR 527 Access: User read-only

32 63

R AT B C U

W

Reset All zeros

Figure 2-8. Alternate Time Base Register Upper (ATBU)

Table 2-7 describes the ATBU fields.

Table 2-7. ATBU Field Descriptions

Bits Name Description

32–63 ATBCU Alternate time base counter upper

Upper 32 bits of the alternate time base counter

2.7 Interrupt Registers

Section 2.7.1, “Interrupt Registers Defined by Book E,” and Section 2.7.2, “e500-Specific
Interrupt Registers,” describe registers used for interrupt handling.

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Register Model

2.7.1 Interrupt Registers Defined by Book E

This section describes the following register bits and their fields:

• Section 2.7.1.1, “Save/Restore Register 0/1 (SRR0 and SRR1)”

• Section 2.7.1.2, “Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)”

• Section 2.7.1.3, “Data Exception Address Register (DEAR)”

• Section 2.7.1.4, “Interrupt Vector Prefix Register (IVPR)”

• Section 2.7.1.5, “Interrupt Vector Offset Registers (IVORs)”

• Section 2.7.1.6, “Exception Syndrome Register (ESR)”

2.7.1.1 Save/Restore Register 0/1 (SRR0 and SRR1)

The e500 implements SRR0 and SRR1 as they are defined by the Book E architecture. On a
noncritical interrupt, SRR0 holds the address of the instruction where the interrupted process
should resume. The instruction is interrupt-specific, although for instruction-caused exceptions, it
is typically the address of the instruction that caused the interrupt. When rfi executes, instruction
execution continues at the address in SRR0.

SRR1 is provided to save and restore machine state on noncritical interrupts. When a noncritical
interrupt is taken, MSR contents are placed in SRR1. When rfi executes, SRR1 contents are placed
into MSR. SRR1 bits that correspond to reserved MSR bits are also reserved. These registers are
not affected by rfci or rfmci. Reserved MSR bits may be altered by rfi, rfci, or rfmci.

2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)

The e500 implements CSRR0 and CSRR1 as they are defined by the Book E architecture. On a
critical interrupt, CSRR0 holds the address of the instruction where the interrupted process should
resume. The instruction is interrupt-specific, although for instruction-caused exceptions, it is
typically the address of the instruction that caused the interrupt. When rfci executes, instruction
execution continues at the address in CSRR0.

CSRR1 is provided to save and restore machine state on critical interrupts. When a critical
interrupt is taken, MSR contents are placed in CSRR1. When rfci executes, SRR1 contents are
placed into MSR. CSRR1 bits that correspond to reserved MSR bits are also reserved. These
registers are not affected by rfi or rfmci. Reserved MSR bits may be altered by rfi, rfci, or rfmci.

2.7.1.3 Data Exception Address Register (DEAR)

The e500 implements DEAR as it is defined by the Book E architecture. DEAR is loaded with the
effective address of a data access (caused by a load, store, or cache management instruction) that
results in an alignment, data TLB miss, or DSI excepti on.

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Register Model

2.7.1.4 Interrupt Vector Prefix Register (IVPR)

The e500 implements IVPR as it is defined by the Book E architecture. It is used with IVORs to
determine the vector address. IVPR[32–47] provides the high-order 16 bits of the address of the
exception processing routines. The 16-bit vector offsets are concatenated to the right of
IVPR[32–47] to form the address of the exception processing routine.

2.7.1.5 Interrupt Vector Offset Registers (IVORs)

The e500 implements the IVORs as defined by the Book E architecture, but use only
IVORn[48–59], as shown in Figure 2-9, to hold the quad-word index from the base address
provided by the IVPR for each interrupt type.

SPR (See Ta bl e 2 - 8 .) Access: Supervisor-only

32 46 47 59 60 63

R

W

Reset All zeros

Figure 2-9. Interrupt Vector Offset Registers (IVORs)

— Interrupt vector offset —

Table 2-8 shows the IVORs implemented on the e500. IVOR0–IVOR15 are defined by the

architecture. (Note that the e500 does not implement IVOR7 and IVOR9.) In addition,
IVOR32–IVOR35 (SPR 528–531) are used by the e500 APUs.

Table 2-8. IVOR Assignments

IVOR Number SPR Interrupt Type

IVOR0 400 Critical input

IVOR1 401 Machine check

IVOR2 402 Data storage

IVOR3 403 Instruction storage

IVOR4 404 External input

IVOR5 405 Alignment

IVOR6 406 Program

IVOR7 407 Floating-point unavailable (Not supported on the e500)

IVOR8 408 System call

IVOR9 409 Auxiliary processor unavailable (Not supported on the e500)

IVOR10 410 Decrementer

IVOR11 411 Fixed-interval timer interrupt

IVOR12 412 Watchdog timer interrupt

IVOR13 413 Data TLB error

IVOR14 414 Instruction TLB error

IVOR15 415 Debug

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Register Model

Table 2-8. IVOR Assignments (continued)

IVOR Number SPR Interrupt Type

IVOR16–IVOR31 — Reserved for future architectural use

IVOR32 528 (e500-specific) SPE APU unavailable

IVOR33 529 (e500-specific) Embedded floating-point data exception

IVOR34 530 (e500-specific) Embedded floating-point round exception

IVOR35 531 (e500-specific) Performance monitor

IVOR36–IVOR63 — Allocated for implementation-dependent use

2.7.1.6 Exception Syndrome Register (ESR)

Figure 2-10 shows the ESR as it is defined on the e500.

The ESR provides a way to differentiate among exceptions that can generate an interrupt type.
When an interrupt is generated, bits corresponding to the specific exception that generated the
interrupt are set and all other ESR bits are cleared. Other interrupt types do not affect ESR
contents. The ESR does not need to be cleared by software. Table 2-9 shows ESR bit definitions.
The e500 defines ESR[SPE] as the SPE/embedded floating-point exception bit. It is set whenever
the processor takes an exception related to the execution of SPE or SPFP instructions. Note that
the e500 does not use the ESR for machine check interrupts, but instead uses the machine check
syndrome register, MCSR, describ ed in Section 2.7.2.4, “Machine Check Syndrome Register

(MCSR).” The ESR is defined in Book E but differs in the following respects:

• The e500 defines ESR[DLK0] (bit 42) as ESR[DLK].

• The e500 defines ESR[DLK1] (bit 43) as ESR[ILK].

• The e500 defines ESR[SPE] (bit 56).

• The e500 does not implement FP, AP, PIE, or PUO.

SPR 62 Access: Supervisor-only

32 35 36 37 38 39 40 41 42 43 44 45 46 47 55 56 57 63

R

W

Reset All zeros

— PIL PPR PTR — ST — DLK ILK — BO — SPE —

Figure 2-10. Exception Syndrome Register (ESR)

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Register Model

Table 2-9 describes the ESR fields, showing the associated interrupts. Note that an implementation

may implement additional ESR bits to identify implementation-specific or architected interrupt
types.

NOTE

ESR information is incomplete, so system software may need to
identify the type of instruction that caused the interrupt, examine the
TLB entry, and examine the ESR to fully identify the exception or
exceptions. For example, a data storage interrupt may be caused by
both a protection violation exception and a byte-ordering exception.
System software would have to look beyond ESR[BO], such as the
state of MSR[PR] in SRR1 and the TLB entry page protection bits to
determine if a protection violation also occurred.

Table 2-9. ESR Field Descriptions

Bits Name Syndrome Interrupt Types

32–35 — Reserved, should be cleared. (Defined by Book E as allocated.) —

36 PIL Illegal instruction exception Program

37 PPR Privileged instruction exception Program

38 PTR Trap exception Program

39 — Not supported on the e500. Defined by Book E as FP (floating-point operations). On the

e500, this bit is reserved and permanently cleared, indicating that the e500 does not
implement a Book E FPU. Setting it has no effect.

40 ST Store operation Alignment, DSI,

41 — Reserved, should be cleared. —

42 DLK Data cache locking (defined by Book E as DLK0). Settings are implementation dependent.

0 Default
1 On the e500, DLK is set when a DSI occurs because dcbtls, dcbtstls, or dcblc is

executed in user mode while MSR[UCLE] = 0.

43 ILK Instruction cache locking. (Book E defines this bit as DLK1.) Set when a DSI occurs

because icbtl or icblc is executed in user mode (MSR[PR] = 1 and MSR[UCLE] = 0)

44 — Not supported on the e500. Defined by Book E as AP (auxiliary processor operation). —

45 — Not supported on the e500. Unimplemented operation exception. On the e500,

unimplemented instructions are handled as illegal instructions.

46 BO Byte-ordering exception DSI, ISI

47 — Not supported on the e500. Defined by Book E as PIE, Imprecise exception. —

—

DTLB error

DSI

DSI

Program

48–55 — Reserved, should be cleared. —

56 SPE SPE/embedded floating-point exception bit (e500-specific)

0 Default
1 Any exception caused by an SPE or and SPFP instruction occurred.

57–63 — Reserved, should be cleared (defined by Book E as allocated). —

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Register Model

2.7.2 e500-Specific Interrupt Registers

This section describes machine check save/store and syndrome registers.

2.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)

When a machine check interrupt is taken, MCSRR0, shown in Figure 2-11, is set to the address of
the instruction where the interrupted process should resume. The instruction is interrupt-specific,
although typically MCSRR0 holds the address of the instruction that caused t he interrupt. After
rfmci executes, instruction execution continues at this address.

SPR 570 Access: Supervisor-only

32 63

R

W

Reset All zeros

Figure 2-11. Machine Check Save/Restore Register 0 (MCSRR0)

2.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)

Next instruction address

MCSRR1 is used to save and restore machine state on machine check interrupts. When a machine
check interrupt is taken, MSR contents are placed into MCSRR1, shown in Figure 2-12. When
rfmci executes, MCSRR1 contents are restored to MSR. MCSRR1 bits that correspond to
reserved MSR bits are also reserved; reserved MSR bits may be altered.

SPR 571 Access: Supervisor-only

32 63

R

W

Reset All zeros

MSR state information

Figure 2-12. Machine Check Save/Restore Register 1 (MCSRR1)

2.7.2.3 Machine Check Address Register (MCAR)

When the core complex takes a machine check interrupt, it updates MCAR (Figure 2-13) to
indicate the address of the data associated with the machin e check. Note that if a machine check
interrupt is caused by a signal, the contents of MCAR are not meaningful.

SPR 573 Access: Supervisor-only

32 63

R

W

Reset All zeros

Machine check address

Figure 2-13. Machine Check Address Register (MCAR)

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Register Model

2.7.2.4 Machine Check Syndrome Register (MCSR)

When the core complex takes a machine check interrupt, it updates MCSR to differentiate between
machine check conditions. The MCSR indicates whether a machine check condition is
recoverable. When a condition bit is set, the core complex asserts MCP_OUT for system
information. ABIST status is logged in MCSR[48–54]. These bits do not initiate machine check
(or any other exception). An ABIST bit being set indicates an error being detected in the
corresponding module. The MCSR is shown in Figure 2-14.

SPR 572 Access: Supervisor-only

32 33 34 35 36 39

R

MCP ICPERR DCP_PERR DCPERR —

W

Reset All zeros

40 47

R

W

Reset All zeros

—

48 55

R

W

Reset All zeros

56 57 58 59 60 61 62 63

R

BUS_IAERR BUS_RAERR BUS_WAERR BUS_IBERR BUS_RBERR BUS_WBERR BUS_IPERR BUS_RPERR

W

Reset All zeros

—

Figure 2-14. Machine Check Syndrome Register (MCSR)

Table 2-10 describes the MCSR fields.

Bit Name Description

32 MCP Machine check input to core

33 ICPERR Instruction cache parity error

34 DCP_PERR Data cache push parity error

35 DCPERR Data cache parity error

36–55 — Reserved, should be cleared.

Table 2-10. MCSR Field Descriptions

mcp

56 BUS_IAERR Bus instruction address error

57 BUS_RAERR Bus read address error

58 BUS_WAERR Bus write address error

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Register Model

Table 2-10. MCSR Field Descriptions (continued)

Bit Name Description

59 BUS_IBERR Bus instruction data bus error

60 BUS_RBERR Bus read data bus error

61 BUS_WBERR Bus write bus error

62 BUS_IPERR Bus instruction parity error

63 BUS_RPERR Bus read parity error

2.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0)

The e500 implements the software-use SPRs (SPRG0–SPRG7 and USPRG0) as defined by the
Book E architecture. They have no defined functionality and are accessed as follows:

• SPRG0–SPRG2—These registers can be accessed only in supervisor mode.

• SPRG3—This register can be written only in supervisor mode. It is readable in supervisor
mode, but whether it can be read in user mode is implementation-dependent. It is readable
in user mode on the e500.

• SPRG4–SPRG7—These registers can be written only in supervisor mode. They are
readable in supervisor or user mode.

• USPRG0—This register can be accessed in supervisor or user mode.

2.9 Branch Target Buffer (BTB) Registers

SPRs are defined in the core complex for enabling the locking and unlocking of entries in the BTB.
These are called the branch buffer entry address register (BBEAR), the branch buffer target address
regis ter (BBTAR), and branch unit control and status register (BUCSR). The user branch locking
enable bit, MSR[UBLE], is defined to allow user-mode programs to lock or unlock BTB entries.

See Section 3.9.1, “Branch T arget Buffer (BTB) Locking Instructions,” for more information
about BTB locking. Section 2.5.1, “Machine State Register (MSR),” describes MSR bits that
support the BTB.

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Register Model

2.9.1 Branch Buffer Entry Address Register (BBEAR)

BBEAR is shown in Figure 2-15. Writing to BBEAR requires synchronization, as described in

Section 2.16, “Synchronization Requirements for SPRs.”

SPR 513 Access: Supervisor/user

32 61 62 63

R

W

Reset All zeros

Figure 2-15. Branch Buffer Entry Address Register (BBEAR)

Table 2-12 describes the BBEAR fields.

Table 2-11. BBEAR Field Descriptions

Bits Name Description

Branch buffer entry address IAB[0–1]

32–61 Branch buffer

entry address

62–63 IAB[0–1] Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the cache block

Branch buffer effective entry address bits 0–29

after the branch. If the branch is the last instruction in the cache block, IAB = 000, to indicate the next
sequential instruction, which resides in the zeroth position of the next cache block.

2.9.2 Branch Buffer Target Address Register (BBTAR)

Figure 2-16 shows the BBTAR. Writing to BBTAR requires synchronization, as described in
Section 2.16, “Synchronization Requirements for SPRs.”

SPR 513 Access: Supervisor/user

32 61 62 63

R

W

Reset All zeros

Figure 2-16. Branch Buffer Target Address Register (BBTAR)

Table 2-12 describes BBTAR fields.

Table 2-12. BBTAR Field Descriptions

Bits Name Description

32–61 Branch buffer

target address

62 IAB2 Instruction after branch bit 2 (with BBEAR[62–63]). IAB is a 3-bit pointer that points to the instruction in

63 BDIRPR Branch direction prediction. The user can pick the direction of the predicted branch.

Branch buffer target address bits 0–29

the cache block after the branch. See the bblels instruction description.

0 The locked address is always predicted as not taken.
1 The locked address is always predicted as taken.

Branch buffer target address IAB2 BDIRPR

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Register Model

2.9.3 Branch Unit Control and Status Register (BUCSR)

The BUCSR, shown in Figure 2-17, is used for general control and status of the branch target
buffer (BTB). Writing to BUCSR requires synchronization, as described in Section 2.16,

“Synchronization Requirements for SPRs.”

SPR 1013 Access: Supervisor-only

32 53 54 55 56 57 58 62 63

R

W

Reset All zeros

Figure 2-17. Branch Unit Control and Status Register (BUCSR)

BUCSR provides control of BTB locking, including the following:

• Enable or disable BTB locking

• Invalidate all BTB entries at once (flash invalidate)

• Unlock all BTB entries at once (flash lock cl ear)

— BBFI BBLO BBUL BBLFC — BPEN

Table 2-13 describes the BUCSR fields.

Bits Name Description

32–53 — Reserved, should be cleared.

54 BBFI Branch buffer flash invalidate. Clearing and then setting BBFI flash clears the valid bit of all entries in the branch

buffer; clearing occurs independently from the value of the enable bit (BPEN). BBFI is always read as 0.

55 BBLO Branch buffer lock overflow status

0 Indicates a lock overflow condition was not encountered in the branch buffer
1 Indicates a lock overflow condition was encountered in the branch buffer
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.

56 BBUL Branch buffer unable to lock

0 Indicates a lock overflow condition in the branch buffer
1 Indicates a lock set instruction failed in the branch buffer, for example, if the BTB is disabled
This sticky bit is set by hardware and is cleared by writing 0 to this bit location.

57 BBLFC Branch buffer lock bits flash clear. Clearing and then setting BBLFC flash clears the lock bit of all entries in the

branch buffer; clearing occurs independently from the value of the enable bit (BPEN). BBLFC is always read as 0.

58–62 — Reserved, should be cleared.

63 BPEN Branch prediction enable

0 Branch prediction disabled
1 Branch prediction enabled (enables BTB to predict branches)

Table 2-13. BUCSR Field Descriptions

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Register Model

2.10 Hardware Implementation-Dependent Registers

This section describes the e500-specific HID0 and HID1 registers.

2.10.1 Hardware Implementation-Dependent Register 0 (HID0)

This section describes the HID0 register, shown in Figure 2-18, as it is defined by the e500 core.

NOTE

Note that some HID fields may not be implemented in a device that
incorporates the e500 core and that some fields may be defined more
specifically by the incorporating device. For specific details it is
important to refer to the “Register Summary” chapter in the device’s
reference manual.

HID0 is used for configuration and control. Writing to HID0 requires synchronization, as
described in Section 2.16, “Synchronization Requirements for SPRs.”

SPR 1008 Access: Supervisor-only

32 33 39 40 41 42 43 47

R

EMCP — DOZE NAP SLEEP —

W

Reset All zeros

48 49 50 51 55 56 57 58 62 63

R

— TBEN SEL_TBCLK — EN_MAS7_UPDATE DCFA — NOPTI

W

Reset All zeros

Figure 2-18. Hardware Implementation-Dependent Register 0 (HID0)

Table 2-14 describes the HID0 fields.

Bits Name Description

32 EMCP Enable machine check signal, mcp

asserting the internal mcp
0mcp
1mcp

33–39 — Reserved, should be cleared.

40 DOZE Doze power management mode. If MSR[WE] is set, this bit controls the

Interpretation of this bit is handled by integrated system logic.
0
1

Table 2-14. HID0 Field Descriptions

. Used to mask out further machine check exceptions caused by

signal.
is disabled.
is enabled. If MSE[ME] = 0, asserting mcp causes checkstop. If MSR[ME] = 1, asserting mcp

causes a machine check exception.

doze

is not asserted.

doze

is asserted.

doze

output signal.

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Register Model

Table 2-14. HID0 Field Descriptions (continued)

Bits Name Description

41 NAP Nap power management mode. If MSR[WE] is set, this bit controls the

Interpretation of this bit is handled by integrated system logic.
0

nap

is not asserted.

1

nap

is asserted.

42 SLEEP Configure for sleep power management mode. If MSR[WE] is set, this bit controls the

signal. Interpretation of this bit is handled by integrated system logic.
0

sleep

is not asserted

1

sleep

is asserted

43–48 — Reserved, should be cleared.

49 TBEN Time base and decrementer enable

0 Time base disabled
1 Time base enabled

50 SEL_TBCLK Select time base clock

0 Time base is based on the processor clock
1 Time base is based on TBCLK input

51–55 — Reserved, should be cleared.

56 EN_MAS7_UPDATE Enable MAS7 update (e500v2 only). Enables updating MAS7 by tlbre and tlbsx.

0 MAS7 is not updated by a tlbre or tlbsx.
1 MAS7 is updated by a tlbre or tlbsx.

57 DCFA Data cache flush assist (e500v2 only). Force data cache to ignore invalid sets on miss replacement

selection.
0 The data cache flush assist facility is disabled
1 The miss replacement algorithm ignores invalid entries and follows the replacement sequence

defined by the PLRU bits. This reduces the series of uniquely addressed load or dcbz instructions
to eight per set. The bit should be set just before beginning a cache flush routine and should be
cleared when the series of instructions is complete.

58–62 — Reserved, should be cleared.

63 NOPTI No-op the data and instruction cache touch instructions.

0 dcbt, dcbtst, and icbt are enabled, as defined by the EIS. Note that on the e500, if CT = 0, icbt

is always a no-op, regardless of the value of NOPTI. If CT = 1, icbt does a touch load to the L2
cache.

1 dcbt, dcbtst, and icbt are treated as no-ops; dcblc and dcbtls are not treated as no-ops.

nap

output signal.

sleep

output

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