Freescale Semiconductor MPC860T User Manual

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MPC860T (Rev. D) Fast Ethernet

Controller

Supplement to the

MPC860 PowerQUICC™ User’s Manual

MPC860TAD/D

Rev. 0.8, 09/1999

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CONTENTS

Paragraph
Number

Title

Chapter 1

Page

Number

Overview

1.1 Document Revision History................................................................................. 1-1

1.2 Overview.............................................................................................................. 1-1

1.3 Comparison with the MPC860............................................................................. 1-2

1.4 Features................................................................................................................1-2

1.4.1 MPC860TBlock Diagram ................................................................................ 1-3

1.4.2 SIU Interrupt Configuration............................................................................. 1-5

1.5 Glueless System Design....................................................................................... 1-5

Chapter 2

FEC External Signals

2.1 Signal Descriptions .............................................................................................. 2-1

Chapter 3

Fast Ethernet Controller Operation

3.1 Transceiver Connection ....................................................................................... 3-1

3.2 FEC Frame Transmission .................................................................................... 3-2

3.3 FEC Frame Reception.......................................................................................... 3-3

3.4 CAM Interface ..................................................................................................... 3-4

3.5 FEC Command Set .............................................................................................. 3-4

3.6 Ethernet Address Recognition ............................................................................. 3-4

3.7 Hash Table Algorithm.......................................................................................... 3-5

3.8 Inter-Packet Gap Time......................................................................................... 3-6

3.9 Collision Handling............................................................................................... 3-6

3.10 Internal and External Loopback........................................................................... 3-7

3.11 Ethernet Error-Handling Procedure ..................................................................... 3-7

3.11.1 Transmission Errors......................................................................................... 3-7

3.11.2 Reception Errors .............................................................................................. 3-7

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CONTENTS

Paragraph
Number

Title

Chapter 4

Page

Number

Parallel I/O Ports

4.1 Port D Pin Functions.............................................................................................4-1

4.1.1 Port D Registers................................................................................................4-2

4.1.2 Enabling MII Mode ..........................................................................................4-2

Chapter 5

SDMA Bus Arbitration and Transfers

5.1 Overview ..............................................................................................................5-1

5.2 The SDMA Registers............................................................................................5-1

5.2.1 SDMA Configuration Register (SDCR)...........................................................5-2

Chapter 6

Programming Model

6.1 Overview ..............................................................................................................6-1

6.2 Parameter RAM....................................................................................................6-1

6.2.1 RAM Perfect Match Address Low Register (ADDR_LOW)...........................6-2

6.2.2 RAM Perfect Match Address High (ADDR_HIGH) .......................................6-3

6.2.3 RAM Hash Table High (HASH_TABLE_HIGH) ...........................................6-3

6.2.4 RAM Hash Table Low (HASH_TABLE_LOW).............................................6-4

6.2.5 Beginning of RxBD Ring (R_DES_START)...................................................6-5

6.2.6 Beginning of TxBD Ring (X_DES_START)...................................................6-5

6.2.7 Receive Buffer Size Register (R_BUFF_SIZE)...............................................6-6

6.2.8 Ethernet Control Register (ECNTRL)..............................................................6-7

6.2.9 Interrupt Event (I_EVENT)/Interrupt Mask Register (I_MASK)....................6-8

6.2.10 Ethernet Interrupt Vector Register (IVEC) ......................................................6-9

6.2.11 RxBD Active Register (R_DES_ACTIVE) ...................................................6-10

6.2.12 TxBD Active Register (X_DES_ACTIVE) ...................................................6-11

6.2.13 MII Management Frame Register (MII_DATA) ...........................................6-12

6.2.14 MII Speed Control Register (MII_SPEED) ...................................................6-14

6.2.15 FIFO Receive Bound Register (R_BOUND) .................................................6-15

6.2.16 FIFO Receive Start Register (R_FSTART) ...................................................6-16

6.2.17 Transmit Watermark Register (X_WMRK ....................................................6-16

6.2.18 FIFO Transmit Start Register (X_FSTART)..................................................6-17

6.2.19 DMA Function Code Register (FUN_CODE) ...............................................6-18

6.2.20 Receive Control Register (R_CNTRL) ..........................................................6-19

6.2.21 Receive Hash Register (R_HASH) ................................................................6-20

6.2.22 Transmit Control Register (X_CNTRL) ........................................................6-21

6.3 Initialization Sequence .......................................................................................6-22

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CONTENTS

Paragraph
Number

6.3.1 Hardware Initialization...................................................................................6-22

6.3.2 User Initialization (before Setting ECNTRL[ETHER_EN]) .........................6-22

6.3.2.1 Descriptor Controller Initialization............................................................6-23

6.3.2.2 User Initialization (after Asserting ECNTRL[ETHER_EN])....................6-23

6.4 Buffer Descriptors (BDs) ...................................................................................6-24

6.4.1 Ethernet Receive Buffer Descriptor (RxBD) .................................................6-24

6.4.2 Ethernet Transmit Buffer Descriptor (TxBD)................................................6-26

Title

Chapter 7

Page

Number

Electrical Characteristics

7.1 DC Electrical Characteristics ...............................................................................7-1

7.2 AC Electrical Characteristics ...............................................................................7-1

7.3 Electrical Specifications.......................................................................................7-1

7.3.1 MII Receive Signal Timing (RXD[3:0], RX_DV, RX_ER, RX_CLK) ..........7-1

7.3.2 MII Transmit Signal Timing (TXD[3:0], TX_EN, TX_ER, TX_CLK) .......... 7-2

7.3.3 MII Async Inputs Signal Timing (CRS, COL) ................................................ 7-3

7.3.4 MII Serial Management Channel Timing (MDIO,MDC)................................7-4

7.4 MPC860T Pin Assignments.................................................................................7-5

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CONTENTS

Paragraph
Number

Title

Page

Number

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ILLUSTRATIONS

Figure
Number

1-1 MPC860T Block Diagram .................................................................................. 1-4

1-2

1-3 MPC860T Serial Configuration.......................................................................... 1-6

3-1 Ethernet Address Recognition Flowchart ........................................................... 3-5

5-1 SDMA Bus Arbitration....................................................................................... 5-1

5-2 SDMA Configuration Register (SDCR) ............................................................. 5-2

6-1 ADDR_LOW Register........................................................................................ 6-2

6-2 ADDR_HIGH Register....................................................................................... 6-3

6-3 HASH_TABLE_HIGH Register ........................................................................ 6-4

6-4 HASH_TABLE_LOW Register ......................................................................... 6-4

6-5 R_DES_START Register ...................................................................................6-5

6-6 X_DES_START Register ................................................................................... 6-6

6-7 R_BUFF_SIZE Register ..................................................................................... 6-7

6-8 ECNTRL Register............................................................................................... 6-7

6-9 I_EVENT/I_MASK Registers ............................................................................ 6-8

6-10 IVEC Register................................................................................................... 6-10

6-11 R_DES_ACTIVE Register ............................................................................... 6-11

6-12 X_DES_ACTIVE Register ............................................................................... 6-12

6-13 MII_DATA Register......................................................................................... 6-13

6-14 MII_SPEED Register........................................................................................ 6-14

6-15 R_BOUND Register .........................................................................................6-15

6-16 R_FSTART Register......................................................................................... 6-16

6-17 X_WMRK Register .......................................................................................... 6-17

6-18 X_FSTART Register ........................................................................................ 6-18

6-19 FUN_CODE Register ....................................................................................... 6-18

6-20 R_CNTRL Register .......................................................................................... 6-19

6-21 R_HASH Register............................................................................................. 6-20

6-22 X_CNTRL Register .......................................................................................... 6-21

6-23 Receive Buffer Descriptor (RxBD) .................................................................. 6-25

6-24 Transmit Buffer Descriptor (TxBD) ................................................................. 6-26

7-1 MII Receive Signal Timing Diagram ................................................................. 7-2

7-2 MII Transmit Signal Timing Diagram................................................................ 7-3

7-3 MII Async Inputs Timing Diagram .................................................................... 7-3

7-4 MII Serial Management Channel Timing Diagram ............................................ 7-4

7-5 MPC860T Pinout DiagramÑTop View ............................................................. 7-5

MPC860T Interrupt Structure ............................................................................. 1-5

Title

Page

Number

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ILLUSTRATIONS

Figure
Number

Title

Page

Number

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TABLES

Tabl e
Number

1-1 Document Revision History................................................................................ 1-1

2-1 FEC Signal Descriptions..................................................................................... 2-1

3-1 MII Signals.......................................................................................................... 3-1

3-2 Serial Mode Connections to the External Transceiver ....................................... 3-2

3-3 Transmission Errors ............................................................................................ 3-7

3-4 Reception Errors ................................................................................................. 3-8

4-1 Port D Pin Assignment........................................................................................ 4-2

5-1 SDCR Field Descriptions.................................................................................... 5-2

6-1 FEC Parameter RAM Memory Map................................................................... 6-1

6-2 ADDR_LOW Field Descriptions........................................................................ 6-3

6-3 ADDR_HIGH Field Descriptions....................................................................... 6-3

6-4 HASH_TABLE_HIGH Field Descriptions ........................................................ 6-4

6-5 HASH_TABLE_LOW Field Descriptions ......................................................... 6-5

6-6 R_DES_START Field Descriptions ................................................................... 6-5

6-7 X_DES_START Field Descriptions ................................................................... 6-6

6-8 R_BUFF_SIZE Field Descriptions..................................................................... 6-7

6-9 ECNTRL Field Descriptions............................................................................... 6-8

6-10 I_EVENT/I_MASK Field Descriptions.............................................................. 6-9

6-11 IVEC Field Descriptions................................................................................... 6-10

6-12 R_DES_ACTIVE Field Descriptions ............................................................... 6-11

6-13 X_DES_ACTIVE Field Descriptions ............................................................... 6-12

6-14 MII_DATA Field Descriptions......................................................................... 6-13

6-15 MII_SPEED Field Descriptions........................................................................ 6-14

6-16 Programming Examples for MII_SPEED Register .......................................... 6-15

6-17 R_BOUND Field Descriptions ......................................................................... 6-15

6-18 R_FSTART Field Descriptions......................................................................... 6-16

6-19 X_WMRK Field Descriptions .......................................................................... 6-17

6-20 X_FSTART Field Descriptions ........................................................................6-18

6-21 FUN_CODE Field Descriptions ....................................................................... 6-19

6-22 R_CNTRL Field Descriptions ..........................................................................6-20

6-23 R_HASH Field Descriptions............................................................................. 6-21

6-24 X_CNTRL Field Descriptions .......................................................................... 6-21

6-25 Hardware Initialization ..................................................................................... 6-22

6-26 ECNTRL[ETHER_EN] Deassertion Initialization........................................... 6-22

6-27 User Initialization (before Setting ECNTRL[ETHER_EN])............................ 6-23

6-27 User Initialization (after Setting ECNTRL[ETHER_EN])............................... 6-24

Title

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TABLES

Tabl e
Number

6-27 Receive Buffer Descriptor (RxBD) Field Description...................................... 6-25

6-29 Transmit Buffer Descriptor (TxBD) Field Descriptions................................... 6-26

7-1 MII Receive Signal Timing ................................................................................ 7-2

7-2 MII Transmit Signal Timing............................................................................... 7-2

7-3 MII Async Inputs Signal Timing ........................................................................ 7-3

7-4 MII Serial Management Channel Timing ........................................................... 7-4

Title

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Number

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Chapter 1
Overview

10
10

This chapter provides an overview of Rev. D of the MPC860T, focussing primarily on the
Fast Ethernet controller (FEC). It provides a discussion of its basic features and a general
look at how the MPC860T can be implemented. This document is provided as a supplement
to the

MPC860 PowerQUICC UserÕs Manual.

Note

This supplement documents Rev D silicon of the MPC860T,
which includes enhancements made to the original MPC860T.
New functionality and changes are shown with change bars and
was made available with Rev D MPC860T at 3Q99. This
document does not replace the supplement that describes the
Rev B.x silicon.

1.1 Document Revision History

Table 1-1 lists signiÞcant changes between revisions of this document.

Table 1-1. Document Revision History

Document Revision Substantive Changes

Rev 0.8 Changed the port D pin function multiplexing control bit Þeld name in the ECNTRL register from

ÔV860TÕ to ÔFEC_PINMUXÕ. See Section Chapter 2, ÒFEC External Signals,Ó and Section 6.2.8,
ÒEthernet Control Register (ECNTRL).Ó

1.2 Overview

The MPC860T is an enhancement to the MPC8xx family with its incorporation of a Fast
Ethernet communication controller. The 10/100 Fast Ethernet controller with integrated
FIFOs and bursting DMA is implemented independently, so high-performance Fast
Ethernet connectivity can be achieved without affecting the CPM performance.

Like the other MPC860 devices, the MPC860T can be used in a variety of controller
applications, excelling particularly in communications and networking products such as
routers that provide WAN-to-LAN functionality. The MPC860T, with the addition of the
10/100Mbps Ethernet channel, adds Fast Ethernet to the already broad list of
communications support.

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The MPC860T integrates three separate processing blocks. The Þrst two, common with all
MPC860 devices, are as follows:

¥ A high-performance PowerPCª core that can be used as a general purpose

processor for application programming

¥ A RISC engine embedded in the communications processor module (CPM)

designed to provide the communications protocol processing provided by the
MPC860MH.

¥ A 10/100 Fast Ethernet controller with integrated FIFOs and bursting DMA.

Because the FEC block is implemented independently, the MPC860T provides
high-performance Fast Ethernet connectivity without affecting the performance of
the CPM. All of the performance and functionality of the MPC860MH is fully
supported, including Ethernet.

Additionally, as the CPM of the MPC860T is based on the CPM of the MPC860MH,
support for the QMC protocol is also provided. This enables the MPC860T to provide
protocol processing (HDLC or transparent mode) for 64 time-division multiplexed
channels at 50 MHz. This support for multichannel protocol processing and 10/100
Ethernet in one chip makes the MPC860T ideal for products such as high-performance,
low-cost remote access routers.

Note that for existing parts, adding FEC functionality affects port D signal multiplexing.

1.3 Comparison with the MPC860

The MPC860T is pin compatible with the MPC860, so it may be used in similar
applications with minimal modiÞcation. The electrical characteristics and mechanical data
are nearly identical, with the exception of port D and the four no connect pins on the
MPC860, which make up the media independent interface (MII). Most of the MII pins are
multiplexed with the port D pins.

1.4 Features

The following sections summarize key FEC features.

¥ 10/100 base-T support

Ñ Full compliance with the IEEE 802.3u standard for 10/100 base-T

Ñ Support for three different physical interfaces: 100-Mbps 802.3

media-independent interface (MII), 10-Mbps 802.3 MII, and 10-Mbps 7-wire
interface

Ñ Large on-chip transmit and receive FIFOs to support a variety of bus latencies

Ñ Retransmission from the transmit FIFO after a collision

1-2

Ñ Automatic internal ßushing of the receive FIFO for runts and collisions

Ñ External BD tables of user-deÞnable size allow nearly unlimited ßexibility in

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management of transmit and receive buffer memory

¥ 10/100 base-T media access control (MAC) features

Ñ Address recognition for broadcast, single station address, promiscuous mode,

and multicast hashing

Ñ Full support of media-independent interface (MII)

Ñ Interrupts supported per frame or per buffer (selectable buffer interrupt

functionality using the I bit is not supported however.)

Ñ Automatic interrupt vector generation for receive and transmit events (Tx

interrupts, Rx interrupts, and non-time critical interrupts)

Ñ Ethernet channel uses DMA burst transactions to transfer data to and from

external memory

1.4.1 MPC860TBlock Diagram

The FEC, the embedded PowerPC core, the system interface unit (SIU), and the
communication processor module (CPM) all use the 32-bit internal bus in an
MPC860Timplementation. Figure 1-1 is a block diagram of the MPC860T. For
information on the other modules, refer to the

MPC860T UserÕs Manual

.

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Instruction

Bus

Embedded

PowerPC

Processor

Core

Fast

Ethernet

Controller

DMAs

FIFOs

Load/Store

Bus

Parallel Interface Port

4-KByte

Instruction Cache

Instruction MMU

4-KByte

Data Cache

Data MMU

Parallel I/O

Baud Rate

Generators

and UTOPIA

4 Timers

32-Bit RISC Controller

Timers

Unified

Bus

Interrupt

Controllers

and Program

ROM

System Interface Unit (SIU)

Memory Controller

Internal

Bus Interface

Unit

System Functions

PCMCIA-ATA Interface

Dual-Port RAM

MAC

External

Bus Interface

Unit

Real-Time Clock

Serial

and

DMA

Channels

10/100

Base-T

Media Access

Control

MII

SCC1 SCC2 SCC3 SCC4 SMC1 SMC2

Time Slot Assigner

Time Slot Assigner

I2CSPI

I2CSPI

Serial Interface

Serial Interface

Figure 1-1. MPC860T Block Diagram

The FEC complies with the IEEE 802.3 speciÞcation for 10- and 100-Mbps connectivity.
Full-duplex 100-Mbps operation is supported at system clock rates of 40 MHz and higher.
A 25-MHz system clock supports 10-Mbps operation or half-duplex 100-Mbps operation.

The implementation of bursting DMA reduces bus usage. Independent DMA channels for
accessing BDs and transmit and receive data minimize latency and FIFO depth
requirements.

Transmit and receive FIFOs further reduce bus usage by localizing all collisions to the FEC.
Transmit FIFOs maintain a full collision window of transmit frame data, eliminating the
need for repeated DMA over the system bus when collisions occur. On the receive side, a
full collision window of data is received before any receive data is transferred into system
memory, allowing the FIFO to be ßushed in the event of a runt or collided frame, with no
DMA activity. However, external memory for buffers and BDs is required; on-chip FIFOs
are designed only to compensate for collisions and for system bus latency.

Independent TxBD and RxBD rings in external memory allow nearly unlimited ßexibility

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in memory management of transmit and receive data frames. External memory (DRAM) is
inexpensive, and because BD rings in external memory have no inherent size limitations,
memory management easily can be optimized to system needs.

1.4.2 SIU Interrupt ConÞguration

As shown in Figure 1-2, the SIU receives interrupts from internal sources, such as the FEC
and other modules and external pins, IRQ

[0Ð7].

System Interface Unit

IRQ[0Ð7]

Edge

Detector

Selector

DEC

SWT

Level 7

IRQ

NMI

GEN

0

NMI

DEC

TB

PIT

RTC

PCMCIA

CPM Interrupt

Controller

FEC

Level 6

Level 5

Level 4

Level 3

Level 2

Level 1

Level 0

PowerPC

IREQ

Interrupt Controller

Core

Debug

Debug

Figure 1-2. MPC860T Interrupt Structure

Note that MII_TXCLK is shared with IRQ7 and becomes active as soon as the ETHER_EN
bit in the Ethernet control register (ECNTRL) is set. IRQ7 must be masked in the system
interface unit (SIU).

1.5 Glueless System Design

A fundamental design goal of the MPC8xx family was ease of interface to other system
components. Examples of system design are located in the MPC860T userÕs manual.

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Figure 1-3 shows the glueless connection of the serial channels to physical layer framers
and transceivers.

MPC8xx

100Base-T
Transceiver

10Base-T

Transceiver

T1 Framer TDM

“7-wire” interface

MII

FEC

SCC1 (Ethernet)

SCC2 (QMC)

SCC3 (QMC)

RS-232

Transceiver

SCC4 (UART)

Figure 1-3. MPC860T Serial Configuration

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Chapter 2
FEC External Signals

20
20

This chapter contains brief descriptions of the MPC860T FEC input and output signals in
their functional groups.

2.1 Signal Descriptions

The MPC860T system bus signals consist of all the lines that interface with the external
bus. Many of these lines perform different functions, depending on how the user assigns
them. The input and output signals, shown in Table 2-1, are identiÞed by their abbreviated
names.

Name

IRQ7
MII_TX_CLK

PD[15]
L1TSYNCA
MII_RXD[3]

PD[14]
L1RSYNCA
MII_RXD[2]

PD[13]
L1TSYNCB
MII_RXD[1]

Table 2-1. FEC Signal Descriptions

Pin

Number

W15 Interrupt request 7ÑThis input is one of the eight external lines that can request (by means

of the internal Interrupt Controller) a service routine from the core. See description of
MII_TXCLK for information about masking IRQ7

MII transmit clockÑInput clock that provides the timing reference for TX_EN, TXD, and
TX_ER. Note that MII_TXCLK becomes active as soon as the ETHER_EN bit in the Ethernet
control register (ECNTRL) is set. IRQ7

U17 General-purpose I/O port D bit 15ÑThis is bit 15 of the general-purpose I/O port D.

Transmit data sync signal for TDM channel A

MII receive data 3ÑInput signal RXD[3] represents bit 3 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.

V19 General-purpose I/O port D bit 14ÑThis is bit 14 of the general-purpose I/O port D.

Input receive data sync signal to the TDM channel A

MII receive data 2ÑInput signal RXD[2] represents bit 2 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.

V18 General-purpose I/O port D bit 13ÑThis is bit 13 of the general-purpose I/O port D.

Transmit data sync signal for TDM channel B

MII receive data 1ÑInput signal RXD[1] represents bit 1 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted.

Description

.

must be masked in the system interface unit (SIU).

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Table 2-1. FEC Signal Descriptions (Continued)

Name

PD[12]
L1RSYNCB
MII_MDC

PD[11]
RXD3
MII_TX_ER

PD[10]
TXD3
MII_RXD[0]

PD[9]
RXD4
MII_TXD[0]

PD[8]
TXD4
MII_RX_CLK

PD[7]
RTS3
MII_RX_ER

PD[6]
RTS4
MII_RX_DV

Pin

Number

R16 General-purpose I/O port D bit 12ÑThis is bit 12 of the general-purpose I/O port D.

L1RSYNCBÑInput receive data sync signal to the TDM channel B.

MII management data clockÑOutput clock provides a timing reference to the PHY for data
transfers on the MDIO signal.

T16 General-purpose I/O port D bit 11ÑThis is bit 11 of the general-purpose I/O port D.

RXD3ÑReceive data for serial channel 3.

MII transmit errorÑOutput signal when asserted for one or more clock cycles while TX_EN is
asserted shall cause the PHY to transmit one or more illegal symbols. Asserting TX_ER has
no effect when operating at 10 Mbps or when TX_EN is negated.

W18 General-purpose I/O port D bit 10ÑThis is bit 10 of the general-purpose I/O port D.

TXD3ÑTransmit data for serial channel 3.

MII receive data 0ÑInput signal RXD[0] represents bit 0 of the nibble of data to be
transferred from the PHY to the MAC when RX_DV is asserted. In 10 Mbps serial mode,
RXD[0] is used and RXD[1Ð3] are ignored.

V17 General-purpose I/O port D bit 9ÑThis is bit 9 of the general-purpose I/O port D.

RXD4ÑReceive data for serial channel 4.

MII transmit data 0ÑOutput signal TXD[0] represents bit 0 of the nibble of data when TX_EN
is asserted and has no meaning when TX_EN is negated. In 10Mbps serial mode, TXD[0] is
used and TXD[1Ð3] are ignored.

W17 General-purpose I/O port D bit 8ÑThis is bit 8 of the general-purpose I/O port D.

TXD4ÑTransmit data for serial channel 4.

MII receive clockÑInput clock which provides a timing reference for RX_DV, RXD, and
RX_ER.

T15 General-purpose I/O port D bit 7ÑThis is bit 7 of the general-purpose I/O port D.

RTS3ÑActive-low request to send output indicates that SCC3 is ready to transmit data.

MII receive errorÑWhen Input signal RX_ER and RX_DV are asserted, the PHY has
detected an error in the current frame. When RX_DV is not asserted, RX_ER has no effect.

V16 General-purpose I/O port D bit 6ÑThis is bit 6 of the general-purpose I/O port D.

RTS4ÑActive low request to send output indicates that SCC4 is ready to transmit data.

MII receive data validÑWhen input signal RX_DV is asserted, the PHY is indicating that a
valid nibble is present on the MII. This signal shall remain asserted from the Þrst recovered
nibble of the frame through the last nibble. Assertion of RX_DV must start no later than the
SFD and exclude any EOF.

Description

PD[5]
REJECT2
MII_TXD[3]

2-2

U15 General-purpose I/O port D bit 5ÑThis is bit 5 of the general-purpose I/O port D.

Reject 2ÑThis input to SCC2 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.

MII transmit data 3ÑOutput signal TXD[3] represents bit 3 of the nibble of data when TX_EN
is asserted and has no meaning when TX_EN is negated.

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Table 2-1. FEC Signal Descriptions (Continued)

Name

PD[4]
REJECT3
MII_TXD[2]

PD[3]
REJECT4
MII_TXD[1]

MII_TX_EN V15 MII transmit enableÑOutput signal TX_EN indicates when there are valid nibbles being

MII_CRS B7 MII carrier receive senseÑWhen input signal CRS is asserted the transmit or receive

MII_COL H4 MII collisionÑInput signal COL is asserted upon detection of a collision, and will remain

MII_MDIO H18 MII management dataÑBidirectional signal, MDIO transfers control information between the

Pin

Number

U16 General-purpose I/O port D bit 4ÑThis is bit 4 of the general-purpose I/O port D.

Reject 3ÑThis input to SCC3 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.

MII transmit data 2ÑOutput signal TXD[2] represents bit 2 of the nibble of data when TX_EN
is asserted and has no meaning when TX_EN is negated.

W16 General-purpose I/O port D bit 3ÑThis is bit 3 of the general-purpose I/O port D.

Reject 4ÑThis input to SCC4 allows a CAM to reject the current Ethernet frame after it
determines the frame address did not match.

MII transmit data 1ÑOutput signal TXD[1] represents bit 1 of the nibble of data when TX_EN
is asserted and has no meaning when TX_EN is negated.

presented on the MII. This signal is asserted with the Þrst nibble of preamble and is negated
prior to the Þrst TX_CLK following the Þnal nibble of the frame.

Note the following:

W

For 860T rev D.1, a 10-k
three-stated following reset until ECNTRL[FEC_PINMUX] is set.
For 860T rev D.2 and later, MII_TX_EN is a dedicated output and no pull-down resister is
required.
For 860T rev E.x (planned), MII_TX_EN resets to three-state with a weak internal
pull-down to ensure compatibility with 860 applications that may have tied SPARE3 (V15)
to VCC or GND. This pin will be 3-V only and must not be pulled up to +5 V.

medium is not idle. In the event of a collision, CRS will remain asserted through the duration
of the collision.

asserted while the collision persists. The behavior of this signal is not speciÞed for full-duplex
mode.

PHY and MAC. Transitions synchronously to MDC.

pull-down resistor must be used with MII_TX_EN, which is

Description

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Chapter 3
Fast Ethernet Controller Operation

30
30

This chapter discusses the operation of the FEC.

3.1 Transceiver Connection

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a seven-wire serial
interface for 10-Mbps Ethernet. The interface mode is selected by
R_CNTRL[MII_MODE], described in Section 6.2.20, ÒReceive Control Register
(R_CNTRL).Ó Table 3-1 shows the 18 MII interface signals that are deÞned by the 802.3
standard.

Table 3-1. MII Signals

Signal Description FEC Signal Name

Transmit clock TX_CLK

Transmit enable TX_EN

Transmit data TXD[3:0]

Transmit error TX_ER

Collision COL

Carrier sense CRS

Receive clock RX_CLK

Receive enable RX_DV

Receive data RXD[3:0]

Receive error RX_ER

Management channel clock MDC

Management channel serial data MDIO

Serial-mode connections to the external transceiver are shown in Table 3-2.

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3-1