Freescale Semiconductor MPC8358E, MPC8360E Hardware Specificftion

Freescale Semiconductor

Document Number: MPC8360EEC

Technical Data

MPC8360E/MPC8358E
PowerQUICC II Pro Processor
Revision 2.x TBGA Silicon
Hardware Specifications

Rev. 4, 01/2011

This document provides an overview of the MPC8360E/58E
PowerQUICC II Pro processor revision 2.x TBGA features,
including a block diagram showing the major functional
components. This device is a cost-effective, highly
integrated communications processor that addresses the
needs of the networking, wireless infrastructure, and
telecommunications markets. Target applications include
next generation DSLAMs, network interface cards for 3G
base stations (Node Bs), routers, media gateways, and high
end IADs. The device extends current PowerQUICC II Pro
offerings, adding higher CPU performance, additional
functionality, faster interfaces, and robust interworking
between protocols while addressing the requirements related
to time-to-market, price, power, and package size. This
device can be used for the control plane and also has data
plane functionality.

For functional characteristics of the processor, refer to the

MPC8360E PowerQUICC II Pro Integrated
Communications Processor Family Reference Manual,

Rev. 3.
To locate any updates for this document, refer to the

MPC8360E product summary page on our website listed on
the back cover of this document or contact your Freescale
sales office.

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . 8

3. Power Characteristics . . . . . . . . . . . . . . . . . . . 13

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . 15

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . 17

6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . 20

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

8. UCC Eth er net Controller: Three-Speed Ethernet,

MII Management . . . . . . . . . . . . . . . . . . . . . . . 28

9. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

2

11. I

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

12. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

13. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

14. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

16. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

17. TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

18. UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . 62

19. H D LC, BISYNC, Transparent, and Synchronous

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

20. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

21. Package and Pin Listings . . . . . . . . . . . . . . . . . 68

22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

24. System Design Information . . . . . . . . . . . . . . 102

25. Ordering Information . . . . . . . . . . . . . . . . . . . 106

26. Document Revision History . . . . . . . . . . . . . 107

© 2011 Freescale Semiconductor, Inc. All rights reserved.

Overview

Memory Controllers

GPCM/UPM/SDRAM

32/64 DDR Interface Unit

PCI Bridge

Local Bus

Bus Arbitration

DUART

Dual I2C

4 Channel DMA

Interrupt Controller

Protection & Configuration

System Reset

Clock Synthesizer

System Interface Unit

(SIU)

Local

Baud Rate

Generators

Multi-User

RAM

UCC8

Parallel I/O

Accelerators

Dual 32-Bit RISC CP

Serial DMA

&

2 Virtual

DMAs

2 GMII/

RGMII/TBI/RTBI

8 MII/

RMII

8 TDM Ports

2 UTOPIA/POS

(124 MPHY)

Serial Interface

QUICC Engine Module

JTAG/COP

Power

Management

Timers

FPU

Classic G2 MMUs

32KB

D-Cache

32KB

I-Cache

Security Engine

e300 Core

PCI

DDRC1

UCC7

UCC6

UCC5

UCC4

UCC3

UCC2

UCC1

MCC

USB

SPI2

Time Slot Assigner

DDRC2

SPI1

1Overview

This section describes a high-level overview including features and general operation of the
MPC8360E/58E PowerQUICC II Pro processor. A major component of this device is the e300 core, which
includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture™
603e instruction set. The new QUICC Engine module provides termination, interworking, and switching
between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine
module’s enhanced interworking eases the transition and reduces investment costs from A TM to IP based
systems. The other major features include adual DDR SDRAM memory controller for the MPC8360E,
which allows equipment providers to partition system para me ters and data in an extr eme ly ef fic ie nt way,
such as using one 32-bit DDR memory controller for control plane processing and the other for data plane
processing. The MPC8358E has a single DDR SDRAM memory controller. The MPC8360E/58E also
offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine.

Figure 1 shows the MPC8360Eblock diagram.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

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Figure 1. MPC8360E Block Diagram

Figure 2 shows the MPC8358E block diagram.

Memory Controllers

GPCM/UPM/SDRAM

32/64 DDR Interface Unit

PCI Bridge

Local Bus

Bus Arbitration

DUART

Dual I2C

4 Channel DMA

Interrupt Controller

Protection & Configuration

System Reset

Clock Synthesizer

System Interface Unit

(SIU)

Local

Baud Rate

Generators

Multi-User

RAM

UCC8

Parallel I/O

Accelerators

Dual 32-Bit RISC CP

Serial DMA

&

2 Virtual

DMAs

2 GMII/

RGMII/TBI/RTBI

6 MII/

RMII

4 TDM Ports

1 UTOPIA/POS
(31/124 MPHY)

Serial Interface

QUICC Engine Module

JTAG/COP

Power

Management

Timers

FPU

Classic G2 MMUs

32KB

D-Cache

32KB

I-Cache

Security Engine

e300 Core

PCI

DDRC

UCC5

UCC4

UCC3

UCC2

UCC1

USB

SPI2

Time Slot Assigner

SPI1

Overview

Figure 2. MPC8358E Block Diagram

Major features of the MPC8360E/58E are as follows:

• e300 PowerPC processor core (enhanced version of the MPC603e core)
— Operates at up to 667 MHz (for the MPC8360E) and 400 MHz (for the MPC8358E)
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the Freescale processor families implementing the Power

Architecture™ technology

• QUICC Engine unit
— Two 32-bit RISC controllers for flexible support of the communications peripherals, each

operating up to 500 M Hz (for the MPC8360E) and 400 MHz (for the MPC8358E)

— Serial DMA channel for receive and transmit on all serial channels

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Overview

— QUICC Engine module peripheral request interface (for SEC, PCI, IEEE Std. 1588™)
— Eight universal communication controllers (UCCs) on the MPC8360E and six UCCs on the

MPC8358E supporting the following protocols and interfaces (not all of them simultaneous ly):
– IEEE 1588 protocol supported
– 10/100 Mbps Ethernet/IEEE Std. 802.3™ CDMA/CS interface through a

media-independent interface (MII, RMII, RGMII)

1

– 1000 Mbps Ethernet/IEEE 802.3 CDMA/CS interface through a media-independent

interfac e (GM II, RGMII, TBI, RTB I) on UCC1 and UCC2
– 9.6-Kbyte jumbo frames
– ATM full-duplex SAR, up to 622 Mbps (OC-12/STM-4), AAL0, AAL1, and AAL5 in

accordance ITU-T I.363.5
– AT M AAL2 CPS, SSSAR, and SSTED up to 155 Mbps (OC-3/STM-1) Mbps full duplex

(with 4 CPS packets per cell) in accordance ITU-T I.366.1 and I.363.2
– ATM traffic shaping for CBR, VBR, UBR, and GFR traffic types compatible with ATM

forum TM4.1 for up to 64-Kbyte simultaneous ATM channels
– ATM AAL1 structured and unstructured circuit emulation service (CES 2.0) in accordance

with ITU-T I.163.1 and ATM Forum af-vtoa-00-0078.000
– IMA (Inverse Multiplexing over ATM) for up to 31 IMA links over 8 IMA groups in

accordance with the ATM forum AF-PHY-0086.000 (Version 1.0) and AF-PHY-0086.001

(Version 1.1)
– AT M Transmission Convergence layer support in accordance with ITU-T I.432
– AT M OAM handling features compatible with ITU-T I.610
– PPP, Multi- Link (ML-PPP) , Multi-Class (MC-PPP ) and PPP mux in accordance with the

following RFCs: 1661, 1662, 1990, 2686, and 3153
– IP support for IPv4 packets including TOS, TTL, and header checksum processing
– Ethernet over first mile IEEE 802.3ah
– Shim header
– Ethernet-to-Ethernet/AAL5/AAL2 inter-working
– L2 Ethernet switching using MAC address or IEEE Std. 802.1P/Q™ VLAN tags
– ATM (AAL2/AAL5) to Ethernet (IP) interworking in accordance with RFC2684 including

bridging of ATM ports to Ethernet ports
– Extensive support for ATM statistics and Ethernet RMON/MIB statistics
– AAL2 protocol rate up to 4 CPS at OC-3/STM-1 rate
– Packet over Sonet (POS) up to 622-Mbps full-duplex 124 MultiPHY
– POS hardware; microcode must be loaded as an IRAM package
– Transparent up to 70-Mbps full-duplex
– HDLC up to 70-Mbps full-duplex
– HDLC BUS up to 10 Mbps

1.SMII or SGMII media-inde pendent interface is not currently supported.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

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Overview

– Asynchronous HDLC
– UART
– BISYNC up to 2 Mbps
– User-programmable Virtual FIFO size
– QUICC multichannel controller (QMC) for 64 TDM channels

— One multichannel communication controller (MCC) only on the MPC8360E supporting the

following:
– 256 HDLC or transparent channels
– 128 SS7 channels
– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces

— Two UTOPIA/POS interfaces on the MPC8360E supporting 124 MultiPHY each (optional

2*128 MultiPHY with extended address) and one UTOPIA/POS interface on the MPC8358E
supporting 31/124 MultiPHY

— Two serial pe rip he ra l in te rfaces (SPI); SPI2 is dedicated to Ethernet PHY management
— Eight TDM interfaces on the MPC8360E and four TDM interfaces on the MPC8358E with

1-bit mode for E3/T3 rates in clear channel

— Sixteen independent baud rate generators and 30 input clock pins for supplying clocks to UCC

and MCC serial channels (MCC is only available on the MPC8360E)

— Four independent 16-bit timers that can be interconnected as four 32-bit timers
— Interworking functionality:

– Layer 2 10/100-Base T Ethernet switch
– ATM-to-ATM switching (AAL0, 2, 5)
– Ethernet-to-ATM switching with L3/L4 support
– PPP interworking

• Security engine is optimized to handle all the algorithms asso ciated with IPS ec, SSL/TLS, SR TP,

802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a
controller, and a set of crypto execution units (EUs).

— Public key execution unit (PKEU) supporting the following:

– RSA and Diffie-Hellman
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits

— Data encryption standard execution unit (DEU)

–DES, 3DES
– Two key (K1, K2) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES

— Advanced encryption standard unit (AESU)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

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Overview

— Implements the Rinjdael symmetric key cipher
— Key lengths of 128, 192, and 256 bits, two key

– ECB, CBC, CCM, and counter modes

— ARC four execution unit (AFEU)

– Implements a stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key

— Message digest execution unit (MDEU)

– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either SHA or MD5 algorithm

— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains

– Static and/or dynamic assignment of crypto-execution units via an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

— Storage/NAS XOR parity generation accelerator for RAID applications

• Dual DDR SDRAM memory controllers on the MPC8360E and a single DDR SDRAM memory
controller on the MPC8358E

— Programmable timing supporting both DDR1 and DDR2 SDRAM
— On the MPC8360E, the DDR buses can be configured as two 32-bit buses or one 64-bit bus;

on the MPC8358E, the DDR bus can be configured as a 32- or 64-bit bus

— 32- or 64-bit data interface, up to 333 MHz (for the MPC8360E) and 266 MHz (for the

MPC8358E) data rate
— Four banks of memory, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gigabit with ×8/×16 data ports
— Full ECC support (when the MPC8360E is configured as 2×32-bit DDR memory controllers,

both support ECC)
— Page mode support (up to 16 s imultaneous open pages for DDR1, up to 32 simultaneous open

pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— Supports source clock mode
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compa tible I/O for DDR1, 1.8-V SST L2 c omp at ible I/ O for DDR2
— External driver impedance calibration
— On-die termination (ODT)

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

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• PCI interface
— PCI Specification Revision 2.3 compatible
— Data bus widths:

– Single 32-bit data PCI interface that operates at up to 66 MHz
— PCI 3.3-V compatible (not 5-V compatible)
— PCI host bridge capabilities on both interfaces
— PCI agent mode supported on PCI interface
— Support for PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Support for posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration, supporting five masters on PCI
— Support for accesses to all PCI address spaces
— Parity support
— Selectable hardware-enforced coherency
— Address translation units for address mapping between host and peripheral
— Dual address cycle supported when the device is the target

Overview

— Internal configuration registers accessible from PCI

• Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:

– General-purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)

– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)

• Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for one external (optional) and seven internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to communication proc ess o r
— Redirects interrupts to external INTA
— Unique vector number for each interrupt source

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 7

pin when in core disable mode

Electrical Characteristics

• Dual industry-standard I2C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I2C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data is optionally loaded from I

embedded hardware

• DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— All channels accessible by local core and remote PCI masters
— Misaligned transfer capability
— Data chaining and direct mode
— Interrupt on completed segment and chain
— DMA external handshake signals: DMA_DREQ[0:3]/DMA_DACK[0:3]/DMA_DONE[0:3].

There is one set for each DMA channel. The pins are multiplexed to the parallel IO pins with
other QE functions.

• DUART

2

C-1 EPROM by boot sequencer

— T wo 4-wire interfaces (RxD, TxD, RTS, CTS)
— Programming model compatible with the original 16450 UART and the PC16550D

• System timers
— Periodic interrupt timer
— Real-time clock
— Software watchdog timer
— Eight general-purpose timers

• IEEE Std. 1149.1™-compliant, JTAG boundary scan

• Integrated PCI bus and SDRAM clock generation

2 Electrical Characteristics

This section provides the AC and DC electrical specificati ons and thermal char act er isti cs f or the
MPC8360E/58E. The device is currently targeted to these specifications. Some of these specifications are
independent of the I/O cell, but are included for a more complete reference. These are not pur ely I/O buffer
design specifications.

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8 Freescale Semiconductor

2.1 Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1 Absolute Maximum Ratings

Table 1 provides the absolute maximum ratings.

Table 1. Absolute Maximum Ratings

Characteristic Symbol Max Value Unit Notes

Electrical Characteristics

1

Core supply voltage

V

For QUICC Engine module frequencies <500 MHz and e300

frequencies <667 MHz

For a QUICC Engine module frequency of 500 MHz or an e300

frequency of 667 MHz

PLL supply voltage

AV

For QUICC Engine module frequencies <500 MHz and e300

frequencies <667 MHz

For a QUICC Engine module frequency of 500 MHz or an e300

frequency of 667 MHz

DDR and DDR2 DRAM I/O voltage

GV

DDR

DDR2

Three-speed Ethernet I/O, MII management voltage LV

PCI, local bus, DUART, system control and power management, I

2

C,

OV

SPI, and JTAG I/O voltage

Input voltage DDR DRAM signals MV

DDR DRAM reference MV

Three-speed Ethernet signals LV

Local bus, DUART, CLKIN, system control
and power management, I

2

C, SPI, and

OV

JTAG signals

DD

DD

DD

DD

DD

REF

IN

V—
–0.3 to 1.32
–0.3 to 1.37

V—
–0.3 to 1.32
–0.3 to 1.37

V—
–0.3 to 2.75
–0.3 to 1.89

–0.3 to 3.63 V —

–0.3 to 3.63 V —

IN

–0.3 to (GVDD + 0.3) V 2, 5

–0.3 to (GVDD + 0.3) V 2, 5

–0.3 to (LVDD + 0.3) V 4, 5

IN

–0.3 to (OVDD + 0.3) V 3, 5

PCI OV

Storage temperature range T

Notes:

1. Functional and tested operating conditions are given in Ta bl e 2 . Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.

2. Caution: MV

must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

IN

power-on reset and power-down sequences.

3. Caution: OV

must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

IN

power-on reset and power-down sequences.

4. Caution: LV

must not exceed LVDD by more than 0.3 V. This limit may be exceeded for a maximum of 100 ms during

IN

power-on reset and power-down sequences.

5. (M,L,O)V

6. OV

on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as

IN

and MV

IN

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 3.

REF

shown in Figure 4.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 9

IN

STG

–0.3 to (OVDD + 0.3) V 6

–55 to 150 °C—

Electrical Characteristics

2.1.2 Power Supply Voltage Specification

Table 2 provides the recommended operating conditions for the device. Note that the values in Table 2 are

the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.

Table 2. Recommended Operating Conditions

Characteristic Symbol

Core supply voltage

For QUICC Engine module frequencies <500 MHz and e300

frequencies <667 MHz

For a QUICC Engine module frequency of 500 MHz or an e300

frequency of 667 MHz

PLL supply voltage

AV

For QUICC Engine module frequencies <500 MHz and e300

frequencies <667 MHz

For a QUICC Engine module frequency of 500 MHz or an e300

frequency of 667 MHz

DDR and DDR2 DRAM I/O supply voltage

GV

DDR

DDR2

Three-speed Ethernet I/O supply voltage LV

Three-speed Ethernet I/O supply voltage LV

Three-speed Ethernet I/O supply voltage LV

PCI, local bus, DUART, system control and power management, I

C, SPI,

OV

2

and JTAG I/O voltage

Recommended

Value

V

DD

1.2 V ± 60 mV

1.3 V ± 50 mV

DD

1.2 V ± 60 mV

1.3 V ± 50 mV

DD

2.5 V ± 125 mV

1.8 V ± 90 mV

0 3.3 V ± 330 mV

DD

2.5 V ± 125 mV

1 3.3 V ± 330 mV

DD

2.5 V ± 125 mV

2 3.3 V ± 330 mV

DD

2.5 V ± 125 mV

DD

3.3 V ± 330 mV V —

Unit Notes

V1

V1

V—

V—

V—

V—

Junction temperature T

J

0 to 105

°C2

–40 to 105

Notes:

1. GV

, LVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or

DD

negative direction.

2. The operating conditions for junction temperature, T
0° to 70 °C. Refer to Errata General9 in

Chip Errata for the MPC8360E, Rev. 1

, on the 600/333/400 MHz and 500/333/500 MHz on rev. 2.0 silicon is

J

.

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10 Freescale Semiconductor

Figure 3 shows the undershoot and overshoot voltages at the interfaces of the device.

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

G/L/OVDD + 20%

G/L/OV

DD

G/L/OVDD + 5%

of t

interface

1

1. Note that t

interface

refers to the clock period associated with the bus clock interface.

V

IH

V

IL

Note:

Undervoltage

Waveform

Overvoltage

Waveform

11 ns

(Min)

+7.1 V

7.1 V p-to-p
(Min)

4 ns
(Max)

–3.5 V

7.1 V p-to-p
(Min)

62.5 ns
+3.6 V

0 V

4 ns
(Max)

Electrical Characteristics

Figure 3. Overshoot/Undershoot Voltage for GVDD/OVDD/LV

DD

Figure 4 shows the undershoot and overshoot voltage of the PCI interface of the device for the 3.3-V

signals, respectively.

Figure 4. Maximum AC Waveforms on PCI interface for 3.3-V Signaling

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

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Electrical Characteristics

2.1.3 Output Driver Characteristics

Table 3 provides information on the characteristics of the output driver strengths. The values are

preliminary estimates.

Table 3. Output Drive Capability

Driver Type Output Impedance (Ω) Supply Voltage

Local bus interface utilities signals 42 OV

PCI signals 25

PCI output clocks (including PCI_SYNC_OUT) 42

DDR signal 20

36 (half-strength mode)

DDR2 signal 18

36 (half-strength mode)

10/100/1000 Ethernet signals 42 LV

DUART, system control, I

GPIO signals 42 OV

1

DDR output impedance values for half strength mode are verified by design and not tested.

2

C, SPI, JTAG 42 OVDD = 3.3 V

1

1

= 3.3 V

DD

GV

= 2.5 V

DD

GVDD = 1.8 V

= 2.5/3.3 V

DD

= 3.3 V

DD

LV

= 2.5/3.3 V

DD

2.2 Power Sequencing

This section details the power sequencing considerations for the MPC8360E/58E.

2.2.1 Power-Up Sequencing

MPC8360E/58E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages
(GVDD, LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the
power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period
of time that all input and output pins will actively be driven and cause contention and excessive current.
In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core
voltage (V
supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise
to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 5.

) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power

DD

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

12 Freescale Semiconductor

Power Characteristics

I/O Voltage (GVDD, LVDD, OVDD)

Core Voltage (V

DD

, AVDD)

90%

0.7 V

Time

Voltage

Figure 5. Power Sequencing Example

I/O voltage supplies (GVDD, L VDD, and OVDD) do not have any ordering require ments with res pect to one
another.

2.2.2 Power-Down Sequencing

The MPC8360E/58E does not requir e the core supply voltage and I/O supply voltages to be powered down
in any particular order.

3 Power Characteristics

The estimated typical power dissipation values are shown in Table 4 and Table 5.

Table 4. MPC8360E TBGA Core Power Dissipation

Core

Frequency (MHz)

266 266 500 5.0 5.6 W 2, 3, 5

400 266 400 4.5 5.0 W 2, 3, 4

533 266 400 4.8 5.3 W 2, 3, 4

667 333 400 5.8 6.3 W 3, 6, 7, 8

500 333 500 5.9 6.4 W 3, 6, 7, 8

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical Maximum Unit Notes

1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 13

Power Characteristics

Table 4. MPC8360E TBGA Core Power Dissipation1 (continued)

Core

Frequency (MHz)

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical Maximum Unit Notes

667 333 500 6.1 6.8 W 2, 3, 5, 9

Notes:

1. The values do not include I/O supply power (OV

2. Typical power is based on a voltage of V

= 1.2 V or 1.3 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark

DD

, LVDD, GVDD) or AVDD. For I/O power values, see Ta b l e 6 .

DD

application.

3. Thermal solutions will likely need to design to a value higher than typical power on the end application, T
power.

4. Maximum power is based on a voltage of V

5. Maximum power is based on a voltage of V
a junction T

= 105°C, and an artificial smoke test.

J

6. Typical power is based on a voltage of V

= 1.2 V, WC process, a junction TJ = 105°C, and an artificial smoke test.

DD

= 1.3 V for applications that use 667 MHz (CPU)/500 (QE) with WC process,

DD

= 1.3 V, a junction temperature of TJ = 70°C, and a Dhrystone benchmark

DD

application.

7. Maximum power is based on a voltage of V
a junction T

= 70°C, and an artificial smoke test.

J

= 1.3 V for applications that use 667 MHz (CPU) or 500 (QE) with WC process,

DD

8. This frequency combination is only available for rev. 2.0 silicon.

9. This frequency combination is not available for rev. 2.0 silicon.

1

Core

Frequency (MHz)

Table 5. MPC8358E TBGA Core Power Dissipation

CSB

Frequency (MHz)

QUICC Engine

Frequency (MHz)

Typical Maximum Unit Notes

target, and I/O

A

266 266 300 4.1 4.5 W 2, 3, 4

400 266 400 4.5 5.0 W 2, 3, 4

Notes:

1. The values do not include I/O supply power (OV

2. Typical power is based on a voltage of V

DD

, LVDD, GVDD) or AVDD. For I/O power values, see Ta b l e 6 .

DD

= 1.2 V, a junction temperature of TJ = 105°C, and a Dhrystone benchmark

application.

3. Thermal solutions will likely need to design to a value higher than typical power on the end application, T
power.

4. Maximum power is based on a voltage of V

= 1.2 V, WC process, a junction TJ = 105°C, and an artificial smoke test.

DD

target, and I/O

A

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

14 Freescale Semiconductor

Table 6 shows the estimated typical I/O power dissipation for the device.

Table 6. Estimated Typical I/O Power Dissipation

Clock Input Timing

Interface Parameter

DDR I/O
65% utilization
R

= 20 Ω

s

R

= 50 Ω

t

2 pairs of clocks

Local Bus I/O
Load = 25 pf
3 pairs of clocks

PCI I/O
Load = 30 pF

200 MHz, 1 × 32 bits 0.3 0.46 — — — W —

200 MHz, 1 × 64 bits 0.4 0.58 — — — W —

200 MHz, 2 × 32 bits 0.6 0.92 — — — W —

266 MHz, 1 × 32 bits 0.35 0.56 — — — W —

266 MHz, 1 × 64 bits 0.46 0.7 — — — W —

266 MHz, 2 × 32 bits 0.7 1.11 — — — W —

333 MHz, 1 × 32 bits 0.4 0.65 — — — W —

333 MHz, 1 × 64 bits 0.53 0.82 — — — W —

333 MHz, 2 × 32 bits 0.81 1.3 — — — W —

133 MHz, 32 bits — — 0.22 — — W —

83 MHz, 32 bits — — 0.14 — — W —

66 MHz, 32 bits — — 0.12 — — W —

50 MHz, 32 bits — — 0.09 — — W —

33 MHz, 32 bits — — 0.05 — — W —

66 MHz, 32 bits — — 0.07 — — W —

GV

DD

(1.8 V)

GV

DD

(2.5 V)

OV

DD

(3.3 V)

LV

DD

(3.3 V)

LV

DD

(2.5 V)

Unit Comments

10/100/1000
Ethernet I/O
Load = 20 pF

Other I/O — — — 0.1 — — W —

MII or RMII — — — 0.01 — W Multiply by

GMII or TBI — — — 0.04 — W

RGMII or RTBI ————0.04W

number of
interfaces used.

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the MPC8360E/58E.

NOTE

The rise/fall time on QUICC Engine block input pins should not exceed 5
ns. This should be enforced especially on clock signals. Rise time refers to
signal transitions from 10% to 90% of VDD; fall time refers to transitions
from 90% to 10% of V

DD

.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 15

Clock Input Timing

4.1 DC Electrical Characteristics

Table 7 provides the clock input (CLKIN/PCI_SYNC_IN) DC timing specifications for the device.

Table 7. CLKIN DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit

Input high voltage — V

Input low voltage — V

CLKIN input current 0 V ≤ V

PCI_SYNC_IN input current 0 V ≤ V

OV

– 0.5V ≤ VIN ≤ OV

DD

PCI_SYNC_IN input current 0.5 V ≤ V

≤ OV

IN

DD

≤ 0.5V or

IN

DD

≤ OVDD – 0.5 V I

IN

IH

IL

I

IN

I

IN

IN

2.7 OVDD + 0.3 V

–0.3 0.4 V

—±10μA

—±10μA

—±100μA

4.2 AC Electrical Characteristics

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. Table 8 provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 8. CLKIN AC Timing Specifications

Parameter/Condition Symbol Min Typical Max Unit Notes

CLKIN/PCI_CLK frequency f

CLKIN/PCI_CLK cycle time t

CLKIN/PCI_CLK rise and fall time t

CLKIN/PCI_CLK duty cycle t

CLKIN

CLKIN

, t

KH

KL

KHK/tCLKIN

CLKIN/PCI_CLK jitter — — — ±150 ps 4, 5

— — 66.67 MHz 1

15 — — ns —

0.6 1.0 2.3 ns 2

40 — 60 % 3

Notes:

1. Caution: The system, core, USB, security, and 10/100/1000 Ethernet must not exceed their respective maximum or minimum
operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter—short term and long term—and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

16 Freescale Semiconductor

4.3 Gigabit Reference Clock Input Timing

Table 9 provides the Gigabit reference clocks (GT X_CLK125) AC timing specifications.

Table 9. GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LVDD = 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter/Condition Symbol Min Typical Max Unit Notes

RESET Initialization

GTX_CLK125 frequency t

GTX_CLK125 cycle time t

GTX_CLK rise and fall time

LV

= 2.5 V

DD

LV

= 3.3 V

DD

GTX_CLK125 duty cycle

GMII & TBI

1000Base-T for RGMII & RTBI

GTX_CLK125 jitter — — — ±150 ps 2

Notes:

1. Rise and fall times for GTX_CLK125 are measured from 0.5 and 2.0 V for LV
LV

=3.3V.

DD

2. GTX_CLK125 is used to generate the GTX clock for the UCC Ethernet transmitter with 2% degradation. The GTX_CLK125
duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle generated by GTX_CLK.
See Section 8.2.2, “MII AC Timing Specifications,” Section 8.2.3, “RMII AC Timing Specifications,” and Section 8.2.5, “RGMII

and RTBI AC Timing Specifications” for the duty cycle for 10Base-T and 100Base-T reference clock.

G125

G125

t

G125R/tG125F

t

G125H/tG125

— 125 — MHz —

—8—ns—

——

—
45
47

= 2.5 V and from 0.6 and 2.7 V for

DD

0.75

1.0

55
53

ns 1

%2

5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the MPC8360E/58E.

5.1 RESET DC Electrical Characteristics

Table 10 provides the DC electrical characteristics for the RESET pins of the device.

Table 10. RESET Pins DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage V

Input low voltage V

Input current I

Output high voltage V

Output low voltage V

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 17

IH

IL

IN

OH

OL

—2.0OV

— –0.3 0.8 V

——±10μA

I

= –8.0 mA 2.4 — V

OH

IOL = 8.0 mA — 0.5 V

+ 0.3 V

DD

RESET Initialization

Table 10. RESET Pins DC Electrical Characteristics (continued)

Characteristic Symbol Condition Min Max Unit

Output low voltage V

OL

I

= 3.2 mA — 0.4 V

OL

Notes:

1. This table applies for pins PORESET

2. HRESET

and SRESET are open drain pins, thus VOH is not relevant for those pins.

, HRESET, SRESET, and QUIESCE.

5.2 RESET AC Electrical Characteristics

This section describes the AC electrical specifications for the reset initialization timing requireme nts of
the device. Table 11 provides the reset initialization AC timing specifications for the DDR SDRAM
component(s).

Table 11. RESET Initialization Timing Specifications

Parameter/Condition Min Max Unit Notes

Required assertion time of HRESET

Required assertion time of PORESET

or SRESET (input) to activate reset flow 32 — t

with stable clock applied to CLKIN

when the device is in PCI host mode

Required assertion time of PORESET

with stable clock applied to

PCI_SYNC_IN when the device is in PCI agent mode

HRESET

HRESET

/SRESET assertion (output) 512 — t

negation to SRESET negation (output) 16 — t

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET

when the device is

in PCI host mode

PCI_SYNC_IN

32 — t

32 — t

4—t

CLKIN

PCI_SYNC_IN

PCI_SYNC_IN

PCI_SYNC_IN

CLKIN

1

2

1

1

1

2

Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET

when the device is

4—t

PCI_SYNC_IN

1

in PCI agent mode

Input hold time for POR config signals with respect to negation of HRESET

Time for the device to turn off POR config signals with respect to the
assertion of HRESET

Time for the device to turn on POR config signals with respect to the negation
of HRESET

0— ns

—4 ns 3

1—t

PCI_SYNC_IN

1, 3

Notes:

1. t

PCI_SYNC_IN

is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary

clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual

2. t

is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the

CLKIN

MPC8360E PowerQUICC II Pro Integrated Communications Processor Family Reference Manual

for more details.

for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

18 Freescale Semiconductor

RESET Initialization

Table 12 provides the PLL and DLL lock times.

Table 12. PLL and DLL Lock Times

Parameter/Condition Min Max Unit Notes

PLL lock times — 100 μs—

DLL lock times 7680 122,880 csb_clk cycles 1, 2

Notes:

1. DLL lock times are a function of the ratio between the output clock and the coherency system bus clock (csb_clk). A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.

2. The csb_clk is determined by the CLKIN and system PLL ratio. See Section 22, “Clocking,” for more information.

5.3 QUICC Engine Block Operating Frequency Limitations

This section specify the limits of the AC electrical characteristics for the opera tion of the QUICC Engine
block’s communication interfaces.

NOTE

The settings listed below are required for correct hardware interface
operation. Each protocol by itself requires a minimal QUICC Engine block
operating frequency setting for meeting the performance target. Because the
performance is a complex function of all the QUICC Engine block settings,
the user should make use of the QUICC Engine block performance utility
tool provided by Freescale to validate their system.

Table 13 lists the maximal QUICC Engine block I/O frequencies and the minimal QUICC Engine block

core frequency for each interface.

Table 13. QUICC Engine Block Operating Frequency Limitations

Interface

Ethernet Management: MDC/MDIO 10 (max) 10 20 —

MII 25 (typ) 100 50 —

RMII 50 (typ) 100 50 —

GMII/RGMII/TBI/RTBI 125 (typ) 1000 250 —

SPI (master/slave) 10 (max) 10 20 —

UCC through TDM 50 (max) 70 8 × F2

MCC 25 (max) 16.67 16 × F 2, 4

UTOPIA L2 50 (max) 800 2 × F2

POS-PHY L2 50 (max) 800 2 × F2

HDLC bus 10 (max) 10 20 —

HDLC/transparent 50 (max) 50 8/3 × F2, 3

Interface Operating

Frequency (MHz)

Max Interface Bit

Rate (Mbps)

Min QUICC Engine

Operating

Frequency

1

(MHz)

Notes

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 19

DDR and DDR2 SDRAM

Table 13. QUICC Engine Block Operating Frequency Limitations (continued)

Interface

Interface Operating

Frequency (MHz)

UART/async HDLC 3.68 (max internal ref

Max Interface Bit

Rate (Mbps)

115 (Kbps) 20 —

Min QUICC Engine

Operating

Frequency

1

(MHz)

Notes

clock)

BISYNC 2 (max) 2 20 —

USB 48 (ref clock) 12 96 —

Notes:

1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.

2. ‘F’ is the actual interface operating frequency.

3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).

4. TDM in high-speed mode for serial data interface.

6 DDR and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8360E/58E.

6.1 DDR and DDR2 SDRAM DC Electrical Characteristics

Table 14 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the

device when GVDD(typ) = 1.8 V.

Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GV

I/O reference voltage MV

I/O termination voltage V

Input high voltage V

Input low voltage V

Output leakage current I

Output high current (V

Output low current (V

MV

input leakage current I

REF

= 1.420 V) I

OUT

= 0.280 V) I

OUT

VREF

TT

IH

OZ

OH

OL

DD

REF

IL

1.71 1.89 V 1

0.49 × GV

MV

MV

REF

DD

– 0.04 MV

REF

+ 0.125 GV

–0.3 MV

0.51 × GV

REF

DD

+ 0.04 V 3

REF

+ 0.3 V —

DD

– 0.125 V —

V2

—±10μA4

–13.4 — mA —

13.4 — mA —

—±10μA—

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

20 Freescale Semiconductor

DDR and DDR2 SDRAM

Table 14. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V (continued)

Parameter/Condition Symbol Min Max Unit Notes

Input current (0 V ≤VIN ≤ OVDD)IIN—±10μA—

Notes:

1. GV

2. MV

3. V

is expected to be within 50 mV of the DRAM GV

DD

is expected to equal 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak noise

REF

on MV

TT

MV

cannot exceed ±2% of the DC value.

REF

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to equal

. This rail should track variations in the DC level of MV

REF

4. Output leakage is measured with all outputs disabled, 0 V

at all times.

DD

≤ V

REF

OUT

.

≤ GVDD.

Table 15 provides the DDR2 capacitance when GVDD(typ) = 1.8 V.

Table 15. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

C

IO

C

DIO

68pF1

—0.5pF1

Note:

1. This parameter is sampled. GV

= 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, V

DD

= GVDD/2, V

OUT

(peak-to-peak) = 0.2 V.

OUT

Table 16 provides the recommended operating conditions for the DDR SDRAM component(s) of the

device when GVDD(typ) = 2.5 V.

Table 16. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

I/O supply voltage GV

I/O reference voltage MV

I/O termination voltage V

Input high voltage V

Input low voltage V

Output leakage current I

Output high current (V

Output low current (V

MV

input leakage current I

REF

Input current (0 V ≤V

= 1.95 V) I

OUT

= 0.35 V) I

OUT

≤ OVDD)I

IN

DD

REF

TT

IH

IL

OZ

OH

OL

VREF

IN

Notes:

1. GV

2. MV

3. V

is expected to be within 50 mV of the DRAM GV

DD

is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak

REF

noise on MV

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

TT

equal to MV

may not exceed ±2% of the DC value.

REF

. This rail should track variations in the DC level of MV

REF

4. Output leakage is measured with all outputs disabled, 0 V

at all times.

DD

≤ V

OUT

2.375 2.625 V 1

0.49 × GV

MV

– 0.04 MV

REF

MV

+ 0.18 GV

REF

–0.3 MV

DD

0.51 × GV

DD

+ 0.04 V 3

REF

+ 0.3 V —

DD

– 0.18 V —

REF

—±10μA4

–15.2 — mA —

15.2 — mA —

—±10μA—

—±10μA—

.

REF

≤ GVDD.

V2

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 21

DDR and DDR2 SDRAM

Table 17 provides the DDR capacitance when GVDD(typ) = 2.5 V.

Table 17. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit Notes

Input/output capacitance: DQ, DQS C

Delta input/output capacitance: DQ, DQS C

Note:

1. This parameter is sampled. GV

= 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, V

DD

IO

DIO

68pF1

—0.5pF1

= GVDD/2, V

OUT

(peak-to-peak) = 0.2 V.

OUT

6.2 DDR and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR and DDR2 SDRAM interface.

6.2.1 DDR and DDR2 SDRAM Input AC Timing Specifications

Table 18 provides the input AC timing specifications for the DDR2 SDRAM interface when

GVDD(typ) = 1.8 V.

Table 18. DDR2 SDRAM Input AC Timing Specifications for GVDD(typ) = 1.8 V

At recommended operating conditions with GVDD of 1.8 V ± 5%.

Parameter Symbol Min Max Unit Notes

AC input low voltage V

AC input high voltage V

IL

IH

Table 19 provides the input AC timing specifications for the DDR SDRAM interface when

GVDD(typ) = 2.5 V.

—MV

MV

+ 0.25 — V —

REF

– 0.25 V —

REF

Table 19. DDR SDRAM Input AC Timing Specifications

At recommended operating conditions with GVDD of 2.5 V ± 5%.

Parameter Symbol Min Max Unit Notes

AC input low voltage V

AC input high voltage V

Note:

1. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7)
or ECC (MECC[{0...7}] if n = 8).

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

22 Freescale Semiconductor

IL

IH

—MV

MV

+ 0.31 — V —

REF

– 0.31 V —

REF

Table 20. DDR and DDR2 SDRAM Input AC Timing Specifications Mode

MCK[n]

MCK[n]

t

MCK

MDQ[x]

MDQS[n]

t

DISKEW

D1D0

t

DISKEW

At recommended operating conditions with GVDD of (1.8 or 2.5 V) ± 5%.

Parameter Symbol Min Max Unit Notes

DDR and DDR2 SDRAM

MDQS—MDQ/MECC input skew per byte

333 MHz
266 MHz
200 MHz

Notes:

1. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

2. Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if 0 ≤ n ≤ 7)
or ECC (MECC[{0...7}] if n = 8).

t

DISKEW

–750
–1125
–1250

750
1125
1250

ps 1, 2

Figure 6 shows the input timing diagram for the DDR controller.

Figure 6. DDR Input Timing Diagram

6.2.2 DDR and DDR2 SDRAM Output AC Timing Specifications

Table 21 and Table 22 provide the output AC timing specifications and measurement conditions for the

DDR and DDR2 SDRAM interface.

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source

Synchronous Mode

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

Parameter

MCK[n] cycle time, (MCK[n]/MCK

Skew between any MCK to ADDR/CMD

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 23

8

[n] crossing) t

333 MHz
266 MHz
200 MHz

Symbol

t

MCK

AOSKEW

1

Min Max Unit Notes

610ns2

ns 3
–1.0
–1.1
–1.2

0.2

0.3

0.4

DDR and DDR2 SDRAM

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source

Synchronous Mode (continued)

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

Parameter

8

ADDR/CMD output setup with respect to MCK

333 MHz
266 MHz
200 MHz

ADDR/CMD output hold with respect to MCK

333 MHz
266 MHz—DDR1
266 MHz—DDR2

200 MHz

MCS

(n) output setup with respect to MCK

333 MHz

266 MHz

200 MHz

MCS

(n) output hold with respect to MCK

333 MHz

266 MHz

200 MHz

MCK to MDQS t

MDQ/MECC/MDM output setup with respect to MDQS

333 MHz

266 MHz

200 MHz

MDQ/MECC/MDM output hold with respect to MDQS

333 MHz

266 MHz

200 MHz

Symbol

t

DDKHAS

t

DDKHAX

t

DDKHCS

t

DDKHCX

DDKHMH

t

DDKHDS

t

DDKLDS

t

DDKHDX

t

DDKLDX

1

Min Max Unit Notes

—ns4

2.1

2.8

3.5

—ns4

2.0

2.7

2.8

3.5

—ns4

2.1

2.8

3.5

—ns4

2.0

2.7

3.5

–0.8 0.7 ns 5, 9

,

—ns6

0.7

1.0

1.2

,

—ns6

0.7

1.0

1.2

MDQS preamble start t

DDKHMP

–0.5 × t

– 0.6 –0.5 × t

MCK

+ 0.6 ns 7

MCK

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

24 Freescale Semiconductor

Table 21. DDR and DDR2 SDRAM Output AC Timing Specifications for Source

Synchronous Mode (continued)

At recommended operating conditions with GVDD of (1.8 V or 2.5 V) ± 5%.

DDR and DDR2 SDRAM

Parameter

8

MDQS epilogue end t

Symbol

DDKHME

1

Min Max Unit Notes

–0.6 0.9 ns 7

Notes:

1. The symbols used for timing specifications follow the pattern of t
inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

(first two letters of functional block)(signal)(state)(reference)(state)

for outputs. Output hold time can be read as DDR timing

for

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
(A) are setup (S) or output valid time. Also, t

symbolizes DDR timing (DD) for the time t

DDKHAS

memory clock reference (K) goes from the high (H) state until outputs

MCK

symbolizes DDR timing (DD) for the time t

DDKLDX

memory clock reference

MCK

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK

3. In the source synchronous mode, MCK/MCK
For the skew measurements referenced for t

referenced measurements are made from the crossing of the two signals ±0.1 V.

can be shifted in ¼ applied cycle increments through the clock control register.

AOSKEW

it is assumed that the clock adjustment is set to align the

address/command valid with the rising edge of MCK.

4. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK

, MCS, and MDQ/MECC/MDM/MDQS. For the
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
½ applied cycle.

5. Note that t

DDKHMH

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t

follows the symbol conventions described in note 1. For example, t

DDKHMH

DDKHMH

describes the DDR timing (DD)

can be modified through control
of the DQSS override bits in the TIMING_CFG_2 register. In source synchronous mode, this will typically be set to the same
delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these two
parameters have been set to the same adjustment value. See the

Communications Processor Family Reference Manual

for a description and understanding of the timing modifications

MPC8360E PowerQUICC II Pro Integrated

enabled by use of these bits.

6. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the device.

7. All outputs are referenced to the rising edge of MCK(n) at the pins of the device. Note that t

DDKHMP

follows the symbol

conventions described in note 1.

8. AC timing values are based on the DDR data rate, which is twice the DDR memory bus frequency.

9. In rev. 2.0 silicon, t

DDKHMH

–0.9 ns. Refer to Errata DDR18 in

maximum meets the specification of 0.6 ns. In rev. 2.0 silicon, due to errata, t

Chip Errata for the MPC8360E, Rev. 1

.

DDKHMH

minimum is

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 25

DDR and DDR2 SDRAM

ADDR/CMD

MCK[n]

MCK[n]

t

MCK

CMD NOOP

t

AOSKEW(min)

ADDR/CMD

CMD NOOP

t

AOSKEW(max)

Output

Z0 = 50 Ω

GVDD/2

R

L

= 50 Ω

Figure 7 shows the DDR SDRAM output timing for address skew with respect to any MCK.

Figure 7. Timing Diagram for t

Figure 8 provides the AC test load for the DDR bus.

Figure 8. DDR AC Test Load

Table 22. DDR and DDR2 SDRAM Measurement Conditions

Symbol DDR DDR2 Unit Notes

V

TH

V

OUT

Notes:

1. Data input threshold measurement point.

2. Data output measurement point.

MV

± 0.31 V MV

REF

0.5 × GV

DD

AOSKEW

REF

0.5 × GV

Measurement

± 0.25 V V 1

DD

V2

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

26 Freescale Semiconductor

Figure 9 shows the DDR SDRAM output timing diagram for source synchronous mode.

ADDR/CMD

t

DDKHAS

, t

DDKHCS

t

DDKHMH

t

DDKLDS

t

DDKHDS

MDQ[x]

MDQS[n]

MCK

[n]

MCK[n]

t

MCK

t

DDKLDX

t

DDKHDX

D1D0

Write A0 NOOP

t

DDKHME

t

DDKHMP

t

DDKHAX

, t

DDKHCX

DUART

Figure 9. DDR SDRAM Output Timing Diagram for Source Synchronous Mode

7DUART

This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8360E/58E.

7.1 DUART DC Electrical Characteristics

Table 23 provides the DC electrical characteristics for the DUART interface of the device.

Table 23. DUART DC Electrical Characteristics

Parameter Symbol Min Max Unit Notes

High-level input voltage V

Low-level input voltage OV

High-level output voltage, I

Low-level output voltage, I

Input current (0 V ≤V

Note:

1. Note that the symbol V

DD

= –100 μAV

OH

= 100 μAV

OL

≤ OVDD)I

IN

, in this case, represents the OVIN symbol referenced in Ta bl e 1 and Ta b le 2 .

IN

IH

V

IL

OH

OL

IN

2OV

+ 0.3 V —

DD

–0.3 0.8 V —

OVDD – 0.4 — V —

—0.2V—

—±10μA1

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 27

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

7.2 DUART AC Electrical Specifications

Table 24 provides the AC timing parameters for the DUART interface of the device.

Table 24. DUART AC Timing Specifications

Parameter Value Unit Notes

Minimum baud rate 256 baud —

Maximum baud rate >1,000,000 baud 1

Oversample rate 16 — 2

Notes:

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values
are sampled each sixteenth sample.

8 UCC Ethernet Controller: Three-Speed Ethernet,

MII Management

This section provides the AC and DC electrical chara cteristics for three-speed, 10/100/1000, and MII
management.

8.1 Three-Speed Ethernet Controller (10/100/1000 Mbps)—
GMII/MII/RMII/TBI/RGMII/RTBI Electrical Characteristics

The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), RMII (reduced media independent interface), TBI (ten-bit interface) ,
RGMII (reduced gigabit media independent interface), and RTBI (reduced ten-bit interface) signals except
MDIO (management data input/output) and MDC (management data clock). The MII, RMII, GMII, and
TBI interfaces are only defined for 3.3 V, while the RGMII and RTBI interfaces are only defined for 2.5 V.
The RGMII and RTBI interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit
Ethernet Physical Layer Device Specification V ersion 1.2a (9/22/2000). The electrical characteristics for
the MDIO and MDC are specified in Section 8.3, “Ethernet Management Interface Electrical

Characteristics.”

8.1.1 10/100/1000 Ethernet DC Electrical Characteristics

The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit
media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent
interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).

The MII and RMII interfaces are defined for 3.3 V , while the RGMII and R T BI interfaces can be operated
at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface

(RGMII) Specification Version 1.3. The RMII interface follo ws the RMII Consortium RMII Specification
Ver sion 1.2.

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28 Freescale Semiconductor

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

Table 25. RGMII/RTBI, GMII, TBI, MII, and RMII DC Electrical Characteristics (when operating at 3.3 V)

Parameter Symbol Conditions Min Max Unit Notes

Supply voltage 3.3 V LV

Output high voltage V

Output low voltage V

Input high voltage V

Input low voltage V

Input current I

DD

OH

OL

IH

IN

IOH = –4.0 mA LVDD = Min 2.40 LVDD + 0.3 V —

IOL = 4.0 mA LVDD = Min GND 0.50 V —

——2.0LV

IL

— — –0.3 0.90 V —

— 2.97 3.63 V 1

0 V ≤ VIN ≤ LV

DD

—±10μA—

Note:

1. GMII/MII pins that are not needed for RGMII, RMII, or RTBI operation are powered by the OV

Table 26. RGMII/RTBI DC Electrical Characteristics (when operating at 2.5 V)

Parameters Symbol Conditions Min Max Unit

Supply voltage 2.5 V LV

Output high voltage V

Output low voltage V

Input high voltage V

Input low voltage V

Input current I

DD

OH

OL

IH

IL

IN

IOH = –1.0 mA LVDD = Min 2.00 LVDD + 0.3 V

I

= 1.0 mA LV

OL

—LV

—LV

— 2.37 2.63 V

= Min GND – 0.3 0.40 V

DD

= Min 1.7 LVDD + 0.3 V

DD

= Min –0.3 0.70 V

DD

0 V ≤ VIN ≤ LV

DD

+ 0.3 V —

DD

supply.

DD

—±10μA

8.2 GMII, MII, RMII, TBI, RGMII, and RTBI AC Timing Specifications

The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.

8.2.1 GMII Timing Specifications

This sections describe the GMII transmit and receive AC timing specifications.

8.2.1.1 GMII Transmit AC Timing Specifications

Table 27 provides the GMII transmit AC timing specifications.

Table 27. GMII Transmit AC Timing Specifications

At recommended operating conditions with LVDD/OV

Parameter/Condition Symbol

GTX_CLK clock period t

GTX_CLK duty cycle t

GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay t

GTX_CLK clock rise time, (20% to 80%) t

of 3.3 V ± 10%.

DD

GTX

GTXH/tGTX

GTKHDX

t

GTKHDV

GTXR

1

Min Typ Max Unit Notes

—8.0—ns—

40 — 60 % —

0.5
—

——

5.0

ns 3

——1.0ns—

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

Freescale Semiconductor 29

UCC Ethernet Controller: Three-Speed Ethernet, MII Management

GTX_CLK

TXD[7:0]

t

GTKHDX

t

GTX

t

GTXH

t

GTXR

t

GTXF

TX_EN
TX_ER

Table 27. GMII Transmit AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OV

Parameter/Condition Symbol

of 3.3 V ± 10%.

DD

1

Min Typ Max Unit Notes

GTX_CLK clock fall time, (80% to 20%) t

GTX_CLK125 clock period t

GTX_CLK125 reference clock duty cycle measured at
LV

DD/2

t

G125H/tG125

GTXF

G125

——1.0ns—

—8.0—ns2

45 — 55 % 2

Notes:

1. The symbols used for timing specifications follow the pattern t
and t

(first two letters of functional block)(reference)(state)(signal)(state)

(GT) with respect to the t

clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching

GTX

the valid state (V) to state or setup time. Also, t

GTKHDX

for outputs. For example, t

symbolizes GMII transmit timing (GT) with respect to the t

(first two letters of functional block)(signal)(state)(reference)(state)

symbolizes GMII transmit timing

GTKHDV

for inputs

GTX

reference (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of t

represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is

GTX

used with the appropriate letter: R (rise) or F (fall).

2. This symbol is used to represent the external GTX_CLK125 signal and does not follow the original symbol naming
convention.

3. In rev. 2.0 silicon, due to errata, t
Refer to Errata

QE_ENET18

in

minimum and t

GTKHDX

GTKHDV

Chip Errata for the MPC8360E, Rev. 1

maximum are not supported when the GTX_CLK is selected.

.

Figure 10 shows the GMII transmit AC timing diagram.

clock

Figure 10. GMII Transmit AC Timing Diagram

8.2.1.2 GMII Receive AC Timing Specifications

Table 28 provides the GMII receive AC timing specifications.

Table 28. GMII Receive AC Timing Specifications

At recommended operating conditions with LVDD/OV

Parameter/Condition Symbol

RX_CLK clock period t

RX_CLK duty cycle t

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK t

RXD[7:0], RX_DV, RX_ER hold time to RX_CLK t

RX_CLK clock rise time, (20% to 80%) t

MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4

30 Freescale Semiconductor

of 3.3 V ± 10%.

DD

GRX

GRXH/tGRX

GRDVKH

GRDXKH

GRXR

1

Min Typ Max Unit Notes

—8.0—ns—

40 — 60 % —

2.0 — — ns —

0.2 — — ns 2

——1.0ns—