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MC68HC908MR16
User Manual
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Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 User Manual

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MC68HC908MR32 MC68HC908MR16
Data Sheet
M68HC08 Microcontrollers
MC68HC908MR32 Rev. 6.1 07/2005
freescale.com
MC68HC908MR32 MC68HC908MR16
Data Sheet
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Freescale Semiconductor 3

Revision History

The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
August,
2001
October,
2001
December,
2001
November,
2003
July,
2005
Revision
Level
Figure 2-1. MC68HC908MR32 Memory Map — Added FLASH Block Protect
3.0
4.0 3.3.3 Conversion Time — Reworked equations and text for clarity. 50
5.0
6.0
6.1 Updated to meet Freescale identity guidelines. Throughout
Register (FLBPR) at address location $FF7E
Figure A-1. MC68HC908MR16 Memory Map — Added FLASH Block Protect Register (FLBPR) at address location $FF7E
Figure 18-8. Monitor Mode Circuit — PTA7 and connecting circuitry added 279
Table 18-2. Monitor Mode Signal Requirements and Options — Switch locations added to column headings for clarity
Section 16. Timer Interface A (TIMA) — Timer discrepancies corrected throughout this section.
Section 17. Timer Interface B (TIMB) — Timer discrepancies corrected throughout this section.
Reformatted to meet current publication standards Throughout
2.8.2 FLASH Page Erase Operation — Procedure reworked for clarity 42
2.8.3 FLASH Mass Erase Operation — Procedure reworked for clarity 42
2.8.4 FLASH Program Operation — Procedure reworked for clarity 43
Figure 14-14. SIM Break Status Register (SBSR) — Clarified definition of SBSW bit. 207
19.5 DC Electrical Characteristics — Corrected maximum value for monitor mode entry voltage (on IRQ
19.6 FLASH Memory Characteristics — Updated table entries 292
)
Description
Page
Number(s)
29
306
281
233
255
291
4 Freescale Semiconductor

List of Chapters

Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Chapter 2 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Chapter 3 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Chapter 4 Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Chapter 5 Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Chapter 6 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Chapter 7 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Chapter 8 External Interrupt (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Chapter 9 Low-Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Chapter 10 Input/Output (I/O) Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
Chapter 11 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) . . . . . . . . . . . . . . . . . . .115
Chapter 13 Serial Communications Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . .157
Chapter 14 System Integration Module (SIM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
Chapter 15 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
Chapter 16 Timer Interface A (TIMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Chapter 17 Timer Interface B (TIMB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
Chapter 18 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Chapter 19 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
Chapter 20 Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . .275
Appendix A MC68HC908MR16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
Freescale Semiconductor 5
List of Chapters
6 Freescale Semiconductor

Table of Contents

Chapter 1
General Description
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.3 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.4.1 Power Supply Pins (V
1.4.2 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.3 External Reset Pin (RST
1.4.4 External Interrupt Pin (IRQ
1.4.5 CGM Power Supply Pins (V
1.4.6 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.7 Analog Power Supply Pins (V
1.4.8 ADC Voltage Decoupling Capacitor Pin (V
1.4.9 ADC Voltage Reference Low Pin (V
1.4.10 Port A Input/Output (I/O) Pins (PTA7–PTA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.12 Port C I/O Pins (PTC6–PTC2 and PTC1/ATD9–PTC0/ATD8). . . . . . . . . . . . . . . . . . . . . . . 23
1.4.13 Port D Input-Only Pins (PTD6/IS3
1.4.14 PWM Pins (PWM6–PWM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.4.15 PWM Ground Pin (PWMGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA and PTE2/TCH1B–PTE0/TCLKB) . . . . . . . . 24
1.4.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD and PTF3/MISO–PTF0/SPSCK) . . . . . . . . . . . . . . 24
and VSS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DDA
DDAD
and V
and V
REFL
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SSAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SSAD
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
–PTD4/IS1 and PTD3/FAULT4–PTD0/FAULT1) . . . . . . 23
Chapter 2
Memory
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.4 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.5 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.6 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.8 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8.1 FLASH Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2.8.2 FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.8.3 FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.8.4 FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.8.5 FLASH Block Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.8.6 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Freescale Semiconductor 7
Table of Contents
2.8.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
2.8.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 3
Analog-to-Digital Converter (ADC)
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3.1 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.2 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.3.3 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.4 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.5 Result Justification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.6 Monotonicity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.6.1 ADC Analog Power Pin (V
3.6.2 ADC Analog Ground Pin (V
3.6.3 ADC Voltage Reference Pin (V
3.6.4 ADC Voltage Reference Low Pin (V
3.6.5 ADC Voltage In (ADVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6.6 ADC External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6.6.1 V
REFH
and V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
REFL
3.6.6.2 ANx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.6.6.3 Grounding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.7.1 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.7.2 ADC Data Register High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.7.3 ADC Data Register Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.7.4 ADC Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
DDAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SSAD
). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
REFH
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
REFL
Chapter 4
Clock Generator Module (CGM)
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.3.1 Crystal Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.2.1 PLL Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.3.2.2 Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.2.3 Manual and Automatic PLL Bandwidth Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3.2.4 Programming the PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.3.2.5 Special Programming Exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.3 Base Clock Selector Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3.4 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
8 Freescale Semiconductor
4.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.1 Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.2 Crystal Amplifier Output Pin (OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.3 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.4 PLL Analog Power Pin (V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
DDA
4.4.5 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.4.6 Crystal Output Frequency Signal (CGMXCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.7 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.4.8 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5 CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.5.1 PLL Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.5.2 PLL Bandwidth Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.5.3 PLL Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.8 Acquisition/Lock Time Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.8.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.8.2 Parametric Influences on Reaction Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.8.3 Choosing a Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
4.8.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Chapter 5
Configuration Register (CONFIG)
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Chapter 6
Computer Operating Properly (COP)
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.1 CGMXCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.3 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.4 Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.6 COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.4 COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.6 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.7 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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Chapter 7
Central Processor Unit (CPU)
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.3.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.3.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.3.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
7.4 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.6 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
7.8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 8
External Interrupt (IRQ)
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
8.4 IRQ
8.5 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Chapter 9
Low-Voltage Inhibit (LVI)
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.1 Polled LVI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.2 Forced Reset Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.3 False Reset Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.4 LVI Trip Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.4 LVI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.5 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.6 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.7 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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Chapter 10
Input/Output (I/O) Ports (PORTS)
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.2.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.3.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.3.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
10.4 Port C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.4.1 Port C Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.4.2 Data Direction Register C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
10.5 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10.6 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.6.1 Port E Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
10.6.2 Data Direction Register E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.7 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.1 Port F Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
10.7.2 Data Direction Register F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Chapter 11
Power-On Reset (POR)
11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
11.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Chapter 12
Pulse-Width Modulator for Motor Control (PWMMC)
12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
12.3 Timebase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.3.1 Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
12.3.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.4 PWM Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.4.1 Load Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
12.4.2 PWM Data Overflow and Underflow Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
12.5 Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
12.5.1 Selecting Six Independent PWMs or Three Complementary PWM Pairs . . . . . . . . . . . . . 126
12.5.2 Dead-Time Insertion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
12.5.3 Top/Bottom Correction with Motor Phase Current Polarity Sensing . . . . . . . . . . . . . . . . . 130
12.5.4 Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
12.5.5 PWM Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
12.6 Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.6.1 Fault Condition Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
12.6.1.1 Fault Pin Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.6.1.2 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
12.6.1.3 Manual Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
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12.6.2 Software Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.6.3 Output Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
12.7 Initialization and the PWMEN Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
12.8 PWM Operation in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.9 Control Logic Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.9.1 PWM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
12.9.2 PWM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
12.9.3 PWMx Value Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
12.9.4 PWM Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
12.9.5 PWM Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
12.9.6 Dead-Time Write-Once Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.9.7 PWM Disable Mapping Write-Once Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.9.8 Fault Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
12.9.9 Fault Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
12.9.10 Fault Acknowledge Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
12.9.11 PWM Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
12.10 PWM Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Chapter 13
Serial Communications Interface Module (SCI)
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
13.3.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
13.3.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
13.3.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.3.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.3.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
13.3.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
13.3.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
13.3.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.3.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
13.3.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.3.3.5 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.3.3.6 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.3.3.7 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
13.4 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.5 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.6.1 PTF5/TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
13.6.2 PTF4/RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.7.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
13.7.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
12 Freescale Semiconductor
13.7.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
13.7.4 SCI Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
13.7.5 SCI Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
13.7.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
13.7.7 SCI Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Chapter 14
System Integration Module (SIM)
14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
14.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.2.2 Clock Startup from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
14.2.3 Clocks in Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
14.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
14.3.2.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.3.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
14.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.3.2.5 Forced Monitor Mode Entry Reset (MENRST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.3.2.6 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.4.2 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
14.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
14.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
14.5.1.2 Software Interrupt (SWI) Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.5.2 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.6 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
14.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.7.1 SIM Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
14.7.2 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
14.7.3 SIM Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Chapter 15
Serial Peripheral Interface Module (SPI)
15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
15.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
15.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.5 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
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Table of Contents
15.5.1 Clock Phase and Polarity Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
15.5.2 Transmission Format When CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
15.5.3 Transmission Format When CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
15.5.4 Transmission Initiation Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
15.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
15.6.1 Overflow Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
15.6.2 Mode Fault Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
15.8 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
15.9 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
15.10 Low-Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
15.11 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
15.11.1 MISO (Master In/Slave Out). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
15.11.2 MOSI (Master Out/Slave In). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
15.11.3 SPSCK (Serial Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
15.11.4 SS
15.11.5 V
(Slave Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
(Clock Ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
SS
15.12 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
15.12.1 SPI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
15.12.2 SPI Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
15.12.3 SPI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Chapter 16
Timer Interface A (TIMA)
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
16.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
16.3.1 TIMA Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
16.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
16.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
16.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
16.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
16.3.4 Pulse-Width Modulation (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
16.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
16.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16.3.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
16.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
16.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.6.1 TIMA Clock Pin (PTE3/TCLKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.6.2 TIMA Channel I/O Pins (PTE4/TCH0A–PTE7/TCH3A) . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.7.1 TIMA Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
16.7.2 TIMA Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
16.7.3 TIMA Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
16.7.4 TIMA Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
16.7.5 TIMA Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
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Chapter 17
Timer Interface B (TIMB)
17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
17.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
17.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
17.3.1 TIMB Counter Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
17.3.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
17.3.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
17.3.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
17.3.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
17.3.4 Pulse-Width Modulation (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
17.3.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
17.3.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
17.3.4.3 PWM Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
17.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.5 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.6 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.6.1 TIMB Clock Pin (PTE0/TCLKB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.6.2 TIMB Channel I/O Pins (PTE1/TCH0B–PTE2/TCH1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
17.7 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
17.7.1 TIMB Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
17.7.2 TIMB Counter Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.7.3 TIMB Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
17.7.4 TIMB Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
17.7.5 TIMB Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Chapter 18
Development Support
18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.2 Break Module (BRK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
18.2.1.2 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.1.3 TIM1 and TIM2 During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.1.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.2.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.2.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.3 Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
18.2.3.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
18.2.3.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
18.2.3.3 Break Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.2.3.4 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Freescale Semiconductor 15
Table of Contents
18.3 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
18.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
18.3.1.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
18.3.1.2 Normal Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
18.3.1.3 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
18.3.1.5 Echoing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.3.1.6 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
18.3.1.8 Baud Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
18.3.2 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
Chapter 19
Electrical Specifications
19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
19.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
19.3 Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
19.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
19.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
19.6 FLASH Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
19.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
19.8 Serial Peripheral Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
19.9 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
19.10 Clock Generation Module Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
19.11 CGM Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272
19.12 CGM Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
19.13 Analog-to-Digital Converter (ADC) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
Chapter 20
Ordering Information and Mechanical Specifications
20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
20.2 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
20.3 64-Pin Plastic Quad Flat Pack (QFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
20.4 56-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
Appendix A
MC68HC908MR16
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
16 Freescale Semiconductor

Chapter 1 General Description

1.1 Introduction

The MC68HC908MR32 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
The information contained in this document pertains to the MC68HC908MR16 with the exceptions shown in Appendix A MC68HC908MR16.

1.2 Features

Features include:
• High-performance M68HC08 architecture
• Fully upward-compatible object code with M6805, M146805, and M68HC05 Families
• 8-MHz internal bus frequency
• On-chip FLASH memory with in-circuit programming capabilities of FLASH program memory: MC68HC908MR32 — 32 Kbytes MC68HC908MR16 — 16 Kbytes
• On-chip programming firmware for use with host personal computer
• FLASH data security
• 768 bytes of on-chip random-access memory (RAM)
• 12-bit, 6-channel center-aligned or edge-aligned pulse-width modulator (PWMMC)
• Serial peripheral interface module (SPI)
• Serial communications interface module (SCI)
• 16-bit, 4-channel timer interface module (TIMA)
• 16-bit, 2-channel timer interface module (TIMB)
• Clock generator module (CGM)
• Low-voltage inhibit (LVI) module with software selectable trip points
• 10-bit, 10-channel analog-to-digital converter (ADC)
• System protection features:
– Optional computer operating properly (COP) reset – Low-voltage detection with optional reset – Illegal opcode or address detection with optional reset – Fault detection with optional PWM disabling
(1)
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
Freescale Semiconductor 17
General Description
• Available packages: – 64-pin plastic quad flat pack (QFP) – 56-pin shrink dual in-line package (SDIP)
• Low-power design, fully static with wait mode
• Master reset pin (RST
) and power-on reset (POR)
• Stop mode as an option
• Break module (BRK) supports setting the in-circuit simulator (ICS) single break point
Features of the CPU08 include:
• Enhanced M68HC05 programming model
• Extensive loop control functions
• 16 addressing modes (eight more than the M68HC05)
• 16-bit index register and stack pointer
• Memory-to-memory data transfers
• Fast 8 × 8 multiply instruction
• Fast 16/8 divide instruction
• Binary-coded decimal (BCD) instructions
• Optimization for controller applications
• C language support

1.3 MCU Block Diagram

Figure 1-1 shows the structure of the MC68HC908MR32.
18 Freescale Semiconductor
Freescale Semiconductor 19
INTERNAL BUS
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
UNIT
LOW-VOLTAGE INHIBIT
MODULE
DDRA
PTA
PTA7–PTA0
PTB7/ATD7
PTB6/ATD6
CONTROL AND STATUS REGISTERS — 112 BYTES
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
USER FLASH — 32,256 BYTES
COMPUTER OPERATING PROPERLY
MODULE
TIMER INTERFACE
MODULE A
DDRB
PTB
USER RAM — 768 BYTES
TIMER INTERFACE
MODULE B
MODULE
MODULE
PTCPTD
DDRC
(2)
OSC1
OSC2
CGMXFC
MONITOR ROM — 240 BYTES
USER FLASH VECTOR SPACE — 46 BYTES
CLOCK GENERATOR
MODULE
SERIAL COMMUNICATIONS INTERFACE
SERIAL PERIPHERAL INTERFACE
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1/ATD9
PTC0/ATD8
PTD6/IS3
PTD5/IS2
PTD4/IS1
(1)
PTD3/FAULT4
PTD2/FAULT3
PTD1/FAULT2
PTD0/FAULT1
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B
PTE1/TCH0B
PTE0/TCLKB
(1)
(1)
(1)
MCU Block Diagram
RST
IRQ
V
DDAD
V
SSAD
V
REFL
V
REFH
PWMGND
PWM6–PWM1
V
V
V
DDAD
V
SSAD
SYSTEM INTEGRATION
MODULE
IRQ
MODULE
(3)
(3)
SS
DD
ANALOG-TO-DIGITAL CONVERTER
MODULE
PULSE-WIDTH MODULATOR
MODULE
POWER
POWER-ON RESET
MODULE
SINGLE BREAK
MODULE
PTF5/TxD
PTF4/RxD
PTF3/MISO PTF2/MOSI
PTF1/SS
PTF0/SPSCK
(1)
(1)
(1)
(1)
PTF
DDRF
DDRE
PTE
Notes:
1. These pins are not available in the 56-pin SDIP package.
2. This module is not available in the 56-pin SDIP package.
3. In the 56-pin SDIP package, these pins are bonded together.
Figure 1-1. MCU Block Diagram
General Description

1.4 Pin Assignments

Figure 1-2 shows the 64-pin QFP pin assignments and Figure 1-3 shows the 56-pin SDIP pin
assignments.
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD6
PTB7/ATD7
PTC0/ATD8
PTC1/ATD9
V
DDAD
V
SSAD
V
REFL
V
REFH
PTC2
PTC3
PTC4
PTC5
PTA2
PTB1/ATD1
PTB0/ATD0
PTA7
PTA6
PTA5
PTA4
PTA3
64
63
62
61
60
59
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
19
20
21
17
58
22
23
PTA1
57
56
24
25
PTA0
55
26
SSAD
V
OSC2
OSC1
54
53
52
27
28
29
DDAD
CGMXFC
V
51
50
30
31
RST
49
47
46
45
44
43
42
41
40
39
38
37
36
35
34
32
48
33
IRQ
PTF5/TxD
PTF4/RxD
PTF3/MISO
PTF2/MOSI
PTF1/SS
PTF0/SPSCK
V
SS
V
DD
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B
PTE1/TCH0B
PTC6
PTD4/IS1
PTD5/IS2
PTD1/FAULT2
PTD0/FAULT1
PTD2/FAULT3
PTD3/FAULT4
PTD6/IS3
PWM1
PWM2
PWM3
PWM4
PWM5
PWMGND
PWM6
PTE0/TCLKB
Figure 1-2. 64-Pin QFP Pin Assignments
20 Freescale Semiconductor
Pin Assignments
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTB0/ATD0
PTB1/ATD1
PTB2/ATD2
PTB3/ATD3
PTB4/ATD4
PTB5/ATD5
PTB6/ATD5
PTB7/ATD7
PTC0/ATD8
V
DDAD
V
SSAD/VREFL
V
REFH
PTC2
PTC3
PTC4
PTC5
PTC6
PTD0/FAULT1
PTD1/FAULT2
PTD2/FAULT3
PTD3/FAULT4
PTD4/IS1 PTD5/IS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PTA1
PTA0
V
SSA
OSC2
OSC1
CGMXFC
V
DDA
RST
IRQ
PTF5/TxD
PTF4/RxD
V
SS
V
DD
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
NC
PWM6
PWM5
PWMGND
PWM4
PWM3
PWM2
PWM1
PTD6/IS3
Note:
PTC1, PTE0, PTE1, PTE2, PTF0, PTF1, PTF2, and PTF3 are removed from this package.
Figure 1-3. 56-Pin SDIP Pin Assignments
Freescale Semiconductor 21
General Description

1.4.1 Power Supply Pins (VDD and VSS)

VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply.
Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-4 shows. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency-response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high-current levels.
MCU
V
DD
C1
0.1 µF
+
C2
1–10 µF
V
DD
Note: Component values shown represent typical applications.
V
SS
Figure 1-4. Power Supply Bypassing

1.4.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. For more detailed information, see Chapter 4 Clock Generator Module (CGM).

1.4.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. See Chapter 14 System
Integration Module (SIM).

1.4.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. See Chapter 8 External Interrupt (IRQ).
1.4.5 CGM Power Supply Pins (V
V
and V
DDA
Decoupling of these pins should be per the digital supply. See Chapter 4 Clock Generator Module (CGM).
22 Freescale Semiconductor
are the power supply pins for the analog portion of the clock generator module (CGM).
SSAD
DDA
and V
SSAD
)
Pin Assignments

1.4.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See Chapter 4 Clock Generator Module
(CGM).
1.4.7 Analog Power Supply Pins (V
V
DDAD
and V
are the power supply pins for the analog-to-digital converter. Decoupling of these pins
SSAD
DDAD
and V
SSAD
)
should be per the digital supply. See Chapter 3 Analog-to-Digital Converter (ADC).
1.4.8 ADC Voltage Decoupling Capacitor Pin (V
V potential as V
1.4.9 ADC Voltage Reference Low Pin (V
V V
is the power supply for setting the reference voltage. Connect the V
REFH
. See Chapter 3 Analog-to-Digital Converter (ADC).
DDAD
)
REFL
is the lower reference supply for the ADC. Connect the V
REFL
. See Chapter 3 Analog-to-Digital Converter (ADC).
SSAD
REFH
)
pin to the same voltage
REFH
pin to the same voltage potential as
REFL
1.4.10 Port A Input/Output (I/O) Pins (PTA7–PTA0)
PTA7–PTA0 are general-purpose bidirectional input/output (I/O) port pins. See Chapter 10 Input/Output
(I/O) Ports (PORTS).
1.4.11 Port B I/O Pins (PTB7/ATD7–PTB0/ATD0)
Port B is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (ADC). See Chapter 3 Analog-to-Digital Converter (ADC) and Chapter 10 Input/Output (I/O) Ports (PORTS).
1.4.12 Port C I/O Pins (PTC6–PTC2 and PTC1/ATD9–PTC0/ATD8)
PTC6–PTC2 are general-purpose bidirectional I/O port pins Chapter 10 Input/Output (I/O) Ports
(PORTS). PTC1/ATD9–PTC0/ATD8 are special function port pins that are shared with the
analog-to-digital converter (ADC). See Chapter 3 Analog-to-Digital Converter (ADC) and Chapter 10
Input/Output (I/O) Ports (PORTS).
1.4.13 Port D Input-Only Pins (PTD6/IS3–PTD4/IS1 and PTD3/FAULT4–PTD0/FAULT1)
PTD6/IS3–PTD4/IS1 are special function input-only port pins that also serve as current sensing pins for the pulse-width modulator module (PWMMC). PTD3/FAULT4–PTD0/FAULT1 are special function port pins that also serve as fault pins for the PWMMC. See Chapter 12 Pulse-Width Modulator for Motor
Control (PWMMC) and Chapter 10 Input/Output (I/O) Ports (PORTS).
1.4.14 PWM Pins (PWM6–PWM1)
PWM6–PWM1 are dedicated pins used for the outputs of the pulse-width modulator module (PWMMC). These are high-current sink pins. See Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC) and Chapter 19 Electrical Specifications.
Freescale Semiconductor 23
General Description

1.4.15 PWM Ground Pin (PWMGND)

PWMGND is the ground pin for the pulse-width modulator module (PWMMC). This dedicated ground pin is used as the ground for the six high-current PWM pins. See Chapter 12 Pulse-Width Modulator for Motor
Control (PWMMC).
1.4.16 Port E I/O Pins (PTE7/TCH3A–PTE3/TCLKA and PTE2/TCH1B–PTE0/TCLKB)
Port E is an 8-bit special function port that shares its pins with the two timer interface modules (TIMA and TIMB). See Chapter 16 Timer Interface A (TIMA), Chapter 17 Timer Interface B (TIMB), and Chapter 10
Input/Output (I/O) Ports (PORTS).
1.4.17 Port F I/O Pins (PTF5/TxD–PTF4/RxD and PTF3/MISO–PTF0/SPSCK)
Port F is a 6-bit special function port that shares two of its pins with the serial communications interface module (SCI) and four of its pins with the serial peripheral interface module (SPI). See Chapter 15 Serial
Peripheral Interface Module (SPI), Chapter 13 Serial Communications Interface Module (SCI), and Chapter 10 Input/Output (I/O) Ports (PORTS).
24 Freescale Semiconductor

Chapter 2 Memory

2.1 Introduction

The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes:
• 32 Kbytes of FLASH
• 768 bytes of random-access memory (RAM)
• 46 bytes of user-defined vectors
• 240 bytes of monitor read-only memory (ROM)

2.2 Unimplemented Memory Locations

Some addresses are unimplemented. Accessing an unimplemented address can cause an illegal address reset. In the memory map and in the input/output (I/O) register summary, unimplemented addresses are shaded.
Some I/O bits are read only; the write function is unimplemented. Writing to a read-only I/O bit has no effect on microcontroller unit (MCU) operation. In register figures, the write function of read-only bits is shaded.
Similarly, some I/O bits are write only; the read function is unimplemented. Reading of write-only I/O bits has no effect on MCU operation. In register figures, the read function of write-only bits is shaded.

2.3 Reserved Memory Locations

Some addresses are reserved. Writing to a reserved address can have unpredictable effects on MCU operation. In the memory map (Figure 2-1) and in the I/O register summary (Figure 2-2) reserved addresses are marked with the word reserved.
Some I/O bits are reserved. Writing to a reserved bit can have unpredictable effects on MCU operation. In register figures, reserved bits are marked with the letter R.
Freescale Semiconductor 25
Memory

2.4 I/O Section

Addresses $0000–$005F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses:
• $FE00, SIM break status register (SBSR)
• $FE01, SIM reset status register (SRSR)
• $FE03, SIM break flag control register (SBFCR)
• $FE07, FLASH control register (FLCR)
• $FE0C, Break address register high (BRKH)
• $FE0D, Break address register low (BRKL)
• $FE0E, Break status and control register (BRKSCR)
• $FE0F, LVI status and control register (LVISCR)
• $FF7E, FLASH block protect register (FLBPR)
• $FFFF, COP control register (COPCTL)

2.5 Memory Map

Figure 2-1 shows the memory map for the MC68HC908MR32 while the memory map for the
MC68HC908MR16 is shown in Appendix A MC68HC908MR16
26 Freescale Semiconductor
$0000
↓
I/O REGISTERS — 96 BYTES
$005F
$0060
↓
RAM — 768 BYTES
$035F
$0360
↓
UNIMPLEMENTED — 31,904 BYTES
$7FFF
$8000
↓
FLASH — 32,256 BYTES
$FDFF
$FE00 SIM BREAK STATUS REGISTER (SBSR)
$FE01 SIM RESET STATUS REGISTER (SRSR)
$FE02 RESERVED
$FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE04 RESERVED
$FE05 RESERVED
$FE06 RESERVED
$FE07 RESERVED
$FE08 FLASH CONTROL REGISTER (FLCR)
$FE09
$FE0A
$FE0B
UNIMPLEMENTED
UNIMPLEMENTED
UNIMPLEMENTED
$FE0C SIM BREAK ADDRESS REGISTER HIGH (BRKH)
$FE0D SIM BREAK ADDRESS REGISTER LOW (BRKL)
$FE0E SIM BREAK FLAG CONTROL REGISTER (SBFCR)
$FE0F LVI STATUS AND CONTROL REGISTER (LVISCR)
$FE10
↓
MONITOR ROM — 240 BYTES
$FEFF
$FF00
↓
UNIMPLEMENTED — 126 BYTES
$FF7D
$FF7E FLASH BLOCK PROTECT REGISTER (FLBPR)
$FF7F
↓
UNIMPLEMENTED — 83 BYTES
$FFD1
$FFD2
↓
VECTORS — 46 BYTES
$FFFF
Memory Map
Figure 2-1. MC68HC908MR32 Memory Map
Freescale Semiconductor 27
Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Port A Data Register
$0000
See page 103.
Port B Data Register
$0001
See page 104.
Port C Data Register
$0002
Port D Data Register
$0003
Data Direction Register A
$0004
Data Direction Register B
$0005
Data Direction Register C
$0006
$0007 Unimplemented
(PTC)
See page 106.
(PTD)
See page 107.
(DDRA)
See page 103.
(DDRB)
See page 105.
(DDRC)
See page 106.
Read:
(PTA)
Write:
Reset: Unaffected by reset
Read:
(PTB)
Write:
Reset: Unaffected by reset
Read: 0
Write: R
Reset: Unaffected by reset
Read: 0 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0
Write: R R R R R R R R
Reset: Unaffected by reset
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: 0
Write: R
Reset: 0 0 0 0 0 0 0 0
PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0
PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
PTC6 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
Port E Data Register
$0008
See page 108.
Port F Data Register
$0009
See page 110.
$000A Unimplemented
$000B Unimplemented
Data Direction Register E
$000C
Data Direction Register F
$000D
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
(DDRE)
See page 109.
(DDRF)
See page 110.
Read:
Write:
(PTE)
Reset: Unaffected by reset
Read: 0 0
Write: R R
(PTF)
Reset: Unaffected by reset
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: 0 0
Write: R R
Reset: 0 0 0 0 0 0
PTE7 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0
PTF5 PTF4 PTF3 PTF2 PTF1 PTF0
DDRE7 DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 1 of 8)
= Unimplemented
28 Freescale Semiconductor
Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
TIMA Status/Control Register
$000E
TIMA Counter Register High
$000F
TIMA Counter Register Low
$0010
TIMA Counter Modulo
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
Register High (TAMODH)
TIMA Counter Modulo
Register Low (TAMODL)
TIMA Channel 0 Status/Control
Register (TASC0)
TIMA Channel 0 Register High
TIMA Channel 0 Register Low
TIMA Channel 1 Status/Control
Register (TASC1)
TIMA Channel 1 Register High
TIMA Channel 1 Register Low
TIMA Channel 2 Status/Control
Register (TASC2)
(TASC)
See page 226.
(TACNTH)
See page 227.
(TACNTL)
See page 227.
See page 228.
See page 228.
See page 229.
(TACH0H)
See page 232.
(TACH0L)
See page 232.
See page 232.
(TACH1H)
See page 232.
(TACH1L)
See page 232.
See page 229.
Read: TOF
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Read:
Bit 15 14 13 12 11 10 9 Bit 8
Write:
Reset: 1 1 1 1 1 1 1 1
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Read: CH0F
Write: 0
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH2F
Write: 0
Reset: 0 0 0 0 0 0 0 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TOIE TSTOP
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
CH1IE
CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX
0
00
MS1A ELS1B ELS1A TOV1 CH1MAX
PS2 PS1 PS0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 2 of 8)
Freescale Semiconductor 29
Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
TIMA Channel 2 Register High
$001A
TIMA Channel 2 Register Low
$001B
TIMA Channel 3 Status/Control
$001C
TIMA Channel 3 Register High
$001D
TIMA Channel 3 Register Low
$001E
Configuration Register
$001F
PWM Control Register 1
$0020
PWM Control Register 2
$0021
Fault Control Register
$0022
Fault Status Register
$0023
Fault Acknowledge Register
$0024
PWM Output Control Register
$0025
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
(TACH2H)
See page 232.
(TACH2L)
See page 232.
Register (TASC3)
See page 229.
(TACH3H)
See page 232.
(TACH3L)
See page 232.
(CONFIG)
See page 74.
(PCTL1)
See page 146.
(PCTL2)
See page 148.
(FCR)
See page 150.
(FSR)
See page 152.
(FTACK)
See page 153.
(PWMOUT)
See page 154.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH3F
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: 0 0 0 0 1 1 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: FPIN4 FFLAG4 FPIN3 FFLAG3 FPIN2 FFLAG2 FPIN1 FFLAG1
Write:
Reset: U 0 U 0 U 0 U 0
Read: 0 0 DT6 DT5 DT4 DT3 DT2 DT1
Write:
Reset: 0 0 0 0 0 0 0 0
Read: 0
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CH3IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD
DISX DISY PWMINT PWMF ISENS1 ISENS0 LDOK PWMEN
LDFQ1 LDFQ0
FINT4 FMODE4 FINT3 FMODE3 FINT2 FMODE2 FINT1 FMODE1
FTACK4 FTACK3 FTACK2 FTACK1
OUTCTL OUT6 OUT5 OUT4 OUT3 OUT2 OUT1
0
0
MS3A ELS3B ELS3A TOV3 CH3MAX
IPOL1 IPOL2 IPOL3 PRSC1 PRSC0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 3 of 8)
30 Freescale Semiconductor
Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
PWM Counter Register High
$0026
PWM Counter Register Low
$0027
PWM Counter Modulo Register
$0028
PWM Counter Modulo Register
$0029
PWM 1 Value Register High
$002A
PWM 1 Value Register Low
$002B
PWM 2 Value Register High
$002C
PWM 2 Value Register Low
$002D
PWM 3 Value Register High
$002E
PWM 3 Value Register Low
$002F
PWM 4 Value Register High
$0030
PWM 4 Value Register Low
$0031
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
(PCNTH)
See page 143.
(PCNTL)
See page 143.
High (PMODH)
See page 144.
Low (PMODL)
See page 144.
(PVAL1H)
See page 145.
(PVAL1L)
See page 145.
(PVAL2H)
See page 145.
(PVAL2L)
See page 145.
(PVAL3H)
See page 145.
(PVAL3L)
See page 145.
(PVAL4H)
See page 145.
(PVAL4L)
See page 145.
Read: 0 0 0 0 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write:
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0
Write:
Reset: 0 0 0 0 X X X X
Read:
Write:
Reset: X X X X X X X X
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 11 Bit 10 Bit 9 Bit 8
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 4 of 8)
Freescale Semiconductor 31
Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
PWM 5 Value Register High
$0032
PWM 5 Value Register Low
$0033
PWM 6 Value Register High
$0034
PWM 6 Value Register Low
$0035
Dead-Time Write-Once
$0036
PWM Disable Mapping
$0037
$0038
$0039
$003A
$003B
$003C
$003D
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
Write-Once Register (DISMAP)
SCI Control Register 1
SCI Control Register 2
SCI Control Register 3
SCI Status Register 1
SCI Status Register 2
(PMVAL5H)
See page 145.
(PVAL5L)
See page 145.
(PVAL6H)
See page 145.
(PMVAL6L)
See page 145.
Register (DEADTM)
See page 150.
See page 137.
(SCC1)
See page 169.
(SCC2)
See page 171.
(SCC3)
See page 173.
(SCS1)
See page 174.
(SCS2)
See page 176.
SCI Data Register
(SCDR)
See page 177.
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: R8
Write: R R R
Reset: U U 0 0 0 0 0 0
Read: SCTE TC SCRF IDLE OR NF FE PE
Write: R R R R R R R R
Reset: 1 1 0 0 0 0 0 0
Read: 0 0 0 0 0 0 BKF RPF
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
LOOPS ENSCI TXINV M WAKE ILTY PEN PTY
SCTIE TCIE SCRIE ILIE TE RE RWU SBK
T8
00
ORIE NEIE FEIE PEIE
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 5 of 8)
32 Freescale Semiconductor
Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
$003E
$003F
$0040
$0041
$0042
$0043
$0044
$0045
$0046
$0047
↓
$0050
SCI Baud Rate Register
(SCBR)
See page 177.
IRQ Status/Control Register
(ISCR)
See page 94.
ADC Status and Control
Register (ADSCR)
See page 52.
ADC Data Register High
Right Justified Mode (ADRH)
See page 54.
ADC Data Register Low
Right Justified Mode (ADRL)
See page 54.
ADC Clock Register
(ADCLK)
See page 55.
SPI Control Register
(SPCR)
See page 211.
SPI Status and Control
Register (SPSCR)
See page 212.
SPI Data Register
(SPDR)
See page 214.
Unimplemented
Read: 0 0
Write: R R R
Reset: 0 0 0 0 0 0 0 0
Read: 0 0 0 0 IRQF 0
Write: R R R R
Reset: 0 0 0 0 0 0 0 0
Read: COCO
Write: R
Reset: 0 0 0 1 1 1 1 1
Read: 0 0 0 0 0 0 AD9 AD8
Write: R R R R R R R R
Reset: Unaffected by reset
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write: R R R R R R R R
Reset: Unaffected by reset
Read:
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0
Write: R
Reset: 0 0 0 0 0 1 0 0
Read:
SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE
Write:
Reset: 0 0 1 0 1 0 0 0
Read: SPRF
Write: R R R R
Reset: 0 0 0 0 1 0 0 0
Read: R7 R6 R5 R4 R3 R2 R1 R0
Write: T7 T6 T5 T4 T3 T2 T1 T0
Reset: Unaffected by reset
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
ERRIE
SCP1 SCP0
OVRF MODF SPTE
0
SCR2 SCR1 SCR0
ACK1
MODFEN SPR1 SPR0
IMASK1 MODE1
0
TIMB Status/Control Register
$0051
TIMB Counter Register High
$0052
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
(TBSC)
See page 244.
(TBCNTH)
See page 246.
Read: TOF
Write: 0 TRST R
Reset: 0 0 1 0 0 0 0 0
Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
TOIE TSTOP
00
PS2 PS1 PS0
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 6 of 8)
Freescale Semiconductor 33
Memory
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
TIMB Counter Register Low
$0053
TIMB Counter Modulo Register
$0054
TIMB Counter Modulo Register
$0055
TIMB Channel 0 Status/Control
$0056
TIMB Channel 0 Register High
$0057
TIMB Channel 0 Register Low
$0058
TIMB Channel 1 Status/Control
$0059
TIMB Channel 1 Register High
$005A
TIMB Channel 1 Register Low
$005B
PLL Control Register
$005C
PLL Bandwidth Control
$005D
PLL Programming Register
$005E
$005F Unimplemented
(TBCNTL)
See page 246.
High (TBMODH)
See page 246.
Low (TBMODL)
See page 246.
Register (TBSC0)
See page 247.
(TBCH0H)
See page 250.
(TBCH0L)
See page 250.
Register (TBSC1)
See page 247.
(TBCH1H)
See page 250.
(TBCH1L)
See page 250.
(PCTL)
See page 66.
Register (PBWC)
See page 67.
(PPG)
See page 68.
Read: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Write: R R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Read:
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Write:
Reset: 1 1 1 1 1 1 1 1
Read:
Write:
Reset: 1 1 1 1 1 1 1 1
Read: CH0F
Write: 0
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read: CH1F
Write: 0 R
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: Indeterminate after reset
Read:
Write:
Reset: Indeterminate after reset
Read:
Write: R R R R R
Reset: 0 0 1 0 1 1 1 1
Read:
Write: R R R R R
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 1 1 0 0 1 1 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CH1IE
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PLLIE
AUTO
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
PLLF
LOCK
0
PLLON BCS
ACQ
MS1A ELS1B ELS1A TOV1 CH1MAX
XLD
1111
0000
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered = Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 7 of 8)
34 Freescale Semiconductor
Memory Map
Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0
Read:
Write:
Reset: 0
Read: POR PIN COP ILOP ILAD MENRST LVI 0
Write: R R R R R R R R
Reset: 1 0 0 0 0 0 0 0
Read:
Write:
Reset: 0
Read: 0 0 0 0
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
Read: LVIOUT 0
Write: R R R R R R R
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Reset: 0 0 0 0 0 0 0 0
RR R R R RBWR
BCFE R R R R R R R
HVEN MASS ERASE PGM
Bit 15 14 13 12 11 10 9 Bit 8
Bit 7 6 5 4 3 2 1 Bit 0
BRKE BRKA
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
00 0 000
TRPSEL
00000
$FE00
$FE01
$FE03
$FE08
$FE0C
$FE0D
$FE0E
$FE0F
$FF7E
SIM Break Status Register
(SBSR)
See page 191.
SIM Reset Status Register
(SRSR)
See page 192.
SIM Break Flag Control
Register (SBFCR)
See page 193.
FLASH Control Register
(FLCR)
See page 38.
Break Address Register High
(BRKH)
See page 254.
Break Address Register Low
(BRKL)
See page 254.
Break Status and Control
Register (BRKSCR)
See page 254.
LVI Status and Control Register
(LVISCR)
See page 99.
FLASH Block Protect Register
(FLBPR)
See page 43.
COP Control Register
$FFFF
U = Unaffected X = Indeterminate R = Reserved Bold = Buffered
(COPCTL)
See page 77.
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
= Unimplemented
Figure 2-2. Control, Status, and Data Registers Summary (Sheet 8 of 8)
Freescale Semiconductor 35
Memory
Table 2-1 is a list of vector locations.
Address Vector
$FFD2 SCI transmit vector (high)
Low
$FFD3 SCI transmit vector (low)
$FFD4 SCI receive vector (high)
$FFD5 SCI receive vector (low)
$FFD6 SCI error vector (high)
$FFD7 SCI error vector (low)
$FFD8
$FFD9
$FFDA
$FFDB
$FFDC A/D vector (high)
Table 2-1. Vector Addresses
SPI transmit vector (high)
SPI transmit vector (low)
SPI receive vector (high)
SPI receive vector (low)
(1)
(1)
(1)
(1)
Priority
$FFDD A/D vector (low)
$FFDE TIMB overflow vector (high)
$FFDF TIMB overflow vector (low)
$FFE0 TIMB channel 1 vector (high)
$FFE1 TIMB channel 1 vector (low)
$FFE2 TIMB channel 0 vector (high)
$FFE3 TIMB channel 0 vector (low)
$FFE4 TIMA overflow vector (high)
$FFE5 TIMA overflow vector (low)
$FFE6 TIMA channel 3 vector (high)
$FFE7 TIMA channel 3 vector (low)
$FFE8 TIMA channel 2 vector (high)
$FFE9 TIMA channel 2 vector (low)
$FFEA TIMA channel 1 vector (high)
$FFEB TIMA channel 1 vector (low)
$FFEC TIMA channel 0 vector (high)
$FFED TIMA channel 0 vector (low)
1. The SPI module is not available in the 56-pin SDIP package.
36 Freescale Semiconductor
Priority
Monitor ROM
Table 2-1. Vector Addresses (Continued)
Address Vector
$FFEE PWMMC vector (high)
$FFEF PWMMC vector (low)
$FFF0 FAULT 4 (high)
$FFF1 FAULT 4 (low)
$FFF2 FAULT 3 (high)
$FFF3 FAULT 3 (low)
$FFF4 FAULT 2 (high)
$FFF5 FAULT 2 (low)
$FFF6 FAULT 1 (high)
$FFF7 FAULT 1 (low)
$FFF8 PLL vector (high)
$FFF9 PLL vector (low)
$FFFA IRQ vector (high)
$FFFB IRQ vector (low)
$FFFC SWI vector (high)
$FFFD SWI vector (low)
$FFFE Reset vector (high)
High
$FFFF Reset vector (low)

2.6 Monitor ROM

The 240 bytes at addresses $FE10–$FEFF are reserved ROM addresses that contain the instructions for the monitor functions. See 18.3 Monitor ROM (MON).

2.7 Random-Access Memory (RAM)

Addresses $0060–$035F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space.
NOTE
For correct operation, the stack pointer must point only to RAM locations.
Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables.
Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers.
NOTE
For M68HC05 and M1468HC05 compatibility, the H register is not stacked.
Freescale Semiconductor 37
Memory
During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls.
NOTE
Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.

2.8 FLASH Memory (FLASH)

The FLASH memory is an array of 32,256 bytes with an additional 46 bytes of user vectors and one byte of block protection.
NOTE
An erased bit reads as a 1 and a programmed bit reads as a 0.
Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section.
Memory in the FLASH array is organized into two rows per page. The page size is 128 bytes per page. The minimum erase page size is 128 bytes. Programming is performed on a row basis, 64 bytes at a time.
The address ranges for the user memory and vectors are:
• $8000–$FDFF, user memory
• $FF7E, block protect register (FLBPR)
• $FE08, FLASH control register (FLCR)
• $FFD2–$FFFF, reserved for user-defined interrupt and reset vectors
Programming tools are available from Freescale. Contact a local Freescale representative for more information.
NOTE
A security feature prevents viewing of the FLASH contents.
(1)

2.8.1 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: $FE08
Bit 7654321Bit 0
Read:0000
Write:
Reset:00000000
= Unimplemented
Figure 2-3. FLASH Control Register (FLCR)
HVEN MASS ERASE PGM
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users.
38 Freescale Semiconductor
FLASH Memory (FLASH)
HVEN — High-Voltage Enable Bit
This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed.
1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off
MASS — Mass Erase Control Bit
Setting this read/write bit configures the 32-Kbyte FLASH array for mass erase operation. Mass erase is disabled if any FLASH block is protected
1 = MASS erase operation selected 0 = MASS erase operation unselected
ERASE — Erase Control Bit
This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Erase operation selected 0 = Erase operation unselected
PGM — Program Control Bit
This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time.
1 = Program operation selected 0 = Program operation unselected

2.8.2 FLASH Page Erase Operation

Use this step-by-step procedure to erase a page (128 bytes) of FLASH memory.
1. Set the ERASE bit and clear the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range of the block to be erased.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Clear the ERASE bit.
8. Wait for a time, t
9. Clear the HVEN bit.
10. After time, t
RCV
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
In applications that require more than 1000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a shorter cycle time.
(minimum 10 µs).
NVS
(minimum 1 ms or 4 ms).
Erase
(minimum 5 µs).
NVH
(typical 1 µs), the memory can be accessed in read mode again.
NOTE
Freescale Semiconductor 39
Memory

2.8.3 FLASH Mass Erase Operation

Use this step-by-step procedure to erase the entire FLASH memory.
1. Set both the ERASE bit and the MASS bit in the FLASH control register.
2. Read the FLASH block protect register.
3. Write any data to any FLASH address
4. Wait for a time, t
(minimum 10 µs).
NVS
5. Set the HVEN bit.
6. Wait for a time, t
MErase
(minimum 4 ms).
7. Clear the ERASE and MASS bits.
Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF).
(1)
within the FLASH memory address range.
NOTE
8. Wait for a time, t
9. Clear the HVEN bit.
10. After time, t
RCV
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps.
(minimum 100 µs).
NVHL
(typical 1 µs), the memory can be accessed in read mode again.
NOTE
1. When in monitor mode, with security sequence failed (see 18.3.2 Security), write to the FLASH block protect register instead of any FLASH address.
40 Freescale Semiconductor
FLASH Memory (FLASH)

2.8.4 FLASH Program Operation

Use the following step-by-step procedure to program a row of FLASH memory. Figure 2-4 shows a flowchart of the programming algorithm.
NOTE
Only bytes which are currently $FF may be programmed.
1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming.
2. Read the FLASH block protect register.
3. Write any data to any FLASH location within the address range desired.
4. Wait for a time, t
5. Set the HVEN bit.
6. Wait for a time, t
7. Write data to the FLASH address being programmed
8. Wait for time, t
9. Repeat step 7 and 8 until all desired bytes within the row are programmed.
10. Clear the PGM bit
11. Wait for time, t
12. Clear the HVEN bit.
13. After time, t
RCV
The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set.
(minimum 10 µs).
NVS
(minimum 5 µs).
PGS
(minimum 30 µs).
PROG
(1)
.
(minimum 5 µs).
NVH
(1)
.
(typical 1 µs), the memory can be accessed in read mode again.
NOTE
This program sequence is repeated throughout the memory until all data is programmed.
NOTE
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed t
maximum, see 19.6 FLASH
PROG
Memory Characteristics.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, t
PROG
maximum.
Freescale Semiconductor 41
Memory
ALGORITHM FOR PROGRAMMING A ROW (64 BYTES) OF FLASH MEMORY
1
2
READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS
WITHIN THE ROW ADDRESS RANGE DESIRED
4
5
6
7
8
WRITE DATA TO THE FLASH ADDRESS
SET PGM BIT
WAIT FOR A TIME, t
SET HVEN BIT
WAIT FOR A TIME, t
TO BE PROGRAMMED
WAIT FOR A TIME, t
PROG
NVS
PGS
Note:
The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, t
PROG
max.
This row program algorithm assumes the row/s to be programmed are initially erased.
Figure 2-4. FLASH Programming Flowchart
COMPLETED
PROGRAMMING
THIS ROW?
NO
YES
10
11
12
13
CLEAR PGM BIT
WAIT FOR A TIME, t
CLEAR HVEN BIT
WAIT FOR A TIME, t
END OF PROGRAMMING
NVH
RCV
42 Freescale Semiconductor
FLASH Memory (FLASH)

2.8.5 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. This protection is done by using a FLASH block protect register (FLBPR).
The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends at the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations.
NOTE
In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit
When the FLBPR is programmed with all 0s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1s), the entire memory is accessible for program and erase.
When bits within the FLBPR are programmed, they lock a block of memory, whose address ranges are shown in 2.8.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, V allows entry from reset into the monitor mode.
, present on the IRQ pin. This voltage also
TST

2.8.6 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can be written only during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory.
Address: $FF7E
Bit 7654321Bit 0
Read:
Write:
Reset:00000000
BPR[7:0] — FLASH Block Protect Bits
These eight bits represent bits [14:7] of a 16-bit memory address. Bit 15 is 1 and bits [6:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory at $FFFF. With this mechanism, the protect start address can be XX00 and XX80 (128 bytes page boundaries) within the FLASH memory.
BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0
U = Unaffected by reset. Initial value from factory is 1. Write to this register by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR)
Freescale Semiconductor 43
Memory
16-BIT MEMORY ADDRESS
START ADDRESS OF FLASH
BLOCK PROTECT
1
FLBPR VALUE
0000000
Figure 2-6. FLASH Block Protect Start Address
Refer to Table 2-2 for examples of the protect start address.
Table 2-2. Examples of Protect Start Address
BPR[7:0] Start of Address of Protect Range
$00 The entire FLASH memory is protected.
$01 (0000 0001) $8080 (1000 0000 1000 0000)
$02 (0000 0010) $8100 (1000 0001 0000 0000)
and so on...
$FE (1111 1110) $FF00 (1111 1111 0000 0000)
$FF The entire FLASH memory is not protected.
Note: The end address of the protected range is always $FFFF.

2.8.7 Wait Mode

Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. Otherwise, the operation will discontinue, and the FLASH will be on standby mode.

2.8.8 Stop Mode

Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive.
The STOP instruction should not be executed while performing a program or erase operation on the FLASH, otherwise the operation will discontinue, and the FLASH will be on standby mode
NOTE
Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.
44 Freescale Semiconductor

Chapter 3 Analog-to-Digital Converter (ADC)

3.1 Introduction

This section describes the 10-bit analog-to-digital converter (ADC).

3.2 Features

Features of the ADC module include:
• 10 channels with multiplexed input
• Linear successive approximation
• 10-bit resolution, 8-bit accuracy
• Single or continuous conversion
• Conversion complete flag or conversion complete interrupt
• Selectable ADC clock
• Left or right justified result
• Left justified sign data mode
• High impedance buffered ADC input

3.3 Functional Description

Ten ADC channels are available for sampling external sources at pins PTC1/ATD9:PTC0/ATD8 and PTB7/ATD7:PTB0/ATD0. To achieve the best possible accuracy, these pins are implemented as input-only pins when the analog-to-digital (A/D) feature is enabled. An analog multiplexer allows the single ADC to select one of the 10 ADC channels as ADC voltage IN (ADCVIN). ADCVIN is converted by the successive approximation algorithm. When the conversion is completed, the ADC places the result in the ADC data register (ADRH and ADRL) and sets a flag or generates an interrupt. See Figure 3-2.
Freescale Semiconductor 45
46 Freescale Semiconductor
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
CONTROL AND STATUS REGISTERS — 112 BYTES
OSC1
OSC2
CGMXFC
RST
IRQ
V
DDA
V
SSA
V
REFL
V
REFH
PWMGND
PWM6–PWM1
V
V
V
DDAD
V
SSAD
M68HC08 CPU
CPU
REGISTERS
ARITHMETIC/LOGIC
USER FLASH — 32,256 BYTES
USER RAM — 768 BYTES
MONITOR ROM — 240 BYTES
USER FLASH VECTOR SPACE — 46 BYTES
CLOCK GENERATOR
MODULE
SYSTEM INTEGRATION
MODULE
IRQ
MODULE
(3)
(3)
SS
DD
ANALOG-TO-DIGITAL CONVERTER
MODULE
PULSE-WIDTH MODULATOR
MODULE
POWER
UNIT
INTERNAL BUS
LOW-VOLTAGE INHIBIT
MODULE
COMPUTER OPERATING PROPERLY
SERIAL COMMUNICATIONS INTERFACE
SERIAL PERIPHERAL INTERFACE
MODULE
TIMER INTERFACE
MODULE A
TIMER INTERFACE
MODULE B
MODULE
(2)
MODULE
POWER-ON RESET
MODULE
SINGLE BREAK
MODULE
PTF5/TxD
PTF4/RxD
PTF3/MISO PTF2/MOSI
PTF1/SS
PTF0/SPSCK
(1)
(1)
(1)
(1)
PTF
DDRF
Notes:
1. These pins are not available in the 56-pin SDIP package.
2. This module is not available in the 56-pin SDIP package.
3. In the 56-pin SDIP package, these pins are bonded together.
DDRA
DDRB
DDRC
DDRE
PTA
PTB
PTCPTD
PTE
PTA7–PTA0
PTB7/ATD7
PTB6/ATD6
PTB5/ATD5
PTB4/ATD4
PTB3/ATD3
PTB2/ATD2
PTB1/ATD1
PTB0/ATD0
PTC6
PTC5
PTC4
PTC3
PTC2
PTC1/ATD9
PTC0/ATD8
PTD6/IS3
PTD5/IS2
PTD4/IS1
PTD3/FAULT4
PTD2/FAULT3
PTD1/FAULT2
PTD0/FAULT1
PTE7/TCH3A
PTE6/TCH2A
PTE5/TCH1A
PTE4/TCH0A
PTE3/TCLKA
PTE2/TCH1B
PTE1/TCH0B
PTE0/TCLKB
Analog-to-Digital Converter (ADC)
(1)
(1)
(1)
(1)
Figure 3-1. Block Diagram Highlighting ADC Block and Pins
INTERNAL DATA BUS
Functional Description
PTB/Cx
INTERRUPT
LOGIC
AIEN
READ PTB/PTC
CONVERSION
COCO
CGMXCLK
BUS CLOCK
COMPLETE
ADC DATA REGISTERS
ADC VOLTAGE IN
ADVIN
ADIV[2:0]
ADC
ADC CLOCK
CLOCK
GENERATOR
ADICLK
Figure 3-2. ADC Block Diagram
DISABLE
CHANNEL
SELECT
ADC CHANNEL x
ADCH[4:0]

3.3.1 ADC Port I/O Pins

PTC1/ATD9:PTC0/ATD8 and PTB7/ATD7:PTB0/ATD0 are general-purpose I/O pins that are shared with the ADC channels.
The channel select bits define which ADC channel/port pin will be used as the input signal. The ADC overrides the port logic when that port is selected by the ADC multiplexer. The remaining ADC channels/port pins are controlled by the port logic and can be used as general-purpose input/output (I/O) pins. Writes to the port register or DDR will not have any effect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0.

3.3.2 Voltage Conversion

When the input voltage to the ADC equals V input voltage equals V
the ADC converts it to $000. Input voltages between V
REFL,
straight-line linear conversions. All other input voltages will result in $3FF if greater than V if less than V
REFL
.
Input voltage should not exceed the analog supply voltages. See
19.13 Analog-to-Digital Converter (ADC) Characteristics.
, the ADC converts the signal to $3FF (full scale). If the
REFH
and V
REFH
REFH
NOTE
are
REFL
and $000
Freescale Semiconductor 47
Analog-to-Digital Converter (ADC)

3.3.3 Conversion Time

Conversion starts after a write to the ADSCR. A conversion is between 16 and 17 ADC clock cycles, therefore:
Conversion time =
Number of Bus Cycles = Conversion Time x CPU Bus Frequency
The ADC conversion time is determined by the clock source chosen and the divide ratio selected. The clock source is either the bus clock or CGMXCLK and is selectable by ADICLK located in the ADC clock register. For example, if CGMXCLK is 4 MHz and is selected as the ADC input clock source, the ADC input clock divide-by-4 prescale is selected and the CPU bus frequency is 8 MHz:
16 to17 ADC Cycles
ADC Frequency
Conversion Time =
16 to 17 ADC Cycles
= 16 to 17 µs
4 MHz/4
Number of bus cycles = 16 µs x 8 MHz = 128 to 136 cycles
NOTE
The ADC frequency must be between f
minimum and f
ADIC
maximum
ADIC
to meet A/D specifications. See 19.13 Analog-to-Digital Converter (ADC)
Characteristics.
Since an ADC cycle may be comprised of several bus cycles (eight, 136 minus 128, in the previous example) and the start of a conversion is initiated by a bus cycle write to the ADSCR, from zero to eight additional bus cycles may occur before the start of the initial ADC cycle. This results in a fractional ADC cycle and is represented as the 17th cycle.

3.3.4 Continuous Conversion

In continuous conversion mode, the ADC data registers ADRH and ADRL will be filled with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit is set after each conversion and will stay set until the next read of the ADC data register.
When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading.

3.3.5 Result Justification

The conversion result may be formatted in four different ways:
1. Left justified
2. Right justified
3. Left Justified sign data mode
4. 8-bit truncation mode
All four of these modes are controlled using MODE0 and MODE1 bits located in the ADC clock register (ADCR).
Left justification will place the eight most significant bits (MSB) in the corresponding ADC data register high, ADRH. This may be useful if the result is to be treated as an 8-bit result where the two least
48 Freescale Semiconductor
Functional Description
significant bits (LSB), located in the ADC data register low, ADRL, can be ignored. However, ADRL must be read after ADRH or else the interlocking will prevent all new conversions from being stored.
Right justification will place only the two MSBs in the corresponding ADC data register high, ADRH, and the eight LSBs in ADC data register low, ADRL. This mode of operation typically is used when a 10-bit unsigned result is desired.
Left justified sign data mode is similar to left justified mode with one exception. The MSB of the 10-bit result, AD9 located in ADRH, is complemented. This mode of operation is useful when a result, represented as a signed magnitude from mid-scale, is needed. Finally, 8-bit truncation mode will place the eight MSBs in ADC data register low, ADRL. The two LSBs are dropped. This mode of operation is used when compatibility with 8-bit ADC designs are required. No interlocking between ADRH and ADRL is present.
NOTE
Quantization error is affected when only the most significant eight bits are used as a result. See Figure 3-3.
8-BIT
RESULT
003
10-BIT
RESULT
00B
IDEAL 8-BIT CHARACTERISTIC WITH QUANTIZATION = ±1/2
10-BIT TRUNCATED TO 8-BIT RESULT
00A
IDEAL 10-BIT CHARACTERISTIC
009
WITH QUANTIZATION = ±1/2
002
001
000
008
007
006
005
004
003
002
001
000
1/2 2 1/2 4 1/2 6 1/2 8 1/2
1 1/2 3 1/2 5 1/2 7 1/2 9 1/2
1/2 2 1/21 1/2
WHEN TRUNCATION IS USED, ERROR FROM IDEAL 8-BIT = 3/8 LSB DUE TO NON-IDEAL QUANTIZATION.
Figure 3-3. 8-Bit Truncation Mode Error

3.3.6 Monotonicity

The conversion process is monotonic and has no missing codes.
INPUT VOLTAGE REPRESENTED AS 10-BIT
INPUT VOLTAGE REPRESENTED AS 8-BIT
Freescale Semiconductor 49
Analog-to-Digital Converter (ADC)

3.4 Interrupts

When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.

3.5 Wait Mode

The WAIT instruction can put the MCU in low power-consumption standby mode.
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting ADCH[4:0] in the ADC status and control register before executing the WAIT instruction.

3.6 I/O Signals

The ADC module has 10 input signals that are shared with port B and port C.
3.6.1 ADC Analog Power Pin (V
The ADC analog portion uses V potential as V
. External filtering may be necessary to ensure clean V
DD
DDAD
)
DDAD
as its power pin. Connect the V
NOTE
Route V
carefully for maximum noise immunity and place bypass
DDAD
capacitors as close as possible to the package.
3.6.2 ADC Analog Ground Pin (V
The ADC analog portion uses V potential as V
SS
.
as its ground pin. Connect the V
SSAD
3.6.3 ADC Voltage Reference Pin (V
V voltage potential as
is the power supply for setting the reference voltage V
REFH
V
. There will be a finite current associated with V
DDAD
SSAD
REFH
)
)
Specifications.
NOTE
Route V
carefully for maximum noise immunity and place bypass
REFH
capacitors as close as possible to the package.
3.6.4 ADC Voltage Reference Low Pin (V
V
is the lower reference supply for the ADC. Connect the V
REFL
V
. A finite current will be associated with V
SSAD
REFL
REFL
NOTE
In the 56-pin shrink dual in-line package (SDIP), V together.
pin to the same voltage
DDAD
for good results.
DDAD
pin to the same voltage
SSAD
. Connect the V
REFH
. See Chapter 19 Electrical
REFH
pin to the same
REFH
)
pin to the same voltage potential as
REFL
. See Chapter 19 Electrical Specifications.
REFL
and V
SSAD
are tied
50 Freescale Semiconductor

3.6.5 ADC Voltage In (ADVIN)

ADVIN is the input voltage signal from one of the 10 ADC channels to the ADC module.

3.6.6 ADC External Connections

I/O Registers
This section describes the ADC external connections: V
3.6.6.1 V
Both ac and dc current are drawn through the V
REFH
and V
REFL
and V
REFH
REFH
and V
loop. The AC current is in the form of
REFL
, ANx, and grounding.
REFL
current spikes required to supply charge to the capacitor array at each successive approximation step. The current flows through the internal resistor string. The best external component to meet both these current demands is a capacitor in the 0.01 µF to 1 µF range with good high frequency characteristics. This capacitor is connected between V
REFH
and V
and must be placed as close as possible to the
REFL
package pins. Resistance in the path is not recommended because the dc current will cause a voltage drop which could result in conversion errors.
3.6.6.2 ANx
Empirical data shows that capacitors from the analog inputs to V
improve ADC performance. 0.01-µF
REFL
and 0.1-µF capacitors with good high-frequency characteristics are sufficient. These capacitors must be placed as close as possible to the package pins.
3.6.6.3 Grounding
In cases where separate power supplies are used for analog and digital power, the ground connection between these supplies should be at the V these supplies if possible. The V pin to the same potential as V
SSAD
pin makes a good single point ground location. Connect the V
SSA
at the single point ground location.
pin. This should be the only ground connection between
SSAD
REFL

3.7 I/O Registers

These I/O registers control and monitor operation of the ADC:
• ADC status and control register, ADSCR
• ADC data registers, ADRH and ARDL
• ADC clock register, ADCLK
Freescale Semiconductor 51
Analog-to-Digital Converter (ADC)

3.7.1 ADC Status and Control Register

This section describes the function of the ADC status and control register (ADSCR). Writing ADSCR aborts the current conversion and initiates a new conversion.
Address: $0040
Bit 7654321Bit 0
Read: COCO
Write: R
Reset:00011111
R= Reserved
Figure 3-4. ADC Status and Control Register (ADSCR)
COCO — Conversions Complete Bit
In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit.
In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a 0.
1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled
(AIEN = 1)
AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0
NOTE
The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO bit position.
AIEN — ADC Interrupt Enable Bit
When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.
1 = ADC interrupt enabled 0 = ADC interrupt disabled
ADCO — ADC Continuous Conversion Bit
When set, the ADC will convert samples continuously and update the ADR register at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.
1 = Continuous ADC conversion 0 = One ADC conversion
ADCH[4:0] — ADC Channel Select Bits
ADCH4, ADCH3, ADCH2, ADCH1, and ADCH0 form a 5-bit field which is used to select one of 10 ADC channels. The ADC channels are detailed in Table 3-1.
NOTE
Take care to prevent switching noise from corrupting the analog signal when simultaneously using a port pin as both an analog and digital input.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not used.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
52 Freescale Semiconductor
I/O Registers
The voltage levels supplied from internal reference nodes as specified in Table 3-1 are used to verify the operation of the ADC both in production test and for user applications.
Table 3-1. Mux Channel Select
ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select
00000 PTB0/ATD0
00001 PTB1/ATD1
00010 PTB2/ATD2
00011 PTB3/ATD3
00100 PTB4/ATD4
00101 PTB5/ATD5
00110 PTB6/ATD6
00111 PTB7/ATD7
01000 PTC0/ATD8
01001
01010
PTC1/ATD9
Unused
01011 Ø
01100 Ø
01101 Ø
01110 Ø
01111 Ø
10000 Ø
11010
11011
1
1 1 0 0
1 1 1 0 1
1 1 1 1 0
Unused
Reserved
Unused
V
V
1 1 1 1 1 ADC power off
1. ATD9 is not available in the 56-pin SDIP package.
2. Used for factory testing.
3. If any unused channels are selected, the resulting ADC conversion will be unknown.
(1)
(2)
(2)
(3)
(2)
REFH
REFL
Freescale Semiconductor 53
Analog-to-Digital Converter (ADC)

3.7.2 ADC Data Register High

In left justified mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated each time an ADC single channel conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
Address: $0041
Bit 7654321Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset: Unaffected by reset
R= Reserved
Figure 3-5. ADC Data Register High (ADRH) Left Justified Mode
In right justified mode, this 8-bit result register holds the two MSBs of the 10-bit result. All other bits read as 0. This register is updated each time a single channel ADC conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
Address: $0041
Bit 7654321Bit 0
Read:000000AD9AD8
Write:RRRRRRRR
Reset: Unaffected by reset
R= Reserved
Figure 3-6. ADC Data Register High (ADRH) Right Justified Mode

3.7.3 ADC Data Register Low

In left justified mode, this 8-bit result register holds the two LSBs of the 10-bit result. All other bits read as
0. This register is updated each time a single channel ADC conversion completes. Reading ADRH latches
the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
Address: $0042
Bit 7654321Bit 0
Read:AD1AD0000000
Write:RRRRRRRR
Reset: Unaffected by reset
R= Reserved
Figure 3-7. ADC Data Register Low (ADRL) Left Justified Mode
In right justified mode, this 8-bit result register holds the eight LSBs of the 10-bit result. This register is updated each time an ADC conversion completes. Reading ADRH latches the contents of ADRL until ADRL is read. Until ADRL is read, all subsequent ADC results will be lost.
54 Freescale Semiconductor
I/O Registers
Address: $0042
Bit 7654321Bit 0
Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
Write:RRRRRRRR
Reset: Unaffected by reset
R= Reserved
Figure 3-8. ADC Data Register Low (ADRL) Right Justified Mode
In 8-bit mode, this 8-bit result register holds the eight MSBs of the 10-bit result. This register is updated each time an ADC conversion completes. In 8-bit mode, this register contains no interlocking with ADRH.
Address: $0042
Bit 7654321Bit 0
Read: AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Write:RRRRRRRR
Reset: Unaffected by reset
R= Reserved
Figure 3-9. ADC Data Register Low (ADRL) 8-Bit Mode

3.7.4 ADC Clock Register

This register selects the clock frequency for the ADC, selecting between modes of operation.
Address: $0043
Bit 7654321Bit 0
Read:
Write: R
Reset:00000100
ADIV2 ADIV1 ADIV0 ADICLK MODE1 MODE0 0
R= Reserved
Figure 3-10. ADC Clock Register (ADCLK)
ADIV2:ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations.
Table 3-2. ADC Clock Divide Ratio
ADIV2 ADIV1 ADIV0 ADC Clock Rate
0 0 0 ADC input clock ÷ 1 0 0 1 ADC input clock ÷ 2 0 1 0 ADC input clock ÷ 4 0 1 1 ADC input clock ÷ 8 1 X X ADC input clock ÷ 16
X = don’t care
0
Freescale Semiconductor 55
Analog-to-Digital Converter (ADC)
ADICLK — ADC Input Clock Select Bit
ADICLK selects either bus clock or CGMXCLK as the input clock source to generate the internal ADC clock. Reset selects CGMXCLK as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz, CGMXCLK can be used as the clock source for the ADC. If CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as the clock source. As long as the internal ADC clock is at f
, correct operation can be guaranteed. See
ADIC
19.13 Analog-to-Digital Converter (ADC) Characteristics.
1 = Internal bus clock 0 = External clock, CGMXCLK
ADIC
ADIV[2:0]
CGMXCLK or bus frequency
=
f
MODE1:MODE0 — Modes of Result Justification Bits
MODE1:MODE0 selects among four modes of operation. The manner in which the ADC conversion results will be placed in the ADC data registers is controlled by these modes of operation. Reset returns right-justified mode.
00 = 8-bit truncation mode 01 = Right justified mode 10 = Left justified mode 11 = Left justified sign data mode
56 Freescale Semiconductor

Chapter 4 Clock Generator Module (CGM)

4.1 Introduction

This section describes the clock generator module (CGM, version A). The CGM generates the crystal clock signal, CGMXCLK, which operates at the frequency of the crystal. The CGM also generates the base clock signal, CGMOUT, from which the system integration module (SIM) derives the system clocks.
CGMOUT is based on either the crystal clock divided by two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. The PLL is a frequency generator designed for use with crystals or ceramic resonators. The PLL can generate an 8-MHz bus frequency without using a 32-MHz external clock.

4.2 Features

Features of the CGM include:
• PLL with output frequency in integer multiples of the crystal reference
• Programmable hardware voltage-controlled oscillator (VCO) for low-jitter operation
• Automatic bandwidth control mode for low-jitter operation
• Automatic frequency lock detector
• Central processor unit (CPU) interrupt on entry or exit from locked condition

4.3 Functional Description

The CGM consists of three major submodules:
1. Crystal oscillator circuit — The crystal oscillator circuit generates the constant crystal frequency clock, CGMXCLK.
2. Phase-locked loop (PLL) — The PLL generates the programmable VCO frequency clock, CGMVCLK.
3. Base clock selector circuit — This software-controlled circuit selects either CGMXCLK divided by two or the VCO clock, CGMVCLK, divided by two as the base clock, CGMOUT. The SIM derives the system clocks from CGMOUT.
Figure 4-1 shows the structure of the CGM.
Freescale Semiconductor 57
Clock Generator Module (CGM)
CRYSTAL OSCILLATOR
OSC2
OSC1
SIMOSCEN
CGMRDV
CGMRCLK
V
DDA
PHASE
DETECTOR
LOCK
DETECTOR
LOCK AUTO ACQ
CGMXFC V
LOOP
FILTER
BANDWIDTH
CONTROL
SS
PLL ANALOG
CLOCK SELECT CIRCUIT
BCS
VRS[7:4]
VOLTAGE
CONTROLLED
OSCILLATOR
INTERRUPT
CONTROL
PLLIE PLLF
÷ 2
CGMXCLK
A
B
S*
CGMOUT
*WHEN S = 1, CGMOUT = B
USER MODE
PTC2
MONITOR MODE
CGMINT
TO SIM
TO SIM
MUL[7:4]
CGMVDV CGMVCLK
FREQUENCY
DIVIDER
Figure 4-1. CGM Block Diagram
Addr. Register Name Bit 7654321Bit 0
$005C
$005D
$005E
PLL Control Register
(PCTL)
See page 66.
PLL Bandwidth Control Register
(PBWC)
See page 67.
PLL Programming Register
(PPG)
See page 68.
Read:
Write: R R R R R
PLLIE
Reset:00101111
Read:
Write: R R R R R
AUTO
Reset:00000000
Read:
Write:
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Reset:01100110
PLLF
LOCK
PLLON BCS
ACQ
XLD
1111
0000
R=Reserved
Figure 4-2. CGM I/O Register Summary
58 Freescale Semiconductor
Functional Description

4.3.1 Crystal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of CGMXCLK is not guaranteed to be 50 percent and depends on external factors, including the crystal and related external components.
An externally generated clock also can feed the OSC1 pin of the crystal oscillator circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.

4.3.2 Phase-Locked Loop Circuit (PLL)

The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes either automatically or manually.
4.3.2.1 PLL Circuits
The PLL consists of these circuits:
• Voltage-controlled oscillator (VCO)
• Modulo VCO frequency divider
• Phase detector
• Loop filter
• Lock detector
The operating range of the VCO is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f CGMXFC pin changes the frequency within this range. By design, f center-of-range frequency, f
, (4.9152 MHz) times a linear factor, L or (L) f
NOM
. Modulating the voltage on the
VRS
is equal to the nominal
VRS
.
NOM
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency, f
, and is fed to the PLL through a buffer. The buffer output is the final reference clock, CGMRDV,
RCLK
running at a frequency, f
RDV=fRCLK
The VCO’s output clock, CGMVCLK, running at a frequency, f
.
, is fed back through a programmable
VCLK
modulo divider. The modulo divider reduces the VCO clock by a factor, N. The divider’s output is the VCO feedback clock, CGMVDV, running at a frequency, f
VDV=fVCLK/N
. (See 4.3.2.4 Programming the PLL for
more information.)
The phase detector then compares the VCO feedback clock, CGMVDV, with the final reference clock, CGMRDV. A correction pulse is generated based on the phase difference between the two signals. The loop filter then slightly alters the dc voltage on the external capacitor connected to CGMXFC based on the width and direction of the correction pulse. The filter can make fast or slow corrections depending on its mode, described in 4.3.2.2 Acquisition and Tracking Modes. The value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the PLL.
Freescale Semiconductor 59
Clock Generator Module (CGM)
The lock detector compares the frequencies of the VCO feedback clock, CGMVDV, and the final reference clock, CGMRDV. Therefore, the speed of the lock detector is directly proportional to the final reference frequency, f
. The circuit determines the mode of the PLL and the lock condition based on
RDV
this comparison.
4.3.2.2 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
1. Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ
bit is clear in
the PLL bandwidth control register. See 4.5.2 PLL Bandwidth Control Register.
2. Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected as the base clock source. See 4.3.3 Base Clock Selector Circuit. The PLL is automatically in tracking mode when not in acquisition mode or when the ACQ
bit is set.
4.3.2.3 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. See 4.5.2 PLL
Bandwidth Control Register. If PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set, the VCO clock is safe to use as the source for the base clock. See 4.3.3 Base Clock Selector Circuit. If the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a severe noise hit and the software must take appropriate action, depending on the application. See 4.6
Interrupts for information and precautions on using interrupts.
These conditions apply when the PLL is in automatic bandwidth control mode:
•The ACQ
bit (see 4.5.2 PLL Bandwidth Control Register) is a read-only indicator of the mode of the
filter. For more information, see 4.3.2.2 Acquisition and Tracking Modes.
•The ACQ
bit is set when the VCO frequency is within a certain tolerance, ∆
the VCO frequency is out of a certain tolerance, ∆
. For more information, see 4.8
UNT
, and is cleared when
TRK
Acquisition/Lock Time Specifications.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆ when the VCO frequency is out of a certain tolerance, ∆
. For more information, see 4.8
UNL
, and is cleared
Lock
Acquisition/Lock Time Specifications.
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling the LOCK bit. For more information, see 4.5.1 PLL Control Register.
60 Freescale Semiconductor
Functional Description
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not require an indicator of the lock condition for proper operation. Such systems typically operate well below f
BUSMAX
and require fast startup. These conditions apply when in manual mode:
•ACQ
• Before entering tracking mode (ACQ
is a writable control bit that controls the mode of the filter. Before turning on the PLL in manual
mode, the ACQ
bit must be clear.
= 1), software must wait a given time, t
ACQ
(see 4.8
Acquisition/Lock Time Specifications), after turning on the PLL by setting PLLON in the PLL control
register (PCTL).
• Software must wait a given time, t
, after entering tracking mode before selecting the PLL as the
AL
clock source to CGMOUT (BCS = 1).
• The LOCK bit is disabled.
• CPU interrupts from the CGM are disabled.
4.3.2.4 Programming the PLL
Use this 9-step procedure to program the PLL. Table 4-1 lists the variables used and their meaning.
Table 4-1. Variable Definitions
Variable Definition
f
BUSDES
f
VCLKDES
f
RCLK
f
VCLK
f
BUS
f
NOM
f
VRS
Desired bus clock frequency
Desired VCO clock frequency
Chosen reference crystal frequency
Calculated VCO clock frequency
Calculated bus clock frequency
Nominal VCO center frequency
Shifted FCO center frequency
1. Choose the desired bus frequency, f Example: f
BUSDES
= 8 MHz
BUSDES
2. Calculate the desired VCO frequency, f
f
VCLKDES
Example: f
VCLKDES
3. Using a reference frequency, f
= 4 x 8 MHz = 32 MHz
, equal to the crystal frequency, calculate the VCO frequency
RCLK
.
VCLKDES
= 4 x f
.
BUSDES
multiplier, N. Round the result to the nearest integer.
f
VCLKDES
Example: N =
N =
32 MHz
f
RCLK
= 8 MHz
4 MHz
4. Calculate the VCO frequency, f
Example: f
Freescale Semiconductor 61
VCLK
.
VCLK
f
= N x f
VCLK
RCLK
= 8 x 4 MHz = 32 MHz
Clock Generator Module (CGM)
5. Calculate the bus frequency, f
Example: N =
, and compare f
BUS
f
BUS
32 MHz
f
VCLK
=
= 8 MHz
4
BUS
with f
BUSDES
4 MHz
6. If the calculated f
another f
RCLK
.
7. Using the value 4.9152 MHz for f
is not within the tolerance limits of the application, select another f
BUS
, calculate the VCO linear range multiplier, L. The linear range
NOM
multiplier controls the frequency range of the PLL.
f
VCLK
NOM
)
. The center-or-range frequency is the midpoint
VRS
(
f
= 7 MHz
Example: L =
L = round
32 MHz
4.9152 MHz
8. Calculate the VCO center-of-range frequency, f
between the minimum and maximum frequencies attainable by the PLL.
f
= L x f
Example: f
VRS
= 7 x 4.9152 MHz = 34.4 MHz
VRS
NOM
For proper operation,
f
f
VRS
– f
VCLK
| ≤
NOM
2
.
BUSDES
or
CAUTION
Exceeding the recommended maximum bus frequency or VCO frequency can crash the MCU.
9. Program the PLL registers accordingly:
a. In the upper four bits of the PLL programming register (PPG), program the binary equivalent
of N.
b. In the lower four bits of the PLL programming register (PPG), program the binary equivalent
of L.
4.3.2.5 Special Programming Exceptions
The programming method described in 4.3.2.4 Programming the PLL does not account for possible exceptions. A value of 0 for N or L is meaningless when used in the equations given. To account for these exceptions:
• A 0 value for N is interpreted exactly the same as a value of 1.
• A 0 value for L disables the PLL and prevents its selection as the source for the base clock. See
4.3.3 Base Clock Selector Circuit.

4.3.3 Base Clock Selector Circuit

This circuit is used to select either the crystal clock, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The two input clocks go through a transition control circuit that waits up to three CGMXCLK cycles and three CGMVCLK cycles to change from one clock source to the other. During this time, CGMOUT is held in stasis. The output of the transition control circuit is then divided by
62 Freescale Semiconductor
Functional Description
two to correct the duty cycle. Therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (CGMXCLK or CGMVCLK).
The BCS bit in the PLL control register (PCTL) selects which clock drives CGMOUT. The VCO clock cannot be selected as the base clock source if the PLL is not turned on. The PLL cannot be turned off if the VCO clock is selected. The PLL cannot be turned on or off simultaneously with the selection or deselection of the VCO clock. The VCO clock also cannot be selected as the base clock source if the factor L is programmed to a 0. This value would set up a condition inconsistent with the operation of the PLL, so that the PLL would be disabled and the crystal clock would be forced as the source of the base clock.

4.3.4 CGM External Connections

In its typical configuration, the CGM requires seven external components. Five of these are for the crystal oscillator and two are for the PLL.
The crystal oscillator is normally connected in a Pierce oscillator configuration, as shown in Figure 4-3.
Figure 4-3 shows only the logical representation of the internal components and may not represent actual
circuitry.
SIMOSCEN
OSC1 OSC2 V
RS*
R
B
X1
C1 C2
Figure 4-3. CGM External Connections
The oscillator configuration uses five components:
1. Crystal, X
2. Fixed capacitor, C
1
1
3. Tuning capacitor, C2 (can also be a fixed capacitor)
4. Feedback resistor, R
B
5. Series resistor, RS (optional)
CGMXCLK
SS
*RS can be 0 (shorted) when used with
higher frequency crystals. Refer to manufacturer’s data.
CGMXFC V
C
F
DDA
C
BYP
V
DD
The series resistor (R
) is included in the diagram to follow strict Pierce oscillator guidelines and may not
S
be required for all ranges of operation, especially with high-frequency crystals. Refer to the crystal manufacturer’s data for more information.
Freescale Semiconductor 63
Clock Generator Module (CGM)
Figure 4-3 also shows the external components for the PLL:
• Bypass capacitor, C
• Filter capacitor, C
BYP
F
NOTE
Routing should be done with great care to minimize signal cross talk and noise. (See 4.8 Acquisition/Lock Time Specifications for routing information and more information on the filter capacitor’s value and its effects on PLL performance.)

4.4 I/O Signals

This section describes the CGM input/output (I/O) signals.

4.4.1 Crystal Amplifier Input Pin (OSC1)

The OSC1 pin is an input to the crystal oscillator amplifier.

4.4.2 Crystal Amplifier Output Pin (OSC2)

The OSC2 pin is the output of the crystal oscillator inverting amplifier.

4.4.3 External Filter Capacitor Pin (CGMXFC)

The CGMXFC pin is required by the loop filter to filter out phase corrections. A small external capacitor is connected to this pin.
NOTE
To prevent noise problems, C
should be placed as close to the CGMXFC
F
pin as possible, with minimum routing distances and no routing of other signals across the C
4.4.4 PLL Analog Power Pin (V
V
is a power pin used by the analog portions of the PLL. Connect the V
DDA
potential as the V
DD
pin.
connection.
F
)
DDA
pin to the same voltage
DDA
NOTE
Route V
carefully for maximum noise immunity and place bypass
DDA
capacitors as close as possible to the package.

4.4.5 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and PLL.
64 Freescale Semiconductor

4.4.6 Crystal Output Frequency Signal (CGMXCLK)

CGM Registers
CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (f
) and comes
XCLK
directly from the crystal oscillator circuit. Figure 4-3 shows only the logical relation of CGMXCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be unstable at startup.

4.4.7 CGM Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGM. This signal goes to the SIM, which generates the MCU clocks. CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK, divided by two.

4.4.8 CGM CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

4.5 CGM Registers

These registers control and monitor operation of the CGM:
• PLL control register (PCTL) — see 4.5.1 PLL Control Register
• PLL bandwidth control register (PBWC) — see 4.5.2 PLL Bandwidth Control Register
• PLL programming register (PPG) — see 4.5.3 PLL Programming Register
Figure 4-4 is a summary of the CGM registers.
Addr. Register Name Bit 7654321Bit 0
PLL Control Register
$005C
PLL Bandwidth Control Register
$005D
PLL Programming Register
$005E
Notes:
1. When AUTO = 0, PLLIE is forced to logic 0 and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic 0.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic 0 and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
(PCTL)
See page 66.
(PBWC)
See page 67.
(PPG)
See page 68.
Read:
PLLIE
Write: R R R R R
Reset:00101111
Read:
AUTO
Write: R R R R R
Reset:00000000
Read:
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Write:
Reset:01100110
R
PLLF
LOCK
= Reserved
PLLON BCS
ACQ
XLD
1111
0000
Figure 4-4. CGM I/O Register Summary
Freescale Semiconductor 65
Clock Generator Module (CGM)

4.5.1 PLL Control Register

The PLL control register (PCTL) contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit.
Address: $005C
Bit 7654321Bit 0
Read:
Write: R RRRR
Reset:00101111
PLLIE
R
PLLIE — PLL Interrupt Enable Bit
This read/write bit enables the PLL to generate an interrupt request when the LOCK bit toggles, setting the PLL flag, PLLF. When the AUTO bit in the PLL bandwidth control register (PBWC) is clear, PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE bit.
1 = PLL interrupts enabled 0 = PLL interrupts disabled
PLLF — PLL Interrupt Flag
This read-only bit is set whenever the LOCK bit toggles. PLLF generates an interrupt request if the PLLIE bit also is set. PLLF always reads as logic 0 when the AUTO bit in the PLL bandwidth control register (PBWC) is clear. Clear the PLLF bit by reading the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition 0 = No change in lock condition
PLLF
= Reserved
PLLON BCS
1111
Figure 4-5. PLL Control Register (PCTL)
NOTE
Do not inadvertently clear the PLLF bit. Any read or read-modify-write operation on the PLL control register clears the PLLF bit.
PLLON — PLL On Bit
This read/write bit activates the PLL and enables the VCO clock, CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the base clock, CGMOUT (BCS = 1). See 4.3.3 Base Clock Selector
Circuit. Reset sets this bit so that the loop can stabilize as the MCU is powering up.
1 = PLL on 0 = PLL off
BCS — Base Clock Select Bit
This read/write bit selects either the crystal oscillator output, CGMXCLK, or the VCO clock, CGMVCLK, as the source of the CGM output, CGMOUT. CGMOUT frequency is one-half the frequency of the selected clock. BCS cannot be set while the PLLON bit is clear. After toggling BCS, it may take up to three CGMXCLK and three CGMVCLK cycles to complete the transition from one source clock to the other. During the transition, CGMOUT is held in stasis. See 4.3.3 Base Clock
Selector Circuit. Reset clears the BCS bit.
1 = CGMVCLK divided by two drives CGMOUT 0 = CGMXCLK divided by two drives CGMOUT
NOTE
PLLON and BCS have built-in protection that prevents the base clock selector circuit from selecting the VCO clock as the source of the base clock
66 Freescale Semiconductor
CGM Registers
if the PLL is off. Therefore, PLLON cannot be cleared when BCS is set, and BCS cannot be set when PLLON is clear. If the PLL is off (PLLON = 0), selecting CGMVCLK requires two writes to the PLL control register. See
4.3.3 Base Clock Selector Circuit.
PCTL[3:0] — Unimplemented Bits
These bits provide no function and always read as logic 1s.

4.5.2 PLL Bandwidth Control Register

The PLL bandwidth control register (PBWC):
• Selects automatic or manual (software-controlled) bandwidth control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking mode
Address: $005D
Bit 7654321Bit 0
Read:
Write: R RRRR
Reset:00000000
AUTO
R
LOCK
= Reserved
ACQ
XLD
0000
Figure 4-6. PLL Bandwidth Control Register (PBWC)
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual operation (AUTO = 0), clear the ACQ
bit before turning on the PLL. Reset clears the AUTO bit. 1 = Automatic bandwidth control 0 = Manual bandwidth control
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK, is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as logic 0 and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked 0 = VCO frequency incorrect or unlocked
ACQ
— Acquisition Mode Bit
When the AUTO bit is set, ACQ or tracking mode. When the AUTO bit is clear, ACQ
is a read-only bit that indicates whether the PLL is in acquisition mode
is a read/write bit that controls whether the PLL is
in acquisition or tracking mode.
In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit, enabling acquisition mode.
1 = Tracking mode 0 = Acquisition mode
Freescale Semiconductor 67
Clock Generator Module (CGM)
XLD — Crystal Loss Detect Bit
When the VCO output, CGMVCLK, is driving CGMOUT, this read/write bit can indicate whether the crystal reference frequency is active or not. To check the status of the crystal reference, follow these steps:
1. Write a logic 1 to XLD.
2. Wait N × 4 cycles. (N is the VCO frequency multiplier.)
3. Read XLD.
The crystal loss detect function works only when the BCS bit is set, selecting CGMVCLK to drive CGMOUT. When BCS is clear, XLD always reads as logic 0.
1 = Crystal reference is not active. 0 = Crystal reference is active.
PBWC[3:0] — Reserved for Test
These bits enable test functions not available in user mode. To ensure software portability from development systems to user applications, software should write 0s to PBWC[3:0] whenever writing to PBWC.

4.5.3 PLL Programming Register

The PLL programming register (PPG) contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the VCO.
Address: $005E
Bit 7654321Bit 0
Read:
Write:
Reset:01100110
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
Figure 4-7. PLL Programming Register (PPG)
MUL[7:4] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects the VCO frequency multiplier, N. See 4.3.2.1 PLL Circuits and 4.3.2.4 Programming the PLL. A value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. Reset initializes these bits to $6 to give a default multiply value of 6.
Table 4-2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4 VCO Frequency Multiplier (N)
0000 1
0001 1
0010 2
0011 3
1101 13
1110 14
1111 15
68 Freescale Semiconductor
Interrupts
NOTE
The multiplier select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1).
VRS[7:4] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear multiplier L, which controls the hardware center-of-range frequency f
. See 4.3.2.1 PLL Circuits, 4.3.2.4 Programming the PLL and
VRS
4.5.1 PLL Control Register. VRS[7:4] cannot be written when the PLLON bit in the PLL control register
(PCTL) is set. See 4.3.2.5 Special Programming Exceptions. A value of $0 in the VCO range select bits disables the PLL and clears the BCS bit in the PCTL. See 4.3.3 Base Clock Selector Circuit and
4.3.2.5 Special Programming Exceptions for more information.
Reset initializes the bits to $6 to give a default range multiply value of 6.
NOTE
The VCO range select bits have built-in protection that prevents them from being written when the PLL is on (PLLON = 1) and prevents selection of the VCO clock as the source of the base clock (BCS = 1) if the VCO range select bits are all clear.
The VCO range select bits must be programmed correctly. Incorrect programming may result in failure of the PLL to achieve lock.

4.6 Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC), the PLL can generate a CPU interrupt request every time the LOCK bit changes state. The PLLIE bit in the PLL control register (PCTL) enables CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL, becomes set whether interrupts are enabled or not. When the AUTO bit is clear, CPU interrupts from the PLL are disabled and PLLF reads as logic 0.
Software should read the LOCK bit after a PLL interrupt request to see if the request was due to an entry into lock or an exit from lock. When the PLL enters lock, the VCO clock, CGMVCLK, divided by two can be selected as the CGMOUT source by setting BCS in the PCTL. When the PLL exits lock, the VCO clock frequency is corrupt, and appropriate precautions should be taken. If the application is not frequency-sensitive, interrupts should be disabled to prevent PLL interrupt service routines from impeding software performance or from exceeding stack limitations.
NOTE
Software can select the CGMVCLK divided by two as the CGMOUT source even if the PLL is not locked (LOCK = 0). Therefore, software should make sure the PLL is locked before setting the BCS bit.

4.7 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode.
The WAIT instruction does not affect the CGM. Before entering wait mode, software can disengage and turn off the PLL by clearing the BCS and PLLON bits in the PLL control register (PCTL). Less power-sensitive applications can disengage the PLL without turning it off. Applications that require the PLL to wake the MCU from wait mode also can deselect the PLL output without turning off the PLL.
Freescale Semiconductor 69
Clock Generator Module (CGM)

4.8 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the most critical PLL design parameters. Proper design and use of the PLL ensures the highest stability and lowest acquisition/lock times.

4.8.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL, the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition, regardless of the size of the step input. For example, consider a system with a 5 percent acquisition time tolerance. If a command instructs the system to change from 0 Hz to 1 MHz, the acquisition time is the time taken for the frequency to reach 1 MHz ± 50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is operating at 1 MHz and suffers a –100-kHz noise hit, the acquisition time is the time taken to return from 900 kHz to 1 MHz ±5 kHz. Five kHz = 5% of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the acquisition or lock time varies according to the original error in the output. Minor errors may not even be registered. Typical PLL applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error.
The discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical PLL. Therefore, the definitions for acquisition and lock times for this module are:
• Acquisition time, t
frequency and the desired output frequency to less than the tracking mode entry tolerance, ∆ Acquisition time is based on an initial frequency error, (f
, is the time the PLL takes to reduce the error between the actual output
ACQ
DES
– f
ORIG
)/f
, of not more than ±100
DES
TRK
percent. In automatic bandwidth control mode (see 4.3.2.3 Manual and Automatic PLL Bandwidth
Modes), acquisition time expires when the ACQ
bit becomes set in the PLL bandwidth control
register (PBWC).
• Lock time, t
and the desired output frequency to less than the lock mode entry tolerance, ∆ based on an initial frequency error, (f
, is the time the PLL takes to reduce the error between the actual output frequency
Lock
. Lock time is
Lock
DES
– f
ORIG
)/f
, of not more than ±100 percent. In automatic
DES
bandwidth control mode, lock time expires when the LOCK bit becomes set in the PLL bandwidth control register (PBWC). See 4.3.2.3 Manual and Automatic PLL Bandwidth Modes.
Obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases.

4.8.2 Parametric Influences on Reaction Time

Acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. These reaction times are not constant, however. Many factors directly and indirectly affect the acquisition time.
The most critical parameter which affects the reaction times of the PLL is the reference frequency, f This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are
RDV
.
.
70 Freescale Semiconductor
Acquisition/Lock Time Specifications
required to reduce the frequency error. Therefore, the slower the reference the longer it takes to make these corrections. This parameter is also under user control via the choice of crystal frequency, f
XCLK
.
Another critical parameter is the external filter capacitor. The PLL modifies the voltage on the VCO by adding or subtracting charge from this capacitor. Therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. The size of the capacitor also is related to the stability of the PLL. If the capacitor is too small, the PLL cannot make small enough adjustments to the voltage and the system cannot lock. If the capacitor is too large, the PLL may not be able to adjust the voltage in a reasonable time. See 4.8.3 Choosing a Filter Capacitor.
Also important is the operating voltage potential applied to V
. The power supply potential alters the
DDA
characteristics of the PLL. A fixed value is best. Variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. Noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the PLL.
Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits. External factors, however, can cause drastic changes in the operation of the PLL. These factors include noise injected into the PLL through the filter capacitor filter, capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination.

4.8.3 Choosing a Filter Capacitor

As described in 4.8.2 Parametric Influences on Reaction Time, the external filter capacitor, CF, is critical to the stability and reaction time of the PLL. The PLL is also dependent on reference frequency and supply voltage. The value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. For proper operation, the external filter capacitor must be chosen according to this equation:
V
⎛⎞
DDA
C
C
=
F
FACT
For acceptable values of C
, see 4.8 Acquisition/Lock Time Specifications. For the value of V
FACT
choose the voltage potential at which the MCU is operating. If the power supply is variable, choose a value near the middle of the range of possible supply values.
---------------
⎜⎟
f
⎝⎠
RDV
DDA
,
This equation does not always yield a commonly available capacitor size, so round to the nearest available size. If the value is between two different sizes, choose the higher value for better stability. Choosing the lower size may seem attractive for acquisition time improvement, but the PLL can become unstable. Also, always choose a capacitor with a tight tolerance (±20 percent or better) and low dissipation.

4.8.4 Reaction Time Calculation

The actual acquisition and lock times can be calculated using the equations here. These equations yield nominal values under these conditions:
• Correct selection of filter capacitor, C
• Room temperature operation
• Negligible external leakage on C
• Negligible noise
Freescale Semiconductor 71
, see 4.8.3 Choosing a Filter Capacitor
F
GMXFC
Clock Generator Module (CGM)
The K factor in the equations is derived from internal PLL parameters. K is configured in acquisition mode, and K
is the K factor when the PLL is configured in tracking mode.
TRK
is the K factor when the PLL
ACQ
See 4.3.2.2 Acquisition and Tracking Modes.
V
t
ACQ
t
⎜⎟
f
⎝⎠
RDV
V
⎛⎞
DDA
---------------
=
⎜⎟
AL
f
⎝⎠
RDV
t
LocktACQtAL
⎛⎞
DDA
---------------
=
8
⎛⎞
---------------
⎝⎠
K
ACQ
4
⎛⎞
--------------
⎝⎠
K
TRK
+=
NOTE
The inverse proportionality between the lock time and the reference frequency.
In automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. See 4.3.2.3 Manual and Automatic PLL Bandwidth Modes A certain number of clock
cycles, n
before exiting acquisition mode. A certain number of clock cycles, n PLL is within the lock mode entry tolerance, ∆ multiple of n
, is required to ascertain that the PLL is within the tracking mode entry tolerance, ∆
ACQ
, is required to ascertain that the
TRK
. Therefore, the acquisition time, t
ACQ/fRDV
Lock
, and the acquisition to lock time, tAL, is an integer multiple of n
ACQ
TRK/fRDV
,
TRK
, is an integer
. Also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t
In manual mode, it is usually necessary to wait considerably longer than t
as calculated in the previous example.
Lock
before selecting the PLL
Lock
clock (see 4.3.3 Base Clock Selector Circuit) because the factors described in 4.8.2 Parametric
Influences on Reaction Time may slow the lock time considerably.
72 Freescale Semiconductor

Chapter 5 Configuration Register (CONFIG)

5.1 Introduction

This section describes the configuration register (CONFIG). This register contains bits that configure these options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• Computer operating properly (COP) module
• Top-side pulse-width modulator (PWM) polarity
• Bottom-side PWM polarity
• Edge-aligned versus center-aligned PWMs
• Six independent PWMs versus three complementary PWM pairs

5.2 Functional Description

The configuration register (CONFIG) is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU), it is recommended that this register be written immediately after reset. The configuration register is located at $001F and may be read at anytime.
NOTE
On a FLASH device, the options are one-time writeable by the user after each reset. The registers are not in the FLASH memory but are special registers containing one-time writeable latches after each reset. Upon a reset, the configuration register defaults to predetermined settings as shown in Figure 5-1.
If the LVI module and the LVI reset signal are enabled, a reset occurs when V
falls to a voltage, V
DD
nine consecutive central processor unit (CPU) cycles. Once an LVI reset occurs, the MCU remains in reset until V
, and remains at or below that level for at least
LVRx
rises to a voltage, V
DD
LVRX
.
Freescale Semiconductor 73
Configuration Register (CONFIG)

5.3 Configuration Register

Address: $001F
Bit 7654321Bit 0
Read:
Write:
Reset:00001100
EDGE — Edge-Align Enable Bit
EDGE determines if the motor control PWM will operate in edge-aligned mode or center-aligned mode. See Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC).
1 = Edge-aligned mode enabled 0 = Center-aligned mode enabled
BOTNEG — Bottom-Side PWM Polarity Bit
BOTNEG determines if the bottom-side PWMs will have positive or negative polarity. See Chapter 12
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Negative polarity 0 = Positive polarity
TOPNEG — Top-Side PWM Polarity Bit
TOPNEG determines if the top-side PWMs will have positive or negative polarity. See Chapter 12
Pulse-Width Modulator for Motor Control (PWMMC).
1 = Negative polarity 0 = Positive polarity
INDEP — Independent Mode Enable Bit
INDEP determines if the motor control PWMs will be six independent PWMs or three complementary PWM pairs. See Chapter 12 Pulse-Width Modulator for Motor Control (PWMMC).
1 = Six independent PWMs 0 = Three complementary PWM pairs
LVIRST — LVI Reset Enable Bit
LVIRST enables the reset signal from the LVI module. See
Chapter 9 Low-Voltage Inhibit (LVI).
1 = LVI module resets enabled 0 = LVI module resets disabled
LVIPWR — LVI Power Enable Bit
LVIPWR enables the LVI module. Chapter 9 Low-Voltage Inhibit (LVI)
1 = LVI module power enabled 0 = LVI module power disabled
STOPE — Stop Enable Bit
Writing a 0 or a 1 to bit 1 has no effect on MCU operation. Bit 1 operates the same as the other bits within this write-once register operate.
1 = STOP mode enabled 0 = STOP mode disabled
COPD — COP Disable Bit
COPD disables the COP module. See Chapter 6 Computer Operating Properly (COP).
1 = COP module disabled 0 = COP module enabled
EDGE BOTNEG TOPNEG INDEP LVIRST LVIPWR STOPE COPD
Figure 5-1. Configuration Register (CONFIG)
74 Freescale Semiconductor

Chapter 6 Computer Operating Properly (COP)

6.1 Introduction

This section describes the computer operating properly module, a free-running counter that generates a reset if allowed to overflow. The computer operating properly (COP) module helps software recover from runaway code. Prevent a COP reset by periodically clearing the COP counter.

6.2 Functional Description

Figure 6-1 shows the structure of the COP module. A summary of the input/output (I/O) register is shown
in Figure 6-2.
SIM
CGMXCLK
INTERNAL RESET SOURCES(1)
RESET VECTOR FETCH
COPCTL WRITE
COPD (FROM CONFIG)
RESET
COPCTL WRITE
Note 1. See 14.3.2 Active Resets from Internal Sources.
13-BIT SIM COUNTER
CLEAR ALL BITS
COP MODULE
CLEAR
COP COUNTER
CLEAR BITS 12–4
6-BIT COP COUNTER
Figure 6-1. COP Block Diagram
SIM RESET CIRCUIT
SIM RESET STATUS REGISTER
Freescale Semiconductor 75
Computer Operating Properly (COP)
Addr. Register Name Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
$FFFF
COP Control Register
(COPCTL)
See page 77.
Figure 6-2. COP I/O Register Summary
The COP counter is a free-running, 6-bit counter preceded by the 13-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after
18–24
2
CGMXCLK cycles. With a 4.9152-MHz crystal, the COP timeout period is 53.3 ms. Writing any
value to location $FFFF before overflow occurs clears the COP counter and prevents reset.
A COP reset pulls the RST
pin low for 32 CGMXCLK cycles and sets the COP bit in the SIM reset status
register (SRSR). See 14.7.2 SIM Reset Status Register.
NOTE
Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.

6.3 I/O Signals

This section describes the signals shown in Figure 6-1.

6.3.1 CGMXCLK

CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency is equal to the crystal frequency.

6.3.2 COPCTL Write

Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP counter and clears bits 12–4 of the SIM counter. Reading the COP control register returns the reset vector.

6.3.3 Power-On Reset

The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 CGMXCLK cycles after power-up.

6.3.4 Internal Reset

An internal reset clears the SIM counter and the COP counter.

6.3.5 Reset Vector Fetch

A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter.
76 Freescale Semiconductor
COP Control Register

6.3.6 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Chapter 5 Configuration Register (CONFIG).

6.4 COP Control Register

The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF
Bit 7654321Bit 0
Read: Low byte of reset vector
Write: Clear COP counter
Reset: Unaffected by reset
Figure 6-3. COP Control Register (COPCTL)

6.5 Interrupts

The COP does not generate CPU interrupt requests.

6.6 Monitor Mode

The COP is disabled in monitor mode when V
is present on the IRQ pin or on the RST pin.
HI

6.7 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode.
The COP continues to operate during wait mode.

6.8 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
Freescale Semiconductor 77
Computer Operating Properly (COP)
78 Freescale Semiconductor

Chapter 7 Central Processor Unit (CPU)

7.1 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.

7.2 Features

Features of the CPU include:
• Object code fully upward-compatible with M68HC05 Family
• 16-bit stack pointer with stack manipulation instructions
• 16-bit index register with x-register manipulation instructions
• 8-MHz CPU internal bus frequency
• 64-Kbyte program/data memory space
• 16 addressing modes
• Memory-to-memory data moves without using accumulator
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• Enhanced binary-coded decimal (BCD) data handling
• Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes
• Low-power stop and wait modes

7.3 CPU Registers

Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
Freescale Semiconductor 79
Central Processor Unit (CPU)
7
15
H X
15
15
70
V11H I NZC
0
ACCUMULATOR (A)
0
INDEX REGISTER (H:X)
0
STACK POINTER (SP)
0
PROGRAM COUNTER (PC)
CONDITION CODE REGISTER (CCR)
CARRY/BORROW FLAG
ZERO FLAG
NEGATIVE FLAG
INTERRUPT MASK
HALF-CARRY FLAG
TWO’S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers

7.3.1 Accumulator

The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7654321Bit 0
Read:
Write:
Reset: Unaffected by reset
Figure 7-2. Accumulator (A)

7.3.2 Index Register

The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register.
In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand.
The index register can serve also as a temporary data storage location.
Bit
151413121110987654321
Read:
Write:
Reset:00000000XXXXXXXX
X = Indeterminate
Figure 7-3. Index Register (H:X)
Bit
0
80 Freescale Semiconductor
CPU Registers

7.3.3 Stack Pointer

The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack.
In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit
151413121110987654321
Read:
Write:
Reset:0000000011111111
Bit
0
Figure 7-4. Stack Pointer (SP)
NOTE
The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.

7.3.4 Program Counter

The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched.
Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location.
During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit
151413121110987654321
Read:
Write:
Reset: Loaded with vector from $FFFE and $FFFF
Bit
0
Figure 7-5. Program Counter (PC)
Freescale Semiconductor 81
Central Processor Unit (CPU)

7.3.5 Condition Code Register

The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7654321Bit 0
Read:
Write:
Reset:X1 1X1XXX
V — Overflow Flag
The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
1 = Overflow 0 = No overflow
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor.
1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4
V11H I NZC
X = Indeterminate
Figure 7-6. Condition Code Register (CCR)
I — Interrupt Mask
When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched.
1 = Interrupts disabled 0 = Interrupts enabled
NOTE
To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions.
After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI).
N — Negative Flag
The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result.
1 = Negative result 0 = Non-negative result
82 Freescale Semiconductor
Arithmetic/Logic Unit (ALU)
Z — Zero Flag
The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00.
1 = Zero result 0 = Non-zero result
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag.
1 = Carry out of bit 7 0 = No carry out of bit 7

7.4 Arithmetic/Logic Unit (ALU)

The ALU performs the arithmetic and logic operations defined by the instruction set.
Refer to the CPU08 Reference Manual (document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.

7.5 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

7.5.1 Wait Mode

The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock

7.5.2 Stop Mode

The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.

7.6 CPU During Break Interrupts

If a break module is present on the MCU, the CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately.
A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
Freescale Semiconductor 83
Central Processor Unit (CPU)

7.7 Instruction Set Summary

Table 7-1 provides a summary of the M68HC08 instruction set.
Table 7-1. Instruction Set Summary (Sheet 1 of 6)
Effect
Source
Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP
ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP
AIS #
opr Add Immediate Value (Signed) to SP
AIX #opr Add Immediate Value (Signed) to H:X
AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP
ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP
ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
BCLR n, opr Clear Bit n in M Mn ← 0 ––––––
BCS rel Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3 BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? (Z) = 1 ––––––REL 27 rr 3
BGE opr
BGT opr
BHCC rel Branch if Half Carry Bit Clear PC ← (PC) + 2 + rel ? (H) = 0 ––––––REL 28 rr 3 BHCS rel Branch if Half Carry Bit Set PC ← (PC) + 2 + rel ? (H) = 1 ––––––REL 29 rr 3 BHI rel Branch if Higher PC ← (PC) + 2 + rel ? (C) | (Z) = 0 ––––––REL 22 rr 3
Add with Carry A ← (A) + (M) + (C) – 
Add without Carry A ← (A) + (M) – 
Logical AND A ← (A) & (M) 0 – – –
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right  ––
Branch if Greater Than or Equal To (Signed Operands)
Branch if Greater Than (Signed Operands)
Operation Description
SP ← (SP) + (16
H:X ← (H:X) + (16
C
b7
b7
PC ← (PC) + 2 + rel ? (N
PC ← (PC) + 2 + rel ? (Z) | (N
« M)
« M)
0
b0
C
b0
⊕ V) = 0
⊕ V) = 0
on CCR
VH I NZC
––––––IMM A7 ii 2
––––––IMM AF ii 2
 ––

––––––REL 90 rr 3
––––––REL 92 rr 3
Address
IMM DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
DIR INH INH IX1 IX SP1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
Mode
9EE9 9ED9
9EEB
9EDB
9EE4 9ED4
9E68
9E67
A9 B9 C9 D9 E9 F9
AB BB CB DB EB FB
A4 B4 C4 D4 E4 F4
38 48 58 68 78
37 47 57 67 77
11 13 15 17 19 1B 1D 1F
Opcode
ii dd hh ll ee ff ff
ff ee ff
ii dd hh ll ee ff ff
ff ee ff
ii dd hh ll ee ff ff
ff ee ff
dd
ff
ff dd
ff
ff
dd dd dd dd dd dd dd dd
Operand
Cycles
2 3 4 4 3 2 4 5
2 3 4 4 3 2 4 5
2 3 4 4 3 2 4 5
4 1 1 4 3 5
4 1 1 4 3 5
4 4 4 4 4 4 4 4
84 Freescale Semiconductor
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 2 of 6)
Effect
Source
Form
BHS rel
BIH rel Branch if IRQ BIL rel Branch if IRQ BIT #opr
BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP
BLE opr
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? (C) = 1 ––––––REL 25 rr 3 BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? (C) | (Z) = 1 ––––––REL 23 rr 3
BLT opr Branch if Less Than (Signed Operands) BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? (I) = 0 ––––––REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? (N) = 1 ––––––REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? (I) = 1 ––––––REL 2D rr 3 BNE rel Branch if Not Equal PC ← (PC) + 2 + rel ? (Z) = 0 ––––––REL 26 rr 3 BPL rel Branch if Plus PC ← (PC) + 2 + rel ? (N) = 0 ––––––REL 2A rr 3 BRA rel Branch Always PC ← (PC) + 2 + rel ––––––REL 20 rr 3
BRCLR n,opr,rel Branch if Bit n in M Clear PC ← (PC) + 3 + rel ? (Mn) = 0 –––––
BRN rel Branch Never PC ← (PC) + 2 ––––––REL 21 rr 3
BRSET n,opr,rel Branch if Bit n in M Set PC ← (PC) + 3 +
BSET n,opr Set Bit n in M Mn ← 1 ––––––
BSR rel Branch to Subroutine
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel
CLC Clear Carry Bit C ← 0 –––––0INH 98 1 CLI Clear Interrupt Mask I ← 0 ––0–––INH 9A 2
Branch if Higher or Same (Same as BCC)
Bit Test (A) & (M) 0 – – –
Branch if Less Than or Equal To (Signed Operands)
Compare and Branch if Equal
Operation Description
PC ← (PC) + 2 + rel ? (C) = 0 ––––––REL 24 rr 3
Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ––––––REL 2F rr 3 Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ––––––REL 2E rr 3
PC ← (PC) + 2 + rel ? (Z) | (N
PC ← (PC) + 2 + rel ? (N
rel ? (Mn) = 1 –––––
PC ← (PC) + 2; push (PCL) SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 3 + rel ? (X) – (M) = $00 PC ← (PC) + 3 + rel ? (A) – (M) = $00 PC ← (PC) + 2 + rel ? (A) – (M) = $00 PC ← (PC) + 4 + rel ? (A) – (M) = $00
⊕ V) = 1
⊕ V) =1
on CCR
VH I NZC
––––––REL 93 rr 3
––––––REL 91 rr 3
––––––REL AD rr 4
––––––
Address
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
DIR IMM IMM IX1+ IX+ SP1
Mode
9EE5 9ED5
9E61
A5 B5 C5 D5 E5 F5
01 03 05 07 09 0B 0D 0F
00 02 04 06 08 0A 0C 0E
10 12 14 16 18 1A 1C 1E
31 41 51 61 71
Opcode
ii dd hh ll ee ff ff
ff ee ff
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr
dd dd dd dd dd dd dd dd
dd rr ii rr ii rr ff rr rr ff rr
Operand
2 3 4 4 3 2 4 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
4 4 4 4 4 4 4 4
5 4 4 5 4 6
Cycles
Freescale Semiconductor 85
Central Processor Unit (CPU)
Source
Form
CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP
CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP
COM
opr
COMA COMX COM opr,X COM ,X COM opr,SP
CPHX #opr CPHX opr
CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP
DAA Decimal Adjust A
DBNZ opr,rel DBNZA rel DBNZX rel DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel
DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP
DIV Divide
EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP
INC opr INCA INCX INC opr,X INC ,X INC opr,SP
Clear
Compare A with M (A) – (M)  ––
Complement (One’s Complement)
Compare H:X with M (H:X) – (M:M + 1)  ––
Compare X with M (X) – (M)  ––
Decrement and Branch if Not Zero
Decrement
Exclusive OR M with A
Increment
Operation Description
Table 7-1. Instruction Set Summary (Sheet 3 of 6)
Effect
on CCR
VH I NZC
M ← $00
A ← $00
X ← $00 H ← $00 M ← $00 M ← $00 M ← $00
M ← (M
) = $FF – (M)
A ← (A
) = $FF – (M)
X ← (X) = $FF – (M)
M ← (M
) = $FF – (M)
M ← (M) = $FF – (M) M ← (M) = $FF – (M)
(A)
10
A ← (A) – 1 or M ← (M) – 1 or X ← (X) – 1
PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 3 + rel ? (result) ≠ 0 PC ← (PC) + 2 + rel ? (result) ≠ 0 PC ← (PC) + 4 + rel ? (result) ≠ 0
M
← (M) – 1 A ← (A) – 1 X ← (X) – 1
M ← (M) – 1 M ← (M) – 1 M ← (M) – 1
A ← (H:A)/(X)
H ← Remainder
A ← (A
⊕ M)
M ← (M) + 1
A ← (A) + 1 X ← (X) + 1
M ← (M) + 1 M ← (M) + 1 M ← (M) + 1
0––01–
0––1
U–– INH 72 2
––––––
–––
––––INH 52 7
0–––
–––
DIR INH INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
IMM DIR
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
DIR INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
Address
Mode
Opcode
Operand
3F
dd 4F 5F 8C 6F
ff 7F
9E6F
ff
ii
A1
dd
B1
hh ll
C1
ee ff
D1
ff
E1 F1
ff
9EE1
ee ff
9ED1
33
dd 43 53 63
ff 73
9E63
ff 6575ii ii+1dd3
A3
ii B3
dd C3
hh ll D3
ee ff E3
ff F3
9EE3
ff
9ED3
ee ff
3B
dd rr 4B
rr 5B
rr 6B
ff rr 7B
rr
9E6B
ff rr 3A
dd 4A 5A 6A
ff 7A
9E6A
ff
A8
ii B8
dd C8
hh ll D8
ee ff E8
ff F8
9EE8
ff
9ED8
ee ff 3C
dd 4C 5C 6C
ff 7C
9E6C
ff
Cycles
3 1 1 1 3 2 4
2 3 4 4 3 2 4 5
4 1 1 4 3 5
4 2
3 4 4 3 2 4 5
5 3 3 5 4 6
4 1 1 4 3 5
2 3 4 4 3 2 4 5
4 1 1 4 3 5
86 Freescale Semiconductor
Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 4 of 6)
Effect
Source
Form
JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X
JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X
LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
LDHX #opr LDHX opr
LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP
LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP
LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP
MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr
MUL Unsigned multiply X:A ← (X) × (A) –0–––0INH 42 5 NEG opr
NEGA NEGX NEG opr,X NEG ,X NEG opr,SP
NOP No Operation None ––––––INH 9D 1 NSA Nibble Swap A A ← (A[3:0]:A[7:4]) ––––––INH 62 3 ORA #opr
ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP
PSHA Push A onto Stack Push (A); SP ← (SP) – 1 ––––––INH 87 2 PSHH Push H onto Stack Push (H); SP ← (SP) – 1 ––––––INH 8B 2 PSHX Push X onto Stack Push (X); SP ← (SP) – 1 ––––––INH 89 2
Jump PC ← Jump Address ––––––
Jump to Subroutine
Load A from M A ← (M) 0–––
Load H:X from M H:X ← (M:M + 1) 0–––
Load X from M X ← (M) 0–––
Logical Shift Left (Same as ASL)
Logical Shift Right  ––0
Move
Negate (Two’s Complement)
Inclusive OR A and M A ← (A) | (M) 0 – – –
Operation Description
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Unconditional Address
C
b7
b7
(M)
Destination
H:X ← (H:X) + 1 (IX+D, DIX+)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X) M ← –(M) = $00 – (M) M ← –(M) = $00 – (M)
← (M)
0
b0
C0
b0
Source
on CCR
VH I NZC
––––––
––
0–––
––
DIR EXT IX2 IX1 IX
DIR EXT IX2 IX1 IX
IMM DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR INH INH IX1 IX SP1
DIR INH INH IX1 IX SP1
DD DIX+ IMD IX+D
DIR INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
Address
Mode
Opcode
BC
dd
CC
hh ll
DC
ee ff
EC
ff
FC BD
dd
CD
hh ll
DD
ee ff
ED
ff
FD
A6
ii
B6
dd
C6
hh ll
D6
ee ff
E6
ff
F6
9EE6
ff
9ED6
ee ff
4555ii jjdd3
AE
ii
BE
dd
CE
hh ll
DE
ee ff
EE
ff
FE
9EEE
ff
9EDE
ee ff
38
dd 48 58 68
ff 78
9E68
ff 34
dd 44 54 64
ff 74
9E64
ff 4E
dd dd 5E
dd 6E
ii dd 7E
dd
30
dd 40 50 60
ff 70
9E60
ff
AA
ii
BA
dd
hh ll
CA
ee ff
DA
ff
EA
FA
ff
9EEA
ee ff
9EDA
Operand
2 3 4 3 2
4 5 6 5 4
2 3 4 4 3 2 4 5
4 2
3 4 4 3 2 4 5
4 1 1 4 3 5
4 1 1 4 3 5
5 4 4 4
4 1 1 4 3 5
2 3 4 4 3 2 4 5
Cycles
Freescale Semiconductor 87
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 5 of 6)
Effect
Source
Form
PULA Pull A from Stack SP ← (SP + 1); Pull (A) ––––––INH 86 2 PULH Pull H from Stack SP ← (SP + 1); Pull (H) ––––––INH 8A 2 PULX Pull X from Stack SP ← (SP + 1); Pull (X) ––––––INH 88 2 ROL opr
ROLA ROLX ROL opr,X ROL ,X ROL opr,SP
ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP
RSP Reset Stack Pointer SP ← $FF ––––––INH 9C 1
RTI Return from Interrupt
RTS Return from Subroutine
SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP
SEC Set Carry Bit C ← 1 –––––1INH 99 1 SEI Set Interrupt Mask I ← 1 ––1–––INH 9B 2 STA opr
STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP
STHX opr Store H:X in M (M:M + 1) ← (H:X) 0 – – – DIR 35 dd 4
STOP
STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP
SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Rotate Left through Carry  ––
Rotate Right through Carry  ––
Subtract with Carry A ← (A) – (M) – (C)  ––
Store A in M M ← (A) 0–––
Enable Interrupts, Stop Processing, Refer to MCU Documentation
Store X in M M ← (X) 0–––
Subtract A ← (A) – (M)  ––
Operation Description
C
b7
b7
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A) SP ← (SP) + 1; Pull (X)
SP ←
(SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
SP ← SP + 1; Pull (PCH) SP ← SP + 1; Pull (PCL)
I ← 0; Stop Processing ––0–––INH 8E 1
b0
b0
C
on CCR
VH I NZC
INH 80 7
––––––INH 81 4

DIR INH INH IX1 IX SP1
DIR INH INH IX1 IX SP1
IMM DIR EXT IX2 IX1 IX SP1 SP2
DIR EXT IX2 IX1 IX SP1 SP2
DIR EXT IX2 IX1 IX SP1 SP2
IMM DIR EXT IX2 IX1 IX SP1 SP2
Address
Mode
9E69
9E66
9EE2 9ED2
9EE7 9ED7
9EEF 9EDF
9EE0 9ED0
39 49 59 69 79
36 46 56 66 76
A2 B2
C2 D2
E2 F2
B7
C7 D7
E7 F7
BF CF DF EF
FF
A0 B0
C0 D0
E0 F0
Opcode
dd
ff
ff
dd
ff
ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
dd
hh ll
ee ff
ff
ff
ee ff
ii
dd
hh ll
ee ff
ff
ff
ee ff
Operand
Cycles
4 1 1 4 3 5
4 1 1 4 3 5
2 3 4 4 3 2 4 5
3 4 4 3 2 4 5
3 4 4 3 2 4 5
2 3 4 4 3 2 4 5
88 Freescale Semiconductor
Opcode Map
Table 7-1. Instruction Set Summary (Sheet 6 of 6)
Effect
Source
Form
SWI Software Interrupt
TAP Transfer A to CCR CCR ← (A) INH 84 2 TAX Transfer A to X X ← (A) ––––––INH 97 1 TPA Transfer CCR to A A ← (CCR) ––––––INH 85 1 TST opr
TSTA TSTX TST opr,X TST ,X TST opr,SP
TSX Transfer SP to H:X H:X ← (SP) + 1 ––––––INH 95 2 TXA Transfer X to A A ← (X) ––––––INH 9F 1 TXS Transfer H:X to SP (SP) ← (H:X) – 1 ––––––INH 94 2
WAIT Enable Interrupts; Wait for Interrupt
A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR
IMM Immediate addressing mode INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location Set or cleared N Negative bit — Not affected
Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – –
Operation Description
PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
I bit ← 0; Inhibit CPU clocking
until interrupted
⊕ Logical EXCLUSIVE OR
« Sign extend
on CCR
VH I NZC
––1–––INH 83 9
––0–––INH 8F 1
DIR INH INH IX1 IX SP1
Address
Mode
9E6D
3D 4D 5D 6D 7D
Opcode
dd
ff
ff
Operand
3 1 1 3 2 4
Cycles

7.8 Opcode Map

See Table 7-2.
Freescale Semiconductor 89
90 Freescale Semiconductor
MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
MSB
LSB
05BRSET0
3DIR
15BRCLR0
3DIR
25BRSET1
3DIR
35BRCLR1
3DIR
45BRSET2
3DIR
55BRCLR2
3DIR
65BRSET3
3DIR
75BRCLR3
3DIR
85BRSET4
3DIR
95BRCLR4
3DIR
A5BRSET5
3DIR
B5BRCLR5
3DIR
C5BRSET6
3DIR
D5BRCLR6
3DIR
E5BRSET7
3DIR
F5BRCLR7
3DIR
Table 7-2. Opcode Map
DIR DIR REL DIR INH INH IX1 SP1 IX INH INH IMM DIR EXT IX2 SP2 IX1 SP1 IX
0 1 2 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F
4
BSET0
2DIR
4
BCLR0
2DIR
4
BSET1
2DIR
4
BCLR1
2DIR
4
BSET2
2DIR
4
BCLR2
2DIR
4
BSET3
2DIR
4
BCLR3
2DIR
4
BSET4
2DIR
4
BCLR4
2DIR
4
BSET5
2DIR
4
BCLR5
2DIR
4
BSET6
2DIR
4
BCLR6
2DIR
4
BSET7
2DIR
4
BCLR7
2DIR
3
BRA
2REL
3
BRN
2REL
3
BHI
2REL
3
BLS
2REL
3
BCC
2REL
3
BCS
2REL
3
BNE
2REL
3
BEQ
2REL
3
BHCC
2REL
3
BHCS
2REL
3
BPL
2REL
3
BMI
2REL
3
BMC
2REL
3
BMS
2REL
3
BIL
2REL
3
BIH
2REL
4
NEG
2DIR
5
CBEQ
3DIR
4
COM
2DIR
4
LSR
2DIR
4
STHX
2DIR
4
ROR
2DIR
4
ASR
2DIR
4
LSL
2DIR
4
ROL
2DIR
4
DEC
2DIR
5
DBNZ
3DIR
4
INC
2DIR
3
TST
2DIR
3
CLR
2DIR
1
NEGA
1INH
4
CBEQA
3IMM
5
MUL
1INH
1
COMA
1INH
1
LSRA
1INH
3
LDHX
3IMM
1
RORA
1INH
1
ASRA
1INH
1
LSLA
1INH
1
ROLA
1INH
1
DECA
1INH
3
DBNZA
2INH
1
INCA
1INH
1
TSTA
1INH
5
MOV
3DD
1
CLRA
1INH
1
NEGX
1INH
4
CBEQX
3IMM
7
DIV
1INH
1
COMX
1INH
1
LSRX
1INH
4
LDHX
2DIR
1
RORX
1INH
1
ASRX
1INH
1
LSLX
1INH
1
ROLX
1INH
1
DECX
1INH
3
DBNZX
2INH
1
INCX
1INH
1
TSTX
1INH
4
MOV
2DIX+
1
CLRX
1INH
4
NEG
2IX1
3IX1+
1INH
2IX1
2IX1
3IMM
2IX1
2IX1
2IX1
2IX1
2IX1
3IX1
2IX1
2IX1
3IMD
2IX1
5
CBEQ
3
NSA
4
COM
4
LSR
3
CPHX
4
ROR
4
ASR
4
LSL
4
ROL
4
DEC
5
DBNZ
4
INC
3
TST
4
MOV
3
CLR
3 SP1
4 SP1
3 SP1
3 SP1
3 SP1
3 SP1
3 SP1
3 SP1
3 SP1
4 SP1
3 SP1
3 SP1
3 SP1
5
NEG
6
CBEQ
5
COM
5
LSR
ROR
5
ASR
5
LSL
5
ROL
5
DEC
6
DBNZ
5
INC
4
TST
4
CLR
NEG
1IX
CBEQ
2IX+
DAA
1INH
COM
1IX
LSR
1IX
CPHX
2DIR
5
ROR
1IX
ASR
1IX
LSL
1IX
ROL
1IX
DEC
1IX
DBNZ
2IX
INC
1IX
TST
1IX
MOV
2IX+D
CLR
1IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
7
RTI
1INH
4
RTS
1INH
9
SWI
1INH
2
TA P
1INH
1
TPA
1INH
2
PULA
1INH
2
PSHA
1INH
2
PULX
1INH
2
PSHX
1INH
2
PULH
1INH
2
PSHH
1INH
1
CLRH
1INH
1
STOP
1INH
1
WAIT
1INH
3
BGE
2REL
3
BLT
2REL
3
BGT
2REL
3
BLE
2REL
2
TXS
1INH
2
TSX
1INH
1
TA X
1INH
1
CLC
1INH
1
SEC
1INH
2
CLI
1INH
2
SEI
1INH
1
RSP
1INH
1
NOP
1INH
*
1
TXA
1INH
2
SUB
2IMM
2
CMP
2IMM
2
SBC
2IMM
2
CPX
2IMM
2
AND
2IMM
2
BIT
2IMM
2
LDA
2IMM
2
AIS
2IMM
2
EOR
2IMM
2
ADC
2IMM
2
ORA
2IMM
2
ADD
2IMM
4
BSR
2REL
2
LDX
2IMM
2
AIX
2IMM
3
SUB
2DIR
3
CMP
2DIR
3
SBC
2DIR
3
CPX
2DIR
3
AND
2DIR
3
BIT
2DIR
3
LDA
2DIR
3
STA
2DIR
3
EOR
2DIR
3
ADC
2DIR
3
ORA
2DIR
3
ADD
2DIR
2
JMP
2DIR
4
JSR
2DIR
3
LDX
2DIR
3
STX
2DIR
4
SUB
3EXT
4
CMP
3EXT
4
SBC
3EXT
4
CPX
3EXT
4
AND
3EXT
4
BIT
3EXT
4
LDA
3EXT
4
STA
3EXT
4
EOR
3EXT
4
ADC
3EXT
4
ORA
3EXT
4
ADD
3EXT
3
JMP
3EXT
5
JSR
3EXT
4
LDX
3EXT
4
STX
3EXT
4
SUB
3IX2
4
CMP
3IX2
4
SBC
3IX2
4
CPX
3IX2
4
AND
3IX2
4
BIT
3IX2
4
LDA
3IX2
4
STA
3IX2
4
EOR
3IX2
4
ADC
3IX2
4
ORA
3IX2
4
ADD
3IX2
4
JMP
3IX2
6
JSR
3IX2
4
LDX
3IX2
4
STX
3IX2
5
SUB
4 SP2
5
CMP
4 SP2
5
SBC
4 SP2
5
CPX
4 SP2
5
AND
4 SP2
5
BIT
4 SP2
5
LDA
4 SP2
5
STA
4 SP2
5
EOR
4 SP2
5
ADC
4 SP2
5
ORA
4 SP2
5
ADD
4 SP2
5
LDX
4 SP2
5
STX
4 SP2
3
SUB
2IX1
3
CMP
2IX1
3
SBC
2IX1
3
CPX
2IX1
3
AND
2IX1
3
BIT
2IX1
3
LDA
2IX1
3
STA
2IX1
3
EOR
2IX1
3
ADC
2IX1
3
ORA
2IX1
3
ADD
2IX1
3
JMP
2IX1
5
JSR
2IX1
3
LDX
2IX1
3
STX
2IX1
4
SUB
3 SP1
4
CMP
3 SP1
4
SBC
3 SP1
4
CPX
3 SP1
4
AND
3 SP1
4
BIT
3 SP1
4
LDA
3 SP1
4
STA
3 SP1
4
EOR
3 SP1
4
ADC
3 SP1
4
ORA
3 SP1
4
ADD
3 SP1
4
LDX
3 SP1
4
STX
3 SP1
SUB
1IX
CMP
1IX
SBC
1IX
CPX
1IX
AND
1IX
BIT
1IX
LDA
1IX
STA
1IX
EOR
1IX
ADC
1IX
ORA
1IX
ADD
1IX
JMP
1IX
JSR
1IX
LDX
1IX
STX
1IX
Central Processor Unit (CPU)
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
INH Inherent REL Relative SP1 Stack Pointer, 8-Bit Offset IMM Immediate IX Indexed, No Offset SP2 Stack Pointer, 16-Bit Offset DIR Direct IX1 Indexed, 8-Bit Offset IX+ Indexed, No Offset with EXT Extended IX2 Indexed, 16-Bit Offset Post Increment DD Direct-Direct IMD Immediate-Direct IX1+ Indexed, 1-Byte Offset with IX+D Indexed-Direct DIX+ Direct-Indexed Post Increment
*Pre-byte for stack pointer indexed instructions
MSB
LSB
Low Byte of Opcode in Hexadecimal 05BRSET0
0 High Byte of Opcode in Hexadecimal
3DIR
Cycles Opcode Mnemonic Number of Bytes / Addressing Mode

Chapter 8 External Interrupt (IRQ)

8.1 Introduction

This section describes the external interrupt (IRQ) module, which supports external interrupt functions.

8.2 Features

Features of the IRQ module include:
• A dedicated external interrupt pin, IRQ
• Hysteresis buffers

8.3 Functional Description

A logic 0 applied to any of the external interrupt pins can latch a CPU interrupt request. Figure 8-1 shows the structure of the IRQ module.
ACK1
V
DD
CLR
IRQ
DQ
CK
IRQ
LATCH
MODE1
IMASK1
SYNCHRO-
NIZER
HIGH
VOLTAGE
DETECT
IRQ INTERRUPT REQUEST
TO MODE SELECT LOGIC
Figure 8-1. IRQ Module Block Diagram
Addr. Register Name Bit 7654321Bit 0
$003F
IRQ Status/Control Register
(ISCR)
See page 94.
Read:0000
Write:RRRR ACK1
Reset:00000000
R= Reserved
IRQF
0
IMASK1 MODE1
Figure 8-2. IRQ I/O Register Summary
Freescale Semiconductor 91
External Interrupt (IRQ)
Interrupt signals on the IRQ pin are latched into the IRQ1 latch. An interrupt latch remains set until one of the following actions occurs:
• Vector fetch — A vector fetch automatically generates an interrupt acknowledge signal that clears the latch that caused the vector fetch.
• Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge bit in the interrupt status and control register (ISCR). Writing a logic 1 to the ACK1 bit clears the IRQ1 latch.
• Reset — A reset automatically clears both interrupt latches.
The external interrupt pins are falling-edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ
pin.
When the interrupt pin is edge-triggered only, the interrupt latch remains set until a vector fetch, software clear, or reset occurs.
When the interrupt pin is both falling-edge and low-level-triggered, the interrupt latch remains set until both of these occur:
• Vector fetch, software clear, or reset
• Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending.
When set, the IMASK1 bit in the ISCR masks all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. (See Figure 8-3.)

8.4 IRQ Pin

A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ set, both of these actions must occur to clear the IRQ1 latch:
• Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software can generate the interrupt acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ
pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set.
pin is both falling-edge-sensitive and low-level- sensitive. With MODE1
pin and require software to clear the IRQ1 latch. Writing to the ACK1
pin. A falling edge that occurs after writing to the ACK1 bit latches another
92 Freescale Semiconductor
FROM RESET
IRQ Pin
YES
I BIT SET?
NO
INTERRUPT?
NO
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
YES
YES
STACK CPU REGISTERS
LOAD PC WITH INTERRUPT VECTOR
SET I BIT
NO
RTI
INSTRUCTION?
NO
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 8-3. IRQ Interrupt Flowchart
Freescale Semiconductor 93
External Interrupt (IRQ)
A logic 0 on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE1 bit is set, the IRQ
pin is both falling-edge-sensitive and low-level- sensitive. With MODE1
set, both of these actions must occur to clear the IRQ1 latch:
• Vector fetch, software clear, or reset — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software can generate the interrupt acknowledge signal by writing a logic 1 to the ACK1 bit in the interrupt status and control register (ISCR). The ACK1 bit is useful in applications that poll the IRQ
pin and require software to clear the IRQ1 latch. Writing to the ACK1 bit can also prevent spurious interrupts due to noise. Setting ACK1 does not affect subsequent transitions on the IRQ
pin. A falling edge that occurs after writing to the ACK1 bit latches another interrupt request. If the IRQ1 mask bit, IMASK1, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB.
• Return of the IRQ
The vector fetch or software clear and the return of the IRQ interrupt request remains pending as long as the IRQ
If the MODE1 bit is clear, the IRQ
pin to logic 1 — As long as the IRQ pin is at logic 0, the IRQ1 latch remains set.
pin to logic 1 can occur in any order. The
pin is at logic 0.
pin is falling-edge-sensitive only. With MODE1 clear, a vector fetch or
software clear immediately clears the IRQ1 latch.
Use the branch if IRQ the IRQ
pin.
pin high (BIH) or branch if IRQ pin low (BIL) instruction to read the logic level on
NOTE
When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine.

8.5 IRQ Status and Control Register

The IRQ status and control register (ISCR) has these functions:
• Clears the IRQ interrupt latch
• Masks IRQ interrupt requests
• Controls triggering sensitivity of the IRQ
Address: $003F
Bit 7654321Bit 0
Read:0000
Write:RRRR ACK1
Reset:00000000
R= Reserved
Figure 8-4. IRQ Status and Control Register (ISCR)
ACK1 — IRQ Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ latch. ACK1 always reads as logic 0. Reset clears ACK1.
interrupt pin
IRQF
0
IMASK1 MODE1
94 Freescale Semiconductor
IRQ Status and Control Register
IMASK1 — IRQ Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK1.
1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled
MODE1 — IRQ Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ
1 = IRQ 0 = IRQ
interrupt requests on falling edges and low levels interrupt requests on falling edges only
pin. Reset clears MODE1.
IRQF — IRQ Flag
This read-only bit acts as a status flag, indicating an IRQ event occurred.
1 = External IRQ event occurred. 0 = External IRQ event did not occur.
Freescale Semiconductor 95
External Interrupt (IRQ)
96 Freescale Semiconductor

Chapter 9 Low-Voltage Inhibit (LVI)

9.1 Introduction

This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the V

9.2 Features

Features of the LVI module include:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of V
pin level
DD
• Selectable LVI trip voltage

9.3 Functional Description

Figure 9-1 shows the structure of the LVI module. The LVI is enabled out of reset. The LVI module
contains a bandgap reference circuit and comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V falls below a voltage, V V
LVRX
LVIRST are in the configuration register (CONFIG). See Chapter 5 Configuration Register (CONFIG).
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate a reset when V
DD
, and remains at or below that level for nine or more consecutive CGMXCLK.
LVRX
and V
are determined by the TRPSEL bit in the LVISCR (see Figure 9-2). LVIPWR and
LVHX
voltage falls to the LVI trip voltage.
DD
DD
V
DD
LVIPWR
FROM CONFIG
FROM CONFIG
LVIRST
LVI RESET
LOW V
DD
DETECTOR
TRPSEL
FROM LVISCR
CPU CLOCK
VDD > LVItrip = 0
V
< LVItrip = 1
DD
ANLGTRIP
V
DD
DIGITAL FILTER
LVIOUT
Figure 9-1. LVI Module Block Diagram
Freescale Semiconductor 97
Low-Voltage Inhibit (LVI)
Once an LVI reset occurs, the MCU remains in reset until V
must be above V
V
DD
LVRX
+ V
for only one CPU cycle to bring the MCU out of reset. See
LVHX
rises above a voltage, V
DD
LVRX
+ V
LVHX
.
14.3.2.6 Low-Voltage Inhibit (LVI) Reset. The output of the comparator controls the state of the LVIOUT
flag in the LVI status register (LVISCR).
An LVI reset also drives the RST
pin low to provide low-voltage protection to external peripheral devices.
See 19.5 DC Electrical Characteristics.
Addr. Register Name Bit 7654321Bit 0
$FE0F
LVI Status and Control Register
(LVISCR)
See page 99.
Read: LVIOUT 0
Write:RR RRRRR
Reset:00000000
=Reserved
R
TRPSEL
00000
Figure 9-2. LVI I/O Register Summary

9.3.1 Polled LVI Operation

In applications that can operate at VDD levels below V LVIOUT bit. In the configuration register, the LVIPWR bit must be 1 to enable the LVI module, and the LVIRST bit must be 0 to disable LVI resets. See Chapter 5 Configuration Register (CONFIG). TRPSEL in the LVISCR selects V
LVRX
.
, software can monitor VDD by polling the
LVRX

9.3.2 Forced Reset Operation

In applications that require VDD to remain above V reset the MCU when V
falls to the V
DD
level and remains at or below that level for nine or more
LVRX
consecutive CPU cycles. In the CONFIG register, the LVIPWR and LVIRST bits must be 1s to enable the LVI module and to enable LVI resets. TRPSEL in the LVISCR selects V
, enabling LVI resets allows the LVI module to
LVRX
.
LVRX

9.3.3 False Reset Protection

The VDD pin level is digitally filtered to reduce false resets due to power supply noise. In order for the LVI module to reset the MCU, V V
must be above V
DD
LVISCR selects V
LVRX
LVRX
+ V
must remain at or below V
DD
+ V
LVHX
for only one CPU cycle to bring the MCU out of reset. TRPSEL in the
LVHX
.
for nine or more consecutive CPU cycles.
LVRX

9.3.4 LVI Trip Selection

The TRPSEL bit allows the user to chose between 5 percent and 10 percent tolerance when monitoring the supply voltage. The 10 percent option is enabled out of reset. Writing a 1 to TRPSEL will enable 5 percent option.
NOTE
The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (VLVR1 or VLVR2) may be lower than this. See 19.5 DC
Electrical Characteristics.
98 Freescale Semiconductor

9.4 LVI Status and Control Register

LVI Status and Control Register
The LVI status register (LVISCR) flags VDD voltages below the V
Address: $FE0F
Bit 7654321Bit 0
Read: LVIOUT 0
Write:RR RRRRR
Reset:00000000
=Reserved
R
TRPSEL
00000
Figure 9-3. LVI Status and Control Register (LVISCR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V
voltage falls below the V
DD
CGMXCLK cycles. See Table 9-1. Reset clears the LVIOUT bit.
Table 9-1. LVIOUT Bit Indication
V
DD
At Level: For Number of CGMXCLK Cycles:
V
LV RX
> V
V
DD
VDD < V
VDD < V
V
< VDD < V
DD
LV RX
< V
+ V
LV RX
LV RX
LV RX
LV RX
LV HX
+ V
LV HX
Any 0
< 32 CGMXCLK cycles 0
Between 32 & 40 CGMXCLK cycles 0 or 1
> 40 CGMXCLK cycles 1
Any Previous value
LVRX
level.
voltage for 32 to 40
LVRX
LVIOUT
TRPSEL — LVI Trip Select Bit
This bit selects the LVI trip point. Reset clears this bit.
1 = 5 percent tolerance. The trip point and recovery point are determined by V
LVR1
and V
LVH1
,
respectively.
0 = 10 percent tolerance. The trip point and recovery point are determined by V
LVR2
and V
LVH2
,
respectively.
NOTE
If LVIRST and LVIPWR are 0s, note that when changing the tolerance, LVI reset will be generated if the supply voltage is below the trip point.

9.5 LVI Interrupts

The LVI module does not generate interrupt requests.

9.6 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode.
With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT instruction.
Freescale Semiconductor 99
Low-Voltage Inhibit (LVI)
With the LVIRST bit in the configuration register programmed to 1, the LVI module can generate a reset and bring the MCU out of wait mode.

9.7 Stop Mode

If enabled, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
100 Freescale Semiconductor
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