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MC68HC08KH12
User Manual
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Freescale Semiconductor MC68HC08KH12 User Manual

MC68HC08KH12 Data Sheet
M68HC08 Microcontrollers
Rev. 1.1 MC68HC08KH12/H July 15, 2005
freescale.com
Advance Information — MC68HC(7)08KH12
Section 1. General Description .......................................23
Section 2. Memory Map ...................................................33
Section 3. Random-Access Memory (RAM) ...................45
Section 4. Read-Only Memory (ROM) .............................47
Section 5. Configuration Register (CONFIG) .................49
Section 6. Central Processor Unit (CPU) .......................51
Section 7. System Integration Module (SIM) .................61

List of Sections

Section 8. Clock Generator Module (CGM) ....................87
Section 9. Universal Serial Bus Module (USB) ............113
Section 10. Monitor ROM (MON) ...................................149
Section 11. Timer Interface Module (TIM) ....................161
Section 12. I/O Ports ......................................................183
Section 13. Computer Operating Properly (COP) .......207
Section 14. External Interrupt (IRQ) .............................213
Section 15. Keyboard Interrupt Module (KBI) ..............219
Section 16. Break Module (BREAK) .............................241
Section 17. Preliminary Electrical Specifications .......247
Section 18. Mechanical Specifications ........................259
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Advance Information MC68HC(7)08KH12 — Rev. 1.1
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Advance Information — MC68HC(7)08KH12

General Description

1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.1 Quad Flat Pack (QFP) Package . . . . . . . . . . . . . . . . . . . . .28
1.5.2 Power Supply Pins (V
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .30
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.5 External Interrupt Pin (IRQ1/VPP) . . . . . . . . . . . . . . . . . . . .30
1.5.6 USB Data Pins
(DPLUS0–DPLUS4 and DMINUS0–DMINUS4). . . . . . .30
1.5.7 Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . .30
1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . .31
1.5.9 Port B I/O Pins (PTB7–PTB0). . . . . . . . . . . . . . . . . . . . . . .31
1.5.10 Port C I/O Pins (PTC4–PTC0). . . . . . . . . . . . . . . . . . . . . . .31
1.5.11 Port D I/O Pins (PTD7/KBD7–PTD0/KBD0) . . . . . . . . . . . .31
1.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK). . . . . . . . . . . . .31
1.5.13 Port F I/O Pins (PTF7/KBF7–PTF0/KBF0) . . . . . . . . . . . . .32
DDA
, V
SSA
, V
DD1
, V
SS1

Table of Contents

, V
DD2
, and V
) . . . . . . . . . .29
SS2

Section 2. Memory Map

2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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2.3 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.4 Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Section 3. Random-Access Memory (RAM)

3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Section 4. Read-Only Memory (ROM)

4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
5.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Section 5. Configuration Register (CONFIG)

Section 6. Central Processor Unit (CPU)

6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.4.1 Accumulator (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6.4.2 Index Register (H:X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6.4.3 Stack Pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6.4.4 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6.4.5 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . .57
6.5 Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . .59
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Section 7. System Integration Module (SIM)

7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
7.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . .65
7.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . .66
7.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . .66
7.4 Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . .66
7.4.1 External Pin Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7.4.2 Active Resets from Internal Sources. . . . . . . . . . . . . . . . . .67
7.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.4.2.2 Computer Operating Properly (COP) Reset. . . . . . . . . . .69
7.4.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.2.4 Illegal Address Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . .70
7.4.2.5 Universal Serial Bus Reset . . . . . . . . . . . . . . . . . . . . . . .70
7.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
7.5.1 SIM Counter During Power-On Reset. . . . . . . . . . . . . . . . .71
7.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . .71
7.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . .71
7.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
7.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7.6.1.2 SWI Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.6.2.1 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . .77
7.6.2.2 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . .78
7.6.2.3 Interrupt Status Register 3. . . . . . . . . . . . . . . . . . . . . . . .78
7.6.3 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.6.4 Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.6.5 Status Flag Protection in Break Mode. . . . . . . . . . . . . . . . .79
7.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
7.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7.7.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
7.8 SIM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
7.8.1 Break Status Register (BSR). . . . . . . . . . . . . . . . . . . . . . . .83
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7.8.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . .84
7.8.3 Break Flag Control Register (BFCR). . . . . . . . . . . . . . . . . .85

Section 8. Clock Generator Module (CGM)

8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
8.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
8.4.1 Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.4.2 Phase-Locked Loop Circuit (PLL) . . . . . . . . . . . . . . . . . . . .91
8.4.3 PLL Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
8.4.4 Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . .93
8.4.5 Manual and Automatic PLL Bandwidth Modes . . . . . . . . . .93
8.4.6 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
8.4.7 Special Programming Exceptions . . . . . . . . . . . . . . . . . . . .95
8.4.8 Base Clock Selector Circuit. . . . . . . . . . . . . . . . . . . . . . . . .96
8.4.9 CGM External Connections. . . . . . . . . . . . . . . . . . . . . . . . .96
8.5 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
8.5.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . .98
8.5.2 Crystal Amplifier Output Pin (OSC2). . . . . . . . . . . . . . . . . .98
8.5.3 External Filter Capacitor Pin (CGMXFC). . . . . . . . . . . . . . .98
8.5.4 PLL Analog Power Pin (V
8.5.5 PLL Analog Ground Pin (V
) . . . . . . . . . . . . . . . . . . . . . .98
DDA
). . . . . . . . . . . . . . . . . . . . . .98
SSA
8.5.6 Buffered Crystal Clock Output (CGMVOUT). . . . . . . . . . . .99
8.5.7 CGMVSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8.5.8 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . .99
8.5.9 Crystal Output Frequency Signal (CGMXCLK). . . . . . . . . .99
8.5.10 CGM Base Clock Output (CGMOUT) . . . . . . . . . . . . . . . . .99
8.5.11 CGM CPU Interrupt (CGMINT) . . . . . . . . . . . . . . . . . . . . . .99
8.6 CGM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
8.6.1 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . .102
8.6.2 PLL Bandwidth Control Register (PBWC). . . . . . . . . . . . .104
8.6.3 PLL Multiplier Select Registers (PMSH:PMSL). . . . . . . . .105
8.6.4 PLL Reference Divider Select Register (PRDS) . . . . . . . .106
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8.7 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.8 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.8.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.8.2 CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .108
8.9 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .108
8.9.1 Acquisition/Lock Time Definitions . . . . . . . . . . . . . . . . . . .108
8.9.2 Parametric Influences on Reaction Time . . . . . . . . . . . . .109
8.9.3 Choosing a Filter Capacitor. . . . . . . . . . . . . . . . . . . . . . . .111
8.9.4 Reaction Time Calculation . . . . . . . . . . . . . . . . . . . . . . . .111

Section 9. Universal Serial Bus Module (USB)

9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.3 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.4 I/O Register Description of the HUB function . . . . . . . . . . . . .116
9.4.1 USB HUB Root Port Control Register (HRPCR). . . . . . . .120
9.4.2 USB HUB Downstream Port Control Register
(HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . .121
9.4.3 USB SIE Timing Interrupt Register (SIETIR). . . . . . . . . . .123
9.4.4 USB SIE Timing Status Register (SIETSR) . . . . . . . . . . .125
9.4.5 USB HUB Address Register (HADDR) . . . . . . . . . . . . . . .127
9.4.6 USB HUB Interrupt Register 0 (HIR0). . . . . . . . . . . . . . . .128
9.4.7 USB HUB Control Register 0 (HCR0). . . . . . . . . . . . . . . .129
9.4.8 USB HUB Endpoint1 Control & Data Register (HCDR) . .131
9.4.9 USB HUB Status Register (HSR) . . . . . . . . . . . . . . . . . . .132
9.4.10 USB HUB Endpoint 0 Data Registers 0-7
(HE0D0-HE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
9.5 I/O Register Description of the Embedded Device Function .134
9.5.1 USB Embedded Device Address Register (DADDR) . . . .138
9.5.2 USB Embedded Device Interrupt Register 0 (DIR0). . . . .138
9.5.3 USB Embedded Device Interrupt Register 1 (DIR1). . . . .140
9.5.4 USB Embedded Device Control Register 0 (DCR0) . . . . .141
9.5.5 USB Embedded Device Control Register 1 (DCR1) . . . . .143
9.5.6 USB Embedded Device Status Register (DSR) . . . . . . . .144
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9.5.7 USB Embedded Device Control Register 2 (DCR2) . . . . .146
9.5.8 USB Embedded Device Endpoint 0 Data Registers
(DE0D0-DE0D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9.5.9 USB Embedded Device Endpoint 1/2 Data Registers
(DE1D0-DE1D7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Section 10. Monitor ROM (MON)

10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
10.4.1 Entering Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .152
10.4.2 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10.4.3 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10.4.4 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.4.5 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
10.4.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

Section 11. Timer Interface Module (TIM)

11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
11.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11.4.2 Input Capture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165
11.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . .166
11.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . .166
11.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . .167
11.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . .168
11.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . .169
11.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
11.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
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11.6 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171
11.7 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .172
11.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
11.8.1 TIM Clock Pin (PTE0/TCLK) . . . . . . . . . . . . . . . . . . . . . . .172
11.8.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1). . . . . . .173
11.9 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
11.9.1 TIM Status and Control Register (TSC) . . . . . . . . . . . . . .173
11.9.2 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . .175
11.9.3 TIM Counter Modulo Registers (TMODH:TMODL). . . . . .176
11.9.4 TIM Channel Status and Control Registers (TSC0:TSC1) 177
11.9.5 TIM Channel Registers (TCH0H/L–TCH1H/L) . . . . . . . . .181

Section 12. I/O Ports

12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184
12.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186
12.3.1 Port A Data Register (PTA). . . . . . . . . . . . . . . . . . . . . . . .186
12.3.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . .186
12.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188
12.4.1 Port B Data Register (PTB). . . . . . . . . . . . . . . . . . . . . . . .188
12.4.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . .189
12.5 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190
12.5.1 Port C Data Register (PTC). . . . . . . . . . . . . . . . . . . . . . . .190
12.5.2 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . .191
12.6 Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12.6.1 Port D Data Register (PTD). . . . . . . . . . . . . . . . . . . . . . . .193
12.6.2 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . .193
12.7 Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195
12.7.1 Port E Data Register (PTE). . . . . . . . . . . . . . . . . . . . . . . .195
12.7.2 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . .196
12.7.3 Port-E Optical Interface Enable Register . . . . . . . . . . . . .198
12.8 Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
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12.8.1 Port F Data Register (PTF) . . . . . . . . . . . . . . . . . . . . . . . .202
12.8.2 Data Direction Register F (DDRF). . . . . . . . . . . . . . . . . . .203
12.9 Port Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204
12.9.1 Port Option Control Register (POC) . . . . . . . . . . . . . . . . .204

Section 13. Computer Operating Properly (COP)

13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
13.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
13.4 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
13.4.1 CGMXCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
13.4.2 COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
13.4.3 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
13.4.4 Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
13.4.5 Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
13.4.6 COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
13.4.7 COPRS (COP Rate Select). . . . . . . . . . . . . . . . . . . . . . . .210
13.5 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .211
13.6 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.7 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
13.8 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.8.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.8.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .212
13.9 COP Module During Break Mode. . . . . . . . . . . . . . . . . . . . . .212

Section 14. External Interrupt (IRQ)

14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
14.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214
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14.4.1 IRQ1/VPP Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215
14.5 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .217
14.6 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .217

Section 15. Keyboard Interrupt Module (KBI)

15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
15.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220
15.4 Port-D Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . .222
15.4.1 Port-D Keyboard Interrupt Functional Description. . . . . . .223
15.4.2 Port-D Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . .224
15.4.3 Port-D Keyboard Interrupt Registers. . . . . . . . . . . . . . . . .225
15.4.3.1 Port-D Keyboard Status and Control Register: . . . . . . .225
15.4.3.2 Port-D Keyboard Interrupt Enable Register . . . . . . . . . .226
15.5 Port-E Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . .228
15.5.1 Port-E Keyboard Interrupt Functional Description. . . . . . .229
15.5.2 Port-E Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . .230
15.5.3 Port-E Keyboard Interrupt Registers. . . . . . . . . . . . . . . . .231
15.5.3.1 Port-E Keyboard Status and Control Register . . . . . . . .231
15.5.3.2 Port-E Keyboard Interrupt Enable Register . . . . . . . . . .232
15.6 Port-F Keyboard Interrupt Block Diagram. . . . . . . . . . . . . . . .234
15.6.1 Port-F Keyboard Interrupt Functional Description. . . . . . .235
15.6.2 Port-F Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . .236
15.6.3 Port-F Keyboard Interrupt Registers . . . . . . . . . . . . . . . . .237
15.6.3.1 Port-F Keyboard Status and Control Register . . . . . . . .237
15.6.3.2 Port-F Keyboard Interrupt Enable Register . . . . . . . . . .238
15.6.3.3 Port-F Pull-up Enable Register . . . . . . . . . . . . . . . . . . .239
15.7 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.8 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239
15.9 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .239
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Section 16. Break Module (BREAK)

16.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
16.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241
16.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242
16.4.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . .244
16.4.2 CPU During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . .244
16.4.3 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . .244
16.4.4 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . .244
16.5 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.1 Break Status and Control Register (BRKSCR) . . . . . . . . .245
16.5.2 Break Address Registers (BRKH and BRKL) . . . . . . . . . .245
16.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
16.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
16.6.2 Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

Section 17. Preliminary Electrical Specifications

17.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
17.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .248
17.4 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . .249
17.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
17.6 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .250
17.7 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
17.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
17.9 USB DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . .252
17.10 USB Low Speed Source Electrical Characteristics. . . . . . . . .253
17.11 USB High Speed Source Electrical Characteristics . . . . . . . .254
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17.12 HUB Repeater Electrical Characteristics . . . . . . . . . . . . . . . .255
17.13 USB Signaling Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256
17.14 TImer Interface Module Characteristics . . . . . . . . . . . . . . . . .256
17.15 Clock Generation Module Characteristics . . . . . . . . . . . . . . .257
17.15.1 CGM Component Specifications. . . . . . . . . . . . . . . . . . . .257
17.15.2 CGM Electrical Specifications. . . . . . . . . . . . . . . . . . . . . .257
17.15.3 Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . .258

Section 18. Mechanical Specifications

18.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
18.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
18.3 Plastic Quad Flat Pack (QFP). . . . . . . . . . . . . . . . . . . . . . . . .260
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1-1 MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1-2 64-Pin QFP Assignments (Top View). . . . . . . . . . . . . . . . . . . .28
1-3 Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2-1 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2-2 Control, Status, and Data Registers. . . . . . . . . . . . . . . . . . . . .36
5-1 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . . .50
6-1 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
6-3 Index Register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
6-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
6-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
6-6 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . . . .57

List of Figures

7-1 SIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7-2 SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . .64
7-3 SIM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
7-4 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
7-5 Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7-6 Sources of Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7-7 POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
7-8 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
7-9 Interrupt Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
7-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . .75
7-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .77
7-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .78
7-14 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .78
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7-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
7-16 Wait Recovery from Interrupt or Break. . . . . . . . . . . . . . . . . . .81
7-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . .81
7-18 Stop Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
7-19 Stop Mode Recovery from Interrupt or Break. . . . . . . . . . . . . .82
7-20 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . .83
7-21 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . .84
7-22 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . .85
8-1 CGM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
8-2 CGM External Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .97
8-3 PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . .102
8-4 PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . .104
8-5 PLL Multiplier Select Registers (PMSH:PMSL) . . . . . . . . . . .105
8-6 PLL Reference Divider Select Register (PRDS). . . . . . . . . . .106
9-2 USB HUB Root Port Control Register (HRPCR) . . . . . . . . . .120
9-3 USB HUB Downstream Port Control Registers
(HDP1CR-HDP4CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9-4 USB SIE Timing Interrupt Register (SIETIR) . . . . . . . . . . . . .123
9-5 USB SIE Timing Status Register (SIETSR) . . . . . . . . . . . . . .125
9-6 USB HUB Address Register (HADDR). . . . . . . . . . . . . . . . . .127
9-7 USB HUB Interrupt Register 0 (HIR0) . . . . . . . . . . . . . . . . . .128
9-8 USB HUB Control Register 0 (HCR0). . . . . . . . . . . . . . . . . . .129
9-9 USB HUB Control Register 1 (HCR1). . . . . . . . . . . . . . . . . . .131
9-10 USB HUB Status Register (HSR). . . . . . . . . . . . . . . . . . . . . .132
9-11 USB HUB Endpoint 0 Data Register (HE0D0-HE0D7). . . . . .134
9-12 USB Embedded Device Address Register (DADDR). . . . . . .138
9-13 USB Embedded Device Interrupt Register 0 (DIR0). . . . . . . .138
9-14 USB Embedded Device Interrupt Register 1 (DIR1). . . . . . . .140
9-15 USB Embedded Device Control Register 0 (DCR0). . . . . . . .141
9-16 USB Embedded Device Control Register 1 (DCR1). . . . . . . .143
9-17 USB Embedded Device Status Register (DSR) . . . . . . . . . . .144
9-18 USB Embedded Device Control Register 2 (DCR2). . . . . . . .146
9-19 USB Embedded Device Endpoint 0 Data Register
(UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
9-1 USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
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9-20 USB Embedded Device Endpoint 0 Data Register
(UE0D0-UE0D7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
10-1 Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
10-2 Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10-3 Sample Monitor Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .154
10-4 Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
10-5 Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
11-1 TIM Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
11-2 PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . .168
11-3 TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . .174
11-4 TIM Counter Registers (TCNTH:TCNTL) . . . . . . . . . . . . . . . .176
11-5 TIM Counter Modulo Registers (TMODH:TMODL). . . . . . . . .177
11-6 TIM Channel Status and Control Registers (TSC0:TSC1) . . .178
11-7 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11-8 TIM Channel Registers (TCH0H/L:TCH1H/L). . . . . . . . . . . . .182
12-1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .186
12-2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . .187
12-3 Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187
12-4 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .188
12-5 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . .189
12-6 Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189
12-7 Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .190
12-8 Data Direction Register C (DDRC). . . . . . . . . . . . . . . . . . . . .191
12-9 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192
12-10 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .193
12-11 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . .194
12-12 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194
12-13 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .195
12-14 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . .197
12-15 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197
12-16 Optical Interface Enable Register E (EOIER). . . . . . . . . . . . .198
12-17 Optical Interface Voltage References. . . . . . . . . . . . . . . . . . .200
12-18 Port E Optical Coupling Interface. . . . . . . . . . . . . . . . . . . . . .201
12-19 Port F Data Register (PTF). . . . . . . . . . . . . . . . . . . . . . . . . . .202
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12-20 Data Direction Register F (DDRF) . . . . . . . . . . . . . . . . . . . . .203
12-21 Port F I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
12-22 Port Option Control Register (POC). . . . . . . . . . . . . . . . . . . .204
13-1 COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
13-2 Configuration Register (CONFIG). . . . . . . . . . . . . . . . . . . . . .210
13-3 COP Control Register (COPCTL). . . . . . . . . . . . . . . . . . . . . .211
14-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .215
14-2 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . . . .217
15-1 Port-D Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . .222
15-2 Port-D Keyboard Status and Control Register (KBDSCR) . . .225
15-3 Port-D Keyboard Interrupt Enable Register (KBDIER). . . . . .226
15-4 Port-E Keyboard Interrupt Block Diagram . . . . . . . . . . . . . . .228
15-5 Port-E Keyboard Status and Control Register (KBESCR) . . .231
15-6 Port-E Keyboard Interrupt Enable Register (KBEIER) . . . . . .232
15-7 Port-F Keyboard Interrupt Block Diagram. . . . . . . . . . . . . . . .234
15-8 Port-F Keyboard Status and Control Register (KBFSCR) . . .237
15-9 Port-F Keyboard Interrupt Enable Register (KBFIER) . . . . . .238
15-10 Port F Pull-up Enable Register (PFPER) . . . . . . . . . . . . . . . .239
16-1 Break Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . .243
16-2 Break Status and Control Register (BRKSCR). . . . . . . . . . . .245
16-3 Break Address Registers (BRKH and BRKL). . . . . . . . . . . . .246
18-1 64-Pin Quad-Flat-Pack (Case 840C-04). . . . . . . . . . . . . . . . .260
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Advance Information — MC68HC(7)08KH12
Table Title Page
2-1 Vector Addresses .....................................................................43
7-1 Signal Name Conventions........................................................65
7-2 PIN Bit Set Timing ....................................................................67
7-3 Interrupt Sources......................................................................76
7-4 SIM Registers...........................................................................83
8-1 CGM Numeric Example............................................................95
8-2 CGM I/O Register Summary...................................................101
8-3 PRE[1:0] Programming...........................................................104

List of Tables

9-1 HUB Control Register Summary.............................................117
9-2 HUB Data Register Summary.................................................119
9-3 Embedded Device Control Register Summary.......................135
9-4 Embedded Device Data Register Summary...........................136
10-1 Mode Selection ......................................................................152
10-2 Mode Differences....................................................................153
10-3 READ (Read Memory) Command..........................................156
10-4 WRITE (Write Memory) Command.........................................156
10-5 IREAD (Indexed Read) Command .........................................157
10-6 IWRITE (Indexed Write) Command........................................157
10-7 READSP (Read Stack Pointer) Command.............................158
10-8 RUN (Run User Program) Command.....................................158
10-9 Monitor Baud Rate Selection..................................................159
11-1 TIM I/O Register Summary.....................................................164
11-2 Prescaler Selection.................................................................175
11-3 Mode, Edge, and Level Selection...........................................180
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Table Title Page
12-1 I/O Port Register Summary.....................................................184
12-2 Port A Pin Functions...............................................................188
12-3 Port B Pin Functions...............................................................190
12-4 Port C Pin Functions...............................................................192
12-5 Port D Pin Functions...............................................................195
12-6 Port E Pin Functions...............................................................198
12-7 Port F Pin Functions...............................................................204
13-1 COP I/O Port Register Summary............................................208
14-1 IRQ I/O Port Register Summary.............................................215
15-1 KBI I/O Register Summary .....................................................221
16-1 Break I/O Register Summary..................................................243
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22 Freescale Semiconductor
Advance Information — MC68HC(7)08KH12

Section 1. General Description

1.1 Contents

1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
1.5.1 Quad Flat Pack (QFP) Package . . . . . . . . . . . . . . . . . . . . .28
1.5.2 Power Supply Pins
(V
1.5.3 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . .30
1.5.4 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.5 External Interrupt Pin (IRQ1/VPP) . . . . . . . . . . . . . . . . . . . .30
1.5.6 USB Data Pins
(DPLUS0–DPLUS4 and DMINUS0–DMINUS4). . . . . . .30
1.5.7 Voltage Regulator Out (REGOUT) . . . . . . . . . . . . . . . . . . .30
1.5.8 Port A Input/Output (I/O) Pins (PTA7–PTA0) . . . . . . . . . . .31
1.5.9 Port B I/O Pins (PTB7–PTB0). . . . . . . . . . . . . . . . . . . . . . .31
1.5.10 Port C I/O Pins (PTC4–PTC0). . . . . . . . . . . . . . . . . . . . . . .31
1.5.11 Port D I/O Pins (PTD7/KBD7–PTD0/KBD0) . . . . . . . . . . . .31
1.5.12 Port E I/O Pins (PTE4, PTE3/KBE3, PTE2/KBE2/TCH1,
PTE1/KBE1/TCH0, PTE0/KBE0/TCLK). . . . . . . . . . . . .31
1.5.13 Port F I/O Pins (PTF7/KBF7–PTF0/KBF0) . . . . . . . . . . . . .32
DDA
, V
SSA
, V
DD1
, V
SS1
, V
DD2
, and V
) . . . . . . . . . .29
SS2
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1.2 Introduction

1.3 Features

The MC68HC(7)08KH12 is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
Features of the MC68HC(7)08KH12 include the following:
• High-Performance M68HC08 Architecture
• Fully Upward-Compatible Object Code with M6805, M146805, and M68HC05 Families
• 6 MHz Internal Bus Operation
• Low-Power Design (Fully Static with Stop and Wait Modes)
• 12 KBytes of User ROM (MC68HC08KH12) or One-Time Programmable (OTP) ROM (MC68HC708KH12)
• On-Chip Programming Firmware for Use with Host Personal Computer
• ROM/OTPROM Data Security
1
• 384 Bytes of On-Chip Random Access Memory (RAM)
• 42 General Purpose I/O, 29 with Software Configurable Pullups
• 16-Bit, 2-Channel Timer Interface Module (TIM)
• 20-Bit Keyboard Interrupt Port
• 5 LED Direct Drive Port Pins
• 48MHz Phase-Locked Loop
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the ROM/OTPROM difficult for unauthorized users.
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24 Freescale Semiconductor
• Full Universal Serial Bus Specification 1.1 Composite HUB with Embedded1 Functions:
–1 × 12MHz Upstream Port –4 × 12MHz/1.5MHz Downstream Ports –1 × Hub Control Endpoint (Endpoint0) with 8 byte transmit
buffer and 8 byte receive buffer
–1 × Hub Interrupt Endpoint (Endpoint1) with 1 byte transmit
buffer
–1 × Device Control Endpoint (Endpoint0) with 8 byte transmit
buffer and 8 byte receive buffer
– D evice Interrupt Endpoints (Endpoint1 and Endpoint2) share
with 8 byte transmit buffer
• On-chip 3.3V regulator for USB Transceiver
• System Protection Features – Optional Computer Operating Properly (COP) Reset – Illegal Opcode Detection with Optional Reset – Illegal Address Detection with Optional Reset
• Master Reset Pin with Internal Pullup and Power-On Reset
• An External Asynchronous Interrupt Pin with Internal Pullup (IRQ1)
• 64-pin plastic quad flatpack (QFP) package
1. Embedded device supports only bulk and interrupt transfers, and does not support isochronous transfers.
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1.4 MCU Block Diagram

Features of the CPU08 include the following:
• Enhanced HC05 Programming Model
• Extensive Loop Control Functions
• 16 Addressing Modes (Eight More Than the HC05)
• 16-Bit Index Register and Stack Pointer
• Memory-to-Memory Data Transfers
• Fast 8 × 8 Multiply Instruction
• Fast 16/8 Divide Instruction
• Binary-Coded Decimal (BCD) Instructions
• Optimization for Controller Applications
• Third Party C Language Support
Figure 1-1 shows the structure of the MC68HC(7)08KH12.
Advance Information MC68HC(7)08KH12 — Rev. 1.1
26 Freescale Semiconductor
Freescale Semiconductor
MC68HC(7)08KH12 — Rev. 1.1 Advance Information
PTD7/KBD7– PTD0/KBD0
PTE3/KBE3– PTE0/KBE0
PTF7/KBF7– PTF0/KBF0
DPLUS4
DMINUS4
DPLUS3
DMINUS3
DPLUS2
DMINUS2
DPLUS1
DMINUS1
DPLUS0
DMINUS0
PTE4
➀➃➅
➀➃
PTC4–PTC0
➄
DS Port 4
DS Port 3
DS Port 2
DS Port 1
PORT D
PORT E
PORT F
US Port
DDRD
DDRE
DDRF
PORT C
DDRC
Embedded USB Function 384 bytes RAM 12k-bytes ROM/OTPROM
➀➁
CPU CONTROL ALU
CPU REGISTERS
CONDITION CODE REGISTER
PTB7–PTB0
PORT B
68HC08 CPU
STACK POINTER
PROGRAM COUNTER
➀
DDRB
ACCUMULATOR
INDEX REGISTER
V11H I NZ C
PTA7–PTA0
PORT A
DDRA
POWER SUPPLY
AND
VOLTAGE REGULATION
CLOCK GENERATION
MODULE AND PLL
SYSTEM INTEGRATION
MODULE
IRQ MODULE
BREAK MODULE
POWER-ON RESET
MODULE
TIMER INTERFACE
MODULE
VDD1
VSS1
VDD2
VSS2
REGOUT
OSC2 OSC1
VDDA VSSA CGMXFC
➂
RST
IRQ1/VPP
TCLK/PTE0
TCH0/PTE1 TCH1/PTE2
➂➃
27
➀ PORTS ARE SOFTWARE CONFIGURABLE WITH PULLUP DEVICE IF INPUT PORT ➁ SOFTWARE CONFIGURABLE LED DIRECT DRIVE 3mA SOURCE /10mA SINK or STANDARD DRIVE ➂ PIN CONTAINS INTEGRATED PULLUP DEVICE ➃ PIN HAS INTERRUPT CAPABILITY ➄ PIN HAS INTERRUPT AND INTEGRATED PULLUP DEVICE. ➅ PIN HAS OPTICAL COUPLING INTERFACE
Figure 1-1. MCU Block Diagram
COP MODULE
MONITOR ROM
240 bytes

1.5 Pin Assignments

1.5.1 Quad Flat Pack (QFP) Package

Figure 1-2 Shows the 64-pin QFP assignments.
PTF0/KBF0
RST
IRQ1/VPP
64
63
VDDA
CGMXFC
OSC1
OSC2
VSSA
REGOUT
DPLUS0
DMINUS0
DPLUS1
DMINUS1
DPLUS2
DMINUS2
DPLUS3
DMINUS3
DPLUS4
DMINUS4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
62
18
19
PTF5/KBF5
PTF4/KBF4
PTF3/KBF3
PTF2/KBF2
PTF1/KBF1
61
60
59
58
57
68HC(7)08KH12
20
21
22
23
24
PTF6/KBF6
PTF7/KBF7
56
55
25
VSS2
VDD2
PTA7
PTA6
PTA5
PTA4
54
53
52
51
26
27
28
30
29
49
50
48
47
46
45
44
42
42
41
40
39
38
37
36
35
34
33
31
32
PTA3
PTA2
PTA1
PTA0
PTB7
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
PTD7/KBD7
PTD6/KBD6
PTD5/KBD5
PTD4/KBD4
PTE4
VSS1
PTE3/KBE3
PTE0/KBE0/TCLK
PTE1/KBE1/TCH0
PTE2/KBE2/TCH1
VDD1
PTC0
PTC1
PTC2
PTC3
PTC4
PTD0/KBD0
PTD1/KBD1
PTD2/KBD2
PTD3/KBD3
Figure 1-2. 64-Pin QFP Assignments (Top View)
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28 Freescale Semiconductor
1.5.2 Power Supply Pins (V
V
DDA
the on-chip Phase-Locked Loop circuit. V
DD2
internal circuitry of the chip. V
DD1
The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as Figure 1-3 shows. Place the bypass capacitors as close to the MCU power pins as possible. Use high-frequency-response ceramic capacitors for C C
BULK
that require the port pins to source high current levels.
, V
DDA
and V
and V
and V
, V
SSA
are the analog power supply and ground pins used by
SSA
are the power supply and ground pins used by the
SS2
are the power supply and ground pins to the I/O pads.
SS1
DD1
, V
SS1
, V
DD2
, and V
SS2
)
BYPASS
are optional bulk current bypass capacitors for use in applications
.
V
DDA
C
BYPASS
10nF
NOTE: Values shown are typical values.
V
SSA
Figure 1-3. Power Supply Bypassing
MCU
V
DD2
C
BYPASS
10nF
V
SS2
V
DD2
Vbus
C
BYPASS
10nF
+
C
BULK
V
SS1
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1.5.3 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. (See Section 8. Clock Generator Module (CGM).)

1.5.4 External Reset Pin (RST)

A logic zero on the RST pin forces the MCU to a known start-up state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. The RST pin contains an internal pullup device. ((See Section 7. System Integration Module
(SIM).)

1.5.5 External Interrupt Pin (IRQ1/VPP)

IRQ1/VPP is an asynchronous external interrupt pin. IRQ1/VPP is also the OTPROM programming power pin. The IRQ1/V internal pullup device. (See Section 14. External Interrupt (IRQ).)
pin contain an
PP
1.5.6 USB Data Pins (DPLUS0–DPLUS4 and DMINUS0–DMINUS4)
DPLUS0–DPLUS4 and DMINUS0–DMINUS4 are the differential data lines used by the USB module. (See Section 9. Universal Serial Bus
Module (USB).)

1.5.7 Voltage Regulator Out (REGOUT)

REGOUT is the 3.3V output of the on-chip voltage regulator. It is used to supply the voltage for the external pullup resistor required by the USB on either DPLUS or DMINUS lines, depending on type of USB function. REGOUT is also used internally for the USB data driver and the Phase­locked Loop circuit. The REGOUT pin requires an external bulk capacitor 1µF or larger and a bypass capacitor. (See Section 9.
Universal Serial Bus Module (USB).)
Advance Information MC68HC(7)08KH12 — Rev. 1.1
30 Freescale Semiconductor
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