Freescale Semiconductor MC68332 User Manual
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© Freescale Semiconductor, Inc., 2004. All rights reserved.
M68300 Family
MC68332
User’s Manual
© MOTOROLA, INC. 1995
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TABLE OF CONTENTS
Paragraph Title Page
SECTION 1 INTRODUCTION
SECTION 2NOMENCLATURE
2.1 Symbols and Operators .................................................................................. 2-1
2.2 CPU32 Registers ............................................................................................ 2-2
2.3 Pin and Signal Mnemonics ............................................................................. 2-3
2.4 Register Mnemonics ....................................................................................... 2-4
2.5 Conventions ................................................................................................... 2-5
SECTION 3OVERVIEW
3.1 MC68332 Features ......................................................................................... 3-1
3.1.1 System Integration Module (SIM) ...........................................................3-1
3.1.2 Central Processing Unit (CPU) ............................................................... 3-1
3.1.3 Time Processor Unit (TPU) .................................................................... 3-1
3.1.4 Queued Serial Module (QSM) ................................................................ 3-2
3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM) ............. 3-2
3.2 System Block Diagram and Pin Assignment Diagrams .................................. 3-2
3.3 Pin Descriptions .............................................................................................3-5
3.4 Signal Descriptions ......................................................................................... 3-7
3.5 Intermodule Bus ............................................................................................. 3-9
3.6 System Memory Map .....................................................................................3-9
3.6.1 Internal Register Map ........................................................................... 3-10
3.6.2 Address Space Maps ...........................................................................3-10
3.7 System Reset ...............................................................................................3-15
3.7.1 SIM Reset Mode Selection ...................................................................3-15
3.7.2 MCU Module Pin Function During Reset .............................................3-16
SECTION 4 SYSTEM INTEGRATION MODULE
4.1 General ........................................................................................................... 4-1
4.2 System Configuration and Protection ............................................................. 4-2
4.2.1 Module Mapping .....................................................................................4-3
4.2.2 Interrupt Arbitration ................................................................................. 4-3
4.2.3 Show Internal Cycles .............................................................................. 4-4
4.2.4 Factory Test Mode .................................................................................4-4
4.2.5 Register Access .....................................................................................4-4
4.2.6 Reset Status ...........................................................................................4-4
4.2.7 Bus Monitor ............................................................................................ 4-5
4.2.8 Halt Monitor ............................................................................................ 4-5
4.2.9 Spurious Interrupt Monitor ......................................................................4-5
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4.2.10 Software Watchdog ................................................................................ 4-5
4.2.11 Periodic Interrupt Timer ..........................................................................4-7
4.2.12 Low-Power Stop Operation .................................................................... 4-8
4.2.13 Freeze Operation ...................................................................................4-9
4.3 System Clock .................................................................................................4-9
4.3.1 Clock Sources ...................................................................................... 4-10
4.3.2 Clock Synthesizer Operation ................................................................4-10
4.3.3 External Bus Clock ............................................................................... 4-15
4.3.4 Low-Power Operation ........................................................................... 4-15
4.3.5 Loss of Reference Signal .....................................................................4-16
4.4 External Bus Interface .................................................................................. 4-17
4.4.1 Bus Signals ..........................................................................................4-18
4.4.1.1 Address Bus ................................................................................. 4-18
4.4.1.2 Address Strobe ............................................................................4-18
4.4.1.3 Data Bus ......................................................................................4-18
4.4.1.4 Data Strobe ..................................................................................4-18
4.4.1.5 Read/Write Signal ........................................................................ 4-18
4.4.1.6 Size Signals .................................................................................4-19
4.4.1.7 Function Codes ............................................................................4-19
4.4.1.8 Data and Size Acknowledge Signals ...........................................4-19
4.4.1.9 Bus Error Signal ...........................................................................4-20
4.4.1.10 Halt Signal .................................................................................... 4-20
4.4.1.11 Autovector Signal .........................................................................4-20
4.4.2 Dynamic Bus Sizing .............................................................................4-20
4.4.3 Operand Alignment ..............................................................................4-21
4.4.4 Misaligned Operands ...........................................................................4-22
4.4.5 Operand Transfer Cases ......................................................................4-22
4.5 Bus Operation ..............................................................................................4-22
4.5.1 Synchronization to CLKOUT ................................................................4-23
4.5.2 Regular Bus Cycles ..............................................................................4-23
4.5.2.1 Read Cycle ................................................................................... 4-24
4.5.2.2 Write Cycle ................................................................................... 4-25
4.5.3 Fast Termination Cycles ....................................................................... 4-26
4.5.4 CPU Space Cycles ...............................................................................4-27
4.5.4.1 Breakpoint Acknowledge Cycle .................................................... 4-28
4.5.4.2 LPSTOP Broadcast Cycle ............................................................ 4-31
4.5.5 Bus Exception Control Cycles .............................................................. 4-31
4.5.5.1 Bus Errors .................................................................................... 4-33
4.5.5.2 Double Bus Faults ........................................................................ 4-33
4.5.5.3 Retry Operation ............................................................................ 4-34
4.5.5.4 Halt Operation ..............................................................................4-34
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4.5.6 External Bus Arbitration ........................................................................ 4-35
4.5.6.1 Slave (Factory Test) Mode Arbitration .........................................4-36
4.5.6.2 Show Cycles ................................................................................4-36
4.6 Reset ............................................................................................................ 4-37
4.6.1 Reset Exception Processing ................................................................4-37
4.6.2 Reset Control Logic ..............................................................................4-38
4.6.3 Reset Mode Selection ..........................................................................4-38
4.6.3.1 Data Bus Mode Selection ............................................................. 4-39
4.6.3.2 Clock Mode Selection ..................................................................4-41
4.6.3.3 Breakpoint Mode Selection .......................................................... 4-41
4.6.4 MCU Module Pin Function During Reset .............................................4-41
4.6.5 Pin State During Reset .........................................................................4-42
4.6.5.1 Reset States of SIM Pins ............................................................. 4-42
4.6.5.2 Reset States of Pins Assigned to Other MCU Modules ...............4-43
4.6.6 Reset Timing ........................................................................................ 4-43
4.6.7 Power-On Reset ...................................................................................4-44
4.6.8 Reset Processing Summary .................................................................4-45
4.6.9 Reset Status Register ..........................................................................4-46
4.7 Interrupts ...................................................................................................... 4-46
4.7.1 Interrupt Exception Processing ............................................................4-46
4.7.2 Interrupt Priority and Recognition .........................................................4-46
4.7.3 Interrupt Acknowledge and Arbitration .................................................4-47
4.7.4 Interrupt Processing Summary .............................................................4-48
4.7.5 Interrupt Acknowledge Bus Cycles ....................................................... 4-49
4.8 Chip Selects ................................................................................................. 4-49
4.8.1 Chip-Select Registers ........................................................................... 4-51
4.8.1.1 Chip-Select Pin Assignment Registers ........................................4-52
4.8.1.2 Chip-Select Base Address Registers ...........................................4-53
4.8.1.3 Chip-Select Option Registers ....................................................... 4-53
4.8.1.4 PORTC Data Register .................................................................. 4-55
4.8.2 Chip-Select Operation .......................................................................... 4-55
4.8.3 Using Chip-Select Signals for Interrupt Acknowledge ..........................4-55
4.8.4 Chip-Select Reset Operation ................................................................ 4-56
4.9 Parallel Input/Output Ports ........................................................................... 4-58
4.9.1 Pin Assignment Registers .................................................................... 4-58
4.9.2 Data Direction Registers ......................................................................4-58
4.9.3 Data Registers ...................................................................................... 4-58
4.10 Factory Test .................................................................................................4-58
SECTION 5 CENTRAL PROCESSING UNIT
5.1 General ........................................................................................................... 5-1
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5.2 CPU32 Registers ............................................................................................ 5-2
5.2.1 Data Registers ........................................................................................ 5-3
5.2.2 Address Registers .................................................................................. 5-5
5.2.3 Program Counter ....................................................................................5-5
5.2.4 Control Registers .................................................................................... 5-5
5.2.4.1 Status Register ............................................................................... 5-5
5.2.4.2 Alternate Function Code Registers ................................................ 5-6
5.2.5 Vector Base Register (VBR) ................................................................... 5-6
5.3 Memory Organization .....................................................................................5-6
5.4 Virtual Memory ............................................................................................... 5-8
5.5 Addressing Modes .......................................................................................... 5-8
5.6 Processing States ..........................................................................................5-8
5.7 Privilege Levels .............................................................................................. 5-9
5.8 Instructions ..................................................................................................... 5-9
5.8.1 M68000 Family Compatibility ............................................................... 5-12
5.8.2 Special Control Instructions .................................................................. 5-13
5.8.2.1 Low Power Stop (LPSTOP) .........................................................5-13
5.8.2.2 Table Lookup and Interpolate (TBL) ............................................5-13
5.9 Exception Processing ................................................................................... 5-13
5.9.1 Exception Vectors ................................................................................5-13
5.9.2 Types of Exceptions ............................................................................. 5-14
5.9.3 Exception Processing Sequence .......................................................... 5-15
5.10 Development Support ................................................................................... 5-15
5.10.1 M68000 Family Development Support ................................................. 5-15
5.10.2 Background Debugging Mode ..............................................................5-16
5.10.2.1 Enabling BDM .............................................................................. 5-17
5.10.2.2 BDM Sources ...............................................................................5-17
5.10.2.3 Entering BDM ............................................................................... 5-18
5.10.2.4 BDM Commands .......................................................................... 5-19
5.10.2.5 Background Mode Registers ........................................................ 5-20
5.10.2.6 Returning from BDM ....................................................................5-20
5.10.2.7 Serial Interface .............................................................................5-20
5.10.3 Recommended BDM Connection .........................................................5-22
5.10.4 Deterministic Opcode Tracking ............................................................ 5-22
5.10.5 On-Chip Breakpoint Hardware ............................................................. 5-23
5.11 Loop Mode Instruction Execution ................................................................. 5-23
SECTION 6QUEUED SERIAL MODULE
6.1 General ........................................................................................................... 6-1
6.2 QSM Registers and Address Map .................................................................. 6-2
6.2.1 QSM Global Registers ........................................................................... 6-2
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6.2.1.1 Low-Power Stop Operation ...........................................................6-2
6.2.1.2 Freeze Operation .......................................................................... 6-3
6.2.1.3 QSM Interrupts .............................................................................. 6-3
6.2.2 QSM Pin Control Registers ................................................................... 6-3
6.3 Queued Serial Peripheral Interface ................................................................6-4
6.3.1 QSPI Registers ...................................................................................... 6-6
6.3.1.1 Control Registers ...........................................................................6-7
6.3.1.2 Status Register .............................................................................. 6-7
6.3.2 QSPI RAM .............................................................................................6-7
6.3.2.1 Receive RAM ................................................................................. 6-7
6.3.2.2 Transmit RAM ................................................................................ 6-8
6.3.2.3 Command RAM ............................................................................. 6-8
6.3.3 QSPI Pins ...............................................................................................6-8
6.3.4 QSPI Operation ...................................................................................... 6-9
6.3.5 QSPI Operating Modes ........................................................................6-10
6.3.5.1 Master Mode ................................................................................ 6-17
6.3.5.2 Master Wraparound Mode ...........................................................6-20
6.3.5.3 Slave Mode .................................................................................. 6-20
6.3.5.4 Slave Wraparound Mode .............................................................6-22
6.3.6 Peripheral Chip Selects ........................................................................6-22
6.4 Serial Communication Interface ................................................................... 6-22
6.4.1 SCI Registers ....................................................................................... 6-22
6.4.1.1 Control Registers .........................................................................6-22
6.4.1.2 Status Register ............................................................................. 6-25
6.4.1.3 Data Register ............................................................................... 6-25
6.4.2 SCI Pins ..............................................................................................6-25
6.4.3 SCI Operation ....................................................................................... 6-25
6.4.3.1 Definition of Terms .......................................................................6-25
6.4.3.2 Serial Formats .............................................................................. 6-26
6.4.3.3 Baud Clock ................................................................................... 6-26
6.4.3.4 Parity Checking ............................................................................6-27
6.4.3.5 Transmitter Operation .................................................................. 6-27
6.4.3.6 Receiver Operation ...................................................................... 6-28
6.4.3.7 Idle-Line Detection ....................................................................... 6-29
6.4.3.8 Receiver Wakeup ......................................................................... 6-30
6.4.3.9 Internal Loop ................................................................................ 6-30
6.5 QSM Initialization .........................................................................................6-31
SECTION 7TIME PROCESSOR UNIT
7.1 General ........................................................................................................... 7-1
7.2 TPU Components ........................................................................................... 7-2
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7.2.1 Time Bases ............................................................................................7-2
7.2.2 Timer Channels ...................................................................................... 7-2
7.2.3 Scheduler ............................................................................................... 7-2
7.2.4 Microengine ............................................................................................ 7-2
7.2.5 Host Interface ......................................................................................... 7-2
7.2.6 Parameter RAM ...................................................................................... 7-3
7.3 TPU Operation ...............................................................................................7-3
7.3.1 Event Timing ..........................................................................................7-3
7.3.2 Channel Orthogonality ............................................................................ 7-4
7.3.3 Interchannel Communication .................................................................. 7-4
7.3.4 Programmable Channel Service Priority ................................................ 7-4
7.3.5 Coherency .............................................................................................. 7-4
7.3.6 Emulation Support ..................................................................................7-4
7.3.7 TPU Interrupts ........................................................................................ 7-5
7.4 Standard and Enhanced Standard Time Functions .......................................7-6
7.4.1 Discrete Input/Output (DIO) .................................................................... 7-6
7.4.2 Input Capture/Input Transition Counter (ITC) .........................................7-6
7.4.3 Output Compare (OC) ............................................................................ 7-6
7.4.4 Pulse-Width Modulation (PWM) ............................................................. 7-7
7.4.5 Synchronized Pulse-Width Modulation (SPWM) .................................... 7-7
7.4.6 Period Measurement with Additional Transition Detect (PMA) ..............7-7
7.4.7 Period Measurement with Missing Transition Detect (PMM) .................7-7
7.4.8 Position-Synchronized Pulse Generator (PSP) ......................................7-7
7.4.9 Stepper Motor (SM) ................................................................................7-8
7.4.10 Period/Pulse-Width Accumulator (PPWA) .............................................. 7-8
7.4.11 Quadrature Decode (QDEC) .................................................................. 7-9
7.5 Motion Control Time Functions ......................................................................7-9
7.5.1 Table Stepper Motor (TSM) .................................................................... 7-9
7.5.2 New Input Capture/Transition Counter (NITC) ....................................... 7-9
7.5.3 Queued Output Match (QOM) .............................................................. 7-10
7.5.4 Programmable Time Accumulator (PTA) .............................................7-10
7.5.5 Multichannel Pulse-Width Modulation (MCPWM) ................................7-10
7.5.6 Fast Quadrature Decode (FQD) ...........................................................7-10
7.5.7 Universal Asynchronous Receiver/Transmitter (UART) ....................... 7-11
7.5.8 Brushless Motor Commutation (COMM) .............................................. 7-11
7.5.9 Frequency Measurement (FQM) .......................................................... 7-11
7.5.10 Hall Effect Decode (HALLD) ................................................................. 7-11
7.6 Host Interface Registers ............................................................................... 7-11
7.6.1 System Configuration Registers ...........................................................7-12
7.6.1.1 Prescaler Control for TCR1 .......................................................... 7-12
7.6.1.2 Prescaler Control for TCR2 .......................................................... 7-12
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7.6.1.3 Emulation Control ......................................................................... 7-13
7.6.1.4 Low-Power Stop Control .............................................................. 7-13
7.6.2 Channel Control Registers ................................................................... 7-14
7.6.2.1 Channel Interrupt Enable and Status Registers ........................... 7-14
7.6.2.2 Channel Function Select Registers .............................................. 7-14
7.6.2.3 Host Sequence Registers ............................................................7-14
7.6.2.4 Host Service Registers ................................................................. 7-14
7.6.2.5 Channel Priority Registers ...........................................................7-14
7.6.3 Development Support and Test Registers ...........................................7-15
SECTION 8STANDBY RAM WITH TPU EMULATION
8.1 General ........................................................................................................... 8-1
8.2 TPURAM Register Block ................................................................................8-1
8.3 TPURAM Array Address Mapping .................................................................. 8-1
8.4 TPURAM Privilege Level ................................................................................ 8-2
8.5 Normal Operation ...........................................................................................8-2
8.6 Standby Operation .........................................................................................8-2
8.7 Low-Power Stop Operation ............................................................................ 8-3
8.8 Reset .............................................................................................................. 8-3
8.9 TPU Microcode Emulation .............................................................................. 8-3
APPENDIX A ELECTRICAL CHARACTERISTICS
APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION
APPENDIX CDEVELOPMENT SUPPORT
C.1 M68MMDS1632 Modular Development System ........................................... C-1
C.2 M68MEVB1632 Modular Evaluation Board ................................................... C-2
APPENDIX D REGISTER SUMMARY
D.1 Central Processing Unit ................................................................................. D-1
D.1.1 CPU32 Register Model .......................................................................... D-2
D.1.2 SR — Status Register ........................................................................... D-3
D.2 System Integration Module ............................................................................ D-3
D.2.1 SIMCR — Module Configuration Register ............................. $YFFA00 D-5
D.2.2 SIMTR — System Integration Test Register .......................... $YFFA02 D-6
D.2.3 SYNCR — Clock Synthesizer Control Register .................... $YFFA04 D-6
D.2.4 RSR — Reset Status Register .............................................. $YFFA07 D-7
D.2.5 SIMTRE — System Integration Test Register (ECLK)........... $YFFA08 D-7
D.2.6 PORTE0/PORTE1 — Port E Data Register.......... $YFFA11, $YFFA13 D-8
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D.2.7 DDRE — Port E Data Direction Register ............................... $YFFA15 D-8
D.2.8 PEPAR — Port E Pin Assignment Register ........................... $YFFA17 D-8
D.2.9 PORTF0/PORTF1 — Port F Data Register...........$YFFA19, $YFFA1B D-9
D.2.10 DDRF — Port F Data Direction Register................................$YFFA1D D-9
D.2.11 PFPAR — Port F Pin Assignment Register............................ $YFFA1F D-9
D.2.12 SYPCR — System Protection Control Register ................... $YFFA21 D-10
D.2.13 PICR — Periodic Interrupt Control Register......................... $YFFA22 D-11
D.2.14 PITR — Periodic Interrupt Timer Register ........................... $YFFA24 D-11
D.2.15 SWSR — Software Service Register ................................... $YFFA27 D-11
D.2.16 TSTMSRA — Master Shift Register A.................................. $YFFA30 D-11
D.2.17 TSTMSRB — Master Shift Register B.................................. $YFFA32 D-11
D.2.18 TSTSC — Test Module Shift Count ..................................... $YFFA34 D-12
D.2.19 TSTRC — Test Module Repetition Count ............................ $YFFA36 D-12
D.2.20 CREG — Test Submodule Control Register ....................... $YFFA38 D-12
D.2.21 DREG — Distributed Register..............................................$YFFA3A D-12
D.2.22 PORTC — Port C Data Register.......................................... $YFFA41 D-12
D.2.23 CSPAR0 — Chip Select Pin Assignment Register 0............ $YFFA44 D-12
D.2.24 CSPAR1 — Chip Select Pin Assignment Register 1............ $YFFA46 D-13
D.2.25 CSBARBT — Chip Select Base Address Register Boot ROM $YFFA48 D13
D.2.26 CSBAR[0:10] — Chip Select Base Address Registers $YFFA4C–$YFFA74
D-13
D.2.27 CSORBT — Chip Select Option Register Boot ROM...........$YFFA4A D-14
D.2.28 CSOR[0:10] — Chip Select Option Registers .....$YFFA4E–$YFFA76 D-14
D.3 Standby RAM Module with TPU Emulation ................................................. D-16
D.3.1 TRAMMCR — TPURAM Module Configuration Register..... $YFFB00 D-16
D.3.2 TRAMTST — TPURAM Test Register ................................. $YFFB02 D-16
D.3.3 TRAMBAR — TPURAM Base Address and Status Register $YFFB04 D-16
D.4 Queued Serial Module ................................................................................. D-18
D.4.1 QSMCR — QSM Configuration Register .............................$YFFC00 D-18
D.4.2 QTEST — QSM Test Register ............................................. $YFFC02 D-19
D.4.3 QILR — QSM Interrupt Level Register..........................................$YFFC04
QIVR — QSM Interrupt Vector Register$YFFC05 .................................................... D-19
D.4.4 SCCR0 — SCI Control Register 0 ....................................... $YFFC08 D-20
D.4.5 SCCR1 — SCI Control Register 1........................................$YFFC0A D-20
D.4.6 SCSR — SCI Status Register ............................................. $YFFC0C D-22
D.4.7 SCDR — SCI Data Register.................................................$YFFC0E D-23
D.4.8 PORTQS — Port QS Data Register.....................................$YFFC15 D-23
D.4.9 PQSPAR — PORT QS Pin Assignment Register .........................$YFFC16
DDRQS — PORT QS Data Direction Register$YFFC17 .......................................... D-23
D.4.10 SPCR0 — QSPI Control Register 0 ..................................... $YFFC18 D-25
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TABLE OF CONTENTS
(Continued)
Paragraph Title Page
D.4.11 SPCR1 — QSPI Control Register 1 ....................................$YFFC1A D-26
D.4.12 SPCR2 — QSPI Control Register 2 ................................... $YFFC1C D-27
D.4.13 SPCR3 — QSPI Control Register 3 ............................................ $YFFC1E
SPSR — QSPI Status Register $YFFC1F ................................................................ D-27
D.4.14 RR[0:F] — Receive Data RAM........................... $YFFD00–$YFFD0E D-28
D.4.15 TR[0:F] — Transmit Data RAM ......................... $YFFD20–$YFFD3E D-28
D.4.16 CR[0:F] — Command RAM................................ $YFFD40–$YFFD4F D-29
D.5.1 TPUMCR — TPU Module Configuration Register................ $YFFE00 D-30
D.5.2 TCR — Test Configuration Register..................................... $YFFE02 D-32
D.5.3 DSCR — Development Support Control Register................ $YFFE04 D-32
D.5.4 DSSR — Development Support Status Register ................. $YFFE06 D-33
D.5.5 TICR — TPU Interrupt Configuration Register..................... $YFFE08 D-33
D.5.6 CIER — Channel Interrupt Enable Register.........................$YFFE0A D-34
D.5.7 CFSR0 — Channel Function Select Register 0 ...................$YFFE0C D-34
D.5.8 CFSR1 — Channel Function Select Register 1 ...................$YFFE0E D-34
D.5.9 CFSR2 — Channel Function Select Register 2 ................... $YFFE10 D-34
D.5.10 CFSR3 — Channel Function Select Register 3 ................... $YFFE12 D-34
D.5.11 HSQR0 — Host Sequence Register 0 ................................. $YFFE14 D-35
D.5.12 HSQR1 — Host Sequence Register 1 ................................. $YFFE16 D-35
D.5.13 HSRR0 — Host Service Request Register 0 ....................... $YFFE18 D-35
D.5.15 CPR0 — Channel Priority Register 0 ..................................$YFFE1C D-36
D.5.16 CPR1 — Channel Priority Register 1 .................................. $YFFE1E D-36
D.5.17 CISR — Channel Interrupt Status Register.......................... $YFFE20 D-36
D.5.18 LR — Link Register .............................................................. $YFFE22 D-36
D.5.19 SGLR — Service Grant Latch Register................................ $YFFE24 D-36
D.5.20 DCNR — Decoded Channel Number Register .................... $YFFE26 D-37
D.5.21 TPU Parameter RAM .......................................................................... D-37
SUMMARY OF CHANGES
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TABLE OF CONTENTS
(Continued)
Paragraph Title Page
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LIST OF ILLUSTRATIONS
Figure Title Page
3-1 MCU Block Diagram ....................................................................................... 3-3
3-2 Pin Assignments for 132-Pin Package ........................................................... 3-4
3-3 Pin Assignments for 144-Pin Package ........................................................... 3-5
3-4 Internal Register Memory Map ..................................................................... 3-10
3-5 Overall Memory Map .................................................................................... 3-11
3-6 Separate Supervisor and User Space Map .................................................. 3-12
3-7 Supervisor Space (Separate Program/Data Space) Map ............................ 3-13
3-8 User Space (Separate Program/Data Space) Map ...................................... 3-14
4-1 System Integration Module Block Diagram .................................................... 4-2
4-2 System Configuration and Protection ............................................................. 4-3
4-3 Periodic Interrupt Timer and Software Watchdog Timer ................................ 4-7
4-4 System Clock Block Diagram ......................................................................... 4-9
4-5 System Clock Oscillator Circuit .................................................................... 4-10
4-6 System Clock Filter Networks ...................................................................... 4-11
4-7 MCU Basic System ...................................................................................... 4-17
4-8 Operand Byte Order ..................................................................................... 4-21
4-9 Word Read Cycle Flowchart ......................................................................... 4-25
4-10 Write Cycle Flowchart .................................................................................. 4-26
4-11 CPU Space Address Encoding .................................................................... 4-27
4-12 Breakpoint Operation Flowchart ................................................................... 4-30
4-13 LPSTOP Interrupt Mask Level ...................................................................... 4-31
4-14 Bus Arbitration Flowchart for Single Request ............................................... 4-36
4-15 Data Bus Mode Select Conditioning ............................................................. 4-40
4-16 Power-On Reset ........................................................................................... 4-45
4-17 Basic MCU System ...................................................................................... 4-50
4-18 Chip-Select Circuit Block Diagram ............................................................... 4-51
4-19 CPU Space Encoding for Interrupt Acknowledge ......................................... 4-56
5-1 CPU32 Block Diagram ................................................................................... 5-2
5-2 User Programming Model .............................................................................. 5-3
5-3 Supervisor Programming Model Supplement ................................................. 5-3
5-4 Data Organization in Data Registers .............................................................. 5-4
5-5 Address Organization in Address Registers ................................................... 5-5
5-6 Memory Operand Addressing ........................................................................ 5-7
5-7 Common in-Circuit Emulator Diagram .......................................................... 5-16
5-8 Bus State Analyzer Configuration ................................................................ 5-17
5-9 Debug Serial I/O Block Diagram .................................................................. 5-21
5-10 BDM Serial Data Word ................................................................................. 5-22
5-11 BDM Connector Pinout ................................................................................. 5-22
5-12 Loop Mode Instruction Sequence ................................................................. 5-23
6-1 QSM Block Diagram ....................................................................................... 6-1
6-2 QSPI Block Diagram ..................................................................................... 6-6
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LIST OF ILLUSTRATIONS
(Continued)
Figure Title Page
6-3 QSPI RAM ...................................................................................................... 6-8
6-4 Flowchart of QSPI Initialization Operation .................................................... 6-11
6-5 Flowchart of QSPI Master Operation (Part 1) .............................................. 6-12
6-5 Flowchart of QSPI Master Operation (Part 2) .............................................. 6-13
6-5 Flowchart of QSPI Master Operation (Part 3) .............................................. 6-14
6-6 Flowchart of QSPI Slave Operation (Part 1) ................................................ 6-15
6-6 Flowchart of QSPI Slave Operation (Part 2) ................................................ 6-16
6-7 SCI Transmitter Block Diagram .................................................................... 6-23
6-8 SCI Receiver Block Diagram ........................................................................ 6-24
7-1 TPU Block Diagram ........................................................................................ 7-1
7-2 TCR1 Prescaler Control ............................................................................... 7-12
7-3 TCR2 Prescaler Control ............................................................................... 7-13
A-1 CLKOUT Output Timing Diagram .................................................................A-14
A-2 External Clock Input Timing Diagram ...........................................................A-14
A-3 ECLK Output Timing Diagram ......................................................................A-14
A-4 Read Cycle Timing Diagram ........................................................................A-15
A-5 Write Cycle Timing Diagram .........................................................................A-16
A-6 Fast Termination Read Cycle Timing Diagram ............................................A-17
A-7 Fast Termination Write Cycle Timing Diagram .............................................A-18
A-8 Bus Arbitration Timing Diagram —Active Bus Case ....................................A-19
A-9 Bus Arbitration Timing Diagram — Idle Bus Case .......................................A-20
A-10 Show Cycle Timing Diagram ........................................................................A-20
A-11 Chip Select Timing Diagram .........................................................................A-21
A-12 Reset and Mode Select Timing Diagram ......................................................A-21
A-13 Background Debugging Mode Timing Diagram — Serial Communication ...A-23
A-14 Background Debugging Mode Timing Diagram — Freeze Assertion ...........A-23
A-15 ECLK Timing Diagram ..................................................................................A-25
A-16 QSPI Timing — Master, CPHA = 0 ..............................................................A-27
A-17 QSPI Timing — Master, CPHA = 1 ..............................................................A-27
A-18 QSPI Timing — Slave, CPHA = 0 ................................................................A-28
A-19 QSPI Timing — Slave, CPHA = 1 ................................................................A-28
A-20 TPU Timing Diagram ....................................................................................A-29
B-1 132-Pin Plastic Surface Mount Package Pin Assignments ............................B-2
B-2 144-Pin Plastic Surface Mount Package Pin Assignments ............................B-3
D-1 User Programming Model ..............................................................................D-2
D-2 Supervisor Programming Model Supplement .................................................D-2
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Table Title Page
3-1 MCU Driver Types........................................................................................... 3-6
3-2 MCU Pin Characteristics ................................................................................. 3-6
3-3 MCU Power Connections ................................................................................ 3-7
3-4 MCU Signal Characteristics ............................................................................ 3-7
3-5 MCU Signal Function ...................................................................................... 3-8
3-6 SIM Reset Mode Selection............................................................................ 3-15
3-7 Module Pin Functions.................................................................................... 3-16
4-1 Show Cycle Enable Bits .................................................................................. 4-4
4-2 Bus Monitor Period.......................................................................................... 4-5
4-3 MODCLK Pin and SWP Bit During Reset ....................................................... 4-6
4-4 Software Watchdog Ratio................................................................................ 4-6
4-5 MODCLK Pin and PTP Bit at Reset ................................................................ 4-7
4-6 Periodic Interrupt Priority................................................................................. 4-8
4-7 Clock Control Multipliers................................................................................ 4-12
4-8 System Frequencies from 32.768–kHz Reference........................................ 4-14
4-9 Clock Control................................................................................................. 4-16
4-10 Size Signal Encoding .................................................................................... 4-19
4-11 Address Space Encoding .............................................................................. 4-19
4-12 Effect of DSACK Signals ............................................................................... 4-21
4-13 Operand Transfer Cases............................................................................... 4-22
4-14 DSA
4-15 Reset Source Summary ................................................................................ 4-38
4-16 Reset Mode Selection ................................................................................... 4-39
4-17 Module Pin Functions.................................................................................... 4-42
4-18 SIM Pin Reset States .................................................................................... 4-43
4-19 Chip-Select Pin Functions ............................................................................. 4-52
4-20 Pin Assignment Field Encoding..................................................................... 4-52
4-21 Block Size Encoding...................................................................................... 4-53
4-22 Option Register Function Summary .............................................................. 4-54
4-23 Chip Select Base and Option Register Reset Values ................................... 4-57
4-24 CSBOOT Base and Option Register Reset Values....................................... 4-58
5-1 Instruction Set Summary............................................................................... 5-10
5-2 Exception Vector Assignments...................................................................... 5-14
5-3 BDM Source Summary.................................................................................. 5-17
5-4 Polling the BDM Entry Source....................................................................... 5-18
5-5 Background Mode Command Summary ....................................................... 5-19
5-6 CPU Generated Message Encoding ............................................................. 5-22
6-1 QSM Pin Function ........................................................................................... 6-4
6-2 QSPI Pin Function........................................................................................... 6-9
6-3 BITS Encoding .............................................................................................. 6-19
6-4 SCI Pin Function ........................................................................................... 6-25
CK, BERR, and HALT Assertion Results ............................................... 4-32
LIST OF TABLES
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LIST OF TABLES
(Continued)
Table Title Page
6-5 Serial Frame Formats.................................................................................... 6-26
6-6 Effect of Parity Checking on Data Size ......................................................... 6-27
7-1 TCR1 Prescaler Control ................................................................................ 7-12
7-2 TCR2 Prescaler Control ................................................................................ 7-13
7-3 Channel Priority Encodings........................................................................... 7-15
A-1 Maximum Ratings............................................................................................A-1
A-2 Typical Ratings, 16.78 MHz Operation............................................................A-2
A-2 a. Typical Ratings, 20.97 MHz Operation............................................................A-2
A-3 Thermal Characteristics ..................................................................................A-3
A-4 16.78 MHz Clock Control Timing.....................................................................A-4
A-4 a. 20.97 MHz Clock Control Timing.....................................................................A-5
A-5 16.78 MHz DC Characteristics ........................................................................A-6
A-5 a. 20.97 MHz DC Characteristics ........................................................................A-7
A-6 16.78 MHz AC Timing .....................................................................................A-9
A-6 a. 20.97 MHz AC Timing ...................................................................................A-11
A-7 Background Debugging Mode Timing ...........................................................A-22
A-8 16.78 MHz ECLK Bus Timing........................................................................A-24
A-8 a. 20.97 MHz ECLK Bus Timing........................................................................A-24
A-9 QSPI Timing ..................................................................................................A-26
A-10 16.78 MHz Time Processor Unit Timing........................................................A-29
A-11 20.97 MHz Time Processor Unit Timing........................................................A-29
B-1 MCU Ordering Information ..............................................................................B-5
B-2 Quantity Order Suffix.......................................................................................B-7
C-1 MC68332 Development Tools.........................................................................C-1
D-1 Module Address Map ......................................................................................D-1
D-2 SIM Address Map............................................................................................D-4
D-3 TPURAM Address Map.................................................................................D-16
D-4 QSM Address Map........................................................................................D-18
D-5 TPU Address Map.........................................................................................D-30
D-6 Parameter RAM Address Map ......................................................................D-37
D-7 MC68332 Module Address Map....................................................................D-38
D-8 Register Bit and Field Mnemonics.................................................................D-41
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SECTION 1 INTRODUCTION
The MC68332, a highly-integrated 32-bit microcontroller, combines high-performance
data manipulation capabilities with powerful peripheral subsystems. The MCU is built
up from standard modules that interface through a common intermodule bus (IMB).
Standardization facilitates rapid development of devices tailored for specific applications.
The MCU incorporates a 32-bit CPU (CPU32), a system integration module (SIM), a
time processor unit (TPU), a queued serial module (QSM), and a 2-Kbyte static RAM
module with TPU emulation capability (TPURAM).
The MCU can either synthesize an internal clock signal from an external reference or
use an external clock input directly. Operation with a 32.768-kHz reference frequency
is standard. System hardware and software allow changes in clock rate during operation. Because MCU operation is fully static, register and memory contents are not affected by clock rate changes.
High-density complementary metal-oxide semiconductor (HCMOS) architecture
makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 instruction set includes a low-power
stop (LPSTOP) command that efficiently implements this capability.
Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each microcontroller has a comprehensive user's manual that provides sufficient information for normal operation of the device. The
user's manual is supplemented by module reference manuals that provide detailed information about module operation and applications. Refer to Freescale publication
vanced Microcontroller Unit (AMCU) Literature
documentation.
(BR1116/D) for a complete listing of
Ad-
MC68332
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INTRODUCTION
1-2 USER’S MANUAL
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SECTION 2 NOMENCLATURE
The following nomenclature is used throughout the manual. Nomenclature used only
in certain sections, such as register bit mnemonics, is defined in those sections.
2.1 Symbols and Operators
+ — Addition
- — Subtraction or negation (two's complement)
* — Multiplication
/ — Division
> — Greater
< — Less
= — Equal
≥
— Equal or greater
≤
— Equal or less
- — Not equal
•
— AND
; — Inclusive OR (OR)
⊕
— Exclusive OR (EOR)
NOT
— Complementation
: — Concatenation
⇒
— Transferred
⇔
— Exchanged
±
— Sign bit; also used to show tolerance
« — Sign extension
% — Binary value
$ — Hexadecimal value
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NOMENCLATURE
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2.2 CPU32 Registers
A6–A0 — Address registers (Index registers)
A7 (SSP) — Supervisor Stack Pointer
A7 (USP) — User Stack Pointer
CCR — Condition code register (user portion of SR)
D7–D0 — Data Registers (Index registers)
DFC — Alternate function code register
PC — Program counter
SFC — Alternate function code register
SR — Status register
VBR — Vector base register
X — Extend indicator
N — Negative indicator
Z — Zero indicator
V — Two's complement overflow indicator
C — Carry/borrow indicator
NOMENCLATURE
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2.3 Pin and Signal Mnemonics
ADDR[23:0] — Address Bus
AS
— Address Strobe
AVEC
BERR
BGACK
BKPT
CLKOUT — System Clock
CS[10:0]
CSBOOT
DATA[15:0] — Data Bus
DSACK[1:0]
DSCLK — Development Serial Clock
DSO — Development Serial Output
EXTAL — External Crystal Oscillator Connection
FC[2:0] — Function Codes
FREEZE — Freeze
HALT
IFETCH
IPIPE
IRQ[7:1]
MISO — Master In Slave Out
MODCLK — Clock Mode Select
MOSI — Master Out Slave In
PC[6:0] — SIM I/O Port C
PCS[3:0] — Peripheral Chip Selects
PE[7:0] — SIM I/O Port E
PF[7:0] — SIM I/O Port F
PQS[7:0] — QSM I/O Port
QUOT — Quotient Out
R/W
RESET
RMC
RXD — SCI Receive Data
SCK — QSPI Serial Clock
SIZ[1:0] — Size
T2CLK — TPU Clock In
TPUCH[15:0] — TPU Channel Signals
TSC — Three-State Control
TXD — SCI Transmit Data
XFC — External Filter Capacitor
XTAL — External Crystal Oscillator Connection
— Autovector
— Bus Error
BG
— Bus Grant
— Bus Grant Acknowledge
— Breakpoint
BR
— Bus Request
— Chip Selects
— Boot ROM Chip Select
DS
— Data Strobe
— Data and Size Acknowledge
DSI — Development Serial Input
— Halt
— Instruction Fetch
— Instruction Pipeline
— Interrupt Request
— Read/Write
— Reset
— Read-Modify-Write Cycle
SS
— Slave Select
MC68332
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NOMENCLATURE
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2.4 Register Mnemonics
CFSR[0:3] — Channel Function Select Registers [0:3]
CIER — Channel Interrupt Enable Register
CISR — Channel Interrupt Status Register
CPR[0:1] — Channel Priority Registers [0:1]
CREG — Test Control Register C
CR[0:F] — QSM Command RAM
CSBARBT — Chip-Select Base Address Register Boot ROM
CSBAR[0:10] — Chip-Select Base Address Registers [0:10]
CSORBT — Chip-Select Option Register Boot ROM
CSOR[0:10] — Chip-Select Option Registers [0:10]
CSPAR[0:1] — Chip-Select Pin Assignment Registers [0:1]
DCNR — Decoded Channel Number Register
DDRE — Port E Data Direction Register
DDRF — Port F Data Direction Register
DDRQS — Port QS Data Direction Register
DREG — SIM Test Module Distributed Register
DSCR — Development Support Control Register
DSSR — Development Support Status Register
HSQR[0:1] — Host Sequence Registers [0:1]
HSRR[0:1] — Host Service Request Registers [0:1]
LR — Link Register
PEPAR — Port E Pin Assignment Register
PFPAR — Port F Pin Assignment Register
PICR — Periodic Interrupt Control Register
PITR — Periodic Interrupt Timer Register
PORTC — Port C Data Register
PORTE — Port E Data Register
PORTF — Port F Data Register
PORTQS — Port QS Data Register
PQSPAR — Port QS Pin Assignment Register
QILR — QSM Interrupt Level Register
QIVR — QSM Interrupt Vector Register
QSMCR — QSM Configuration Register
QTEST — QSM Test Register
RR[0:F] — QSM Receive Data RAM
RSR — Reset Status Register
SCCR[0:1] — SCI Control Registers [0:1]
SCDR — SCI Data Register
SCSR — SCI Status Register
SGLR — Service Grant Latch Register
SIMCR — SIM Module Configuration Register
SIMTR — System Integration Test Register
SIMTRE — System Integration Test Register (ECLK)
SPCR[0:3] — QSPI Control Registers [0:3]
SPSR — QSPI Status Register
NOMENCLATURE
2-4 USER’S MANUAL
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SWSR — Software Watchdog Service Register
SYNCR — Clock Synthesizer Control Register
SYPCR — System Protection Control Register
TCR — TPU Test Configuration Register
TICR — TPU Interrupt Configuration Register
TPUMCR — TPU Module Configuration Register
TRAMBAR — TPURAM Base Address/Status Register
TRAMMCR — TPURAM Module Configuration Register
TRAMTST — TPURAM Test Register
TR[0:F] — QSM Transmit Data RAM
TSTMSRA — Test Module Master Shift Register A
TSTMSRB — Test Module Master Shift Register B
TSTRC — Test Module Repetition Counter
TSTSC — Test Module Shift Count Register
2.5 Conventions
Logic level one
Logic level zero
is the voltage that corresponds to a Boolean true (1) state.
is the voltage that corresponds to a Boolean false (0) state.
Set
refers specifically to establishing logic level one on a bit or bits.
Clear
refers specifically to establishing logic level zero on a bit or bits.
Asserted
from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one.
Negated
changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero.
A specific mnemonic
bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0.
that define the range. AM[35:30] are bits 35 to 30 of accumulator M; CSOR[0:5] are
the first six option registers
Parentheses
than the register or memory location itself. (A) is the content of accumulator A. (M
+
1) is the content of the word at address M.
LSB
ences to low and high bytes are spelled out.
means that a signal is in active logic state. An active low signal changes
means that an asserted signal changes logic state. An active low signal
within a range is referred to by mnemonic and number. A15 is
A range of mnemonics
are used to indicate the content of a register or memory location, rather
means least significant bit or bits.
is referred to by mnemonic and the numbers
MSB
means most significant bit or bits. Refer-
:
M
LSW
means least significant word or words.
words.
ADDR
DATA
MC68332
USER’S MANUAL 2-5
is the address bus. ADDR[7:0] are the eight LSB of the address bus.
is the data bus. DATA[15:8] are the eight MSB of the data bus.
NOMENCLATURE
MSW
means most significant word or
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NOMENCLATURE
2-6 USER’S MANUAL
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SECTION 3 OVERVIEW
This section contains information about the entire modular microcontroller. It lists the
features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system
memory maps. Timing and electrical specifications for the entire microcontroller and
for individual modules are provided in
. Comprehensive module register descriptions and memory maps are provided
TICS
APPENDIX D REGISTER SUMMARY
in
3.1 MC68332 Features
The following paragraphs highlight capabilities of each of the microcontroller modules.
Each module is discussed separately in a subsequent section of this user's manual.
3.1.1 System Integration Module (SIM)
• External Bus Support
• Programmable Chip-Select Outputs
• System Protection Logic
• Watchdog Timer, Clock Monitor, and Bus Monitor
• System Protection Logic
• System Clock Based on 32.768-kHz Crystal for Low Power Operation
• Test/Debug Submodule for Factory/User Test and Development
3.1.2 Central Processing Unit (CPU)
• Upward Object Code Compatible
• New Instructions for Controller Applications
• 32-Bit Architecture
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Table Lookup and Interpolate Instruction
• Improved Exception Handling for Controller Applications
• Trace on Change of Flow
• Hardware Breakpoint Signal, Background Mode
• Fully Static Operation
APPENDIX A ELECTRICAL CHARACTERIS-
.
3.1.3 Time Processor Unit (TPU)
• Dedicated Microengine Operating Independently of CPU32
• 16 Independent, Programmable Channels and Pins
• Any Channel can Perform any Time Function
• Two Timer Count Registers with Programmable Prescalers
• Selectable Channel Priority Levels
MC68332
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OVERVIEW
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3.1.4 Queued Serial Module (QSM)
• Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmitter (UART): Modulus Baud Rate, Parity
• Queued Serial Peripheral Interface (SPI): 80-Byte RAM, Up to 16 Automatic
Transfers
• Dual Function I/O Ports
• Continuous Cycling, 8–16 Bits per Transfer
3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM)
• 2-Kbytes of Static RAM
• May be Used as Normal RAM or TPU Microcode Emulation RAM
3.2 System Block Diagram and Pin Assignment Diagrams
Figure 3-1 is a functional diagram of the MCU. Although diagram blocks represent the
relative size of the physical modules, there is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integratedcircuit modules. Figure 3-2 shows the pin assignments of the 132-pin plastic surfacemount package. Figure 3-3 shows the pin assignments of the 144-pin plastic surfacemount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING IN-
FORMATION for package dimensions. All pin functions and signal names are shown
in this drawing. Refer to subsequent paragraphs in this section for pin and signal descriptions.
OVERVIEW MC68332
3-2 USER’S MANUAL
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V
STBY
TPUCH[15:0] TPUCH[15:0]
T2CLK T2CLK
RXD
PQS7/TXD
PQS6/PCS3
PQS5/PCS2
PQS4/PCS1
PQS3/PCS0/SS PCS0/SS
PQS2/SCK
PQS1/MOSI
PQS0/MISO
BKPT/DSCLK
IFETCH
/DSI
IPIPE/DSO
PORT QS
CONTROL
TXD
PCS3
PCS2
PCS1
SCK
MOSI
MISO
QSM
TPU
IMB
IFETCH
BKPT
2 KBYTES
RAM
CPU 32
DSI
IPIPE
DSO
FREEZE
DSCLK
CHIP
SELECTS
BR
BG
BGACK
[10:0]
CS
FC2
FC1
FC0
ADDR[23:0]
EBI
DSACK1 PE1/DSACK1
DSACK0
IRQ[7:1]
MODCLK
CLOCK
TEST
ADDR[23:19]
SIZ1 PE7/SIZ1
SIZ0 PE6/SIZ0
DS PE5/DS
AS
RMC
AVEC PE2/AVEC
TSC
QUOT
PORT C
CONTROL
PORT E
CONTROL
PORT F
CONTROL
CONTROL
CSBOOT
ADDR23/CS10
PC6/ADDR22/CS9
PC5/ADDR21/CS8
PC4/ADDR20/CS7
PC3/ADDR19/CS6
PC2/FC2/CS5
PC1/FC1/CS4
PC0/FC0/CS3
BGACK/CS2
BG/CS1
BR/CS0
ADDR[18:0]
PE4/AS
PE3/RMC
PE0/DSACK0
DATA[15:0]DATA[15:0]
R/W
RESET
HALT
BERR
PF7/IRQ7
PF6/IRQ6
PF5/IRQ5
PF4/IRQ4
PF3/IRQ3
PF2/IRQ2
PF1/IRQ1
PF0/MODCLK
CLKOUT
XTAL
EXTAL
XFC
V
FREEZE/QUOT
DDSYN
TSC
CONTROL
332 BLOCK
Figure 3-1 MCU Block Diagram
MC68332 OVERVIEW
USER’S MANUAL 3-3
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V
DD
V
STBY
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
V
DD
V
SS
ADDR9
ADDR10
ADDR11
ADDR12
V
SS
ADDR13
ADDR14
ADDR15
ADDR16
V
DD
V
SS
ADDR17
ADDR18
PQS0/MISO
PQS1/MOSI
PQS2/SCK
PQS3/PCS0/SS
PQS4/PCS1
PQS5/PCS2
PQS6/PCS3
V
DD
SS
TPUCH0
TPUCH1
TPUCH2
TPUCH3
TPUCH4
TPUCH5
TSC
/DSCLK
BKPT
TPUCH6
FREEZE/QUOT
V
17
16151413121110
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52535455565758596061626364656667686970717273747576777879808182
SS
V
PQS7/TXD
RXD
/DSO
IPIPE
/DSI
IFETCH
DD
TPUCH7
9876543
SS
V
VSSV
XTAL
TPUCH8
EXTAL
DDSYN
V
TPUCH9
TPUCH10
XFC
VDDVDDV
DD
TPUCH11
VSSV
2
1
MC68332
SS
CLKOUT
TPUCH13
TPUCH14
TPUCH12
132
131
130
HALT
BERR
RESET
TPUCH15
T2CLK
V
129
128
PF6/IRQ6
PF7/IRQ7
SS
V
ADDR23/CS10
127
126
125
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PC2/FC2/CS5
PC3/ADDR19/CS6
PC4/ADDR20/CS7
PC5/ADDR21/CS8
PC6/ADDR22/CS9
124
123
122
121
120
R/W
PF1/IRQ1
PF2/IRQ2
PE7/SIZ1
PF0/MODCLK
DD
SS
V
PC0/FC0/CS3
PC1/FC1/CS4
117
119
118
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
AS
SS
V
PE6/SIZ0
V
DD
BGACK/CS2
BG/CS1
BR/CS0
CSBOOT
DATA0
DATA1
DATA2
DATA3
V
DD
V
SS
DATA4
DATA5
DATA6
DATA7
V
SS
DATA8
DATA9
DATA10
DATA11
V
DD
V
SS
DATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
PE5/DS
V
DD
332 132-PIN QFP
Figure 3-2 Pin Assignments for 132-Pin Package
OVERVIEW MC68332
3-4 USER’S MANUAL
DD
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V
/CS2
/CS1
/CS0
BGACK
BG
BR
CSBOOT
DATA0
DATA1
DATA2
DD
DATA3
VSSV
DATA4
DATA5
DATA6
DATA7NCDATA8NCDATA9
V
SS
DATA10NCDATA11
V
DD
VSSDATA12
DATA13
DATA14
DATA15
ADDR0
PE0/DSACK0
PE1/DSACK1
PE2/AVEC
PE3/RMC
DD
PE5/DS
V
NC
V
SS
FC0/CS3
FC1/CS4
FC2/CS5
ADDR19/CS6
ADDR20/CS7
ADDR21/CS8
ADDR22/CS9
ADDR23/CS10
V
DD
V
SS
T2CLK
TPUCH15
TPUCH14
TPUCH13
TPUCH12
NC
V
DD
V
SS
TPUCH11
TPUCH10
TPUCH9
TPUCH8
V
DDE
V
SSE
TPUCH7
TPUCH6
TPUCH5
TPUCH4
TPUCH3
TPUCH2
TPUCH1
TPUCH0
V
SS
NC
143
144
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
ADDR13
ADDR14
122
ADDR15NCADDR16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
383940414243444546474849505152535455565758596061626364
SS
ADDR6
ADDR7
DD
V
ADDR8
V
DD
V
STBY
V
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ADDR9
ADDR10
MC68332
ADDR11
ADDR12
NC
SS
NC
V
121
V
120
DD
119
SS
V
118
117
116
65
ADDR17
ADDR18
PQS0/MISO
115
114
113
112
111
68
6667697071
PQS2/SCK
PQS1/MOSI
PQS4/PCS1
PQS5/PCS2
PQS3/PCS0/SS
109
110
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
DD
V
PQS6/PCS3
NC
V
SS
PE4/AS
PE6/SIZ0
PE7/SIZ1
R/W
PF0/MODCLK
PF1/IRQ1
PF2/IRQ2
PF3/IRQ3
PF4/IRQ4
PF5/IRQ5
PF6/IRQ6
PF7/IRQ7
BERR
HALT
RESET
V
SS
CLKOUT
V
DD
NC
XFC
V
DD
EXTAL
V
DD
XTAL
V
SS
FREEZE/QUOT
TSC
BKPT/DSCLK
IFETCH/DSI
IPIPE
/DSO
RXD
PQS7/TXD
V
SS
NC
332 144-PIN QFP
Figure 3-3 Pin Assignments for 144-Pin Package
3.3 Pin Descriptions
The following tables summarize functional characteristics of MCU pins. Table 3-1
shows types of output drivers. Table 3-2 shows all inputs and outputs. Digital inputs
and outputs use CMOS logic levels. An entry in the Discrete I/O column indicates that
a pin can also be used for general-purpose input, output, or both. The I/O port designation is given when it applies. Table 3-3 shows characteristics of power pins. Refer
to Figure 3-1 for port organization.
MC68332 OVERVIEW
USER’S MANUAL 3-5
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