Freescale Semiconductor MC13851 Quick Start Manual

Freescale Semiconductor

Quick Start Guide

Document Number:

MC138512400QSG

Rev . 0, 11/2010

MC13851 Evaluation Board Quick Start —
2400 MHz

INTRODUCTION

This evaluation board design demonstrates one possible
design at 2.75 V that satisfies competing requirements for NF,
IP3, gain, return losses and current consumption. By
changing any of the requirements, the performance for a
particular parameter can be improved to meet a particular
spec requirement.

This circuit was designed to provide NF of 1.5 dB, S21 gain
>15dBusingR1=1.2k! and 1.5 k!.

Bias resistor R1 is used to adjust for the desired current
drain and IP3 performance.

Gain or NF can be improved with matching changes to meet
specific requirements.

Resistor R3 is used to de--Q output inductor L2 and adjust
gain and return losses. Lowering R3 lowers gain and improves
return losses.

The LNA is bias stabilized for variations in device and
temperature.

NOTE: Tables 1 and 2 list measured parameters on three
typical evaluation boards and are meant as a guide to the RF
performance possible for this application circuit. Variations in
matching component performance may result in variation in
evaluation board performance results.

Table 1. Evaluation Board Measurements

at P

=--30dBm)

in

Input

Power

Serial #

1 1.2k Active --30.00 --13.91 16.09 17.59 1.5 8.29 -- 7 . 8 1.51 5.1

1 1.2k Bypass --30.00 --34.91 --4.91 20.29 25.2 — — 5.21 1.56n A

2 1.2k Active --30.00 --13.76 16.24 16.99 0.75 8.04 -- 8 . 2 1.5 4.47

2 1.2k Bypass --30.00 --35.09 --5.09 20.31 25.4 — — 5.47 3.6 nA

3 1.2k Active --30.00 --13.90 16.10 17.80 1.7 8.20 -- 7 . 9 1.51 4.54

3 1.2k Bypass --30.00 --34.82 --4.82 20.48 25.3 — — 5.08 7.6 nA

1 1.5k Active --30.00 --14.09 15.91 19.01 3.1 8.01 -- 7 . 9 1.5 4.02

1 1.5k Bypass --30.00 --34.88 --4.88 20.82 25.7 — — 5 1.56 nA

2 1.5k Active --30.00 --14.17 15.83 17.33 1.5 7.83 -- 8 . 0 1.52 3.55

2 1.5k Bypass --30.00 --35.08 --5.08 20.22 25.3 — — 5.29 3.6 nA

3 1.5k Active --30.00 --14.18 15.82 17.92 2.1 8.12 -- 7 . 7 1.52 3.63

3 1.5k Bypass --30.00 --34.85 --4.85 20.15 25 — — 5.09 7.6 nA

R1 Mode

Table 2. S--Parameters (2400 MHz, V

Serial #

1 1.2k Active -- 11 . 9 6 15.76 --23.6 --13.4

1 1.2k Bypass --15.05 --5.03 -- 5 . 3 --22.8

2 1.2k Active --12.27 15.75 --23.8 -- 11 . 6 3

2 1.2k Bypass --14.27 --5.09 -- 5 . 4 --23.5

3 1.2k Active --13.12 15.68 --23.5 -- 11 . 4 7

3 1.2k Bypass --14.83 --4.96 --5.19 --21.7

1 1.5k Active --10.7 15.57 --23.7 --12.38

1 1.5k Bypass --14.7 --5.06 -- 5 . 4 --21.40

2 1.5k Active --10.4 15.43 --23.2 --10.91

2 1.5k Bypass --14.3 --5.14 --5.44 -- 23.20

3 1.5k Active -- 11 . 1 4 15.32 --23.1 --10.8

3 1.5k Bypass --14.77 --5.02 --5.26 --21.17

(dBm)

CC

R1 Mode S11 (dB) S21 (dB) S12 (dB) S22 (dB)

(2400 MHz, VCC= 2.75 V, Frequency Spacing = 200 kHz, Non--Linear Measurements

Output

Power
(dBm)

=2.75V)

Power

Gain

(dB)

Output

IP3

(dBm)

Input

IP3

(dBm)

Output Ref

P

1dB

(dBm)

Input Ref

P

1dB

(dBm)

NF

(dB)

I

CC

(mA)

" Freescale Semiconductor, Inc., 2010.All rights reserved.

RF Engineering Bulletin
Freescale Semiconductor

MC138512400QSG

1

Piccolo High Band

MC13851 V1R1

RF

IN

C1

Enable

Gain

L1

GND

5

6

Logic

7

8

Pin 1 Locator

on Package

4

GND

RF

3

R1

C2

RF

OUT

IN

C1

Q1

L1

2

R2

1

L2

L3

C3

C4

R3

Pin 1

V

CC

Enable

Gain

Figure 1. MC13851 2400 MHz Schematic Figure 2. MC13851 2400 MHz Evaluation Circuit

Component Layout

Table 3. Evaluation Circuit Component Designations and Values

Component Val ue Case Manufacturer Comments

C1 2.4 pF 402 Murata Input match

C2 0.9 pF 402 Murata Output match

C3 33 pF 402 Murata RF bypass

C4 0.01 #F 805 Murata Low freq bypass

L1 3.6 nH 402 Murata Input match

L2 2.0 nH 402 Murata Output match

L3 270 nH 402 Murata Bias couple to logic

R1 1.2, 1.5 k! 402 KOA LNA bias

R2 10 ! 402 KOA Stability

R3 360 402 KOA De--Q L2, adjust gain, RLs

Q1 MC13851 MLP8 Freescale eSiGe LNA

R1

RF

L2

OUT

C2R2

R3

C4

L3

V

CC

C3

GND

Tab l e 4. Truth Table

Pin Function Pin Name Low Gain High Gain Low Gain High Gain

Logic Circuit Bias V

CC

Toggles Gain Mode (Active or Bypass) Gain 0 1 0 1

Toggles LNA On/Off Enable 1 1 0 0

Notes: 1. Logic state “1” equals VCCvoltage. Logic state of “0” equals ground potential.

is inductively coupled to LNA Out pin and VCCpin.

2. V

CC

MC138512400QSG

2

Enable Disable

V

CC

1 1 1 1

Quick Start Guide

Freescale Semiconductor