Freescale Semiconductor MC13192, MC13193 Technical Data Manual

Freescale Semiconductor

Technical Data

MC13192/MC13193

MC13192/D

Rev. 2.7, 12/2004

MC13192/MC13193

(Scale 1:1)

Package Information

Plastic Package

Case 1311-03

(QFN-32)

2.4 GHz Low Power Transceiver
for the IEEE

1 Introduction

The MC13192 and MC13193 are short range, low
power, 2.4 GHz Industrial, Scientific, and Medical
(ISM) band transceivers. The MC13192/MC13193
contain a complete 802.15.4 physical layer (PHY)
modem designed for the IEEE® 802.15.4 wireless
standard which supports peer-to-peer, star, and mesh
networking.

The MC13192 includes the 802.15.4 PHY/MAC for use
with the HCS08 Family of MCUs. The MC13193 also
includes the 802.15.4 PHY/MAC plus the ZigBee
Protocol Stack for use with the HCS08 Family of MCUs.
With the exception of the addition of the ZigBee Protocol
Stack, the MC13193 functionality is the same as the
MC13192.

®

802.15.4 Standard

Ordering Information

Device Device Marking Package

MC13192
MC13193

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 3

4 Data Transfer Modes . . . . . . . . . . . . . . . . . . . 3

5 Electrical Characteristics . . . . . . . . . . . . . . . 8

6 Functional Description . . . . . . . . . . . . . . . . 11

7 Pin Connections . . . . . . . . . . . . . . . . . . . . . . 14

8 Applications Information . . . . . . . . . . . . . . . 17

9 Packaging Information . . . . . . . . . . . . . . . . . 21

13192
13193

QFN-32
QFN-32

When combined with an appropriate microcontroller
(MCU), the MC13192/MC13193 provide a
cost-effective solution for short-range data links and
networks. Interface with the MCU is accomplished using
a four wire serial peripheral interface (SPI) connection
and an interrupt request output which allows for the use
of a variety of processors. The software and processor

Freescale reserves the right to change the detail specificatio ns as may be required to permit improvements in the design of i ts
products.

© Freescale Semiconductor, Inc., 2004. All rights reserved.

Features

can be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee™
networking.

For more detailed information about MC13192/MC13192 operation, refer to the MC13192/MC13193
Reference Manual, part number MC13192RM/D.

Applications include, but are not limited to, the following:

• Remote control and wire replacement in industrial systems such as wireless sensor networks

• Factory automation and motor control

• Energy Management (lighting, HVAC, etc.)

• Asset tracking and monitoring

Potential consumer applications include:

• Home automation and control (lighting, thermostats, etc.)

• Human interface devices (keyboard, mice, etc.)

• Remote entertainment control

• Wireless toys

The transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator
(VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device
supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with

5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output
are used for receive (RX) and transmit (TX) data transfer and control.

2 Features

• Recommended power supply range: 2.0 to 3.4 V

• 16 Channels

• 0 dBm nominal, programmable up to 4 dBm typical maximum output power

• Buffered transmit and receive data packets for simplified use with low cost MCUs

• Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode
(compatible with IEEE Standard 802.15.4)

• Three power down modes for power conservation:
—< 1 µA Off current
— 2.3 µA Typical Hibernate current
— 35 µA Typical Doze current (no CLKO)

• RX sensitivity of -92 dBm (typical) at 1.0% packet error rate

• Four internal timer comparators available to reduce MCU resource requirements

• Programmable frequency clock output for use by MCU

• Seven general purpose input/output (GPIO) signals

• Operating temperature range: -40 °C to 85 °C

MC13192/MC13193 Technical Data, Rev. 2.7

2 Freescale Semiconductor

Block Diagrams

• Small form factor QFN-32 Package
— Meets moisture sensitivity level (MSL) 3
— 260 °C peak reflow temperature
— Meets lead-free requirements

3 Block Diagrams

Figure 3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard

802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY)
specification. Figure 4 shows the basic system block diagram for the MC13192/MC13193 in an
application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request
line. The media access control (MAC), drivers, and network and application software (as required) reside
on the host processor . The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor
depending on application requirements.

4 Data Transfer Modes

The MC13192/MC13193 has two data transfer modes:

1. Packet Mode — Data is buffered in on-chip RAM

2. Streaming Mode — Data is processed word-by-word

The Freescale 802.15.4 MAC software only supports the streaming mode of data transfer . For proprietary
applications, packet mode can be used to conserve MCU resources.

4.1 Packet Structure

Figure 5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported.

The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a
one-byte Frame Length Indicator (FLI) before the data. A Frame Check Sequence (FCS) is calculated and
appended to the end of the data.

MC13192/MC13193 Technical Data, Rev. 2.7

Freescale Semiconductor 3

Data Transfer Modes

4.2 Receive Path Description

In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.

The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.

If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is
notified that an entire packet has been received via an interrupt.

If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word
basis.

Figure 1 shows CCA reported power level versus input power. Note that CCA reported power saturates at

about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure 2 shows
energy detection/LQI reported level versus input power. Note that for both graphs the required IEEE

802.15.4 Standard accuracy and range limits are shown.

-50

-60

-70

-80

-90

Reported Power Level (dBm)

-100

-90 -80 -70 -60 -50
Input Pow er (dBm)

Figure 1. Reported Power Level versus Input Power in Clear Channel Assessment Mode

802.15.4 Accura cy
and ran ge Re quirements

MC13192/MC13193 Technical Data, Rev. 2.7

4 Freescale Semiconductor

-25

-35

-45

-55

Data Transfer Modes

-65

Reported Power Level (dBm)

-75

-85

-85 -75 -65 -55 -45 -35 -25 -15
Input Pow er Level (dBm)

802.1 5.4 Accur acy
and Range Requirements

Figure 2. Reported Power Level Versus Input Power for Energy Detect or Link Quality Indicator

MC13192/MC13193 Technical Data, Rev. 2.7

Freescale Semiconductor 5

Data Transfer Modes

4.3 Transmit Path Description

For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX
data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then
up-converted to the transmit frequency.

If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is
notified via an interrupt when the whole packet has successfully been transmitted.

In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt
serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the
whole packet is transmitted.

RFIN+

RFIN-

VDDLO2

XTAL1
XTAL2

VDDLO1

PAO+

PAO-

1st IF Mix er
IF = 65 M Hz

LNA

256 MHz

Crystal

Osc illator

16 MHz

PA

2nd IF Mixer

IF = 1 M Hz

÷4

Phase Shift Modulator

PMA

Decima tion

Filter

AGC

Sy n the sizer

Baseband

Mixer

2.45 GHz

VCO

Matched

Filter

Programmable

Prescaler

MUX

CCA

Transmit

Packet RAM 2

Transmit

Packet RAM 1

FCS

Generation

DCD

Receive

Packet RAM

24 Bit Ev ent Timer

4 Programmable

Timer Comparators

Transmit RAM

Arbiter

Header

Generation

Packet

Process or

Symbol

Correlator

Synch & Det

Receive RAM

Arbiter

Sym bol

Generation

Figure 3. MC13192 Simplified Block Diagram

Pow er-U p

Control

Logic

Sequence

Manager

(Control Logic)

Analog

Regulator VBATT

Digital

Regulator L

Digital

Regulator H

Crystal

Regulator

VCO

Regulator

SERIAL

PERIPHERAL

IRQ

Arbiter

INTERFACE

VDDINT

VDDD

VDDVCO

(SPI)

VDDA

RXTXEN

CE
MOSI
MISO
SPICLK
ATTN

RST

GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7

IRQ

CLKO

MC13192/MC13193 Technical Data, Rev. 2.7

6 Freescale Semiconductor

Data Transfer Modes

MC13192/MC13193

Analog Receiver

Frequency

Generation

Analog

Transmitter

Voltage

Regulators

Power Up

Management

Control

Logic

Digital Transceiver

IRQ Arbiter

Buffer RAM

SPI

and GPIO

Timer

RAM Arbiter

Microcontroller

SPI

CPU A/D

ROM

(Flash)

RAM

Application

Network

MAC

PHY Driver

Figure 4. System Level Block Diagram

4 bytes 1 byte 1 byte 125 bytes maximum 2 bytes

Preamble SFD FLI Payload Data FCS

Timer

Figure 5. MC13192/MC13193 Packet Structure

MC13192/MC13193 Technical Data, Rev. 2.7

Freescale Semiconductor 7