Freescale Semiconductor M68HC08RG, M68HC08AD Reference Manual
Reference Guide
M68HC08RG/AD
Rev . 2, 3/ 2002
M68HC08
Family Reference Guide
Programming Model
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70
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A ACCUMULATOR (A)
15 8 7 0
H X INDEX REGISTER (H:X)
15 0
15 0
70
V11HINZC
TWO’ S COMPLEME NT OVERFLOW
FLAG (V)
ZERO FLAG (Z)
HALF-CAR RY FL AG (H )
NEGATIVE FLAG (N)
INTERRUP T MA SK ( I)
STACK POINTER (SP)
PROGRAM COUNTE R (PC)
CONDITION CODE
REGISTER (CCR)
CARRY/BORROW FLAG (C)
Figure 1. Programming Model
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Stacking
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UNSTACKING
ORDER
5
1
4
2
3
3
2
4
1
5
70
•
•
•
CONDITION CODE RE G ISTE R
ACCUMULATOR
INDEX REGISTER (LOW BYTE X)
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
(1)
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•
•
STACKING
ORDER
1. High byte (H) of index register is not stacked.
•
$00FF (DEFAULT ADDRESS
ON RESET)
Figure 2. Interrupt Stack Frame
NOTE: To maintain compatibility with the M6805 Family, H (the high byte of the index
register) is n ot stacked during interru pt processing . If th e interrupt se rv ic e
routine modifies H or uses the indexed addressing mode, it is
the user’s responsibility to save and restor e it prior to returning.
IRQINT PSHH
|
|Interrupt service routine
|
|
PULH
RTI
2 M68HC08 Family Reference Guide MOTOROLA
Figure 3. H Register Storage
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Interrup t Vect or Lo cat io ns
Address Reset Priority
FFFE Reset 1
FFFC SWI 2
FFFA IREQ[0] 3
:::
FF02 IREQ[124] 127
FF00 IREQ[125] 128
Notation Used in Instruction Set Summary
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See Table 2 for the instruction set summary.
M68HC08RG/AD
Table 1. M68HC08 Vectors
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Operators
= Contents of register or memory location shown inside parentheses
( )
= Is loaded with (read: “gets”)
←
= Boolean AND
&
= Boolean OR
|
= Boolean exclusive OR
⊕
= Multiply
×
= Divide
÷
= Concatenate
:
=Add
+
= Negate (two’s complement)
–
= Sign extend
«
CPU Registers
A = Accumulator
CCR = Condition code register
H = Index register, higher order (most significant) eight bits
X = Index register, lower order (least significant) eight bits
PC = Program counter
PCH = Prog ram counter, higher order (most significant) eight bits
PCL = Program count er, lower order (least significant) eight bits
SP = Stack pointer
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Memory and Addressing
M:M + $0001
Condition Code Register (CCR) Bits
=Two’s complement overflow indicator, bit 7
V
= Half carry, bit 4
H
= Interrupt mask, bit 3
I
= Negative i n d icator, bit 2
N
= Zero indicator , bit 1
Z
= Carry/borrow, bit 0 (carry out of bit 7)
C
= A memory location or absolute data, depending on addressing
M
mode
= A 16-bit value in two consecutive memory locations. The higher-
order (most significant) eight bits are located at the address of M,
and the lower-order (least significant) eight bits are located at the
next higher sequential address.
= The relative offset, which is the two’s complement number stored
rel
in the last byte of machine code corresponding to a branch
instruction
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Bit Status BEFORE Execution of an Instruction (n = 7, 6, 5, ... 0)
=Bit n of memory location used in operation
Mn
=Bit n of accumulator
An
=Bit n of index register H
Hn
=Bit n of index register X
Xn
=Bit n of the source operand (M, A, or X)
bn
1. For 2-byte operati ons such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
Bit Status A F TE R Execution of an Instructio n
=Bit n of the result of an operation (n = 7, 6, 5, … 0)
Rn
1. For 2-byte operations such as LDHX, STHX, and CPHX, n = 15 refers to bit 15 of the
2-byte word or bit 7 of the most significant (first) byte.
CCR Activity Figure Notation
– = Bit not affected
0 = Bit forced to 0
1 = Bit forced to 1
= Bit set or cleared according to results of operation
U = Undefined after the operation
(1)
(1)
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Machine Coding Notation
dd = Low-order eight bits of a direct address $0000–$00FF (high byte assumed
ee = Upper eight bits of 16-bit offset
ff = Lower eight bits of 16-bit offset or 8-bit offset
ii = One byte of immediate data
jj = High-order byte of a 16-bit immediate data value
kk = Low-order byte of a 16-bit immediate data value
hh = High-order byte of 16-bit extended address
ll = Low-order byte of 16-bit extended address
rr = Relative offset
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to be $00)
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Explanation of Italic Expressions in Source Form Col umn
n = Any label or expression that evaluates to a single integer in the range 0–7
opr8i = Any label or expression that evaluates to an 8-bit immediate value
opr16i = Any label or expression that evaluates to a 16-bit immediate value
opr8a = Any label or expression that evaluates to an 8-bit value. The instruction
treats this 8-bit value as the low order eight bits of an address in the direct
page of the 64-Kbyte address space ($00xx).
opr16a = Any label or expression that evaluates to a 16-bit value. The instruction
treats this value as an address in the 64-Kbyte address space.
oprx8 = Any label or expression that evaluates to an unsigned 8-bit value; used
for indexed addressing
oprx16 = Any label or expression that evaluates to a 16-bit value. Since the
MC68HC08S has a 16-bit address bus, this can be either a signed or an
unsigned value.
rel = Any label or expression that refers to an address that is within –128 to
+127 locations from the next address after the last byte of object code for
the current instruction. The assembler will calculate the 8-bit signed
offset and include it in the object code for this instruction.
Address Modes
INH = Inherent (no operands)
IMM = 8-bit or 16-bit immediate
DIR = 8-bit direct
EXT = 16-bit extended
IX = 16-bit indexed no offset
IX+ = 16-bit indexed no offset, post increment (CBEQ and MOV only)
IX1 = 16-bit indexed with 8-bit offset from H:X
IX1+ = 16-bit indexed with 8-bit offset, post increment (CBEQ only)
IX2 = 16-bit indexed with 16-bit offset from H:X
REL = 8-bit relative offset
SP1 = Stack pointer relative with 8-bit offset
SP2 = Stack pointer relative with 16-bit offset
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Table 2. Instruction Set Summ ar y (Sheet 1 o f 8)
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Source
Form
ADC #opr8i
ADC opr8a
ADC opr16a
ADC oprx16,X
ADC oprx8,X
ADC ,X
ADC oprx16,SP
ADC oprx8,SP
ADD #opr8i
ADD opr8a
ADD opr16a
ADD oprx16,X
ADD oprx8,X
ADD ,X
ADD oprx16,SP
ADD oprx8,SP
AIS #opr8i
AIX #opr8i
AND #opr8i
AND opr8a
AND opr16a
AND oprx16,X
AND oprx8,X
AND ,X
AND oprx16,SP
AND oprx8,SP
ASL opr8a
ASLA
ASLX
ASL oprx8,X
ASL ,X
ASL oprx8,SP
ASR opr8a
ASRA
ASRX
ASR oprx8,X
ASR ,X
ASR oprx8,SP
BCC rel Branch if Carry Bit Clear Branch if (C) = 0 ––––––REL 24 rr 3
Operation Description
Add with Carry A ← (A) + (M) + (C)
Add wit hout Carry A ← (A) + (M)
Add Immediate Value
(Signed) to Stack Pointer
Add Immediate Value
(Signed) to Index
Register (H:X)
Logical AND A ← (A) & (M) 0 ––
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right
M is sign extended to a 16-bit value
M is sign extended to a 16-bit value
SP ← (SP) + (M)
H:X ← (H:X) + (M)
C
b7
b7
0
b0
C
b0
on CCR
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
IMM
DIR
EXT
IX2
IX1
IX
SP2
SP1
DIR
INH
INH
IX1
IX
SP1
DIR
INH
INH
IX1
IX
SP1
Mode
Address
Opcode
A9
B9
C9
D9
E9
F9
9ED9
9EE9
AB
BB
CB
DB
EB
FB
9EDB
9EEB
A4
B4
C4
D4
E4
F4
9ED4
9EE4
38
48
58
68
78
9E68
37
47
57
67
77
9E67
Operand
ii
dd
hh ll
ee ff
ff
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
ii
dd
hh ll
ee ff
ff
ee ff
ff
dd
ff
ff
dd
ff
ff
VH INZC
–
–
––––––IMM A7 ii 2
––––––IMM AF ii 2
–
––
––
Effect
Cycles
2
3
4
4
3
2
5
4
2
3
4
4
3
2
5
4
2
3
4
4
3
2
5
4
4
1
1
4
3
5
4
1
1
4
3
5
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