Freescale Semiconductor M5407C3 User Manual

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M5407C3 User's Manual

M5407C3UM/D

Rev. 1.1, 8/2000

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Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor pro ducts are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

[e-mail]

USA/Europe or Locations Not Listed:

Freescale Semiconductor
Technical Information Center, CH370
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[phone] or [phone]
[e-mail]

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Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
[phone] (English)
[phone] (English)
[phone] (German)
[phone] (French)
[e-mail]

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Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
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Japan
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For Literature Requests Only:

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P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: [phone]
[e-mail]

© Motorola Inc., 2000. All rights reserved.

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Matrix Design warrants this product against defects in material and workmanship for
a period of sixty (60) days from the original date of purchase.

to the original customer only and is in lieu of all other warrants, including
implied warranties of merchantability and fitness.

liable for any incidental or consequential damages. During the warranty period,
Matrix Design will replace, at no charge, components that fail, provided the product
is returned (properly packed and shipped prepaid) to Matrix Design at address below.
Dated proof of purchase (such as a copy of the invoice) must be enclosed with the
shipment. We will return the shipment prepaid via UPS.

This warranty does not apply if, in the opinion of Matrix Design, the product has been
damaged by accident, misuse, neglect, misapplication, or as a result of service or
modification (other than specified in the manual) by others.

Please send the board and cables with a complete description of the problem to:

LIMITED W ARRANTY

This warranty extends

In no event will the seller be

Matrix Design & Manufacturing, Inc.

2914 Montopolis Drive #290

Austin, TX 78741

Phone: [phone]

Fax: [phone]

http://www.cadreiii.com

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This board generates, uses, and can radiate radio frequency energy and, if not installed
properly , may cause interference to radio communications. As temporarily permitted
by regulation, it has not been tested for compliance with the limits for class a
computing devices pursuant to Subpart J of Part 15 of FCC rules, which are designed
to provide reasonable protection against such interference. Operation of this product
in a residential area is likely to cause interference, in which case the user, at his/her
own expense, will be required to correct the interference.

WARNING

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CONTENTS

Paragraph
Number

Title

Chapter 1

M5407C3 Board

1.1 General Hardware Description ........................................................................... 1-1

1.2 System Memory.................................................................................................. 1-4

1.3 Serial Communication Channels......................................................................... 1-4

1.4 Parallel I/O Ports................................................................................................. 1-4

1.5 Programmable Timer/Counter............................................................................ 1-5

1.6 PCI Controller..................................................................................................... 1-5

1.7 On Board Ethernet .............................................................................................. 1-5

1.8 System Configuration ......................................................................................... 1-5

1.9 Installation And Setup......................................................................................... 1-7

1.9.1 Unpacking....................................................................................................... 1-7

1.9.2 Preparing the Board for Use ........................................................................... 1-7

1.9.3 Providing Power to the Board......................................................................... 1-8

1.9.4 Selecting Terminal Baud Rate........................................................................ 1-8

1.9.5 The Terminal Character Format ..................................................................... 1-8

1.9.6 Connecting the Terminal ................................................................................ 1-8

1.9.7 Using a Personal Computer as a Terminal...................................................... 1-8

1.10 System Power-up and Initial Operation............................................................ 1-11

1.11 M5407C3 Jumper Setup ................................................................................... 1-11

1.12 Using The BDM Port........................................................................................ 1-13

Chapter 2

Using the Monitor/Debug Firmware

Page

Number

2.1 What Is dBUG?................................................................................................... 2-1

2.2 Operational Procedure ........................................................................................ 2-3

2.2.1 System Power-up............................................................................................ 2-3

2.2.2 System Initialization....................................................................................... 2-4

2.2.2.1 Hard RESET Button. .................................................................................. 2-5

2.2.2.2 ABORT Button........................................................................................... 2-5

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Paragraph
Number

2.5 TRAP #15 Functions ........................................................................................ 2-39

2.5.1 OUT_CHAR................................................................................................. 2-39

2.5.2 IN_CHAR..................................................................................................... 2-39

2.5.3 CHAR_PRESENT........................................................................................ 2-40

2.5.4 EXIT_TO_dBUG.......................................................................................... 2-40

CONTENTS

Title

Page

Number

Chapter 3

Hardware Description and Reconfiguration

3.1 The Processor and Support Logic....................................................................... 3-1

3.1.1 Processor......................................................................................................... 3-1

3.1.2 Reset Logic..................................................................................................... 3-1

3.1.3 HIZ Signal....................................................................................................... 3-2

3.1.4 Clock Circuitry ............................................................................................... 3-2

3.1.5 Watchdog Timer............................................................................................. 3-2

3.1.6 Interrupt Sources............................................................................................. 3-2

3.1.7 Internal SRAM................................................................................................ 3-3

3.1.8 The MCF5407 Registers and Memory Map................................................... 3-4

3.1.9 Reset Vector Mapping.................................................................................... 3-5

3.1.10 TA Generation ................................................................................................ 3-5

3.1.11 Wait State Generator....................................................................................... 3-6

3.1.12 SDRAM DIMM.............................................................................................. 3-6

3.1.13 Flash ROM...................................................................................................... 3-7

3.1.14 JP15 Jumper and User’s Program................................................................... 3-7

3.2 Serial Communication Channels......................................................................... 3-7

3.2.1 MCF5407 UARTs........................................................................................... 3-7

3.2.2 I2C Module..................................................................................................... 3-8

3.3 Real-Time Clock................................................................................................. 3-8

3.4 Parallel I/O Port .................................................................................................. 3-8

3.5 On-Board Ethernet Logic.................................................................................... 3-8

3.6 Connectors and Expansion Bus ........................................................................ 3-11

3.6.1 Expansion Connectors - J1 and J2................................................................ 3-11

3.6.2 The Debug Connector J5 .............................................................................. 3-13

Appendix A

Configuring dBUG for Network Downloads

Appendix B

ColdFire to ISA, IRQ7 and Reset Logic Abel Code

Appendix C

M5407C3 User’s Manual

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Paragraph
Number

CONTENTS

Title

Page

Number

SDRAM MUX PAL Equation

Appendix D

Evaluation Board BOM

Appendix E Schematics

Appendix F

Errata

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CONTENTS

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ILLUSTRATIONS

Figure
Number

1-1 5407 Block Diagram..................................................................................................... 1-3

1-2 Minimum System Configuration .................................................................................. 1-6

1-3 Pin assignment for female P4 (Terminal) connector. ................................................... 1-9

1-4 Jumper Locations........................................................................................................ 1-10

2-1 Flow Diagram of dBUG Operational Mode. ................................................................ 2-4

3-1 The J5 Connector pin assignment............................................................................... 3-14

Title

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Figure
Number

ILLUSTRATIONS

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TABLES

Table
Number

1-1 Power Supply Connections........................................................................................... 1-8

1-2 Jumper Settings........................................................................................................... 1-11

1-3 Jumper Settings........................................................................................................... 1-13

1-4 Jumper Settings........................................................................................................... 1-13

2-1 dBUG Command Summary.......................................................................................... 2-7

3-1 The M5407C3 Memory Map........................................................................................ 3-5

3-2 J1 Connector Pin Assignment..................................................................................... 3-11

3-3 J2 Connector pin assignment......................................................................................3-12

D-1 MCF5407EVM_BOM.................................................................................................D-1

Title

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Table
Number

TABLES

Title

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Number

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Chapter 1
M5407C3 Board

The M5407C3 is a versatile single board computer based on MCF5407 ColdFire®
Processor. It may be used as a powerful microprocessor based controller in a variety of
applications. With the addition of a terminal, it serves as a complete microcomputer for
reference, development/evaluation, training and educational use. The user need only
connect an RS-232 compatible terminal (or a personal computer with terminal emulation
software) and power supply to have a fully functional system.

Provisions have been made to connect this board to additional user supplied peripherals, via
the Microprocessor Expansion Bus connectors, to expand memory and I/O capabilities.
Additional peripherals may require bus buffers to minimize additional bus loading.

Furthermore, provisions have been made in the PC-board to permit configuration of the
board in a way, which best suits, an application. Options available are: upgrade to
512MBytes SDRAM, 512K SRAM, and commercially available slave PCI devices.

1.1 General Hardware Description

The M5407C3 board provides the RAM, Flash ROM, on board NE2000 compatible
Ethernet interface (10M bit/sec), RS232, and all the built-in I/O functions of the MCF5407
for learning and evaluating the attrib utes of the microprocessor . The MCF5407 is a member
of the ColdFire® family of processors. It is a 32-bit processor with 32-bit of address bus
and 32 lines of data. The processor has eight 32-bit data registers, eight 32-bit address
registers, a 32-bit program counter, and a 16-bit status register.

The MCF5407 has a System Integration Module referred to as the SIM. The module
incorporates many of the functions needed for system design. These include programmable
chip-select logic, System Protection logic, General purpose I/O, and Interrupt controller
logic. The chip-select logic can select up to eight memory banks and peripherals in addition
to two banks of DRAM’s. The chip-select logic also allows programmable number of
wait-states to allow the use of slower memory (refer to
Freescale for detailed information about the SIM.). The M5407C3 uses four (CS[3:0]) of
the eight chip selects to access the Flash ROM’s (CS0), PCI bridge chip (CS1), SRAM

MCF5407 User's Manual by

Chapter 1. M5407C3 Board 1-1

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General Hardware Description

to the user.
The M5407C3 will work with most PC100 SDRAM DIMMs with a few exceptions. The

MCF5407 supports up to two banks of SDRAM, but double-sided DIMMs require 4 bank
selects to access all of the chips. Therefore when using double-sided DIMMs only half of
the available memory will be accessible. Since DIMMs are manuf actured primarily for use
in PCs the DQM signals on some DIMMS are routed so that the SDRAM can only be
accessed correctly as a 64-bit port so the M5407C3 will not be able to access the SDRAM
correctly.

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Figure 1-1 shows the 5407 block diagram.

General Hardware Description

(1) DB-9

(1) RS232

drivers

(1) RS232

drivers

(1) DB-9

Expansion Connector#1
Expansion Connector#2

Osc.

EEPROM

Osc.

PCI slot

PCI Interface

PAL

Davicom
10 Mb/sec

RJ45 Connector

ColdFire® MCF5407

data[31:0]

External

Data

Bus

addr[31:0]

Buffers

External
Address

Bus

Debug
Module

Control Signals

Control Signals

26-pin debug connector

Bus Clk Drv

512KB Sync
FSRAM
32 bit 3.3V

(not populated)

Flash
16 bit
1MB minimum

Real TIme
Clock

Osc.

SDRAM
External

Mux (PAL)

SDRAM
32bit 3.3V

Osc.

Figure 1-1. 5407 Block Diagram

Chapter 1. M5407C3 Board 1-3

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System Memory

1.2 System Memory

One on board Flash ROM (U12) is used to store the M5407C3 dBUG debugger/monitor
firmware in the lower 128 KBytes. The AM29PL160C-XX device is 16Mbits (16 bit by 1
MByte) giving a total of 2MBytes of Flash memory.

The PCI bridge chip provides the interface to the Universal 32-bit PCI on board connector
allowing the user to experiment and develop new applications to commercially available
slave PCI based peripherals products.

The MCF5407 has 4KBytes of internal SRAM organized as two independently
configurable 2 Kbyte blocks. each block can be configured for either data or instruction
space.

There is one 168-pin DIMM socket for SDRAM. System ships with 1M x 8 Bank x 16-Bits
SDRAM totaling 16M of volatile memory. Various SDRAM configurations are supported.

The internal caches of the MCF5407 are non-blocking. The data cache is 8 KByte, 4-way
set-associative with a 16-byte line size. The instruction cache is 16 KBytes, 4-way
set-associative with a 16-byte line size. The ROM Monitor currently does not utilize the
caches, but programs downloaded with the ROM Monitor can use the cache.

The M5407C3 evaluation board has a foot print for 512 KByte SRAM but is unpopulated.

1.3 Serial Communication Channels

The MCF5407 has 2 built-in UART’s (UART0 and UART1) with independent baud rate
generators. The signals of both channels are passed through external Driver/Receivers to
make the channel compatible with RS-232. An RS232 serial cable with DB9 connectors is
included. UART0 (P4) is used by the debugger for the user to access with a terminal. In
addition, the signals of both channels are available on the 120 pin expansion connector J2.
UART0 channel is the “TERMINAL” channel used by the debugger for communication
with external terminal/PC. The “TERMINAL’ baud rate defaults to 19200.

1.4 Parallel I/O Ports

MCF5407 offers one 16-bit general-purpose parallel I/O port. Each pin can be individually
programmed as input or output. The parallel port bits PP[7:0] are multiplexed with
TT[1:0], TM[2:0], DREQ[1:0], and XTIP. The second set of parallel port bits PP[15:8] is
multiplexed with address bus bits A[31:24]. Both bytes of the parallel port are controlled
by the Pin Assignment Register (PAR). The pins are programmable on a pin by pin basis.
The setting of the multiplexed pins is determined by the configuration byte during reset.
After reset, PP[7:0] are configured as parallel port output pins and the PP[15:8] are
configured as A[31:24]. PP[7:4] are general purpose outputs and PP[3:0] are used by the
ROM Monitor to automatically configure the SDRAM address lines via the U27 mux.

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Programmable Timer/Counter

1.5 Programmable Timer/Counter

The MCF5407 has two built in general purpose timer/counters. These timers are available
to the user . The signals for each timer are a v ailable on the 120 pin e xpansion connector J2.

1.6 PCI Controller

The MCF5407 connects to the PCI controller (U17) via the PCI host interface. The PCI
controller is configured for master mode. U18 contains the arbitration logic for the PCI bus.
This logic is such that the PCI controller (U17) defaults to allowing the 5407 bus
mastership. A PCI card wishing to arbitrate the bus away from the controller must use
signal REQ# to request the bus. U18 will then arbitrate the bus away from U17 and assert
GNT# to the PCI card to show that the card has been granted the bus. Similarly the
controller can arbitrate the bus back using signals /REQ and /GNT . By default the controller
currently has priority over the card in the equations in U18, if the user wanted to alter this
priority they could do so by editing file "ISA5407.abl" available on the ColdFire website
(www.mot.com/coldfire).

1.7 On Board Ethernet

The M5407C3 has an on board Ethernet (NE2000 compatible controller) operating at 10M
bits/sec. The on board dBUG ROM monitor is programmed to allow a user to download
files from a network to memory in different formats. The current compiler formats
supported are S-Record, COFF, ELF, or Image. Refer to Appenix A for details on how to
configure.

1.8 System Configuration

The M5407C3 board requires only the following items for minimum system configuration:

• The M5407C3 board (provided).

• Power supply, 7V to 14V DC with minimum of 1.0 Amp.

• RS-232C compatible terminal or a PC with terminal emulation software.

• RS-232 Communication cable (provided).

Refer to Section 2.2.2, “System Initialization” for initial setup.

Chapter 1. M5407C3 Board 1-5

System Configuration

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Figure 1-2 displays minimum system configuration.

dBUG>

RS-232 Terminal

Or PC

+7.0 to +14VDC

Input Power

BDM
Conne ctor

1-6

Figure 1-2. Minimum System Configuration

M5407C3 User’s Manual

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Installation And Setup

1.9 Installation And Setup

The following sections describe all the steps needed to prepare the board for operation.
Please read the following sections carefully before using the board. When you are
preparing the board for the first time, be sure to check that all jumpers are in the default
locations. Default marking are on the board next to the individual jumpers and a master
jumper table is on the underside of the board. After the board is functional in its default
mode, you may use the Ethernet by following the instructions provided in Appendix A.

1.9.1 Unpacking

Unpack the computer board from its shipping box. Save the box for storing or reshipping.
Refer to the following list and verify that all the items are present. You should have
received:

• M5407C3 Single Board Computer

• M5407C3 User's Manual, this documentation

• One RS-232 communication cable

• One debug wiggler cable

• Programmers Reference Manual

• A selection of Third Party Developer Tools and Literature

NOTE:

Avoid touching the mos devices. Static discharge can and will
damage these devices.

Once you verified that all the items are present, remove the board from its protecti ve jack et.
Check the board for any visible damage. Ensure that there are no broken, damaged, or
missing parts. If you have not received all the items listed above or they are damaged,
please contact Matrix Design immediately.

1.9.2 Preparing the Board for Use

The board as shipped is ready to be connected to a terminal and the power supply without
any need for modification. Howe ver , follow the steps below to insure proper operation from
the first time you apply the power. Figure 3 Jumper Table and Locations shows the
placement of the jumpers and the connectors, which you need to refer to in the following
sections. The steps to be taken are:

a) Connecting the power supply.
b) Connecting the terminal.

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Installation And Setup

1.9.3 Providing Power to the Board

The board accepts two means of power supply connections. Connector P6 is a 2.1mm
power jack and P3 lever actuated connector. The board accepts 7V to 14V DC at 1.5 Amp
via either one of the connectors.

Table 1-1. Power Supply Connections

Contact Number Voltage

1 +7–14V DC
2 Ground

1.9.4 Selecting Terminal Baud Rate

The serial channel of MCF5407 which is used for serial communication has a built in timer
used by the dBUG ROM monitor to generate the baud rate used to communicate with a
terminal.. It can be programmed to a number of baud rates. After the power -up or a manual
RESET, the dBUG ROM monitor firmware configures the channel for 19200 baud. After
the dBUG ROM monitor is running, you may issue the SET command to choose any baud
rate supported by the dBUG ROM monitor. Refer to Chapter 2 for the discussion of this
command.

1.9.5 The Terminal Character Format

The character format of the communication channel is fixed at the power-up or RESET.
The character format is 8 bits per character, no parity, and one stop bit. You need to insure
that your terminal or PC is set to this format.

1.9.6 Connecting the Terminal

The board is now ready to be connected to a terminal. Use the RS-232 male/female DB-9
serial cable to connect the PC to the M5407C3. The cable has a 9-pin female D-sub
terminal connector at one end and a 9-pin male D-sub connector at the other end. Connect
the 9-pin male connector to P4 connector on M5407C3. Connect the 9-pin female
connector to one of the available serial communication channels normally referred to as
COM1 (COM2, etc.) on the IBM PC’s or compatible. Depending on the kind of serial
connector on the back of your PC, the connector on your PC may be a male 25-pin or 9-pin.
You may need to obtain a 9-pin-to-25-pin adapter to make the connection. If you need to
build an adapter , refer to Figure 2 which shows the pin assignment for the 9-pin connector
on the board.

1.9.7 Using a Personal Computer as a Terminal

You may use your personal computer as a terminal provided you also have a terminal
emulation software such as PROCOMM, KERMIT, QMODEM, Windows 95/98/2000

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Installation And Setup

Hyper Terminal or similar packages. Then connect as described in 1.9.6, “Connecting the
Terminal.”

Once the connection to the PC is made, you are ready to power-up the PC and run the
terminal emulation software. When you are in the terminal mode, you need to select the
baud rate and the character format for the channel. Most terminal emulation software
packages provide a command known as "Alt-p" (press the p ke y while pressing the Alt k ey)
to choose the baud rate and character format. Make sure you select 8 bits, no parity, one
stop bit, see section The Terminal Character Format. Then, select the baud rate as 19200.
Now you are ready to apply power to the board.

Figur 1-3 shows pin assignments for female terminal connector.

5

Figure 1-3. Pin assignment for female P4 (Terminal) connector.

1

69

Pin assignments are as follows.

1. Data Carrier Detect, Output (shorted to pins 4 and 6).

2. Receive Data, Output from board (receive refers to terminal side).

3. Transmit Data, Input to board (transmit refers to terminal side).

4. Data Terminal Ready, input (shorted to pin 1 and 6).

5. Signal Ground.

6. Data Set Ready, Output (shorted to pins 1 and 4).

7. Request to Send, input.

8. Clear to send, output.

9. Not connected.

Figure 1-4 shows jumper locations.

Chapter 1. M5407C3 Board 1-9

Installation And Setup

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1-10

Figure 1-4. Jumper Locations

M5407C3 User’s Manual

System Power-up and Initial Operation

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1.10 System Power-up and Initial Operation

Now that you hav e connected all the cables, you may apply power to the board. After power
is applied, the dBUG initializes the board then displays the power-up message on the
terminal, which includes the amount of memory present.

Hard Reset
DRAM Size: 32M

Copyright 1995-2000 Motorola, Inc. All Rights Reserved.
ColdFire MCF5407 EVS Firmware v2e.1a.1a (Build XXX on XXX XX 20XX
17:27:52)

Enter 'help' for help.

dBUG>

The board is now ready for operation under the control of the debugger as described in
Chapter 2. If you do not get the above response, perform the following checks:

1. Make sure that the power supply is properly configured for polarity, voltage level,
and current capability (~1A) and is connected to the board.

2. Check that the terminal and board are set for the same character format and baud.

3. Press the RESET button to insure that the board has been initialized properly.

If dBUG does not come up try removing power from the board and then powering up the
board with the SDRAM DIMM removed. The LEDs (D1-D8) should flash indicating that
there is a problem with the serial cable, terminal, or SDRAM jumpers.

If you still are not receiving the proper response, your board may have been damaged in
shipping. Contact Matrix Design for further instructions.

1.11 M5407C3 Jumper Setup

Jumper settings are as follows:
Note ‘*’ is used to indicate that default setting.

‘**’ is used to indicate mandatory setting for proper operation.

Table 1-2. Jumper Settings

Jumper Function

JP1 * ON LED D10 driven by TOUT0

OFF LED D10 NOT driven by TOUT0

JP2 * ON LED D9 driven by TOUT1

Chapter 1. M5407C3 Board 1-11

M5407C3 Jumper Setup

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Jumper Function

On/On/x Reserved --­On/Off/On Reserved --­On/Off/Off *1/3 40.0–54.0/120.0–162 MHz
Off/On/On 1/4 25.0–40.5/100.0–162 MHz
Off/On/Off 1/5 25.0–32.4/125.0–162 MHz
Off/Off/On 1/6 25.0–27.0/150.0–162 MHz
Off/Off/Off Reserved ---

Table 1-2. Jumper Settings (Continued)

JP6/D[3]/
BE[3:0] CONF

JP7/D[4]/
ADDR_CONF

JP9/D[6]/PS1 JP8/D[5]/PS0 Boot CS0 Port Size at Reset
ON / 0 ON / 0 32-bit Port
ON / 0 OFF / 1 8-bit Port
OFF / 1 ON / 0 16-bit Port
* OFF / 1 * OFF / 1 16-bit Port
JP10/D[7]/AA ON / 0 Boot CS0 Auto Acknowledge (AA) DISABLED

JP11 * ON EVCC (+3.3V) Power to ColdFire MCF5407 I/O
JP12 ** ON IVCC (+1.8V) Power to ColdFire MCF5407 core
JP13 * ON Pull up enabled on !DREQ1 / PP[5]
JP14 * ON Pull up enabled on !DREQ0 / PP[6]
JP15 * 1-2 Boot ROM Monitor from Flash

JP16 * 1-2 Enable writes to PCI EEPROM

JP17 * 1-2 +3.3 V to J5 Debug Header Pin 9

ON / 0 BE[3:0] is enabled as byte write enables only

* OFF / 1 BE[3:0] is enabled as byte enables for reads & write
ON / 0 PP[15:0], defaulted to inputs upon reset

* OFF / 1 ADDR[31:24]/TIP/DREQ[1:0]/TM[2:1]

* OFF / 1 Boot CS AA Enabled with 15 wait states

2-3 Boot User Code from user Flash Space

1

2-3 Disable writes to PCI EEPROM

2-3 +1.8 V to J5 Debug Header Pin 9

1

JP18 ** 1-2 Default Clocking

2-3 Alternate Clocking

JP19 ** OFF Default Clocking

ON Alternate Clocking

JP20 ** 1-2 Default Core Power (+1.8V)

2-3 Alternate Core Power (+3.3V)

1

JP16 functionality is opposite that of the silkscreen. The table is correct.

1-12 M5407C3 User’s Manual

Using The BDM Port

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Table 1-3. Jumper Settings

JP21 JP22 JP23 JP24 Function
* 1-2 * 1-2 * 1-2 * 1-2 Driven by PP[3:0]
2-3 2-3 2-3 2-3 8 col, 11 row
OFF 2-3 2-3 2-3 9 col, 11 row
2-3 OFF 2-3 2-3 10 col, 11 row
OFF OFF 2-3 2-3 8 col, 12 row
2-3 2-3 OFF 2-3 9 col, 12 row
OFF 2-3 OFF 2-3 10 col, 12 row
2-3 OFF OFF 2-3 11 col, 12 row
OFF OFF OFF 2-3 8 col, 13 row
2-3 2-3 2-3 OFF 9 col, 13 row
OFF 2-3 2-3 OFF 10 col, 13 row
2-3 OFF 2-3 OFF 11 col, 13 row

Table 1-4. Jumper Settings

Jumper Function

1

JP25
JP26 * 1-2 +3.3 V to J5 Debug Header Pin 25

JP27 * 1-2 ColdFire CS1 used on PCI !SELECT

JP28 * 1-2 ColdFire Normal/BDM Mode

1

JP29
JP30 * 1-2 STROBE signal on PCI controller tied to GND

1

The settings for JP25 and JP29 differ from those given on the back of the silkscreen. The settings
listed in this table are correct.

*ON Enable serial clock SCL to PCI EEPROM

2-3 +1.8 V to J5 Debug Header Pin 25

2-3 ColdFire !A31 used on PCI !SELECT

2-3 ColdFire Normal/JTAG Mode
*ON Enable serial data SDA to PCI EEPROM

2-3 STROBE signal on PCI controller tied to !TS

1.12 Using The BDM Port

The MCF5407 has a built in debug mechanism referred to as BDM (background debug
module). The M5407C3 has the Freescale defined debug module connector , J5, to facilitate
this connection.

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Using The BDM Port

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In order to use the BDM, simply connect the 26-pin connector at the end of the BDM
wiggler cable provided Freescale from P&E Microcomputer Systems to the J5 connector.
No special setting is needed. Refer to the ColdFire® User's Manual BDM Section for
additional instructions.

NOTE:

BDM functionality and use is supported via third party
developer software and hardware tools.

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Chapter 2
Using the Monitor/Debug Firmware

The M5407C3 single board computer has a resident firmware package that provides a
self-contained programming and operating environment. The firmware, named dBUG,
provides the user with monitor/debug interface, inline assembler and disassembly, program
download, register and memory manipulation, and I/O control functions. This Chapter is a
how-to-use description of the dBUG package, including the user interface and command
structure.

2.1 What Is dBUG?

dBUG is a traditional ROM monitor/debugger that offers a comfortable and intuitive
command line interface that can be used to download and execute code. It contains all the
primary features needed in a debugger to create a useful debugging environment.

dBUG is a resident firmware package for the ColdFire® family single board computers.
The firmware (stored in one 1Mx16 Flash ROM device) provides a self-contained
programming and operating environment. dBUG interacts with the user through
pre-defined commands that are entered via the terminal. These commands are defined in
Section 2.4, “Commands.”

The user interface to dBUG is the command line. A number of features have been
implemented to achieve an easy and intuitive command line interface.

dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the
debugger. For serial communications, dBUG requires eight data bits, no parity, and one
stop bit, 8N1. The default baud rate is 19200 but can be changed after the power-up.

The command line prompt is “dBUG> “. Any dBUG command may be entered from this
prompt. dBUG does not allow command lines to exceed 80 characters. Where ver possible,
dBUG displays data in 80 columns or less. dBUG echoes each character as it is typed,
eliminating the need for any “local echo” on the terminal side.

In general, dBUG is not case sensitive. Commands may be entered either in upper or lo wer
case, depending upon the user’s equipment and preference. Only symbol names require

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Most commands can be recognized by using an abbreviated name. For instance, entering
“h” is the same as entering “help”. Thus, it is not necessary to type the entire command
name.

The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging.
dBUG recognizes this and allows for repeated execution of these commands with minimal
typing. After a command is entered, simply press <RETURN> or <ENTER> to in v oke the
command again. The command is executed as if no command line parameters were
provided.

An additional function called the "TRAP 15 handler" allows the user program to utilize
various routines within dBUG. The TRAP 15 handler is discussed at the end of this chapter .

The operational mode of dBUG is demonstrated in Figure 2-1. After the system
initialization, the board waits for a command-line input from the user terminal. When a
proper command is entered, the operation continues in one of the two basic modes. If the
command causes execution of the user program, the dBUG firmware may or may not be
re-entered, depending on the discretion of the user. For the alternate case, the command
will be executed under control of the dBUG firmw are, and after command completion, the
system returns to command entry mode.

During command execution, additional user input may be required depending on the command function.

For commands that accept an optional <width> to modify the memory access size, the valid values are:

• B8-bit (byte) access

• W16-bit (word) access

• L32-bit (long) access

When no <width> option is provided, the default width is .W, 16-bit.
The core ColdFire® register set is maintained by dBUG. These are listed below:

• A0-A7

• D0-D7

•PC

•SR

All control registers on ColdFire® are not readable by the supervisor-programming model,
and thus not accessible via dBUG. User code may change these registers, but caution must
be exercised as changes may render dBUG inoperable.

A reference to “SP” (stack pointer) actually refers to general purpose address register seven, “A7."

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Operational Procedure

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2.2 Operational Procedure

System power-up and initial operation are described in detail in Chapter 1. This information
is repeated here for convenience and to prevent possible damage.

2.2.1 System Power-up

• Be sure the power supply is connected properly prior to power-up.

• Make sure the terminal is connected to TERMINAL (P4) connector.

• Turn power on to the board.

Chapter 2. Using the Monitor/Debug Firmware 2-3

Operational Procedure

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Figur 2-1shows the dUBG operational mode.

Figure 2-1. Flow Diagram of dBUG Operational Mode.

2.2.2 System Initialization

The act of powering up the board will initialize the system. The processor is reset and
dBUG is invoked.

dBUG performs the following configurations of internal resources during the initialization.

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