Freescale Semiconductor i.MX 6Solo, i.MX 6DualLite Reference Manual
i.MX 6Solo/6DualLite Linux Reference
Manual
Document Number: IMX6SDLLXRM
Rev L3.0.35_4.1.0, 09/2013
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Contents
Section number Title Page
Chapter 1
About This Book
1.1 Audience.......................................................................................................................................................................23
1.1.1 Conventions.....................................................................................................................................................23
1.1.2 Definitions, Acronyms, and Abbreviations......................................................................................................23
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................27
2.1.1 Software Base..................................................................................................................................................27
2.1.2 Features............................................................................................................................................................27
Chapter 3
Machine Specific Layer (MSL)
3.1 Introduction...................................................................................................................................................................33
3.2 Interrupts (Operation)...................................................................................................................................................34
3.2.1 Interrupt Hardware Operation..........................................................................................................................34
3.2.2 Interrupt Software Operation...........................................................................................................................34
3.2.3 Interrupt Features.............................................................................................................................................35
3.2.4 Interrupt Source Code Structure......................................................................................................................35
3.2.5 Interrupt Programming Interface.....................................................................................................................35
3.3 Timer.............................................................................................................................................................................36
3.3.1 Timer Software Operation...............................................................................................................................36
3.3.2 Timer Features.................................................................................................................................................36
3.3.3 Timer Source Code Structure...........................................................................................................................37
3.3.4 Timer Programming Interface..........................................................................................................................37
3.4 Memory Map................................................................................................................................................................37
3.4.1 Memory Map Hardware Operation..................................................................................................................37
3.4.2 Memory Map Software Operation...................................................................................................................37
3.4.3 Memory Map Features.....................................................................................................................................37
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3.4.4 Memory Map Source Code Structure..............................................................................................................38
3.4.5 Memory Map Programming Interface.............................................................................................................38
3.5 IOMUX.........................................................................................................................................................................38
3.5.1 IOMUX Hardware Operation..........................................................................................................................39
3.5.2 IOMUX Software Operation............................................................................................................................39
3.5.3 IOMUX Features..............................................................................................................................................40
3.5.4 IOMUX Source Code Structure.......................................................................................................................40
3.5.5 IOMUX Programming Interface......................................................................................................................40
3.5.6 IOMUX Control Through GPIO Module........................................................................................................40
3.5.6.1 GPIO Hardware Operation...............................................................................................................41
3.5.6.1.1 Muxing Control...............................................................................................................41
3.5.6.1.2 PULLUP Control............................................................................................................41
3.5.6.2 GPIO Software Operation (general)................................................................................................41
3.5.6.3 GPIO Implementation......................................................................................................................41
3.5.6.4 GPIO Source Code Structure...........................................................................................................42
3.5.6.5 GPIO Programming Interface..........................................................................................................42
3.6 General Purpose Input/Output(GPIO)..........................................................................................................................42
3.6.1 GPIO Software Operation................................................................................................................................42
3.6.1.1 API for GPIO...................................................................................................................................43
3.6.2 GPIO Features..................................................................................................................................................43
3.6.3 GPIO Module Source Code Structure..............................................................................................................43
3.6.4 GPIO Programming Interface 2.......................................................................................................................44
Chapter 4
Smart Direct Memory Access (SDMA) API
4.1 Overview.......................................................................................................................................................................45
4.1.1 Hardware Operation.........................................................................................................................................45
4.1.2 Software Operation..........................................................................................................................................45
4.1.3 Source Code Structure.....................................................................................................................................46
4.1.4 Menu Configuration Options...........................................................................................................................47
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4.1.5 Programming Interface....................................................................................................................................47
4.1.6 Usage Example................................................................................................................................................47
Chapter 5
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
5.1 Overview.......................................................................................................................................................................49
5.1.1 Hardware Operation.........................................................................................................................................49
5.1.2 Software Operation..........................................................................................................................................50
5.1.3 Source Code Structure.....................................................................................................................................50
5.1.4 Menu Configuration Options...........................................................................................................................51
5.1.5 Programming Interface....................................................................................................................................51
5.1.6 Usage Example................................................................................................................................................51
Chapter 6
Image Processing Unit (IPU) Drivers
6.1 Introduction...................................................................................................................................................................53
6.2 Hardware Operation......................................................................................................................................................55
6.3 Software Operation.......................................................................................................................................................55
6.3.1 Overview of IPU Frame Buffer Drivers..........................................................................................................56
6.3.1.1 IPU Frame Buffer Hardware Operation...........................................................................................57
6.3.1.2 IPU Frame Buffer Software Operation............................................................................................57
6.3.1.3 Synchronous Frame Buffer Driver...................................................................................................58
6.3.2 IPU Backlight Driver.......................................................................................................................................59
6.3.3 IPU Device Driver...........................................................................................................................................59
6.4 Source Code Structure .................................................................................................................................................60
6.4.1 Menu Configuration Options...........................................................................................................................61
6.5 Unit Test........................................................................................................................................................................64
6.5.1 Framebuffer Tests............................................................................................................................................65
6.5.2 Video4Linux API test......................................................................................................................................65
6.5.3 IPU Device Unit test........................................................................................................................................66
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Chapter 7
MIPI DSI Driver
7.1 Introduction...................................................................................................................................................................71
7.1.1 Overview of MIPI DSI IP Driver.....................................................................................................................71
7.1.2 Overview of MIPI DSI Display Panel Driver..................................................................................................72
7.1.3 Hardware Operation.........................................................................................................................................72
7.2 Software Operation.......................................................................................................................................................72
7.2.1 MIPI DSI IP Driver Software Operation.........................................................................................................72
7.2.2 MIPI DSI Display Panel Driver Software Operation.......................................................................................73
7.3 Driver Features..............................................................................................................................................................73
7.3.1 Source Code Structure.....................................................................................................................................74
7.3.2 Menu Configuration Options...........................................................................................................................74
7.3.3 Programming Interface....................................................................................................................................74
Chapter 8
Video for Linux Two (V4L2) Driver
8.1 Introduction...................................................................................................................................................................75
8.2 V4L2 Capture Device...................................................................................................................................................76
8.2.1 V4L2 Capture IOCTLs....................................................................................................................................76
8.2.2 Using the V4L2 Capture APIs.........................................................................................................................78
8.3 V4L2 Output Device.....................................................................................................................................................79
8.3.1 V4L2 Output IOCTLs......................................................................................................................................79
8.3.2 Using the V4L2 Output APIs...........................................................................................................................80
8.4 Source Code Structure .................................................................................................................................................80
8.4.1 Menu Configuration Options...........................................................................................................................81
8.4.2 V4L2 Programming Interface..........................................................................................................................81
Chapter 9
Electrophoretic Display Controller (EPDC) Frame Buffer Driver
9.1 Introduction...................................................................................................................................................................83
9.2 Hardware Operation......................................................................................................................................................84
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9.3 Software Operation.......................................................................................................................................................84
9.3.1 EPDC Frame Buffer Driver Overview.............................................................................................................84
9.3.2 EPDC Frame Buffer Driver Extensions...........................................................................................................85
9.3.3 EPDC Panel Configuration..............................................................................................................................85
9.3.3.1 Boot Command Line Parameters.....................................................................................................86
9.3.4 EPDC Waveform Loading...............................................................................................................................87
9.3.4.1 Using a Default Waveform File.......................................................................................................87
9.3.4.2 Using a Custom Waveform File.......................................................................................................88
9.3.5 EPDC Panel Initialization................................................................................................................................88
9.3.6 Grayscale Framebuffer Selection.....................................................................................................................89
9.3.7 Enabling An EPDC Splash Screen...................................................................................................................89
9.4 Source Code Structure .................................................................................................................................................90
9.5 Menu Configuration Options........................................................................................................................................90
9.6 Programming Interface.................................................................................................................................................91
9.6.1 IOCTLs/Functions...........................................................................................................................................91
9.6.2 Structures and Defines.....................................................................................................................................94
Chapter 10
Pixel Pipeline (PxP) DMA-ENGINE Driver
10.1 Introduction...................................................................................................................................................................97
10.2 Hardware Operation......................................................................................................................................................97
10.3 Software Operation.......................................................................................................................................................97
10.3.1 Key Data Structs..............................................................................................................................................97
10.3.2 Channel Management......................................................................................................................................98
10.3.3 Descriptor Management...................................................................................................................................98
10.3.4 Completion Notification..................................................................................................................................98
10.3.5 Limitations.......................................................................................................................................................99
10.4 Menu Configuration Options........................................................................................................................................99
10.5 Source Code Structure..................................................................................................................................................99
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Chapter 11
Graphics Processing Unit (GPU)
11.1 Introduction...................................................................................................................................................................101
11.1.1 Driver Features.................................................................................................................................................101
11.1.1.1 Hardware Operation.........................................................................................................................101
11.1.1.2 Software Operation..........................................................................................................................102
11.1.1.3 Source Code Structure ....................................................................................................................102
11.1.1.4 Library Structure .............................................................................................................................102
11.1.1.5 API References................................................................................................................................104
11.1.1.6 Menu Configuration Options...........................................................................................................104
Chapter 12
Direct FB
12.1 Introduction...................................................................................................................................................................105
12.1.1 Hardware Operation.........................................................................................................................................105
12.2 Software Operation.......................................................................................................................................................105
12.2.1 DirectFB Acceleration Architecture................................................................................................................106
12.2.2 i.MX DirectFB Driver Details.........................................................................................................................107
12.2.3 The gal_config File for i.MX DirectFB Driver................................................................................................107
12.3 DirectFB EGL...............................................................................................................................................................109
12.4 Setting Up DirectFB Acceleration................................................................................................................................109
Chapter 13
HDMI Driver
13.1 Introduction...................................................................................................................................................................111
13.1.1 Hardware Operation.........................................................................................................................................111
13.2 Software Operation.......................................................................................................................................................113
13.2.1 Core..................................................................................................................................................................113
13.2.2 Video................................................................................................................................................................114
13.2.3 Display Device Registration and Initialization................................................................................................115
13.2.4 Hotplug Handling and Video Mode Changes..................................................................................................116
13.2.5 Audio................................................................................................................................................................116
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13.2.6 CEC..................................................................................................................................................................118
13.3 Source Code Structure..................................................................................................................................................118
13.3.1 Linux Menu Configuration Options.................................................................................................................120
13.4 Unit Test........................................................................................................................................................................121
13.4.1 Video................................................................................................................................................................121
13.4.2 Audio................................................................................................................................................................122
13.4.3 CEC..................................................................................................................................................................122
Chapter 14
X Windows Acceleration
14.1 Introduction...................................................................................................................................................................123
14.2 Hardware Operation......................................................................................................................................................123
14.3 Software Operation.......................................................................................................................................................123
14.3.1 X Windows Acceleration Architecture............................................................................................................124
14.3.2 i.MX 6 Driver for X-Windows System............................................................................................................125
14.3.3 i.MX 6 Direct Rendering Infrastructure (DRI) for X-Windows System.........................................................127
14.3.4 EGL- X Library................................................................................................................................................128
14.3.5 xorg.conf for i.MX 6........................................................................................................................................128
14.3.6 Setup X-Windows System Acceleration..........................................................................................................130
Chapter 15
Video Processing Unit (VPU) Driver
15.1 Hardware Operation......................................................................................................................................................133
15.1.1 Software Operation..........................................................................................................................................134
15.1.2 Source Code Structure.....................................................................................................................................135
15.1.3 Menu Configuration Options...........................................................................................................................136
15.1.4 Programming Interface....................................................................................................................................137
15.1.5 Defining an Application...................................................................................................................................138
Chapter 16
OmniVision Camera Driver
16.1 OV5640 Using MIPI CSI-2 interface...........................................................................................................................139
16.1.1 Hardware Operation.........................................................................................................................................139
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16.1.2 Software Operation..........................................................................................................................................139
16.1.3 Source Code Structure.....................................................................................................................................140
16.1.4 Linux Menu Configuration Options.................................................................................................................140
16.2 OV5640 Using parallel interface..................................................................................................................................141
16.2.1 Hardware Operation.........................................................................................................................................141
16.2.2 Software Operation..........................................................................................................................................141
16.2.3 Source Code Structure.....................................................................................................................................142
16.2.4 Linux Menu Configuration Options.................................................................................................................142
Chapter 17
MIPI CSI2 Driver
17.1 Introduction...................................................................................................................................................................143
17.1.1 MIPI CSI2 Driver Overview............................................................................................................................143
17.1.2 Hardware Operation.........................................................................................................................................144
17.2 Software Operation.......................................................................................................................................................144
17.2.1 MIPI CSI2 Driver Initialize Operation............................................................................................................144
17.2.2 MIPI CSI2 Common API Operation................................................................................................................145
17.3 Driver Features..............................................................................................................................................................145
17.3.1 Source Code Structure.....................................................................................................................................146
17.3.2 Menu Configuration Options...........................................................................................................................146
17.3.3 Programming Interface....................................................................................................................................146
17.3.4 Interrupt Requirements....................................................................................................................................147
Chapter 18
Low-level Power Management (PM) Driver
18.1 Hardware Operation......................................................................................................................................................149
18.1.1 Software Operation..........................................................................................................................................149
18.1.2 Source Code Structure.....................................................................................................................................150
18.1.3 Menu Configuration Options...........................................................................................................................150
18.1.4 Programming Interface....................................................................................................................................151
18.1.5 Unit Test...........................................................................................................................................................151
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Chapter 19
PF100 Regulator Driver
19.1 Introduction...................................................................................................................................................................153
19.2 Hardware Operation......................................................................................................................................................153
19.2.1 Driver Features.................................................................................................................................................154
19.3 Software Operation.......................................................................................................................................................154
19.3.1 Regulator APIs.................................................................................................................................................154
19.4 Driver Architecture.......................................................................................................................................................156
19.4.1 Driver Interface Details....................................................................................................................................157
19.4.2 Source Code Structure.....................................................................................................................................157
19.4.3 Menu Configuration Options...........................................................................................................................157
Chapter 20
CPU Frequency Scaling (CPUFREQ) Driver
20.1 Introduction...................................................................................................................................................................159
20.1.1 Software Operation..........................................................................................................................................159
20.1.2 Source Code Structure.....................................................................................................................................160
20.2 Menu Configuration Options........................................................................................................................................160
20.2.1 Board Configuration Options...........................................................................................................................161
Chapter 21
Dynamic Bus Frequency Driver
21.1 Introduction...................................................................................................................................................................163
21.1.1 Operation..........................................................................................................................................................163
21.1.2 Software Operation..........................................................................................................................................163
21.1.3 Source Code Structure.....................................................................................................................................164
21.2 Menu Configuration Options........................................................................................................................................164
21.2.1 Board Configuration Options...........................................................................................................................164
Chapter 22
Thermal Driver
22.1 Introduction...................................................................................................................................................................165
22.1.1 Thermal Driver Overview................................................................................................................................165
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22.2 Hardware Operation......................................................................................................................................................165
22.2.1 Thermal Driver Software Operation................................................................................................................166
22.3 Driver Features..............................................................................................................................................................166
22.3.1 Source Code Structure.....................................................................................................................................166
22.3.2 Menu Configuration Options...........................................................................................................................166
22.3.3 Programming Interface....................................................................................................................................166
22.3.4 Interrupt Requirements....................................................................................................................................167
22.4 Unit Test........................................................................................................................................................................167
Chapter 23
Anatop Regulator Driver
23.1 Introduction...................................................................................................................................................................169
23.1.1 Hardware Operation.........................................................................................................................................169
23.2 Driver Features..............................................................................................................................................................170
23.2.1 Software Operation..........................................................................................................................................170
23.2.2 Regulator APIs.................................................................................................................................................170
23.2.3 Driver Interface Details....................................................................................................................................171
23.2.4 Source Code Structure.....................................................................................................................................171
23.2.5 Menu Configuration Options...........................................................................................................................171
Chapter 24
SNVS Real Time Clock (SRTC) Driver
24.1 Introduction...................................................................................................................................................................173
24.1.1 Hardware Operation.........................................................................................................................................173
24.2 Software Operation.......................................................................................................................................................173
24.2.1 IOCTL..............................................................................................................................................................173
24.2.2 Keeping Alive in the Power Off State.............................................................................................................174
24.3 Driver Features..............................................................................................................................................................174
24.3.1 Source Code Structure.....................................................................................................................................174
24.3.2 Menu Configuration Options...........................................................................................................................175
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Chapter 25
Advanced Linux Sound Architecture (ALSA) System on a Chip (ASoC) Sound Driver
25.1 ALSA Sound Driver Introduction.................................................................................................................................177
25.2 SoC Sound Card ...........................................................................................................................................................180
25.2.1 Stereo CODEC Features..................................................................................................................................180
25.2.2 7.1 Audio Codec Features................................................................................................................................181
25.2.3 AM/FM Codec Features...................................................................................................................................181
25.2.4 Sound Card Information...................................................................................................................................181
25.3 Hardware Operation......................................................................................................................................................182
25.3.1 Stereo Audio CODEC......................................................................................................................................182
25.3.2 7.1 Audio Codec..............................................................................................................................................183
25.3.3 AM/FM Codec.................................................................................................................................................183
25.4 Software Operation.......................................................................................................................................................183
25.4.1 ASoC Driver Source Architecture...................................................................................................................184
25.4.2 Sound Card Registration..................................................................................................................................185
25.4.3 Device Open.....................................................................................................................................................185
25.4.4 Platform Data...................................................................................................................................................186
25.4.5 Menu Configuration Options...........................................................................................................................186
25.5 Unit Test........................................................................................................................................................................187
25.5.1 Stereo CODEC Unit Test.................................................................................................................................187
25.5.2 7.1 Audio Codec Unit Test..............................................................................................................................188
25.5.3 AM/FM Codec Unit Test.................................................................................................................................189
Chapter 26
Asynchronous Sample Rate Converter (ASRC) Driver
26.1 Introduction...................................................................................................................................................................191
26.1.1 Hardware Operation.........................................................................................................................................191
26.2 Software Operation.......................................................................................................................................................192
26.2.1 Sequence for Memory to ASRC to Memory...................................................................................................193
26.2.2 Sequence for Memory to ASRC to Peripheral.................................................................................................193
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26.3 Source Code Structure..................................................................................................................................................194
26.3.1 Linux Menu Configuration Options.................................................................................................................194
26.4 Platform Data................................................................................................................................................................194
26.4.1 Programming Interface (Exported API and IOCTLs)......................................................................................195
Chapter 27
The Sony/Philips Digital Interface (S/PDIF) Driver
27.1 Introduction...................................................................................................................................................................197
27.1.1 S/PDIF Overview.............................................................................................................................................197
27.1.2 Hardware Overview.........................................................................................................................................198
27.1.3 Software Overview..........................................................................................................................................199
27.1.4 ASoC layer.......................................................................................................................................................199
27.2 S/PDIF Tx Driver..........................................................................................................................................................199
27.2.1 Driver Design...................................................................................................................................................200
27.2.2 Provided User Interface...................................................................................................................................200
27.3 S/PDIF Rx Driver.........................................................................................................................................................201
27.3.1 Driver Design...................................................................................................................................................202
27.3.2 Provided User Interfaces..................................................................................................................................202
27.4 Source Code Structure .................................................................................................................................................204
27.5 Menu Configuration Options........................................................................................................................................205
27.6 Platform Data................................................................................................................................................................205
27.7 Interrupts and Exceptions.............................................................................................................................................206
27.8 Unit Test Preparation....................................................................................................................................................206
27.8.1 Tx test step.......................................................................................................................................................206
27.8.2 Rx test step.......................................................................................................................................................206
Chapter 28
SPI NOR Flash Memory Technology Device (MTD) Driver
28.1 Introduction...................................................................................................................................................................209
28.1.1 Hardware Operation.........................................................................................................................................209
28.1.2 Software Operation..........................................................................................................................................210
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28.1.3 Driver Features.................................................................................................................................................210
28.1.4 Source Code Structure.....................................................................................................................................210
28.1.5 Menu Configuration Options...........................................................................................................................211
Chapter 29
MMC/SD/SDIO Host Driver
29.1 Introduction...................................................................................................................................................................213
29.1.1 Hardware Operation.........................................................................................................................................213
29.1.2 Software Operation..........................................................................................................................................214
29.2 Driver Features..............................................................................................................................................................216
29.2.1 Source Code Structure.....................................................................................................................................217
29.2.2 Menu Configuration Options...........................................................................................................................217
29.2.3 Platform Data...................................................................................................................................................218
29.2.4 Programming Interface....................................................................................................................................218
29.2.5 Loadable Module Operations...........................................................................................................................219
Chapter 30
NAND GPMI Flash Driver
30.1 Introduction...................................................................................................................................................................221
30.1.1 Hardware Operation.........................................................................................................................................221
30.2 Software Operation.......................................................................................................................................................221
30.2.1 Basic Operations: Read/Write..........................................................................................................................222
30.2.2 Error Correction...............................................................................................................................................222
30.2.3 Boot Control Block Management....................................................................................................................222
30.2.4 Bad Block Handling.........................................................................................................................................223
30.3 Source Code Structure..................................................................................................................................................223
30.3.1 Menu Configuration Options...........................................................................................................................223
Chapter 31
Inter-IC (I2C) Driver
31.1 Introduction...................................................................................................................................................................225
31.1.1 I2C Bus Driver Overview................................................................................................................................225
31.1.2 I2C Device Driver Overview...........................................................................................................................226
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31.1.3 Hardware Operation.........................................................................................................................................226
31.2 Software Operation.......................................................................................................................................................226
31.2.1 I2C Bus Driver Software Operation.................................................................................................................226
31.2.2 I2C Device Driver Software Operation...........................................................................................................227
31.3 Driver Features..............................................................................................................................................................227
31.3.1 Source Code Structure.....................................................................................................................................228
31.3.2 Menu Configuration Options...........................................................................................................................228
31.3.3 Programming Interface....................................................................................................................................228
31.3.4 Interrupt Requirements....................................................................................................................................228
Chapter 32
Enhanced Configurable Serial Peripheral Interface (ECSPI) Driver
32.1 Introduction...................................................................................................................................................................231
32.1.1 Hardware Operation.........................................................................................................................................231
32.2 Software Operation.......................................................................................................................................................232
32.2.1 SPI Sub-System in Linux.................................................................................................................................232
32.2.2 Software Limitations........................................................................................................................................233
32.2.3 Standard Operations.........................................................................................................................................233
32.2.4 ECSPI Synchronous Operation........................................................................................................................234
32.3 Driver Features..............................................................................................................................................................236
32.3.1 Source Code Structure.....................................................................................................................................236
32.3.2 Menu Configuration Options...........................................................................................................................236
32.3.3 Programming Interface....................................................................................................................................236
32.3.4 Interrupt Requirements....................................................................................................................................237
Chapter 33
FlexCAN Driver
33.1 Driver Overview...........................................................................................................................................................239
33.1.1 Hardware Operation.........................................................................................................................................239
33.1.2 Software Operation..........................................................................................................................................239
33.1.3 Source Code Structure.....................................................................................................................................239
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33.1.4 Linux Menu Configuration Options.................................................................................................................240
Chapter 34
Media Local Bus Driver
34.1 Introduction...................................................................................................................................................................241
34.1.1 MLB Device Module.......................................................................................................................................241
34.1.2 Supported Feature............................................................................................................................................242
34.1.3 Modes of Operation.........................................................................................................................................243
34.1.4 MLB Driver Overview.....................................................................................................................................243
34.2 MLB Driver..................................................................................................................................................................243
34.2.1 Supported Features...........................................................................................................................................243
34.2.2 MLB Driver Architecture.................................................................................................................................243
34.2.3 Software Operation..........................................................................................................................................245
34.3 Driver Files...................................................................................................................................................................246
34.4 Menu Configuration Options........................................................................................................................................246
Chapter 35
ARC USB Driver
35.1 Introduction...................................................................................................................................................................247
35.1.1 Architectural Overview....................................................................................................................................247
35.2 Hardware Operation......................................................................................................................................................248
35.2.1 Software Operation..........................................................................................................................................248
35.2.2 Source Code Structure.....................................................................................................................................249
35.2.3 Menu Configuration Options...........................................................................................................................250
35.2.4 Programming Interface....................................................................................................................................253
35.3 System WakeUp............................................................................................................................................................253
35.3.1 USB Wakeup usage.........................................................................................................................................253
35.3.2 How to Enable USB WakeUp System Ability.................................................................................................253
35.3.3 WakeUp Events Supported by USB................................................................................................................254
35.3.4 How to Close the USB Child Device Power....................................................................................................255
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Chapter 36
i.MX 6 PCI Express Root Complex Driver
36.1 Introduction...................................................................................................................................................................257
36.1.1 PCIe..................................................................................................................................................................257
36.1.2 Terminology and Conventions.........................................................................................................................257
36.1.3 PCIe Topology on i.MX 6 in PCIe RC Mode..................................................................................................259
36.1.4 Features............................................................................................................................................................261
36.2 Linux PCI Subsystem and RC driver............................................................................................................................261
36.2.1 RC driver source files......................................................................................................................................262
36.2.2 Kernel configurations.......................................................................................................................................262
36.3 System Resource: Memory Layout...............................................................................................................................263
36.3.1 System Resource: Interrupt lines.....................................................................................................................263
36.4 Using PCIe Endpoint and running Tests.......................................................................................................................264
36.4.1 Ensuring PCIe System Initialization................................................................................................................265
36.4.2 Tests.................................................................................................................................................................265
36.4.3 Known Issues...................................................................................................................................................266
36.5 i.MX 6Quad SD PCIe RC/EP Validation System........................................................................................................266
36.5.1 Hardware Setup................................................................................................................................................266
36.5.2 Software Configurations..................................................................................................................................266
36.5.3 Features............................................................................................................................................................267
36.5.4 Results..............................................................................................................................................................267
Chapter 37
Fast Ethernet Controller (FEC) Driver
37.1 Introduction...................................................................................................................................................................271
37.2 Hardware Operation......................................................................................................................................................271
37.2.1 Software Operation..........................................................................................................................................274
37.2.2 Source Code Structure.....................................................................................................................................274
37.2.3 Menu Configuration Options...........................................................................................................................274
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37.3 Programming Interface.................................................................................................................................................275
37.3.1 Device-Specific Defines..................................................................................................................................275
37.3.2 Getting a MAC Address...................................................................................................................................276
Chapter 38
ENET IEEE-1588 Driver
38.1 Hardware Operation......................................................................................................................................................277
38.1.1 Transmit Timestamping...................................................................................................................................278
38.1.2 Receive Timestamping.....................................................................................................................................278
38.2 Software Operation.......................................................................................................................................................278
38.2.1 Source Code Structure.....................................................................................................................................279
38.2.2 Linux Menu Configuration Options.................................................................................................................279
38.3 Programming Interface.................................................................................................................................................279
38.3.1 IXXAT Specific Data structure Defines..........................................................................................................279
38.3.2 IXXAT IOCTL Commands Defines................................................................................................................280
Chapter 39
Universal Asynchronous Receiver/Transmitter (UART) Driver
39.1 Introduction...................................................................................................................................................................283
39.2 Hardware Operation......................................................................................................................................................284
39.2.1 Software Operation..........................................................................................................................................284
39.2.2 Driver Features.................................................................................................................................................285
39.2.3 Source Code Structure.....................................................................................................................................285
39.3 Configuration................................................................................................................................................................286
39.3.1 Menu Configuration Options...........................................................................................................................286
39.3.2 Source Code Configuration Options................................................................................................................287
39.3.3 Chip Configuration Options.............................................................................................................................287
39.3.4 Board Configuration Options...........................................................................................................................287
39.4 Programming Interface.................................................................................................................................................287
39.4.1 Interrupt Requirements....................................................................................................................................287
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Section number Title Page
Chapter 40
AR6003 WiFi
40.1 Hardware Operation......................................................................................................................................................289
40.1.1 Software Operation..........................................................................................................................................289
40.1.2 Driver features..................................................................................................................................................289
40.1.3 Source Code Structure.....................................................................................................................................290
40.1.4 Linux Menu Configuration Options.................................................................................................................290
Chapter 41
Bluetooth Driver
41.1 Introduction...................................................................................................................................................................291
41.1.1 Hardware Operation.........................................................................................................................................291
41.2 Software Operation.......................................................................................................................................................293
41.2.1 UART Control..................................................................................................................................................294
41.2.2 Reset and Power control..................................................................................................................................295
41.2.3 Configuration...................................................................................................................................................295
Chapter 42
Pulse-Width Modulator (PWM) Driver
42.1 Introduction...................................................................................................................................................................297
42.1.1 Hardware Operation.........................................................................................................................................297
42.1.2 Clocks...............................................................................................................................................................298
42.1.3 Software Operation..........................................................................................................................................299
42.1.4 Driver Features.................................................................................................................................................299
42.1.5 Source Code Structure.....................................................................................................................................299
42.1.6 Menu Configuration Options...........................................................................................................................300
Chapter 43
Watchdog (WDOG) Driver
43.1 Introduction...................................................................................................................................................................301
43.1.1 Hardware Operation.........................................................................................................................................301
43.1.2 Software Operation..........................................................................................................................................301
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Section number Title Page
43.2 Generic WDOG Driver.................................................................................................................................................302
43.2.1 Driver Features.................................................................................................................................................302
43.2.2 Menu Configuration Options...........................................................................................................................302
43.2.3 Source Code Structure.....................................................................................................................................302
43.2.4 Programming Interface....................................................................................................................................303
Chapter 44
OProfile
44.1 Introduction...................................................................................................................................................................305
44.1.1 Overview..........................................................................................................................................................305
44.1.2 Features............................................................................................................................................................305
44.1.3 Hardware Operation.........................................................................................................................................306
44.2 Software Operation.......................................................................................................................................................306
44.2.1 Architecture Specific Components..................................................................................................................306
44.2.2 oprofilefs Pseudo Filesystem...........................................................................................................................307
44.2.3 Generic Kernel Driver......................................................................................................................................307
44.2.4 OProfile Daemon.............................................................................................................................................307
44.2.5 Post Profiling Tools.........................................................................................................................................308
44.3 Requirements................................................................................................................................................................308
44.3.1 Source Code Structure.....................................................................................................................................308
44.3.2 Menu Configuration Options...........................................................................................................................308
44.3.3 Programming Interface....................................................................................................................................309
44.3.4 Interrupt Requirements....................................................................................................................................309
Chapter 45
CAAM (Cryptographic Acceleration and Assurance Module)
45.1 CAAM Device Driver Overview..................................................................................................................................311
45.2 Configuration and Job Execution Level.......................................................................................................................311
45.3 Control/Configuration Driver.......................................................................................................................................312
45.4 Job Ring Driver.............................................................................................................................................................312
45.5 API Interface Level.......................................................................................................................................................314
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Section number Title Page
45.6 Driver Configuration.....................................................................................................................................................316
45.7 Limitations....................................................................................................................................................................317
45.8 Limitations in the Existing Implementation Overview.................................................................................................318
45.9 Initialize Keystore Management Interface....................................................................................................................318
45.10 Detect Available Secure Memory Storage Units..........................................................................................................319
45.11 Establish Keystore in Detected Unit.............................................................................................................................319
45.12 Release Keystore...........................................................................................................................................................320
45.13 Allocate a Slot from the Keystore.................................................................................................................................320
45.14 Load Data into a Keystore Slot.....................................................................................................................................321
45.15 Demo Image Update.....................................................................................................................................................321
45.16 Decapsulate Data in the Keystore.................................................................................................................................322
45.17 Read Data From a Keystore Slot..................................................................................................................................323
45.18 Release a Slot back to the Keystore..............................................................................................................................323
45.19 CAAM/SNVS - Security Violation Handling Interface Overview...............................................................................325
45.20 Operation.......................................................................................................................................................................325
45.21 Configuration Interface.................................................................................................................................................326
45.22 Install a Handler............................................................................................................................................................326
45.23 Remove an Installed Driver..........................................................................................................................................326
45.24 Driver Configuration CAAM/SNVS............................................................................................................................327
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Chapter 1
About This Book
1.1 Audience
This document is targeted to individuals who will port the i.MX Linux BSP to customerspecific products.
The audience is expected to have a working knowledge of the Linux 3.0 kernel internals,
driver models, and i.MX processors.
1.1.1 Conventions
This document uses the following notational conventions:
• Courier monospaced type indicate commands, command parameters, code examples,
and file and directory names.
• Italic type indicates replaceable command or function parameters.
• Bold type indicates function names.
1.1.2 Definitions, Acronyms, and Abbreviations
The following table defines the acronyms and abbreviations used in this document.
Definitions and Acronyms
Term Definition
ADC Asynchronous Display Controller
address
translation
API Application Programming Interface
®
ARM
Freescale Semiconductor, Inc. 23
Address conversion from virtual domain to physical domain
Advanced RISC Machines processor architecture
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Audience
Term Definition
AUDMUX Digital audio MUX-provides a programmable interconnection for voice, audio, and synchronous data routing
between host serial interfaces and peripheral serial interfaces
BCD Binary Coded Decimal
bus A path between several devices through data lines
bus load The percentage of time a bus is busy
CODEC Coder/decoder or compression/decompression algorithm-used to encode and decode (or compress and
decompress) various types of data
CPU Central Processing Unit-generic term used to describe a processing core
CRC Cyclic Redundancy Check-Bit error protection method for data communication
CSI Camera Sensor Interface
DFS Dynamic Frequency Scaling
DMA Direct Memory Access-an independent block that can initiate memory-to-memory data transfers
DPM Dynamic Power Management
DRAM Dynamic Random Access Memory
DVFS Dynamic Voltage Frequency Scaling
EMI External Memory Interface-controls all IC external memory accesses (read/write/erase/program) from all the
masters in the system
Endian Refers to byte ordering of data in memory. Little endian means that the least significant byte of the data is
stored in a lower address than the most significant byte. In big endian, the order of the bytes is reversed
EPIT Enhanced Periodic Interrupt Timer-a 32-bit set and forget timer capable of providing precise interrupts at
regular intervals with minimal processor intervention
FCS Frame Checker Sequence
FIFO First In First Out
FIPS Federal Information Processing Standards-United States Government technical standards published by the
National Institute of Standards and Technology (NIST). NIST develops FIPS when there are compelling
Federal government requirements such as for security and interoperability but no acceptable industry
standards
FIPS-140 Security requirements for cryptographic modules-Federal Information Processing Standard 140-2(FIPS 140-2)
is a standard that describes US Federal government requirements that IT products should meet for Sensitive,
but Unclassified (SBU) use
Flash A non-volatile storage device similar to EEPROM, where erasing can be done only in blocks or the entire chip.
Flash path Path within ROM bootstrap pointing to an executable Flash application
Flush Procedure to reach cache coherency. Refers to removing a data line from cache. This process includes
cleaning the line, invalidating its VBR and resetting the tag valid indicator. The flush is triggered by a software
command
GPIO General Purpose Input/Output
hash Hash values are produced to access secure data. A hash value (or simply hash), also called a message
digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and is
generated by a formula in such a way that it is extremely unlikely that some other text produces the same hash
value.
I/O Input/Output
ICE In-Circuit Emulation
IP Intellectual Property
IPU Image Processing Unit -supports video and graphics processing functions and provides an interface to video/
still image sensors and displays
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24 Freescale Semiconductor, Inc.
Chapter 1 About This Book
Term Definition
IrDA Infrared Data Association-a nonprofit organization whose goal is to develop globally adopted specifications for
infrared wireless communication
ISR Interrupt Service Routine
JTAG JTAG (IEEE Standard 1149.1) A standard specifying how to control and monitor the pins of compliant devices
on a printed circuit board
Kill Abort a memory access
KPP KeyPad Port-16-bit peripheral used as a keypad matrix interface or as general purpose input/output (I/O)
line Refers to a unit of information in the cache that is associated with a tag
LRU Least Recently Used-a policy for line replacement in the cache
MMU Memory Management Unit-a component responsible for memory protection and address translation
MPEG Moving Picture Experts Group-an ISO committee that generates standards for digital video compression and
audio. It is also the name of the algorithms used to compress moving pictures and video
MPEG
standards
MQSPI Multiple Queue Serial Peripheral Interface-used to perform serial programming operations necessary to
MSHC Memory Stick Host Controller
NAND Flash Flash ROM technology-NAND Flash architecture is one of two flash technologies (the other being NOR) used
NOR Flash See NAND Flash
PCMCIA Personal Computer Memory Card International Association-a multi-company organization that has developed
physical
address
PLL Phase Locked Loop-an electronic circuit controlling an oscillator so that it maintains a constant phase angle (a
RAM Random Access Memory
RAM path Path within ROM bootstrap leading to the downloading and the execution of a RAM application
RGB The RGB color model is based on the additive model in which Red, Green, and Blue light are combined to
RGBA RGBA color space stands for Red Green Blue Alpha. The alpha channel is the transparency channel, and is
RNGA Random Number Generator Accelerator-a security hardware module that produces 32-bit pseudo random
ROM Read Only Memory
ROM
bootstrap
RTIC Real-Time Integrity Checker-a security hardware module
SCC SeCurity Controller-a security hardware module
Several standards of compression for moving pictures and video:
• MPEG-1 is optimized for CD-ROM and is the basis for MP3
• MPEG-2 is defined for broadcast video in applications such as digital television set-top boxes and DVD
• MPEG-3 was merged into MPEG-2
• MPEG-4 is a standard for low-bandwidth video telephony and multimedia on the World-Wide Web
configure radio subsystems and selected peripherals
in memory cards such as the Compact Flash cards. NAND is best suited to flash devices requiring high
capacity data storage. NAND flash devices offer storage space up to 512-Mbyte and offers faster erase, write,
and read capabilities over NOR architecture
a standard for small, credit card-sized devices, called PC Cards. There are three types of PCMCIA cards that
have the same rectangular size (85.6 by 54 millimeters), but different widths
The address by which the memory in the system is physically accessed
lock) on the frequency of an input, or reference, signal
create other colors. The abbreviation RGB comes from the three primary colors in additive light models
unique to this color space. RGBA, like RGB, is an additive color space, so the more of a color placed, the
lighter the picture gets. PNG is the best known image format that uses the RGBA color space
numbers as part of the security module
Internal boot code encompassing the main boot flow as well as exception vectors
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Freescale Semiconductor, Inc. 25
Audience
Term Definition
SDMA Smart Direct Memory Access
SDRAM Synchronous Dynamic Random Access Memory
SoC System on a Chip
SPBA Shared Peripheral Bus Arbiter-a three-to-one IP-Bus arbiter, with a resource-locking mechanism
SPI Serial Peripheral Interface-a full-duplex synchronous serial interface for connecting low-/medium-bandwidth
external devices using four wires. SPI devices communicate using a master/slave relationship over two data
lines and two control lines: Also see SS, SCLK, MISO, and MOSI
SRAM Static Random Access Memory
SSI Synchronous-Serial Interface-standardized interface for serial data transfer
TBD To Be Determined
UART Universal Asynchronous Receiver/Transmitter-asynchronous serial communication to external devices
UID Unique ID-a field in the processor and CSF identifying a device or group of devices
USB Universal Serial Bus-an external bus standard that supports high speed data transfers. The USB 1.1
specification supports data transfer rates of up to 12 Mb/s and USB 2.0 has a maximum transfer rate of 480
Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and
keyboards. USB also supports Plug-and-Play installation and hot plugging
USBOTG USB On The Go-an extension of the USB 2.0 specification for connecting peripheral devices to each other.
USBOTG devices, also known as dual-role peripherals, can act as limited hosts or peripherals themselves
depending on how the cables are connected to the devices, and they also can connect to a host PC
word A group of bits comprising 32-bits
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26 Freescale Semiconductor, Inc.
Chapter 2
Introduction
2.1 Overview
The purpose of this software package is to support Linux on the i.MX 6Solo/6DualLite
family of Integrated Circuits (ICs) and their associated platforms. It provides the
necessary software to interface the standard open-source Linux kernel to the i.MX
hardware. The goal is to enable Freescale customers to rapidly build products based on
i.MX devices that use the Linux OS.
The BSP is not a platform or product reference implementation. It does not contain all of
the product-specific drivers, hardware-independent software stacks, Graphical User
Interface (GUI) components, Java Virtual Machine (JVM), and applications required for
a product. Some of these are made available in their original open-source form as part of
the base kernel.
The BSP is not intended to be used for silicon verification. While it can play a role in
this, the BSP functionality and the tests run on the BSP do not have sufficient coverage to
replace traditional silicon verification test suites.
2.1.1 Software Base
The i.MX BSP is based on version 3.0.35 of the Linux kernel from the official Linux
kernel web site (http://www.kernel.org ). It is enhanced with the features provided by
Freescale.
2.1.2 Features
Table below describes the features supported by the Linux BSP for specific platforms.
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Freescale Semiconductor, Inc. 27
Overview
Table 2-1. Linux BSP Supported Features
Feature Description Chapter Source Applicable
Machine Specific Layer
MSL Machine Specific Layer (MSL) supports interrupts,
Timer, Memory Map, GPIO/IOMUX, SPBA, SDMA.
• Interrupts GIC: The linux kernel contains common
ARM GIC interrupts handling code.
• Timer (GPT): The General Purpose Timer (GPT)
is set up to generate an interrupt as programmed
to provide OS ticks. Linux facilitates timer use
through various functions for timing delays,
measurement, events, alarms, high resolution
timer features, and so on. Linux defines the MSL
timer API required for the OS-tick timer and does
not expose it beyond the kernel tick
implementation.
• GPIO/EDIO/IOMUX: The GPIO and EDIO
components in the MSL provide an abstraction
layer between the various drivers and the
configuration and utilization of the system,
including GPIO, IOMUX, and external board I/O.
The IO software module is board-specific, and
resides in the MSL layer as a self-contained set
of files. I/O configuration changes are centralized
in the GPIO module so that changes are not
required in the various drivers.
• SPBA: The Shared Peripheral Bus Arbiter
(SPBA) provides an arbitration mechanism
among multiple masters to allow access to the
shared peripherals. The SPBA implementation
under MSL defines the API to allow different
masters to take or release ownership of a shared
peripheral.
SDMA API The Smart Direct Memory Access (SDMA) API driver
controls the SDMA hardware. It provides an API to
other drivers for transferring data between MCU, DSP
and peripherals. . The SDMA controller is responsible
for transferring data between the MCU memory space,
peripherals, and the DSP memory space. The SDMA
API allows other drivers to initialize the scripts, pass
parameters and control their execution. SDMA is based
on a microRISC engine that runs channel-specific
scripts.
DMAC Both AHB-to-APBH and AHB-to-APBX DMA support
configurable DMA descript chain.
Low-level PM
Drivers
CPU Frequency
Scaling
The low-level power management driver is responsible
for implementing hardware-specific operations to meet
power requirements and also to conserve power on the
development platforms. Driver implementations are
often different for different platforms. It is used by the
DPM layer.
The CPU frequency scaling device driver allows the
clock speed of the CPUs to be changed on the fly.
Machine Specific Layer (MSL) All
Smart Direct Memory Access
(SDMA) API
AHB-to-APBH Bridge with DMA
(APBH-Bridge-DMA)
Low-level Power Management
(PM) Driver
CPU Frequency Scaling
(CPUFREQ) Driver
Platform
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
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28 Freescale Semiconductor, Inc.
Chapter 2 Introduction
Table 2-1. Linux BSP Supported Features (continued)
Feature Description Chapter Source Applicable
Platform
DVFS The Dynamic Voltage Frequency Scaling (DVFS)
device driver allows simple dynamic voltage frequency
scaling. The frequency of the core clock domain and
the voltage of the core power domain can be changed
on the fly with all modules continuing their normal
operations.
Multimedia Drivers
IPU The Image Processing Unit (IPU) is designed to
support video and graphics processing functions and to
interface with video/still image sensors and displays.
The IPU driver is a self-contained driver module in the
Linux kernel. It contains a custom kernel-level API to
manipulate logical channels. A logical channel
represents a complete IPU processing flow. The IPU
driver includes a frame buffer driver, a V4L2 device
driver, and low-level IPU drivers.
HDMI This driver provides the support HDMI module HDMI Driver i.MX 6Solo/
Dual Display This chapter introduces the basic infromation about
dual display
V4L2 Output The Video for Linux 2 (V4L2) output driver uses the IPU
post-processing functions for video output. The driver
implements the standard V4L2 API for output devices.
V4L2 Capture The Video for Linux 2 (V4L2) capture device includes
two interfaces: the capture interface and the overlay
interface. The capture interface records the video
stream. The overlay interface displays the preview
video.
VPU The Video Processing Unit (VPU) is a multi-standard
video decoder and encoder that can perform decoding
and encoding of various video formats.
Sound Drivers
ALSA Sound The Advanced Linux Sound Architecture (ALSA) is a
sound driver that provides ALSA and OSS compatible
applications with the means to perform audio playback
and recording functions. ALSA has a user-space
component called ALSAlib that can extend the features
of audio hardware by emulating the same in software
(user space), such as resampling, software mixing,
snooping, and so on. The ASoC Sound driver supports
stereo CODEC playback and capture through SSI.
S/PDIF The S/PDIF driver is designed under the Linux ALSA
subsystem. It implements one playback device for Tx
and one capture device for Rx.
Memory Drivers
SPI NOR MTD The SPI NOR MTD driver provides the support to the
Atmel data Flash using the SPI interface.
Dynamic Voltage Frequency
Scaling (DVFS) Driver
Image Processing Unit (IPU)
Drivers
Dual Display i.MX 6Solo/
Video for Linux Two (V4L2) Driver i.MX 6Solo/
Video for Linux Two (V4L2) Driver i.MX 6Solo/
Video Processing Unit (VPU)
Driver
ALSA Sound Driver i.MX 6Solo/
The Sony/Philips Digital Interface
(S/PDIF) Driver
SPI NOR Flash Memory
Technology Device (MTD) Driver
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
6DualLite
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
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Freescale Semiconductor, Inc. 29
Overview
Table 2-1. Linux BSP Supported Features (continued)
Feature Description Chapter Source Applicable
NAND MTD The NAND MTD driver interfaces with the integrated
NAND controller. It can support various file systems,
such as UBIFS, CRAMFS and JFFS2UBI and
UBIFSCRAMFS and JFFS2. The driver implementation
supports the lowest level operations on the external
NAND Flash chip, such as block read, block write and
block erase as the NAND Flash technology only
supports block access. Because blocks in a NAND
Flash are not guaranteed to be good, the NAND MTD
driver is also able to detect bad blocks and feed that
information to the upper layer to handle bad block
management.
Input Device Drivers
Networking Drivers
ENET The ENET Driver performs the full set of IEEE 802.3/
Ethernet CSMA/CD media access control and channel
interface functions. The FEC requires an external
interface adaptor and transceiver function to complete
the interface to the Ethernet media. It supports half or
full-duplex operation on 10M\100M related Ethernet
networks.
Bus Drivers
I2C The I2C bus driver is a low-level interface that is used
to interface with the I2C bus. This driver is invoked by
the I2C chip driver; it is not exposed to the user space.
The standard Linux kernel contains a core I2C module
that is used by the chip driver to access the bus driver
to transfer data over the I2C bus. This bus driver
supports:
• Compatibility with the I2C bus standard
• Bit rates up to 400 Kbps
• Standard I2C master mode
• Power management features by suspending and
resuming I2C.
CSPI The low-level Enhanced Configurable Serial Peripheral
Interface (ECSPI) driver interfaces a custom, kernelspace API to both ECSPI modules. It supports the
following features:
• Interrupt-driven transmit/receive of SPI frames
• Multi-client management
• Priority management between clients
• SPI device configuration per client
MMC/SD/SDIO uSDHC
UART Drivers
MXC UART The Universal Asynchronous Receiver/Transmitter
The MMC/SD/SDIO Host driver implements the
standard Linux driver interface to eSDHC.
(UART) driver interfaces the Linux serial driver API to
all of the UART ports. A kernel configuration parameter
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NAND GPMI Flash Driver i.MX 6Solo/
Fast Ethernet Controller (FEC)
Driver
Inter-IC (I2C) Driver i.MX 6Solo/
Enhanced Configurable Serial
Peripheral Interface (ECSPI) Driver
MMC/SD/SDIO Host Driver i.MX 6Solo/
Universal Asynchronous Receiver/
Transmitter (UART) Driver
Platform
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
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