i.MX 6Solo/6DualLite Linux Reference
Manual
Document Number: IMX6SDLLXRM
Rev L3.0.35_4.1.0, 09/2013
i.MX 6Solo/6DualLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
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Contents
Section number Title Page
Chapter 1
About This Book
1.1 Audience.......................................................................................................................................................................23
1.1.1 Conventions.....................................................................................................................................................23
1.1.2 Definitions, Acronyms, and Abbreviations......................................................................................................23
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................27
2.1.1 Software Base..................................................................................................................................................27
2.1.2 Features............................................................................................................................................................27
Chapter 3
Machine Specific Layer (MSL)
3.1 Introduction...................................................................................................................................................................33
3.2 Interrupts (Operation)...................................................................................................................................................34
3.2.1 Interrupt Hardware Operation..........................................................................................................................34
3.2.2 Interrupt Software Operation...........................................................................................................................34
3.2.3 Interrupt Features.............................................................................................................................................35
3.2.4 Interrupt Source Code Structure......................................................................................................................35
3.2.5 Interrupt Programming Interface.....................................................................................................................35
3.3 Timer.............................................................................................................................................................................36
3.3.1 Timer Software Operation...............................................................................................................................36
3.3.2 Timer Features.................................................................................................................................................36
3.3.3 Timer Source Code Structure...........................................................................................................................37
3.3.4 Timer Programming Interface..........................................................................................................................37
3.4 Memory Map................................................................................................................................................................37
3.4.1 Memory Map Hardware Operation..................................................................................................................37
3.4.2 Memory Map Software Operation...................................................................................................................37
3.4.3 Memory Map Features.....................................................................................................................................37
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3.4.4 Memory Map Source Code Structure..............................................................................................................38
3.4.5 Memory Map Programming Interface.............................................................................................................38
3.5 IOMUX.........................................................................................................................................................................38
3.5.1 IOMUX Hardware Operation..........................................................................................................................39
3.5.2 IOMUX Software Operation............................................................................................................................39
3.5.3 IOMUX Features..............................................................................................................................................40
3.5.4 IOMUX Source Code Structure.......................................................................................................................40
3.5.5 IOMUX Programming Interface......................................................................................................................40
3.5.6 IOMUX Control Through GPIO Module........................................................................................................40
3.5.6.1 GPIO Hardware Operation...............................................................................................................41
3.5.6.1.1 Muxing Control...............................................................................................................41
3.5.6.1.2 PULLUP Control............................................................................................................41
3.5.6.2 GPIO Software Operation (general)................................................................................................41
3.5.6.3 GPIO Implementation......................................................................................................................41
3.5.6.4 GPIO Source Code Structure...........................................................................................................42
3.5.6.5 GPIO Programming Interface..........................................................................................................42
3.6 General Purpose Input/Output(GPIO)..........................................................................................................................42
3.6.1 GPIO Software Operation................................................................................................................................42
3.6.1.1 API for GPIO...................................................................................................................................43
3.6.2 GPIO Features..................................................................................................................................................43
3.6.3 GPIO Module Source Code Structure..............................................................................................................43
3.6.4 GPIO Programming Interface 2.......................................................................................................................44
Chapter 4
Smart Direct Memory Access (SDMA) API
4.1 Overview.......................................................................................................................................................................45
4.1.1 Hardware Operation.........................................................................................................................................45
4.1.2 Software Operation..........................................................................................................................................45
4.1.3 Source Code Structure.....................................................................................................................................46
4.1.4 Menu Configuration Options...........................................................................................................................47
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4.1.5 Programming Interface....................................................................................................................................47
4.1.6 Usage Example................................................................................................................................................47
Chapter 5
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
5.1 Overview.......................................................................................................................................................................49
5.1.1 Hardware Operation.........................................................................................................................................49
5.1.2 Software Operation..........................................................................................................................................50
5.1.3 Source Code Structure.....................................................................................................................................50
5.1.4 Menu Configuration Options...........................................................................................................................51
5.1.5 Programming Interface....................................................................................................................................51
5.1.6 Usage Example................................................................................................................................................51
Chapter 6
Image Processing Unit (IPU) Drivers
6.1 Introduction...................................................................................................................................................................53
6.2 Hardware Operation......................................................................................................................................................55
6.3 Software Operation.......................................................................................................................................................55
6.3.1 Overview of IPU Frame Buffer Drivers..........................................................................................................56
6.3.1.1 IPU Frame Buffer Hardware Operation...........................................................................................57
6.3.1.2 IPU Frame Buffer Software Operation............................................................................................57
6.3.1.3 Synchronous Frame Buffer Driver...................................................................................................58
6.3.2 IPU Backlight Driver.......................................................................................................................................59
6.3.3 IPU Device Driver...........................................................................................................................................59
6.4 Source Code Structure .................................................................................................................................................60
6.4.1 Menu Configuration Options...........................................................................................................................61
6.5 Unit Test........................................................................................................................................................................64
6.5.1 Framebuffer Tests............................................................................................................................................65
6.5.2 Video4Linux API test......................................................................................................................................65
6.5.3 IPU Device Unit test........................................................................................................................................66
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Chapter 7
MIPI DSI Driver
7.1 Introduction...................................................................................................................................................................71
7.1.1 Overview of MIPI DSI IP Driver.....................................................................................................................71
7.1.2 Overview of MIPI DSI Display Panel Driver..................................................................................................72
7.1.3 Hardware Operation.........................................................................................................................................72
7.2 Software Operation.......................................................................................................................................................72
7.2.1 MIPI DSI IP Driver Software Operation.........................................................................................................72
7.2.2 MIPI DSI Display Panel Driver Software Operation.......................................................................................73
7.3 Driver Features..............................................................................................................................................................73
7.3.1 Source Code Structure.....................................................................................................................................74
7.3.2 Menu Configuration Options...........................................................................................................................74
7.3.3 Programming Interface....................................................................................................................................74
Chapter 8
Video for Linux Two (V4L2) Driver
8.1 Introduction...................................................................................................................................................................75
8.2 V4L2 Capture Device...................................................................................................................................................76
8.2.1 V4L2 Capture IOCTLs....................................................................................................................................76
8.2.2 Using the V4L2 Capture APIs.........................................................................................................................78
8.3 V4L2 Output Device.....................................................................................................................................................79
8.3.1 V4L2 Output IOCTLs......................................................................................................................................79
8.3.2 Using the V4L2 Output APIs...........................................................................................................................80
8.4 Source Code Structure .................................................................................................................................................80
8.4.1 Menu Configuration Options...........................................................................................................................81
8.4.2 V4L2 Programming Interface..........................................................................................................................81
Chapter 9
Electrophoretic Display Controller (EPDC) Frame Buffer Driver
9.1 Introduction...................................................................................................................................................................83
9.2 Hardware Operation......................................................................................................................................................84
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9.3 Software Operation.......................................................................................................................................................84
9.3.1 EPDC Frame Buffer Driver Overview.............................................................................................................84
9.3.2 EPDC Frame Buffer Driver Extensions...........................................................................................................85
9.3.3 EPDC Panel Configuration..............................................................................................................................85
9.3.3.1 Boot Command Line Parameters.....................................................................................................86
9.3.4 EPDC Waveform Loading...............................................................................................................................87
9.3.4.1 Using a Default Waveform File.......................................................................................................87
9.3.4.2 Using a Custom Waveform File.......................................................................................................88
9.3.5 EPDC Panel Initialization................................................................................................................................88
9.3.6 Grayscale Framebuffer Selection.....................................................................................................................89
9.3.7 Enabling An EPDC Splash Screen...................................................................................................................89
9.4 Source Code Structure .................................................................................................................................................90
9.5 Menu Configuration Options........................................................................................................................................90
9.6 Programming Interface.................................................................................................................................................91
9.6.1 IOCTLs/Functions...........................................................................................................................................91
9.6.2 Structures and Defines.....................................................................................................................................94
Chapter 10
Pixel Pipeline (PxP) DMA-ENGINE Driver
10.1 Introduction...................................................................................................................................................................97
10.2 Hardware Operation......................................................................................................................................................97
10.3 Software Operation.......................................................................................................................................................97
10.3.1 Key Data Structs..............................................................................................................................................97
10.3.2 Channel Management......................................................................................................................................98
10.3.3 Descriptor Management...................................................................................................................................98
10.3.4 Completion Notification..................................................................................................................................98
10.3.5 Limitations.......................................................................................................................................................99
10.4 Menu Configuration Options........................................................................................................................................99
10.5 Source Code Structure..................................................................................................................................................99
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Chapter 11
Graphics Processing Unit (GPU)
11.1 Introduction...................................................................................................................................................................101
11.1.1 Driver Features.................................................................................................................................................101
11.1.1.1 Hardware Operation.........................................................................................................................101
11.1.1.2 Software Operation..........................................................................................................................102
11.1.1.3 Source Code Structure ....................................................................................................................102
11.1.1.4 Library Structure .............................................................................................................................102
11.1.1.5 API References................................................................................................................................104
11.1.1.6 Menu Configuration Options...........................................................................................................104
Chapter 12
Direct FB
12.1 Introduction...................................................................................................................................................................105
12.1.1 Hardware Operation.........................................................................................................................................105
12.2 Software Operation.......................................................................................................................................................105
12.2.1 DirectFB Acceleration Architecture................................................................................................................106
12.2.2 i.MX DirectFB Driver Details.........................................................................................................................107
12.2.3 The gal_config File for i.MX DirectFB Driver................................................................................................107
12.3 DirectFB EGL...............................................................................................................................................................109
12.4 Setting Up DirectFB Acceleration................................................................................................................................109
Chapter 13
HDMI Driver
13.1 Introduction...................................................................................................................................................................111
13.1.1 Hardware Operation.........................................................................................................................................111
13.2 Software Operation.......................................................................................................................................................113
13.2.1 Core..................................................................................................................................................................113
13.2.2 Video................................................................................................................................................................114
13.2.3 Display Device Registration and Initialization................................................................................................115
13.2.4 Hotplug Handling and Video Mode Changes..................................................................................................116
13.2.5 Audio................................................................................................................................................................116
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13.2.6 CEC..................................................................................................................................................................118
13.3 Source Code Structure..................................................................................................................................................118
13.3.1 Linux Menu Configuration Options.................................................................................................................120
13.4 Unit Test........................................................................................................................................................................121
13.4.1 Video................................................................................................................................................................121
13.4.2 Audio................................................................................................................................................................122
13.4.3 CEC..................................................................................................................................................................122
Chapter 14
X Windows Acceleration
14.1 Introduction...................................................................................................................................................................123
14.2 Hardware Operation......................................................................................................................................................123
14.3 Software Operation.......................................................................................................................................................123
14.3.1 X Windows Acceleration Architecture............................................................................................................124
14.3.2 i.MX 6 Driver for X-Windows System............................................................................................................125
14.3.3 i.MX 6 Direct Rendering Infrastructure (DRI) for X-Windows System.........................................................127
14.3.4 EGL- X Library................................................................................................................................................128
14.3.5 xorg.conf for i.MX 6........................................................................................................................................128
14.3.6 Setup X-Windows System Acceleration..........................................................................................................130
Chapter 15
Video Processing Unit (VPU) Driver
15.1 Hardware Operation......................................................................................................................................................133
15.1.1 Software Operation..........................................................................................................................................134
15.1.2 Source Code Structure.....................................................................................................................................135
15.1.3 Menu Configuration Options...........................................................................................................................136
15.1.4 Programming Interface....................................................................................................................................137
15.1.5 Defining an Application...................................................................................................................................138
Chapter 16
OmniVision Camera Driver
16.1 OV5640 Using MIPI CSI-2 interface...........................................................................................................................139
16.1.1 Hardware Operation.........................................................................................................................................139
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16.1.2 Software Operation..........................................................................................................................................139
16.1.3 Source Code Structure.....................................................................................................................................140
16.1.4 Linux Menu Configuration Options.................................................................................................................140
16.2 OV5640 Using parallel interface..................................................................................................................................141
16.2.1 Hardware Operation.........................................................................................................................................141
16.2.2 Software Operation..........................................................................................................................................141
16.2.3 Source Code Structure.....................................................................................................................................142
16.2.4 Linux Menu Configuration Options.................................................................................................................142
Chapter 17
MIPI CSI2 Driver
17.1 Introduction...................................................................................................................................................................143
17.1.1 MIPI CSI2 Driver Overview............................................................................................................................143
17.1.2 Hardware Operation.........................................................................................................................................144
17.2 Software Operation.......................................................................................................................................................144
17.2.1 MIPI CSI2 Driver Initialize Operation............................................................................................................144
17.2.2 MIPI CSI2 Common API Operation................................................................................................................145
17.3 Driver Features..............................................................................................................................................................145
17.3.1 Source Code Structure.....................................................................................................................................146
17.3.2 Menu Configuration Options...........................................................................................................................146
17.3.3 Programming Interface....................................................................................................................................146
17.3.4 Interrupt Requirements....................................................................................................................................147
Chapter 18
Low-level Power Management (PM) Driver
18.1 Hardware Operation......................................................................................................................................................149
18.1.1 Software Operation..........................................................................................................................................149
18.1.2 Source Code Structure.....................................................................................................................................150
18.1.3 Menu Configuration Options...........................................................................................................................150
18.1.4 Programming Interface....................................................................................................................................151
18.1.5 Unit Test...........................................................................................................................................................151
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Chapter 19
PF100 Regulator Driver
19.1 Introduction...................................................................................................................................................................153
19.2 Hardware Operation......................................................................................................................................................153
19.2.1 Driver Features.................................................................................................................................................154
19.3 Software Operation.......................................................................................................................................................154
19.3.1 Regulator APIs.................................................................................................................................................154
19.4 Driver Architecture.......................................................................................................................................................156
19.4.1 Driver Interface Details....................................................................................................................................157
19.4.2 Source Code Structure.....................................................................................................................................157
19.4.3 Menu Configuration Options...........................................................................................................................157
Chapter 20
CPU Frequency Scaling (CPUFREQ) Driver
20.1 Introduction...................................................................................................................................................................159
20.1.1 Software Operation..........................................................................................................................................159
20.1.2 Source Code Structure.....................................................................................................................................160
20.2 Menu Configuration Options........................................................................................................................................160
20.2.1 Board Configuration Options...........................................................................................................................161
Chapter 21
Dynamic Bus Frequency Driver
21.1 Introduction...................................................................................................................................................................163
21.1.1 Operation..........................................................................................................................................................163
21.1.2 Software Operation..........................................................................................................................................163
21.1.3 Source Code Structure.....................................................................................................................................164
21.2 Menu Configuration Options........................................................................................................................................164
21.2.1 Board Configuration Options...........................................................................................................................164
Chapter 22
Thermal Driver
22.1 Introduction...................................................................................................................................................................165
22.1.1 Thermal Driver Overview................................................................................................................................165
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22.2 Hardware Operation......................................................................................................................................................165
22.2.1 Thermal Driver Software Operation................................................................................................................166
22.3 Driver Features..............................................................................................................................................................166
22.3.1 Source Code Structure.....................................................................................................................................166
22.3.2 Menu Configuration Options...........................................................................................................................166
22.3.3 Programming Interface....................................................................................................................................166
22.3.4 Interrupt Requirements....................................................................................................................................167
22.4 Unit Test........................................................................................................................................................................167
Chapter 23
Anatop Regulator Driver
23.1 Introduction...................................................................................................................................................................169
23.1.1 Hardware Operation.........................................................................................................................................169
23.2 Driver Features..............................................................................................................................................................170
23.2.1 Software Operation..........................................................................................................................................170
23.2.2 Regulator APIs.................................................................................................................................................170
23.2.3 Driver Interface Details....................................................................................................................................171
23.2.4 Source Code Structure.....................................................................................................................................171
23.2.5 Menu Configuration Options...........................................................................................................................171
Chapter 24
SNVS Real Time Clock (SRTC) Driver
24.1 Introduction...................................................................................................................................................................173
24.1.1 Hardware Operation.........................................................................................................................................173
24.2 Software Operation.......................................................................................................................................................173
24.2.1 IOCTL..............................................................................................................................................................173
24.2.2 Keeping Alive in the Power Off State.............................................................................................................174
24.3 Driver Features..............................................................................................................................................................174
24.3.1 Source Code Structure.....................................................................................................................................174
24.3.2 Menu Configuration Options...........................................................................................................................175
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Chapter 25
Advanced Linux Sound Architecture (ALSA) System on a Chip (ASoC) Sound Driver
25.1 ALSA Sound Driver Introduction.................................................................................................................................177
25.2 SoC Sound Card ...........................................................................................................................................................180
25.2.1 Stereo CODEC Features..................................................................................................................................180
25.2.2 7.1 Audio Codec Features................................................................................................................................181
25.2.3 AM/FM Codec Features...................................................................................................................................181
25.2.4 Sound Card Information...................................................................................................................................181
25.3 Hardware Operation......................................................................................................................................................182
25.3.1 Stereo Audio CODEC......................................................................................................................................182
25.3.2 7.1 Audio Codec..............................................................................................................................................183
25.3.3 AM/FM Codec.................................................................................................................................................183
25.4 Software Operation.......................................................................................................................................................183
25.4.1 ASoC Driver Source Architecture...................................................................................................................184
25.4.2 Sound Card Registration..................................................................................................................................185
25.4.3 Device Open.....................................................................................................................................................185
25.4.4 Platform Data...................................................................................................................................................186
25.4.5 Menu Configuration Options...........................................................................................................................186
25.5 Unit Test........................................................................................................................................................................187
25.5.1 Stereo CODEC Unit Test.................................................................................................................................187
25.5.2 7.1 Audio Codec Unit Test..............................................................................................................................188
25.5.3 AM/FM Codec Unit Test.................................................................................................................................189
Chapter 26
Asynchronous Sample Rate Converter (ASRC) Driver
26.1 Introduction...................................................................................................................................................................191
26.1.1 Hardware Operation.........................................................................................................................................191
26.2 Software Operation.......................................................................................................................................................192
26.2.1 Sequence for Memory to ASRC to Memory...................................................................................................193
26.2.2 Sequence for Memory to ASRC to Peripheral.................................................................................................193
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26.3 Source Code Structure..................................................................................................................................................194
26.3.1 Linux Menu Configuration Options.................................................................................................................194
26.4 Platform Data................................................................................................................................................................194
26.4.1 Programming Interface (Exported API and IOCTLs)......................................................................................195
Chapter 27
The Sony/Philips Digital Interface (S/PDIF) Driver
27.1 Introduction...................................................................................................................................................................197
27.1.1 S/PDIF Overview.............................................................................................................................................197
27.1.2 Hardware Overview.........................................................................................................................................198
27.1.3 Software Overview..........................................................................................................................................199
27.1.4 ASoC layer.......................................................................................................................................................199
27.2 S/PDIF Tx Driver..........................................................................................................................................................199
27.2.1 Driver Design...................................................................................................................................................200
27.2.2 Provided User Interface...................................................................................................................................200
27.3 S/PDIF Rx Driver.........................................................................................................................................................201
27.3.1 Driver Design...................................................................................................................................................202
27.3.2 Provided User Interfaces..................................................................................................................................202
27.4 Source Code Structure .................................................................................................................................................204
27.5 Menu Configuration Options........................................................................................................................................205
27.6 Platform Data................................................................................................................................................................205
27.7 Interrupts and Exceptions.............................................................................................................................................206
27.8 Unit Test Preparation....................................................................................................................................................206
27.8.1 Tx test step.......................................................................................................................................................206
27.8.2 Rx test step.......................................................................................................................................................206
Chapter 28
SPI NOR Flash Memory Technology Device (MTD) Driver
28.1 Introduction...................................................................................................................................................................209
28.1.1 Hardware Operation.........................................................................................................................................209
28.1.2 Software Operation..........................................................................................................................................210
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28.1.3 Driver Features.................................................................................................................................................210
28.1.4 Source Code Structure.....................................................................................................................................210
28.1.5 Menu Configuration Options...........................................................................................................................211
Chapter 29
MMC/SD/SDIO Host Driver
29.1 Introduction...................................................................................................................................................................213
29.1.1 Hardware Operation.........................................................................................................................................213
29.1.2 Software Operation..........................................................................................................................................214
29.2 Driver Features..............................................................................................................................................................216
29.2.1 Source Code Structure.....................................................................................................................................217
29.2.2 Menu Configuration Options...........................................................................................................................217
29.2.3 Platform Data...................................................................................................................................................218
29.2.4 Programming Interface....................................................................................................................................218
29.2.5 Loadable Module Operations...........................................................................................................................219
Chapter 30
NAND GPMI Flash Driver
30.1 Introduction...................................................................................................................................................................221
30.1.1 Hardware Operation.........................................................................................................................................221
30.2 Software Operation.......................................................................................................................................................221
30.2.1 Basic Operations: Read/Write..........................................................................................................................222
30.2.2 Error Correction...............................................................................................................................................222
30.2.3 Boot Control Block Management....................................................................................................................222
30.2.4 Bad Block Handling.........................................................................................................................................223
30.3 Source Code Structure..................................................................................................................................................223
30.3.1 Menu Configuration Options...........................................................................................................................223
Chapter 31
Inter-IC (I2C) Driver
31.1 Introduction...................................................................................................................................................................225
31.1.1 I2C Bus Driver Overview................................................................................................................................225
31.1.2 I2C Device Driver Overview...........................................................................................................................226
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31.1.3 Hardware Operation.........................................................................................................................................226
31.2 Software Operation.......................................................................................................................................................226
31.2.1 I2C Bus Driver Software Operation.................................................................................................................226
31.2.2 I2C Device Driver Software Operation...........................................................................................................227
31.3 Driver Features..............................................................................................................................................................227
31.3.1 Source Code Structure.....................................................................................................................................228
31.3.2 Menu Configuration Options...........................................................................................................................228
31.3.3 Programming Interface....................................................................................................................................228
31.3.4 Interrupt Requirements....................................................................................................................................228
Chapter 32
Enhanced Configurable Serial Peripheral Interface (ECSPI) Driver
32.1 Introduction...................................................................................................................................................................231
32.1.1 Hardware Operation.........................................................................................................................................231
32.2 Software Operation.......................................................................................................................................................232
32.2.1 SPI Sub-System in Linux.................................................................................................................................232
32.2.2 Software Limitations........................................................................................................................................233
32.2.3 Standard Operations.........................................................................................................................................233
32.2.4 ECSPI Synchronous Operation........................................................................................................................234
32.3 Driver Features..............................................................................................................................................................236
32.3.1 Source Code Structure.....................................................................................................................................236
32.3.2 Menu Configuration Options...........................................................................................................................236
32.3.3 Programming Interface....................................................................................................................................236
32.3.4 Interrupt Requirements....................................................................................................................................237
Chapter 33
FlexCAN Driver
33.1 Driver Overview...........................................................................................................................................................239
33.1.1 Hardware Operation.........................................................................................................................................239
33.1.2 Software Operation..........................................................................................................................................239
33.1.3 Source Code Structure.....................................................................................................................................239
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33.1.4 Linux Menu Configuration Options.................................................................................................................240
Chapter 34
Media Local Bus Driver
34.1 Introduction...................................................................................................................................................................241
34.1.1 MLB Device Module.......................................................................................................................................241
34.1.2 Supported Feature............................................................................................................................................242
34.1.3 Modes of Operation.........................................................................................................................................243
34.1.4 MLB Driver Overview.....................................................................................................................................243
34.2 MLB Driver..................................................................................................................................................................243
34.2.1 Supported Features...........................................................................................................................................243
34.2.2 MLB Driver Architecture.................................................................................................................................243
34.2.3 Software Operation..........................................................................................................................................245
34.3 Driver Files...................................................................................................................................................................246
34.4 Menu Configuration Options........................................................................................................................................246
Chapter 35
ARC USB Driver
35.1 Introduction...................................................................................................................................................................247
35.1.1 Architectural Overview....................................................................................................................................247
35.2 Hardware Operation......................................................................................................................................................248
35.2.1 Software Operation..........................................................................................................................................248
35.2.2 Source Code Structure.....................................................................................................................................249
35.2.3 Menu Configuration Options...........................................................................................................................250
35.2.4 Programming Interface....................................................................................................................................253
35.3 System WakeUp............................................................................................................................................................253
35.3.1 USB Wakeup usage.........................................................................................................................................253
35.3.2 How to Enable USB WakeUp System Ability.................................................................................................253
35.3.3 WakeUp Events Supported by USB................................................................................................................254
35.3.4 How to Close the USB Child Device Power....................................................................................................255
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Chapter 36
i.MX 6 PCI Express Root Complex Driver
36.1 Introduction...................................................................................................................................................................257
36.1.1 PCIe..................................................................................................................................................................257
36.1.2 Terminology and Conventions.........................................................................................................................257
36.1.3 PCIe Topology on i.MX 6 in PCIe RC Mode..................................................................................................259
36.1.4 Features............................................................................................................................................................261
36.2 Linux PCI Subsystem and RC driver............................................................................................................................261
36.2.1 RC driver source files......................................................................................................................................262
36.2.2 Kernel configurations.......................................................................................................................................262
36.3 System Resource: Memory Layout...............................................................................................................................263
36.3.1 System Resource: Interrupt lines.....................................................................................................................263
36.4 Using PCIe Endpoint and running Tests.......................................................................................................................264
36.4.1 Ensuring PCIe System Initialization................................................................................................................265
36.4.2 Tests.................................................................................................................................................................265
36.4.3 Known Issues...................................................................................................................................................266
36.5 i.MX 6Quad SD PCIe RC/EP Validation System........................................................................................................266
36.5.1 Hardware Setup................................................................................................................................................266
36.5.2 Software Configurations..................................................................................................................................266
36.5.3 Features............................................................................................................................................................267
36.5.4 Results..............................................................................................................................................................267
Chapter 37
Fast Ethernet Controller (FEC) Driver
37.1 Introduction...................................................................................................................................................................271
37.2 Hardware Operation......................................................................................................................................................271
37.2.1 Software Operation..........................................................................................................................................274
37.2.2 Source Code Structure.....................................................................................................................................274
37.2.3 Menu Configuration Options...........................................................................................................................274
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37.3 Programming Interface.................................................................................................................................................275
37.3.1 Device-Specific Defines..................................................................................................................................275
37.3.2 Getting a MAC Address...................................................................................................................................276
Chapter 38
ENET IEEE-1588 Driver
38.1 Hardware Operation......................................................................................................................................................277
38.1.1 Transmit Timestamping...................................................................................................................................278
38.1.2 Receive Timestamping.....................................................................................................................................278
38.2 Software Operation.......................................................................................................................................................278
38.2.1 Source Code Structure.....................................................................................................................................279
38.2.2 Linux Menu Configuration Options.................................................................................................................279
38.3 Programming Interface.................................................................................................................................................279
38.3.1 IXXAT Specific Data structure Defines..........................................................................................................279
38.3.2 IXXAT IOCTL Commands Defines................................................................................................................280
Chapter 39
Universal Asynchronous Receiver/Transmitter (UART) Driver
39.1 Introduction...................................................................................................................................................................283
39.2 Hardware Operation......................................................................................................................................................284
39.2.1 Software Operation..........................................................................................................................................284
39.2.2 Driver Features.................................................................................................................................................285
39.2.3 Source Code Structure.....................................................................................................................................285
39.3 Configuration................................................................................................................................................................286
39.3.1 Menu Configuration Options...........................................................................................................................286
39.3.2 Source Code Configuration Options................................................................................................................287
39.3.3 Chip Configuration Options.............................................................................................................................287
39.3.4 Board Configuration Options...........................................................................................................................287
39.4 Programming Interface.................................................................................................................................................287
39.4.1 Interrupt Requirements....................................................................................................................................287
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Section number Title Page
Chapter 40
AR6003 WiFi
40.1 Hardware Operation......................................................................................................................................................289
40.1.1 Software Operation..........................................................................................................................................289
40.1.2 Driver features..................................................................................................................................................289
40.1.3 Source Code Structure.....................................................................................................................................290
40.1.4 Linux Menu Configuration Options.................................................................................................................290
Chapter 41
Bluetooth Driver
41.1 Introduction...................................................................................................................................................................291
41.1.1 Hardware Operation.........................................................................................................................................291
41.2 Software Operation.......................................................................................................................................................293
41.2.1 UART Control..................................................................................................................................................294
41.2.2 Reset and Power control..................................................................................................................................295
41.2.3 Configuration...................................................................................................................................................295
Chapter 42
Pulse-Width Modulator (PWM) Driver
42.1 Introduction...................................................................................................................................................................297
42.1.1 Hardware Operation.........................................................................................................................................297
42.1.2 Clocks...............................................................................................................................................................298
42.1.3 Software Operation..........................................................................................................................................299
42.1.4 Driver Features.................................................................................................................................................299
42.1.5 Source Code Structure.....................................................................................................................................299
42.1.6 Menu Configuration Options...........................................................................................................................300
Chapter 43
Watchdog (WDOG) Driver
43.1 Introduction...................................................................................................................................................................301
43.1.1 Hardware Operation.........................................................................................................................................301
43.1.2 Software Operation..........................................................................................................................................301
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20 Freescale Semiconductor, Inc.
Section number Title Page
43.2 Generic WDOG Driver.................................................................................................................................................302
43.2.1 Driver Features.................................................................................................................................................302
43.2.2 Menu Configuration Options...........................................................................................................................302
43.2.3 Source Code Structure.....................................................................................................................................302
43.2.4 Programming Interface....................................................................................................................................303
Chapter 44
OProfile
44.1 Introduction...................................................................................................................................................................305
44.1.1 Overview..........................................................................................................................................................305
44.1.2 Features............................................................................................................................................................305
44.1.3 Hardware Operation.........................................................................................................................................306
44.2 Software Operation.......................................................................................................................................................306
44.2.1 Architecture Specific Components..................................................................................................................306
44.2.2 oprofilefs Pseudo Filesystem...........................................................................................................................307
44.2.3 Generic Kernel Driver......................................................................................................................................307
44.2.4 OProfile Daemon.............................................................................................................................................307
44.2.5 Post Profiling Tools.........................................................................................................................................308
44.3 Requirements................................................................................................................................................................308
44.3.1 Source Code Structure.....................................................................................................................................308
44.3.2 Menu Configuration Options...........................................................................................................................308
44.3.3 Programming Interface....................................................................................................................................309
44.3.4 Interrupt Requirements....................................................................................................................................309
Chapter 45
CAAM (Cryptographic Acceleration and Assurance Module)
45.1 CAAM Device Driver Overview..................................................................................................................................311
45.2 Configuration and Job Execution Level.......................................................................................................................311
45.3 Control/Configuration Driver.......................................................................................................................................312
45.4 Job Ring Driver.............................................................................................................................................................312
45.5 API Interface Level.......................................................................................................................................................314
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Section number Title Page
45.6 Driver Configuration.....................................................................................................................................................316
45.7 Limitations....................................................................................................................................................................317
45.8 Limitations in the Existing Implementation Overview.................................................................................................318
45.9 Initialize Keystore Management Interface....................................................................................................................318
45.10 Detect Available Secure Memory Storage Units..........................................................................................................319
45.11 Establish Keystore in Detected Unit.............................................................................................................................319
45.12 Release Keystore...........................................................................................................................................................320
45.13 Allocate a Slot from the Keystore.................................................................................................................................320
45.14 Load Data into a Keystore Slot.....................................................................................................................................321
45.15 Demo Image Update.....................................................................................................................................................321
45.16 Decapsulate Data in the Keystore.................................................................................................................................322
45.17 Read Data From a Keystore Slot..................................................................................................................................323
45.18 Release a Slot back to the Keystore..............................................................................................................................323
45.19 CAAM/SNVS - Security Violation Handling Interface Overview...............................................................................325
45.20 Operation.......................................................................................................................................................................325
45.21 Configuration Interface.................................................................................................................................................326
45.22 Install a Handler............................................................................................................................................................326
45.23 Remove an Installed Driver..........................................................................................................................................326
45.24 Driver Configuration CAAM/SNVS............................................................................................................................327
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22 Freescale Semiconductor, Inc.
Chapter 1
About This Book
1.1 Audience
This document is targeted to individuals who will port the i.MX Linux BSP to customerspecific products.
The audience is expected to have a working knowledge of the Linux 3.0 kernel internals,
driver models, and i.MX processors.
1.1.1 Conventions
This document uses the following notational conventions:
• Courier monospaced type indicate commands, command parameters, code examples,
and file and directory names.
• Italic type indicates replaceable command or function parameters.
• Bold type indicates function names.
1.1.2 Definitions, Acronyms, and Abbreviations
The following table defines the acronyms and abbreviations used in this document.
Definitions and Acronyms
Term Definition
ADC Asynchronous Display Controller
address
translation
API Application Programming Interface
®
ARM
Freescale Semiconductor, Inc. 23
Address conversion from virtual domain to physical domain
Advanced RISC Machines processor architecture
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Audience
Term Definition
AUDMUX Digital audio MUX-provides a programmable interconnection for voice, audio, and synchronous data routing
between host serial interfaces and peripheral serial interfaces
BCD Binary Coded Decimal
bus A path between several devices through data lines
bus load The percentage of time a bus is busy
CODEC Coder/decoder or compression/decompression algorithm-used to encode and decode (or compress and
decompress) various types of data
CPU Central Processing Unit-generic term used to describe a processing core
CRC Cyclic Redundancy Check-Bit error protection method for data communication
CSI Camera Sensor Interface
DFS Dynamic Frequency Scaling
DMA Direct Memory Access-an independent block that can initiate memory-to-memory data transfers
DPM Dynamic Power Management
DRAM Dynamic Random Access Memory
DVFS Dynamic Voltage Frequency Scaling
EMI External Memory Interface-controls all IC external memory accesses (read/write/erase/program) from all the
masters in the system
Endian Refers to byte ordering of data in memory. Little endian means that the least significant byte of the data is
stored in a lower address than the most significant byte. In big endian, the order of the bytes is reversed
EPIT Enhanced Periodic Interrupt Timer-a 32-bit set and forget timer capable of providing precise interrupts at
regular intervals with minimal processor intervention
FCS Frame Checker Sequence
FIFO First In First Out
FIPS Federal Information Processing Standards-United States Government technical standards published by the
National Institute of Standards and Technology (NIST). NIST develops FIPS when there are compelling
Federal government requirements such as for security and interoperability but no acceptable industry
standards
FIPS-140 Security requirements for cryptographic modules-Federal Information Processing Standard 140-2(FIPS 140-2)
is a standard that describes US Federal government requirements that IT products should meet for Sensitive,
but Unclassified (SBU) use
Flash A non-volatile storage device similar to EEPROM, where erasing can be done only in blocks or the entire chip.
Flash path Path within ROM bootstrap pointing to an executable Flash application
Flush Procedure to reach cache coherency. Refers to removing a data line from cache. This process includes
cleaning the line, invalidating its VBR and resetting the tag valid indicator. The flush is triggered by a software
command
GPIO General Purpose Input/Output
hash Hash values are produced to access secure data. A hash value (or simply hash), also called a message
digest, is a number generated from a string of text. The hash is substantially smaller than the text itself, and is
generated by a formula in such a way that it is extremely unlikely that some other text produces the same hash
value.
I/O Input/Output
ICE In-Circuit Emulation
IP Intellectual Property
IPU Image Processing Unit -supports video and graphics processing functions and provides an interface to video/
still image sensors and displays
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24 Freescale Semiconductor, Inc.
Chapter 1 About This Book
Term Definition
IrDA Infrared Data Association-a nonprofit organization whose goal is to develop globally adopted specifications for
infrared wireless communication
ISR Interrupt Service Routine
JTAG JTAG (IEEE Standard 1149.1) A standard specifying how to control and monitor the pins of compliant devices
on a printed circuit board
Kill Abort a memory access
KPP KeyPad Port-16-bit peripheral used as a keypad matrix interface or as general purpose input/output (I/O)
line Refers to a unit of information in the cache that is associated with a tag
LRU Least Recently Used-a policy for line replacement in the cache
MMU Memory Management Unit-a component responsible for memory protection and address translation
MPEG Moving Picture Experts Group-an ISO committee that generates standards for digital video compression and
audio. It is also the name of the algorithms used to compress moving pictures and video
MPEG
standards
MQSPI Multiple Queue Serial Peripheral Interface-used to perform serial programming operations necessary to
MSHC Memory Stick Host Controller
NAND Flash Flash ROM technology-NAND Flash architecture is one of two flash technologies (the other being NOR) used
NOR Flash See NAND Flash
PCMCIA Personal Computer Memory Card International Association-a multi-company organization that has developed
physical
address
PLL Phase Locked Loop-an electronic circuit controlling an oscillator so that it maintains a constant phase angle (a
RAM Random Access Memory
RAM path Path within ROM bootstrap leading to the downloading and the execution of a RAM application
RGB The RGB color model is based on the additive model in which Red, Green, and Blue light are combined to
RGBA RGBA color space stands for Red Green Blue Alpha. The alpha channel is the transparency channel, and is
RNGA Random Number Generator Accelerator-a security hardware module that produces 32-bit pseudo random
ROM Read Only Memory
ROM
bootstrap
RTIC Real-Time Integrity Checker-a security hardware module
SCC SeCurity Controller-a security hardware module
Several standards of compression for moving pictures and video:
• MPEG-1 is optimized for CD-ROM and is the basis for MP3
• MPEG-2 is defined for broadcast video in applications such as digital television set-top boxes and DVD
• MPEG-3 was merged into MPEG-2
• MPEG-4 is a standard for low-bandwidth video telephony and multimedia on the World-Wide Web
configure radio subsystems and selected peripherals
in memory cards such as the Compact Flash cards. NAND is best suited to flash devices requiring high
capacity data storage. NAND flash devices offer storage space up to 512-Mbyte and offers faster erase, write,
and read capabilities over NOR architecture
a standard for small, credit card-sized devices, called PC Cards. There are three types of PCMCIA cards that
have the same rectangular size (85.6 by 54 millimeters), but different widths
The address by which the memory in the system is physically accessed
lock) on the frequency of an input, or reference, signal
create other colors. The abbreviation RGB comes from the three primary colors in additive light models
unique to this color space. RGBA, like RGB, is an additive color space, so the more of a color placed, the
lighter the picture gets. PNG is the best known image format that uses the RGBA color space
numbers as part of the security module
Internal boot code encompassing the main boot flow as well as exception vectors
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Freescale Semiconductor, Inc. 25
Audience
Term Definition
SDMA Smart Direct Memory Access
SDRAM Synchronous Dynamic Random Access Memory
SoC System on a Chip
SPBA Shared Peripheral Bus Arbiter-a three-to-one IP-Bus arbiter, with a resource-locking mechanism
SPI Serial Peripheral Interface-a full-duplex synchronous serial interface for connecting low-/medium-bandwidth
external devices using four wires. SPI devices communicate using a master/slave relationship over two data
lines and two control lines: Also see SS, SCLK, MISO, and MOSI
SRAM Static Random Access Memory
SSI Synchronous-Serial Interface-standardized interface for serial data transfer
TBD To Be Determined
UART Universal Asynchronous Receiver/Transmitter-asynchronous serial communication to external devices
UID Unique ID-a field in the processor and CSF identifying a device or group of devices
USB Universal Serial Bus-an external bus standard that supports high speed data transfers. The USB 1.1
specification supports data transfer rates of up to 12 Mb/s and USB 2.0 has a maximum transfer rate of 480
Mbps. A single USB port can be used to connect up to 127 peripheral devices, such as mice, modems, and
keyboards. USB also supports Plug-and-Play installation and hot plugging
USBOTG USB On The Go-an extension of the USB 2.0 specification for connecting peripheral devices to each other.
USBOTG devices, also known as dual-role peripherals, can act as limited hosts or peripherals themselves
depending on how the cables are connected to the devices, and they also can connect to a host PC
word A group of bits comprising 32-bits
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26 Freescale Semiconductor, Inc.
Chapter 2
Introduction
2.1 Overview
The purpose of this software package is to support Linux on the i.MX 6Solo/6DualLite
family of Integrated Circuits (ICs) and their associated platforms. It provides the
necessary software to interface the standard open-source Linux kernel to the i.MX
hardware. The goal is to enable Freescale customers to rapidly build products based on
i.MX devices that use the Linux OS.
The BSP is not a platform or product reference implementation. It does not contain all of
the product-specific drivers, hardware-independent software stacks, Graphical User
Interface (GUI) components, Java Virtual Machine (JVM), and applications required for
a product. Some of these are made available in their original open-source form as part of
the base kernel.
The BSP is not intended to be used for silicon verification. While it can play a role in
this, the BSP functionality and the tests run on the BSP do not have sufficient coverage to
replace traditional silicon verification test suites.
2.1.1 Software Base
The i.MX BSP is based on version 3.0.35 of the Linux kernel from the official Linux
kernel web site (http://www.kernel.org ). It is enhanced with the features provided by
Freescale.
2.1.2 Features
Table below describes the features supported by the Linux BSP for specific platforms.
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Freescale Semiconductor, Inc. 27
Overview
Table 2-1. Linux BSP Supported Features
Feature Description Chapter Source Applicable
Machine Specific Layer
MSL Machine Specific Layer (MSL) supports interrupts,
Timer, Memory Map, GPIO/IOMUX, SPBA, SDMA.
• Interrupts GIC: The linux kernel contains common
ARM GIC interrupts handling code.
• Timer (GPT): The General Purpose Timer (GPT)
is set up to generate an interrupt as programmed
to provide OS ticks. Linux facilitates timer use
through various functions for timing delays,
measurement, events, alarms, high resolution
timer features, and so on. Linux defines the MSL
timer API required for the OS-tick timer and does
not expose it beyond the kernel tick
implementation.
• GPIO/EDIO/IOMUX: The GPIO and EDIO
components in the MSL provide an abstraction
layer between the various drivers and the
configuration and utilization of the system,
including GPIO, IOMUX, and external board I/O.
The IO software module is board-specific, and
resides in the MSL layer as a self-contained set
of files. I/O configuration changes are centralized
in the GPIO module so that changes are not
required in the various drivers.
• SPBA: The Shared Peripheral Bus Arbiter
(SPBA) provides an arbitration mechanism
among multiple masters to allow access to the
shared peripherals. The SPBA implementation
under MSL defines the API to allow different
masters to take or release ownership of a shared
peripheral.
SDMA API The Smart Direct Memory Access (SDMA) API driver
controls the SDMA hardware. It provides an API to
other drivers for transferring data between MCU, DSP
and peripherals. . The SDMA controller is responsible
for transferring data between the MCU memory space,
peripherals, and the DSP memory space. The SDMA
API allows other drivers to initialize the scripts, pass
parameters and control their execution. SDMA is based
on a microRISC engine that runs channel-specific
scripts.
DMAC Both AHB-to-APBH and AHB-to-APBX DMA support
configurable DMA descript chain.
Low-level PM
Drivers
CPU Frequency
Scaling
The low-level power management driver is responsible
for implementing hardware-specific operations to meet
power requirements and also to conserve power on the
development platforms. Driver implementations are
often different for different platforms. It is used by the
DPM layer.
The CPU frequency scaling device driver allows the
clock speed of the CPUs to be changed on the fly.
Machine Specific Layer (MSL) All
Smart Direct Memory Access
(SDMA) API
AHB-to-APBH Bridge with DMA
(APBH-Bridge-DMA)
Low-level Power Management
(PM) Driver
CPU Frequency Scaling
(CPUFREQ) Driver
Platform
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
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28 Freescale Semiconductor, Inc.
Chapter 2 Introduction
Table 2-1. Linux BSP Supported Features (continued)
Feature Description Chapter Source Applicable
Platform
DVFS The Dynamic Voltage Frequency Scaling (DVFS)
device driver allows simple dynamic voltage frequency
scaling. The frequency of the core clock domain and
the voltage of the core power domain can be changed
on the fly with all modules continuing their normal
operations.
Multimedia Drivers
IPU The Image Processing Unit (IPU) is designed to
support video and graphics processing functions and to
interface with video/still image sensors and displays.
The IPU driver is a self-contained driver module in the
Linux kernel. It contains a custom kernel-level API to
manipulate logical channels. A logical channel
represents a complete IPU processing flow. The IPU
driver includes a frame buffer driver, a V4L2 device
driver, and low-level IPU drivers.
HDMI This driver provides the support HDMI module HDMI Driver i.MX 6Solo/
Dual Display This chapter introduces the basic infromation about
dual display
V4L2 Output The Video for Linux 2 (V4L2) output driver uses the IPU
post-processing functions for video output. The driver
implements the standard V4L2 API for output devices.
V4L2 Capture The Video for Linux 2 (V4L2) capture device includes
two interfaces: the capture interface and the overlay
interface. The capture interface records the video
stream. The overlay interface displays the preview
video.
VPU The Video Processing Unit (VPU) is a multi-standard
video decoder and encoder that can perform decoding
and encoding of various video formats.
Sound Drivers
ALSA Sound The Advanced Linux Sound Architecture (ALSA) is a
sound driver that provides ALSA and OSS compatible
applications with the means to perform audio playback
and recording functions. ALSA has a user-space
component called ALSAlib that can extend the features
of audio hardware by emulating the same in software
(user space), such as resampling, software mixing,
snooping, and so on. The ASoC Sound driver supports
stereo CODEC playback and capture through SSI.
S/PDIF The S/PDIF driver is designed under the Linux ALSA
subsystem. It implements one playback device for Tx
and one capture device for Rx.
Memory Drivers
SPI NOR MTD The SPI NOR MTD driver provides the support to the
Atmel data Flash using the SPI interface.
Dynamic Voltage Frequency
Scaling (DVFS) Driver
Image Processing Unit (IPU)
Drivers
Dual Display i.MX 6Solo/
Video for Linux Two (V4L2) Driver i.MX 6Solo/
Video for Linux Two (V4L2) Driver i.MX 6Solo/
Video Processing Unit (VPU)
Driver
ALSA Sound Driver i.MX 6Solo/
The Sony/Philips Digital Interface
(S/PDIF) Driver
SPI NOR Flash Memory
Technology Device (MTD) Driver
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
6DualLite
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
i.MX 6Solo/
6DualLite
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Freescale Semiconductor, Inc. 29
Overview
Table 2-1. Linux BSP Supported Features (continued)
Feature Description Chapter Source Applicable
NAND MTD The NAND MTD driver interfaces with the integrated
NAND controller. It can support various file systems,
such as UBIFS, CRAMFS and JFFS2UBI and
UBIFSCRAMFS and JFFS2. The driver implementation
supports the lowest level operations on the external
NAND Flash chip, such as block read, block write and
block erase as the NAND Flash technology only
supports block access. Because blocks in a NAND
Flash are not guaranteed to be good, the NAND MTD
driver is also able to detect bad blocks and feed that
information to the upper layer to handle bad block
management.
Input Device Drivers
Networking Drivers
ENET The ENET Driver performs the full set of IEEE 802.3/
Ethernet CSMA/CD media access control and channel
interface functions. The FEC requires an external
interface adaptor and transceiver function to complete
the interface to the Ethernet media. It supports half or
full-duplex operation on 10M\100M related Ethernet
networks.
Bus Drivers
I2C The I2C bus driver is a low-level interface that is used
to interface with the I2C bus. This driver is invoked by
the I2C chip driver; it is not exposed to the user space.
The standard Linux kernel contains a core I2C module
that is used by the chip driver to access the bus driver
to transfer data over the I2C bus. This bus driver
supports:
• Compatibility with the I2C bus standard
• Bit rates up to 400 Kbps
• Standard I2C master mode
• Power management features by suspending and
resuming I2C.
CSPI The low-level Enhanced Configurable Serial Peripheral
Interface (ECSPI) driver interfaces a custom, kernelspace API to both ECSPI modules. It supports the
following features:
• Interrupt-driven transmit/receive of SPI frames
• Multi-client management
• Priority management between clients
• SPI device configuration per client
MMC/SD/SDIO uSDHC
UART Drivers
MXC UART The Universal Asynchronous Receiver/Transmitter
The MMC/SD/SDIO Host driver implements the
standard Linux driver interface to eSDHC.
(UART) driver interfaces the Linux serial driver API to
all of the UART ports. A kernel configuration parameter
Table continues on the next page...
NAND GPMI Flash Driver i.MX 6Solo/
Fast Ethernet Controller (FEC)
Driver
Inter-IC (I2C) Driver i.MX 6Solo/
Enhanced Configurable Serial
Peripheral Interface (ECSPI) Driver
MMC/SD/SDIO Host Driver i.MX 6Solo/
Universal Asynchronous Receiver/
Transmitter (UART) Driver
Platform
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
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30 Freescale Semiconductor, Inc.
Chapter 2 Introduction
Table 2-1. Linux BSP Supported Features (continued)
Feature Description Chapter Source Applicable
gives the user the ability to choose the UART driver
and also to choose whether the UART should be used
as the system console.
General Drivers
USB The USB driver implements a standard Linux driver
interface to the ARC USB-OTG controller.
FlexCAN The FlexCAN driver is designed as a network device
driver. It provides the interfaces to send and receive
CAN messages. The CAN protocol was primarily
designed to be used as a vehicle serial data bus,
meeting the specific requirements of this field: real-time
processing, reliable operation in the EMI environment
of a vehicle, cost-effectiveness and required bandwidth.
ASRC The Asynchronous Sample Rate Converter (ASRC)
driver provides the interfaces to access the
asynchronous sample rate converter module.
WatchDog The Watchdog Timer module protects against system
failures by providing an escape from unexpected hang
or infinite loop situations or programming errors. This
WDOG implements the following features:
• Generates a reset signal if it is enabled but not
serviced within a predefined time-out value
• Does not generate a reset signal if it is serviced
within a predefined time-out value
MXC PWM driver The MXC PWM driver provides the interfaces to access
MXC PWM signals
Thermal Driver Thermal driver is a necessary driver for monitoring and
protecting the SoC. The thermal driver will monitor the
SoC's temperature in a certain frequency. It defines
three trip points: critical, hot, and active.
OProfile OProfile is a system-wide profiler for Linux systems,
capable of profiling all running code at low overhead.
ARC USB Driver i.MX 6Solo/
6DualLite
FlexCAN Driver i.MX 6Solo/
6DualLite
Asynchronous Sample Rate
Converter (ASRC) Driver
Watchdog (WDOG) Driver i.MX 6Solo/
Pulse-Width Modulator (PWM)
Driver
Thermal Driver i.MX 6Solo/
OProfile i.MX 6Solo/
i.MX 6Solo/
6DualLite
6DualLite
i.MX 6Solo/
6DualLite
6DualLite
6DualLite
Platform
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Overview
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32 Freescale Semiconductor, Inc.
Chapter 3
Machine Specific Layer (MSL)
3.1 Introduction
The Machine Specific Layer (MSL) provides the Linux kernel with the following
machine-dependent components:
• Interrupts including GPIO and EDIO (only on certain platforms)
• Timer
• Memory map
• General Purpose Input/Output (GPIO) including IOMUX on certain platforms
• Shared Peripheral Bus Arbiter (SPBA)
• Smart Direct Memory Access (SDMA)
These modules are normally available in the following directory:
<ltib_dir>/rpm/BUILD/linux/arch/arm/mach-mx6 for i.MX 6 platform
The header files are implemented under the following directory:
<ltib_dir>/rpm/BUILD/linux/arch/arm/plat-mxc/include/mach
The MSL layer contains not only the modules common to all the boards using the same
processor, such as the interrupts and timer, but it also contains modules specific to each
board, such as the memory map. The following sections describe the basic hardware and
software operations and the software interfaces for MSL modules. First, the common
modules, such as Interrupts and Timer are discussed. Next, the board-specific modules,
such as Memory Map and General Purpose Input/Output (GPIO) (including IOMUX on
some platforms) are detailed. Because of the complexity of the SDMA module, its design
is explained in SDMA relevant chapter.
Each of the following sections contains an overview of the hardware operation. For more
information, see the corresponding device documentation.
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Freescale Semiconductor, Inc. 33
Interrupts (Operation)
3.2 Interrupts (Operation)
This section explains the hardware and software operation of interrupts on the device.
3.2.1 Interrupt Hardware Operation
The Interrupt Controller controls and prioritizes a maximum of 128 internal and external
interrupt sources.
Each source can be enabled or disabled by configuring the Interrupt Enable Register or
using the Interrupt Enable/Disable Number Registers. When an interrupt source is
enabled and the corresponding interrupt source is asserted, the Interrupt Controller asserts
a normal or a fast interrupt request depending on the associated Interrupt Type Register
settings.
Interrupt Controller registers can only be accessed in supervisor mode. The Interrupt
Controller interrupt requests are prioritized in the following order: fast interrupts and
normal interrupts for the highest priority level, then highest source number with the same
priority. There are 16 normal interrupt levels for all interrupt sources, with level zero
being the lowest priority. The interrupt levels are configurable through eight normal
interrupt priority level registers. Those registers, along with the Normal Interrupt Mask
Register, support software-controlled priority levels for normal interrupts and priority
masking.
3.2.2 Interrupt Software Operation
For ARM-based processors, normal interrupt and fast interrupt are two different
exception types. The exception vector addresses can be configured to start at low address
(0x0) or high address (0xFFFF0000).
The ARM Linux implementation chooses the high vector address model.
The following file describes the ARM interrupt architecture.
<ltib_dir>/rpm/BUILD/linux/Documentation/arm/Interrupts
The software provides a processor-specific interrupt structure with callback functions
defined in the irqchip structure and exports one initialization function, which is called
during system startup.
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3.2.3 Interrupt Features
The interrupt implementation supports the following features:
• Interrupt Controller interrupt disable and enable
• Functions required by the Linux interrupt architecture as defined in the standard
ARM interrupt source code (mainly the <ltib_dir>/rpm/BUILD/linux/arch/arm/
kernel/irq.c file)
3.2.4 Interrupt Source Code Structure
The interrupt module is implemented in the following file (located in the directory
<ltib_dir>/rpm/BUILD/linux/arch/arm/plat-mxc):
irq.c (If CONFIG_MXC_TZIC is not selected)
tzic.c (If CONFIG_MXC_TZIC is selected)
gic.c (If CONFIG_ARM_GIC is selected)
There are also two header files (located in the include directory specified at the beginning
of this chapter):
hardware.h
irqs.h
The following table lists the source files for interrupts.
Table 3-1. Interrupt Files
File Description
hardware.h Register descriptions
irqs.h Declarations for number of interrupts supported
gic.c Actual interrupt functions for GIC modules
3.2.5 Interrupt Programming Interface
The machine-specific interrupt implementation exports a single function.
This function initializes the Interrupt Controller hardware and registers functions for
interrupt enable and disable from each interrupt source.
This is done with the global structure irq_desc of type struct irqdesc. After the
initialization, the interrupt can be used by the drivers through the request_irq() function to
register device-specific interrupt handlers.
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Timer
In addition to the native interrupt lines supported by the Interrupt Controller, the number
of interrupts is also expanded to support GPIO interrupt and (on some platforms) EDIO
interrupts. This allows drivers to use the standard interrupt interface supported by ARM
Linux, such as the request_irq() and free_irq() functions.
3.3 Timer
The Linux kernel relies on the underlying hardware to provide support for both the
system timer (which generates periodic interrupts) and the dynamic timers (to schedule
events).
After the system timer interrupt occurs, it performs the following operations:
• Updates the system uptime.
• Updates the time of day.
• Reschedules a new process if the current process has exhausted its time slice.
• Runs any dynamic timers that have expired.
• Updates resource usage and processor time statistics.
The timer hardware on most i.MX platforms consists of either Enhanced Periodic
Interrupt Timer (EPIT) or general purpose timer (GPT) or both. GPT is configured to
generate a periodic interrupt at a certain interval (every 10 ms) and is used by the Linux
kernel.
3.3.1 Timer Software Operation
The timer software implementation provides an initialization function that initializes the
GPT with the proper clock source, interrupt mode and interrupt interval.
The timer then registers its interrupt service routine and starts timing. The interrupt
service routine is required to service the OS for the purposes mentioned in Timer.
Another function provides the time elapsed as the last timer interrupt.
3.3.2 Timer Features
The timer implementation supports the following features:
• Functions required by Linux to provide the system timer and dynamic timers.
• Generates an interrupt every 10 ms.
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3.3.3 Timer Source Code Structure
The timer module is implemented in the arch/arm/plat-mxc/time.c file.
3.3.4 Timer Programming Interface
The timer module utilizes four hardware timers, to implement clock source and clock
event objects.
This is done with the clocksource_mxc structure of struct clocksource type and
clockevent_mxc structure of struct clockevent_device type. Both structures provide
routines required for reading current timer values and scheduling the next timer event.
The module implements a timer interrupt routine that services the Linux OS with timer
events for the purposes mentioned in the beginning of this chapter.
3.4 Memory Map
A predefined virtual-to-physical memory map table is required for the device drivers to
access to the device registers since the Linux kernel is running under the virtual address
space with the Memory Management Unit (MMU) enabled.
3.4.1 Memory Map Hardware Operation
The MMU, as a part of the ARM core, provides the virtual-to-physical address mapping
defined by the page table. For more information, see the ARM Technical Reference
Manual (TRM) from ARM Limited.
3.4.2 Memory Map Software Operation
A table mapping the virtual memory to physical memory is implemented for i.MX
platforms as defined in the file in <ltib_dir>/rpm/BUILD/linux/arch/arm/mach-mx6/
mm.c .
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IOMUX
3.4.3 Memory Map Features
The Memory Map implementation programs the Memory Map module to create the
physical-to-virtual memory map for all the I/O modules.
3.4.4 Memory Map Source Code Structure
The Memory Map module implementation is in mm.c under the platform-specific MSL
directory. The hardware.h header file is used to provide macros for all the I/O module
physical and virtual base addresses and physical to virtual mapping macros. All of the
memory map source code is in the following directory:
<ltib_dir>/rpm/BUILD/linux/arch/arm/plat-mxc/include/mach
The following table lists the source files for the memory map.
Table 3-2. Memory Map Files
File Description
mx6.h Header files for the I/O module physical addresses
3.4.5 Memory Map Programming Interface
The Memory Map is implemented in the mm.c file to provide the map between physical
and virtual addresses. It defines an initialization function to be called during system
startup.
3.5 IOMUX
The limited number of pins of highly integrated processors can have multiple purposes.
The IOMUX module controls a pin usage so that the same pin can be configured for
different purposes and can be used by different modules.
This is a common way to reduce the pin count while meeting the requirements from
various customers. Platforms that do not have the IOMUX hardware module can do pin
muxing through the GPIO module.
The IOMUX module provides the multiplexing control so that each pin may be
configured either as a functional pin or as a GPIO pin. A functional pin can be subdivided
into either a primary function or alternate functions. The pin operation is controlled by a
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specific hardware module. A GPIO pin, is controlled by the user through software with
further configuration through the GPIO module. For example, the TXD1 pin might have
the following functions:
• TXD1: internal UART1 Transmit Data. This is the primary function of this pin.
• UART2 DTR: alternate mode 3
• LCDC_CLS: alternate mode 4
• GPIO4[22]: alternate mode 5
• SLCDC_DATA[8]: alternate mode 6
If the hardware modes are chosen at the system integration level, this pin is dedicated
only to that purpose and cannot be changed by software. Otherwise, the IOMUX module
needs to be configured to serve a particular purpose that is dictated by the system (board)
design.
• If the pin is connected to an external UART transceiver and therefore to be used as
the UART data transmit signal, it should be configured as the primary function.
• If the pin is connected to an external Ethernet controller for interrupting the ARM
core, it should be configured as GPIO input pin with interrupt enabled.
The software does not have control over what function a pin should have. The software
only configures pin usage according to the system design.
3.5.1 IOMUX Hardware Operation
The following information applies only to those processors that have an IOMUX
hardware module.
The IOMUX controller registers are briefly described in this section.
For detailed information, see the pin multiplexing section of the IC reference manual.
• SW_MUX_CTL: Selects the primary or alternate function of a pin, and enables
loopback mode when applicable.
• SW_SELECT_INPUT: Controls pin input path. This register is only required when
multiple pads drive the same internal port.
• SW_PAD_CTL: Controls pad slew rate, driver strength, pull-up/down resistance, and
so on.
3.5.2 IOMUX Software Operation
The IOMUX software implementation provides an API to set up pin functions and pad
features.
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IOMUX
3.5.3 IOMUX Features
The IOMUX implementation programs the IOMUX module to configure the pins that are
supported by the hardware.
3.5.4 IOMUX Source Code Structure
The following table lists the source files for the IOMUX module. The files are in the
directory:
<ltib_dir>/rpm/BUILD/arch/arm/plat-mxc/
<ltib_dir>/rpm/BUILD/arch/arm/plat-mxc/include/mach
Table 3-3. IOMUX Files
File Description
iomux-v3.c IOMUX function implementation
iomux-mx6dl.h Pin definitions in the iomux_pins enum
3.5.5 IOMUX Programming Interface
All the IOMUX functions required for the Linux port are implemented in the iomux-v3.c
file.
3.5.6 IOMUX Control Through GPIO Module
For a multi-purpose pin, the GPIO controller provides the multiplexing control so that
each pin may be configured either as a functional pin or a GPIO pin.
The operation of the functional pin, which can be subdivided into either major function or
one alternate function, is controlled by a specific hardware module. If it is configured as a
GPIO pin, the pin is controlled by the user through software with further configuration
through the GPIO module. In addition, there are some special configurations for a GPIO
pin (such as output based A_IN, B_IN, C_IN or DATA register, but input based A_OUT
or B_OUT).
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The following discussion applies to those platforms that control the muxing of a pin
through the general purpose input/output (GPIO) module.
If the hardware modes are chosen at the system integration level, this pin is dedicated
only to that purpose which can not be changed by software. Otherwise, the GPIO module
needs to be configured properly to serve a particular purpose that is dictated with the
system (board) design.
• If this pin is connected to an external UART transceiver, it should be configured as
the primary function.
• If this pin is connected to an external Ethernet controller for interrupting the core, it
should be configured as GPIO input pin with interrupt enabled.
The software does not have control over what function a pin should have. The software
only configures a pin for that usage according to the system design.
3.5.6.1 GPIO Hardware Operation
The GPIO controller module is divided into MUX control and PULLUP control sub
modules. The following sections briefly describe the hardware operation. For detailed
information, refer to the relevant device documentation.
3.5.6.1.1 Muxing Control
The GPIO In Use Registers control a multiplexer in the GPIO module.
The settings in these registers choose if a pin is utilized for a peripheral function or for its
GPIO function. One 32-bit general purpose register is dedicated to each GPIO port.
These registers may be used for software control of IOMUX block of the GPIO.
3.5.6.1.2 PULLUP Control
The GPIO module has a PULLUP control register (PUEN) for each GPIO port to control
every pin of that port.
3.5.6.2 GPIO Software Operation (general)
The GPIO software implementation provides an API to setup pin functions and pad
features.
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General Purpose Input/Output(GPIO)
3.5.6.3 GPIO Implementation
The GPIO implementation programs the GPIO module to configure the pins that are
supported by the hardware.
3.5.6.4 GPIO Source Code Structure
The GPIO module is implemented in the iomux.cgpio_mux.c file under the relevant MSL
directory. The header file to define the pin names is under:
<ltib_dir>/rpm/BUILD/arch/arm/plat-mxc/include/mach
The following table lists the source files for the IOMUX.
Table 3-4. IOMUX Through GPIO Files
File Description
iomux-mx6dl.h Pin name definitions
3.5.6.5 GPIO Programming Interface
All the GPIO muxing functions required for the Linux port are implemented in the
iomux-v3.c file.
3.6 General Purpose Input/Output(GPIO)
The GPIO module provides general-purpose pins that can be configured as either inputs
or outputs.
When configured as an output, the pin state (high or low) can be controlled by writing to
an internal register. When configured as an input, the pin input state can be read from an
internal register.
3.6.1 GPIO Software Operation
The general purpose input/output (GPIO) module provides an API to configure the i.MX
processor external pins and a central place to control the GPIO interrupts.
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The GPIO utility functions should be called to configure a pin instead of directly
accessing the GPIO registers. The GPIO interrupt implementation contains functions,
such as the interrupt service routine (ISR) registration/un-registration and ISR
dispatching once an interrupt occurs. All driver-specific GPIO setup functions should be
made during device initialization at the MSL layer to provide better portability and
maintainability. This GPIO interrupt is initialized automatically during the system
startup.
If a pin is configured to GPIO by the IOMUX, the state of the pin should also be set
because it is not initialized by a dedicated hardware module. Setting the pad pull-up, pulldown, slew rate and so on, with the pad control function may be required as well.
3.6.1.1 API for GPIO
API for GPIO lists the features supported by the GPIO implementation.
The GPIO implementation supports the following features:
• An API for registering an interrupt service routine to a GPIO interrupt. This is made
possible as the number of interrupts defined by NR_IRQS is expanded to
accommodate all the possible GPIO pins that are capable of generating interrupts.
• Functions to request and free an IOMUX pin. If a pin is used as GPIO, another set of
request/free function calls are provided. The user should check the return value of the
request calls to see if the pin has already been reserved before modifying the pin
state. The free function calls should be made when the pin is not needed. See the API
document for more details.
• Aligned parameter passing for both IOMUX and GPIO function calls. In this
implementation the same enumeration for iomux_pins is used for both IOMUX and
GPIO calls and the user does not have to figure out in which bit position a pin is
located in the GPIO module.
• Minimal changes required for the public drivers such as Ethernet and UART drivers
as no special GPIO function call is needed for registering an interrupt.
3.6.2 GPIO Features
This GPIO implementation supports the following features:
• Implementing the functions for accessing the GPIO hardware modules
• Provideing a way to control GPIO signal direction and GPIO interrupts
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General Purpose Input/Output(GPIO)
3.6.3 GPIO Module Source Code Structure
All of the GPIO module source code is at the MSL layer, in the following files, located in
the directories indicated at the beginning of this chapter:
Table 3-5. GPIO Files
File Description
iomux-mx .h IOMUX common header file
gpio.h GPIO public header file
gpio.c Function implementation
3.6.4 GPIO Programming Interface 2
For more information, see the Documentation/gpio.txt under the Linux source code
directory for the programming interface.
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Chapter 4
Smart Direct Memory Access (SDMA) API
4.1 Overview
The Smart Direct Memory Access (SDMA) API driver controls the SDMA hardware.
It provides an API to other drivers for transferring data between MCU memory space and
the peripherals. It supports the following features:
• Loading channel scripts from the MCU memory space into SDMA internal RAM
• Loading context parameters of the scripts
• Loading buffer descriptor parameters of the scripts
• Controlling execution of the scripts
• Callback mechanism at the end of script execution
4.1.1 Hardware Operation
The SDMA controller is responsible for transferring data between the MCU memory
space and peripherals. It has the following features:
• Multi-channel DMA, supporting up to 32 time-division multiplexed DMA channels.
• Powered by a 16-bit Instruction-Set micro-RISC engine.
• Each channel executes specific script.
• Very fast context-switching with two-level priority based preemptive multi-tasking.
• 4-KB ROM containing startup scripts (that is, boot code) and other common utilities
that can be referenced by RAM-located scripts.
• 8-KB RAM area is divided into a processor context area and a code space area used
to store channel scripts that are downloaded from the system memory.
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4.1.2 Software Operation
The driver provides an API for other drivers to control SDMA channels. SDMA channels
run dedicated scripts according to peripheral and transfer types. The SDMA API driver is
responsible for loading the scripts into SDMA memory, initializing the channel
descriptors, and controlling the buffer descriptors and SDMA registers.
The table below provides a list of drivers that use SDMA and the number of SDMA
physical channels used by each driver. A driver can specify the SDMA channel number
that it wishes to use, which is called static channel allocation. It can also have the SDMA
driver and provide a free SDMA channel for the driver to use, which is called dynamic
channel allocation. For dynamic channel allocation, the list of SDMA channels is scanned
from channel 32 to channel 1. Upon finding a free channel, that channel is allocated for
the requested DMA transfers.
Table 4-1. SDMA Channel Usage
Driver Name Number of
SDMA Channels
SDMA CMD 1 Static Channel allocation-uses SDMA channels 0
SSI 2 per device Dynamic channel allocation
UART 2 per device Dynamic channel allocation
SPDIF 2 per device Dynamic channel allocation
ESAI 2 per device Dynamic channel allocation
SDMA Channel Used
4.1.3 Source Code Structure
The dmaengine.h (header file for SDMA API) is available in the directory /<ltib_dir>/
rpm/BUILD/linux/include/linux
The following table shows the source files available in the directory /<ltib_dir>/rpm/
BUILD/linux/drivers/dma
Table 4-2. SDMA API Source Files
File Description
dmaengine.c SDMA management routine
imx-sdma.c SDMA implement driver
The following table shows the image files available in the directory /<ltib_dir>/rpm/
BUILD/linux/firmware/imx/sdma
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Chapter 4 Smart Direct Memory Access (SDMA) API
Table 4-3. SDMA Script Files
File Description
4.1.4 Menu Configuration Options
The following Linux kernel configuration option is provided for this module. To get to
this options, use the ./ltib -c command when located in the <ltib dir>. On the screen
displayed, select Configure the Kernel and exit. When the next screen appears, select
the following option to enable this module:
• CONFIG_IMX_SDMA_: This is the configuration option for the SDMA API driver.
In menuconfig, this option is available under DMA Engine support.
4.1.5 Programming Interface
The module implements standard DMA API. For more information on the functions
implemented in the driver, refer to the API documents, which are included in the Linux
documentation package. For additional information, refer to the ESAI driver.
4.1.6 Usage Example
Refer to one of the drivers, such as SPDIF driver, UART driver or SSI driver, that uses
the SDMA API driver as a usage example.
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Chapter 5
AHB-to-APBH Bridge with DMA (APBH-Bridge-DMA)
5.1 Overview
The AHB-to-APBH bridge provides the processor with an inexpensive peripheral
attachment bus running on the AHB's HCLK.
(The H in APBH indicates that the APBH is synchronous to HCLK.)
The AHB-to-APBH bridge includes the AHB-to-APB PIO bridge for a memory-mapped
I/O to the APB devices, a central DMA facility for devices on this bus and a vectored
interrupt controller for the ARM core. Each one of the APB peripherals, including the
vectored interrupt controller, is documented in its own chapter in this document.
There is no separated DMA bus for these devices. An internal arbitration logic solves the
conflict that occurs when the DMA uses the APBH bus and the AHB-to-APB bridge
functions use the APBH. For conflict between these two units, the DMA is master and
the AHB is standby, which will report "not ready" through its HREADY output until the
bridge transfer is complete. The arbiter tracks repeated lockouts and inverts the priority,
guaranteeing the ARM platform every four rounds of transfer on the APB.
5.1.1 Hardware Operation
The SDMA controller is responsible for transferring data between the MCU memory
space and peripherals. It has the following features:
• Multi-channel DMA supporting up to 32 time-division multiplexed DMA channels
• Powered by a 16-bit Instruction-Set micro-RISC engine
• Each channel executes specific script
• Very fast context-switching with preemptive multi-tasking based on two-level
priority
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• 4-KB ROM containing startup scripts (that is, boot code) and other common utilities
that can be referenced by RAM-located scripts
• 8-KB RAM area divided into a processor context area and a code space area used to
store channel scripts that are downloaded from the system memory.
5.1.2 Software Operation
The DMA supports 16 channels of DMA services, as shown in the following table. The
shared DMA resource allows each independent channel to follow a simple chained
command list. Command chains are built up by using the general structure.
Table 5-1. APBH DMA Channel Assignments
APBH DMA Channel # Usage
0 GPMI0
1 GPMI1
2 GPMI2
3 GPMI3
4 GPMI4
5 GPMI5
6 GPMI6
7 GPMI7
8 EMPTY
9 EMPTY
10 EMPTY
11 EMPTY
12 EMPTY
13 EMPTY
14 EMPTY
15 EMPTY
5.1.3 Source Code Structure
The following table shows the source files available in the directory drivers/dma/
Table 5-2. APBH DMA Source Files
File Description
mxs-dma.c APBH DMA implement driver
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5.1.4 Menu Configuration Options
MXS_DMA is the configuration option for the APBH DMA driver. In menu
configuration, this option is available under Device Drivers > DMA Engine support >
MXS DMA support.
5.1.5 Programming Interface
The module implements standard DMA API. For more information on the functions
implemented in the driver such as GPMI NAND driver, refer to the API documents,
which are located in the Linux documentation package.
5.1.6 Usage Example
Refer to one of the drivers, such as the GPMI NAND driver, that uses the APBH DMA
driver as a usage example.
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Chapter 6
Image Processing Unit (IPU) Drivers
6.1 Introduction
The image processing unit (IPU) is designed to support video and graphics processing
functions and to connect with video and still image sensors and displays. The IPU driver
provides a kernel-level API to manipulate logical channels. A logical channel represents
a complete IPU processing flow. For example,
• A complete IPU processing flow (logical channel) might consist of reading a YUV
buffer from memory, performing post-processing, and writing an RGB buffer to
memory.
• A logical channel maps one to three IDMA channels and maps to either zero or one
IC tasks.
• A logical channel can have one input, one output, and one secondary input IDMA
channel.
The IPU API consists of a set of common functions for all channels. It aims to initialize
channels, set up buffers, enable and disable channels, link channels for auto frame
synchronization, and set up interrupts.
Typical logical channels include:
• CSI direct to memory
• CSI to viewfinder pre-processing to memory
• Memory to viewfinder pre-processing to memory
• Memory to viewfinder rotation to memory
• Previous field channel of memory to video deinterlacing and viewfinder preprocessing to memory
• Current field channel of memory to video deinterlacing and viewfinder preprocessing to memory
• Next field channel of memory to video deinterlacing and viewfinder pre-processing
to memory
• CSI to encoder pre-processing to memory
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Introduction
• Memory to encoder pre-processing to memory
• Memory to encoder rotation to memory
• Memory to post-processing rotation to memory
• Memory to synchronous frame buffer background
• Memory to synchronous frame buffer foreground
• Memory to synchronous frame buffer mask
The IPU API has some additional functions that are not common across all channels, and
are specific to an IPU sub-module. The types of functions for the IPU sub-modules are as
follows:
• Synchronous frame buffer functions
• Panel interface initialization
• Set foreground positions
• Set local/global alpha and color key
• Set gamma
• CSI functions
• Sensor interface initialization
• Set sensor clock
• Set capture size
The higher level drivers are responsible for memory allocation, chaining of channels, and
providing user-level API.
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Chapter 6 Image Processing Unit (IPU) Drivers
6.2 Hardware Operation
The detailed hardware operation of the IPU is described in the Applications Processor
Reference Manual. The following figure shows the IPU hardware modules.
Figure 6-1. IPUv3EX/IPUv3H IPU Module Overview
6.3 Software Operation
The IPU driver is a self-contained driver module in the Linux kernel.
It consists of a custom kernel-level API for the following blocks:
• Synchronous frame buffer driver
• Display Interface (DI)
• Display Processor (DP)
• Image DMA Controller (IDMAC)
• CMOS Sensor Interface (CSI)
• Image Converter (IC)
The following figure shows the interaction between the different graphics/video drivers
and the IPU.
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Figure 6-2. Graphics/Video Drivers Software Interaction for IPUv3
The IPU drivers are sub-divided as follows:
• Device drivers: include the frame buffer driver for the synchronous frame buffer, the
frame buffer driver for the displays, V4L2 capture drivers for IPU pre-processing, the
V4L2 output driver for IPU post-processing, and the IPU processing driver that
provides a system interface to the user space or V4L2 drivers. The frame buffer
device drivers are available in the <ltib_dir>/rpm/BUILD/linux/drivers/video/mxc
directory of the Linux kernel. The V4L2 device drivers are available in the
<ltib_dir>/rpm/BUILD/linux/drivers/media/video directory of the Linux kernel.
• The MXC display driver is a simple framework to manage interaction between the
IPU and display device drivers (such as LCD, LVDS, HDMI, and MIPI).
• Low-level library routines: connect to the IPU hardware registers. They take input
from the high-level device drivers and communicate with the IPU hardware. The
low-level libraries are available in the directory of the Linux kernel.
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6.3.1 Overview of IPU Frame Buffer Drivers
The frame buffer device provides an abstraction for the graphics hardware. It represents
the frame buffer video hardware, and allows the application software to access the
graphics hardware through a well-defined interface. Therefore, the software is not
required to know anything about the low-level hardware registers.
The driver is enabled by selecting the frame buffer option under the graphics parameters
in the kernel configuration. To supplement the frame buffer driver, the kernel builder
may also include support for fonts and a startup logo. This device depends on the virtual
terminal (VT) console to switch from serial to graphics mode. The device is accessed
through special device nodes, located in the /dev directory, as /dev/fb*. fb0 is generally
the primary frame buffer.
Besides the physical memory allocation and LCD panel configuration, the common
kernel video API is used for setting colors, palette registration, image blitting, and
memory mapping. The IPU reads the raw pixel data from the frame buffer memory and
sends it to the panel for display.
6.3.1.1 IPU Frame Buffer Hardware Operation
The frame buffer interacts with the IPU hardware driver module.
6.3.1.2 IPU Frame Buffer Software Operation
A frame buffer device is a memory device, such as /dev/mem, and it has features similar
to a memory device. Users can read it, write to it, seek to some location in it, and mmap()
it, which is the main function. The difference is that the memory that appears in the
special file is not the whole memory, but the frame buffer of some video hardware.
/dev/fb* also interacts with several IOCTLs, which allows users to query and set
information about the hardware. The color map is also handled through IOCTLs. For
more information on what IOCTLs exist and which data structures they use, see
<ltib_dir>/rpm/BUILD/linux/include/linux/fb.h. The following are some of the IOCTLs
functions:
• Requesting general information about the hardware, such as name, organization of
the screen memory (planes, packed pixels, and so on), and address and length of the
screen memory.
• Requesting and changing variable information about the hardware, such as visible
and virtual geometry, depth, color map format, timing. The driver suggests values to
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meet the hardware capabilities (the hardware returns EINVAL if that is not possible)
if this information is changed.
• Getting and setting parts of the color map. Communication is 16 bits-per-pixel
(values for red, green, blue, transparency) to support all existing hardware. The
driver does all the calculations required to apply the options to the hardware (round
to fewer bits, possibly discard transparency value).
The hardware abstraction makes the implementation of application programs easier and
more portable. The only thing that must be built into the application programs is the
screen organization (bitplanes or chunky pixels, and so on), because it works on the
frame buffer image data directly.
The MXC frame buffer driver ( ) interacts closely with the generic Linux frame buffer
driver (<ltib_dir>/rpm/BUILD/linux/drivers/video/fbmem.c).
6.3.1.3 Synchronous Frame Buffer Driver
The synchronous frame buffer screen driver implements a Linux standard frame buffer
driver API for synchronous LCD panels or those without memory. The synchronous
frame buffer screen driver is the top-level kernel video driver that interacts with kernel
and user level applications. This is enabled by selecting the Synchronous Panel Frame
buffer option under the graphics support device drivers in the kernel configuration. To
supplement the frame buffer driver, the kernel builder may also include support for fonts
and a startup logo. This depends on the VT console for switching from serial to graphics
mode.
Except for physical memory allocation and LCD panel configuration, the common kernel
video API is used for color setting, palette registration, image blitting and memory
mapping. The IPU reads the raw pixel data from the frame buffer memory and sends it to
the panel for display.
The frame buffer driver supports different panels as a kernel configuration option.
Support for new panels can be added by defining new values for a structure of panel
settings.
The frame buffer interacts with the IPU driver by using custom APIs that allow:
• Initialization of panel interface settings
• Initialization of IPU channel settings for LCD refresh
• Changing the frame buffer address for double buffering support
The following features are supported:
• Configurable screen resolution
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• Configurable RGB 16, 24 or 32 bits per pixel frame buffer
• Configurable panel interface signal timings and polarities
• Palette/color conversion management
• Power management
• LCD power off/on
User applications use the generic video API (the standard Linux frame buffer driver API)
to perform functions with the frame buffer. These include the following:
• Obtaining screen information, such as the resolution or scan length
• Allocating user space memory by using mmap for performing direct blitting
operations
A second frame buffer driver supports a second video/graphics plane.
6.3.2 IPU Backlight Driver
The IPU backlight driver implements IPU PWM backlight control for panels. It exports a
system control file under /sys/class/backlight/pwm-backlight.0/brightness to user space.
The default backlight intensity value is 128.
6.3.3 IPU Device Driver
IPU (processing) device driver provide image processing features, including resizing,
rotation, CSC, combination, and deinterlacing based on IC/IRT modules in IPUv3.
The IPU device driver is task based. Users only need to prepare for task setting, queue
task, and then the block waits for the task to finish. The driver now supports the blocking
method only, and the non-block method will be added in the future. The task structures
are as follows:
struct ipu_task {
struct ipu_input input;
struct ipu_output output;
bool overlay_en;
struct ipu_overlay overlay;
#define IPU_TASK_PRIORITY_NORMAL 0
#define IPU_TASK_PRIORITY_HIGH 1
u8 priority;
#define IPU_TASK_ID_ANY 0
#define IPU_TASK_ID_VF 1
#define IPU_TASK_ID_PP 2
#define IPU_TASK_ID_MAX 3
u8 task_id;
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int timeout;
};
struct ipu_input {
u32 width;
u32 height;
u32 format;
struct ipu_crop crop;
dma_addr_t paddr;
struct ipu_deinterlace deinterlace;
dma_addr_t paddr_n; /*valid when deinterlace enable*/
};
struct ipu_overlay {
u32 width;
u32 height;
u32 format;
struct ipu_crop crop;
struct ipu_alpha alpha;
struct ipu_colorkey colorkey;
dma_addr_t
paddr;
};
struct ipu_output
{
u32 width;
u32 height;
u32 format;
u8 rotate;
struct ipu_crop crop;
dma_addr_t paddr;
};
To prepare for the task, users only need to enter the task.input, task.overlay(if need
combine) and task.output parameters, and then queue task either by int
ipu_queue_task(struct ipu_task *task); if from kernel level(v4l2 driver for example), or by
IPU_QUEUE_TASK ioctl under /dev/mxc_ipu if from application level.
6.4 Source Code Structure
Table 6-1 lists the source files associated with the IPU, Sensor, V4L2, and Panel drivers.
These files are available in the following directories:
<ltib_dir>/rpm/BUILD/linux/drivers/mxc/ipu3
<ltib_dir>/rpm/BUILD/linux/drivers/video/mxc
<ltib_dir>/rpm/BUILD/linux/drivers/media/video/mxc
<ltib_dir>/rpm/BUILD/linux/drivers/video/backlight
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Table 6-1. IPU Driver Files
File Description
ipu_common.c IPU common library functions
ipu_ic.c IPU IC base driver
ipu_device.c IPU driver device interface and fops functions
ipu_capture.c IPU CSI capture base driver
ipu_disp.c IPU display functions
ipu_calc_stripes_sizes.c Multi-stripes method functions for ipu_device.c
mxc_ipuv3_fb.c Driver for synchronous frame buffer
mxc_lcdif.c Display Driver for CLAA-WVGA and SEIKO-WVGA LCD support
mxc_hdmi.c Display Driver for HDMI interface
ldb.c Driver for synchronous frame buffer for on chip LVDS
mxc_dispdrv.c Display Driver framework for synchronous frame buffer
mxc_dvi.c Display Driver for DVI interface
mxc_edid.c Driver for EDID
vdoa.c VDOA post-processing driver, used by ipu_device.c
Table 6-2 lists the global header files associated with the IPU and Panel drivers. These
files are available in the following directories:
<ltib_dir>/rpm/BUILD/linux/drivers/mxc/ipu3/
<ltib_dir>/rpm/BUILD/linux/include/linux/
<ltib_dir>/rpm/BUILD/linux/drivers/media/video/mxc/
Table 6-2. IPU Global Header Files
File Description
ipu_param_mem.h Helper functions for IPU parameter memory access
ipu_prv.h Header file for Pre-processing drivers
ipu_regs.h IPU register definitions
vdoa.h Header file for VDOA drivers
mxc_dispdrv.h Header file for display driver
mxcfb.h Header file for the synchronous framebuffer driver
ipu.h Header file for ipu basic driver
6.4.1 Menu Configuration Options
The following Linux kernel configuration options are provided for the IPU module.
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To get to these options, use the command ./ltib -c when located in the <ltib dir>. On the
displayed screen, select Configure the kernel and exit. When the next screen appears,
select the options to configure.
• CONFIG_MXC_IPU: includes support for the Image Processing Unit. In menu
configuration, this option is available under:
Device Drivers > MXC support drivers > Image Processing Unit Driver
By default, this option is Y for all architectures.
If ARCH_MX37 or ARCH_MX5 is true, CONFIG_MXC_IPU_V3 will be set.
Otherwise, CONFIG_MXC_IPU_V1 will be set.
• CONFIG_MXC_CAMERA_OV5640_MIPI: option for both the OV 5640 mipi
sensor driver and the use case driver. This option is dependent on the MXC_IPU
option. In menu configuration, this option is available under:
Device Drivers > Multimedia devices > Video capture adapters > MXC Video For
Linux Camera > MXC Camera/V4L2 PRP Features support > OV 5640 Camera
support using mipi
Only one sensor should be installed at a time.
• CONFIG_MXC_CAMERA_OV5642: option for both the OV5642 sensor driver and
the use case driver. This option is dependent on the MXC_IPU option. In menu
configuration, this option is available under:
Device Drivers > Multimedia devices > Video capture adapters > MXC Video For
Linux Camera > MXC Camera/V4L2 PRP Features support > OmniVision ov5642
camera support
Only one sensor should be installed at a time.
• CONFIG_MXC_CAMERA_OV5642: option for both the OV5642 sensor driver and
the use case driver. This option is dependent on the MXC_IPU option. In menu
configuration, this option is available under:
Device Drivers > Multimedia devices > Video capture adapters > MXC Video For
Linux Camera > MXC Camera/V4L2 PRP Features support > OmniVision ov3640
camera support
Only one sensor should be installed at a time.
• CONFIG_MXC_IPU_PRP_VF_SDC: option for the IPU (here the > symbols
illustrates data flow direction between HW blocks):
CSI > IC > MEM MEM > IC (PRP VF) > MEM
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Use case driver for dumb sensor or
CSI > IC(PRP VF) > MEM
for smart sensors. In menu configuration, this option is available under:
Multimedia devices > Video capture adapters > MXC Video For Linux Camera >
MXC Camera/V4L2 PRP Features support > Pre-Processor VF SDC library
By default, this option is M for all.
• CONFIG_MXC_IPU_PRP_ENC: option for the IPU:
Use case driver for dumb sensors
CSI > IC > MEM MEM > IC (PRP ENC) > MEM
or for smart sensors
CSI > IC(PRP ENC) > MEM.
In menu configuration, this option is available under:
Device Drivers > Multimedia Devices > Video capture adapters > MXC Video For
Linux Camera > MXC Camera/V4L2 PRP Features support > Pre-processor Encoder
library
By default, this option is set to M for all.
• CONFIG_VIDEO_MXC_CAMERA: option for V4L2 capture Driver. This option is
dependent on the following expression:
VIDEO_DEV && MXC_IPU && MXC_IPU_PRP_VF_SDC &&
MXC_IPU_PRP_ENC
In menu configuration, this option is available under:
Device Drivers > Multimedia devices > Video capture adapters > MXC Video For
Linux Camera
By default, this option is M for all.
• CONFIG_VIDEO_MXC_OUTPUT: option for V4L2 output Driver. This option is
dependent on VIDEO_DEV && MXC_IPU option. In menu configuration, this
option is available under:
Device Drivers > Multimedia devices > Video capture adapters > MXC Video for
Linux Video Output
By default, this option is Y for all.
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• CONFIG_FB: includes frame buffer support in the Linux kernel. In menu
configuration, this option is available under:
Device Drivers > Graphics support > Support for frame buffer devices
By default, this option is Y for all architectures.
• CONFIG_FB_MXC: option for the MXC Frame buffer driver. This option is
dependent on the CONFIG_FB option. In menu configuration, this option is
available under:
Device Drivers > Graphics support > MXC Framebuffer support
By default, this option is Y for all architectures.
• CONFIG_FB_MXC_SYNC_PANEL: chooses the synchronous panel framebuffer.
This option is dependent on the CONFIG_FB_MXC option. In menu configuration,
this option is available under:
Device Drivers > Graphics support > MXC Framebuffer support > Synchronous
Panel Framebuffer
By default this option is Y for all architectures.
• CONFIG_FB_MXC_LDB: selects the LVDS module on iMX53 chip. This option is
dependent on CONFIG_FB_MXC_SYNC_PANEL and CONFIG_MXC_IPU_V3
option. In menu configuration, this option is available under:
Device Drivers > Graphics support > MXC Framebuffer support > Synchronous
Panel Framebuffer > MXC LDB
• CONFIG_FB_MXC_SII9022: selects the SII9022 HDMI chip. This option is
dependent on CONFIG_FB_MXC_SYNC_PANEL option. In menu configuration,
this option is available under:
Device Drivers > Graphics support > MXC Framebuffer support > Synchronous
Panel Framebuffer > Si Image SII9022 DVI/HDMI Interface Chip
6.5 Unit Test
NOTE
In order to execute the tests properly, make sure that you select
the util-linux package and load the following modules:
insmod ipu_prp_enc.ko
insmod ipu_bg_overlay_sdc.ko
insmod ipu_fg_overlay_sdc.ko
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insmod ipu_csi_enc.ko
insmod ov5642_camera.ko
insmod mxc_v4l2_capture.ko
6.5.1 Framebuffer Tests
There is a test application named mxc_fb_test.c under the <ltib_dir>/rpm/BUILD/imxtest-"version"/test/mxc_fb_test directory.
Execute the fb test as follows:
./mxc_fb_test.out
The result should be Exiting PASS. The test includes fb0(background) and
fb1(foreground) devices open, framebuffer parameters configure, global alpha blending,
fb pan display test and gamma test.
Redirect an image directly to the framebuffer device as follows:
# cat image.bin > /dev/fb0
6.5.2 Video4Linux API test
There are test applications named mxc_v4l2_test.c and mxc_v4l2_output.c under the
<ltib_dir>/rpm/BUILD/imx-test-"version"/test/mxc_v4l2_test directory.
Before running the v4l2 capture test application, make sure that the /dev/v4l/video0 is
created.
Test ID: FSL-UT-V4L2-capture-0010
# mxc_v4l2_capture.out -iw 640 -ih 480 -m 0 -r 0 -c 50 -fr 30 test.yuv
Capture the camera and store the 50 frames of YUV420 (VGA size)to a file called
test.yuv and set the frame rate to 30 fps. Look at mxc_v4l2_capture.out -help to see
usage.
Test ID: FSL-UT-V4L2-overlay-sdc-0010
# mxc_v4l2_overlay.out -iw 640 -ih 480 -it 0 -il 0 -ow 160 -oh 160 -ot 20 -ol 20 -r
0 -t 50 -d 0 -fg -fr 30
Direct preview the camera to SDC foreground, and set frame rate to 30 fps, window
of
interest is 640 X 480 with starting offset(0,0), the preview size is 160 X 160 with
starting offset (20,20). mxc_v4l2_overlay.out -help to see the usage.
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Test ID: FSL-UT-V4L2-overlay-sdc-0020
# mxc_v4l2_overlay.out -iw 640 -ih 480 -it 0 -il 0 -ow 160 -oh 160 -ot 20 -ol 20 -r
4 -t 50 -d 0 -fr 30
Direct preview(90 degree rotation) the camera to SDC background, and set frame rate
to 30 fps.
Test ID: FSL-UT-V4L2-overlay-adc-0010
# mxc_v4l2_overlay.out -iw 640 -ih 480 -it 0 -il 0 -ow 120 -oh 120 -ot 40 -ol 40 -r
0 -t 50 -d 1 -fg -fr 30
Direct preview the camera to foreground, and set frame rate to 30 fps.
Test ID: FSL-UT-V4L2-overlay-adc-0020
# mxc_v4l2_overlay.out -iw 640 -ih 480 -it 0 -il 0 -ow 120 -oh 120 -ot 40 -ol 40 -r
4 -t 50 -d 1 -fg -fr 30
Direct preview(90 degree rotation) the camera to foreground, and set frame rate to
30
fps.
Test ID: FSL-UT-V4L2-output-0010
# mxc_v4l2_output.out -iw 640 -ih 480 -ow 1024 -oh 768 -r 0 -fr 60 test.yuv
Read the YUV420 stream file on test.yuv created by the mxc_v4l2_capture test as run
in test FSL-UT-V4L2-capture-0010. Apply color space conversion and resize, then
display on the framebuffer.
NOTE
The PRP channels require the stride line to be a multiple of 8.
For example, with no rotation, the width needs to be 8 bit
aligned; with 90 degree rotation, the height needs to be 8 bit
aligned. Downsizing cannot exceed 8:1. For example, for a
VGA sensor, the smallest downsize will be 80x60.
6.5.3 IPU Device Unit test
There is a test application named mxc_ipudev_test.c under the <ltib_dir>/rpm/BUILD/
imx-test-"version"/test/mxc_ipudev_test directory.
Before running the ipu device test application, make sure that the /dev/mxc_ipu is
created.
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Run the test as follows:
./mxc_ipudev_test.out -C config_file raw_data_file
./mxc_ipudev_test.out -command_line_options raw_data_file
For file configuration instructions, refer to <ltib_dir>/rpm/BUILD/imx-test-"version"/
test/ipudev_config_file.
Below is a simple test source code of IPU device overlay which useS alpha (global/local)
blending to combine two layers:
static unsigned int fmt_to_bpp(unsigned int pixelformat)
{
unsigned int bpp;
switch (pixelformat) {
case IPU_PIX_FMT_RGB565:
/*interleaved 422*/
case IPU_PIX_FMT_YUYV:
case IPU_PIX_FMT_UYVY:
/*non-interleaved 422*/
case IPU_PIX_FMT_YUV422P:
case IPU_PIX_FMT_YVU422P:
bpp = 16;
break;
case IPU_PIX_FMT_BGR24:
case IPU_PIX_FMT_RGB24:
case IPU_PIX_FMT_YUV444:
bpp = 24;
break;
case IPU_PIX_FMT_BGR32:
case IPU_PIX_FMT_BGRA32:
case IPU_PIX_FMT_RGB32:
case IPU_PIX_FMT_RGBA32:
case IPU_PIX_FMT_ABGR32:
bpp = 32;
break;
/*non-interleaved 420*/
case IPU_PIX_FMT_YUV420P:
case IPU_PIX_FMT_YVU420P:
case IPU_PIX_FMT_YUV420P2:
case IPU_PIX_FMT_NV12:
bpp = 12;
break;
default:
bpp = 8;
break;
}
return bpp;
}
static void dump_ipu_task(struct ipu_task *t)
{
printf("====== ipu task ======\n");
printf("input:\n");
printf("\twidth: %d\n", t->input.width);
printf("\theight: %d\n", t->input.height);
printf("\tcrop.w = %d\n", t->input.crop.w);
printf("\tcrop.h = %d\n", t->input.crop.h);
printf("\tcrop.pos.x = %d\n", t->input.crop.pos.x);
printf("\tcrop.pos.y = %d\n", t->input.crop.pos.y);
printf("output:\n");
printf("\twidth: %d\n", t->output.width);
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printf("\theight: %d\n", t->output.height);
printf("\tcrop.w = %d\n", t->output.crop.w);
printf("\tcrop.h = %d\n", t->output.crop.h);
printf("\tcrop.pos.x = %d\n", t->output.crop.pos.x);
printf("\tcrop.pos.y = %d\n", t->output.crop.pos.y);
if (t->overlay_en) {
printf("overlay:\n");
printf("\twidth: %d\n", t->overlay.width);
printf("\theight: %d\n", t->overlay.height);
printf("\tcrop.w = %d\n", t->overlay.crop.w);
printf("\tcrop.h = %d\n", t->overlay.crop.h);
printf("\tcrop.pos.x = %d\n", t->overlay.crop.pos.x);
printf("\tcrop.pos.y = %d\n", t->overlay.crop.pos.y);
}
}
int main(int argc, char *argv[])
{
int fd, fd_fb, isize, ovsize, alpsize, cnt = 50;
int blank, ret;
FILE * file_in = NULL;
struct ipu_task task;
struct fb_var_screeninfo fb_var;
struct fb_fix_screeninfo fb_fix;
void *inbuf, *ovbuf, *alpbuf, *vdibuf;
fd = open("/dev/mxc_ipu", O_RDWR, 0);
fd_fb = open("/dev/fb1", O_RDWR, 0);
file_in = fopen(argv[argc-1], "rb");
memset(&task, 0, sizeof(task));
/* input setting */
task.input.width = 320;
task.input.height = 240;
task.input.crop.pos.x = 0;
task.input.crop.pos.y = 0;
task.input.crop.w = 0;
task.input.crop.h = 0;
task.input.format = IPU_PIX_FMT_YUV420P;
isize = task.input.paddr =
task.input.width * task.input.height
* fmt_to_bpp(task.input.format)/8;
ioctl(fd, IPU_ALLOC, &task.input.paddr);
inbuf = mmap(0, isize, PROT_READ | PROT_WRITE,
MAP_SHARED, fd, task.input.paddr);
/*overlay setting */
task.overlay_en = 1;
task.overlay.width = 1024;
task.overlay.height = 768;
task.overlay.crop.pos.x = 0;
task.overlay.crop.pos.y = 0;
task.overlay.crop.w = 0;
task.overlay.crop.h = 0;
task.overlay.format = IPU_PIX_FMT_RGB24;
#ifdef GLOBAL_ALP
task.overlay.alpha.mode = IPU_ALPHA_MODE_GLOBAL;
task.overlay.alpha.gvalue = 255;
task.overlay.colorkey.enable = 1;
task.overlay.colorkey.value = 0x555555;
#else
task.overlay.alpha.mode = IPU_ALPHA_MODE_LOCAL;
alpsize = task.overlay.alpha.loc_alp_paddr =
task.overlay.width * task.overlay.height;
ioctl(fd, IPU_ALLOC, &task.overlay.alpha.loc_alp_paddr);
alpbuf = mmap(0, alpsize, PROT_READ | PROT_WRITE,
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MAP_SHARED, fd, task.overlay.alpha.loc_alp_paddr);
memset(alpbuf, 0x00, alpsize/4);
memset(alpbuf+alpsize/4, 0x55, alpsize/4);
memset(alpbuf+alpsize/2, 0x80, alpsize/4);
memset(alpbuf+alpsize*3/4, 0xff, alpsize/4);
#endif
ovsize = task.overlay.paddr =
task.overlay.width * task.overlay.height
* fmt_to_bpp(task.overlay.format)/8;
ioctl(fd, IPU_ALLOC, &task.overlay.paddr);
ovbuf = mmap(0, ovsize, PROT_READ | PROT_WRITE,
MAP_SHARED, fd, task.overlay.paddr);
#ifdef GLOBAL_ALP
memset(ovbuf, 0x55, ovsize/4);
memset(ovbuf+ovsize/4, 0xff, ovsize/4);
memset(ovbuf+ovsize/2, 0x55, ovsize/4);
memset(ovbuf+ovsize*3/4, 0x00, ovsize/4);
#else
memset(ovbuf, 0x55, ovsize);
#endif
#endif
/* output setting*/
task.output.width = 1024;
task.output.height = 768;
task.output.crop.pos.x = 0;
task.output.crop.pos.y = 0;
task.output.crop.w = 0;
task.output.crop.h = 0;
task.output.format = IPU_PIX_FMT_RGB565;
task.output.rotate = IPU_ROTATE_NONE;
ioctl(fd_fb, FBIOGET_VSCREENINFO, &fb_var);
fb_var.xres = task.output.width;
fb_var.xres_virtual = fb_var.xres;
fb_var.yres = task.output.height;
fb_var.yres_virtual = fb_var.yres * 3;
fb_var.activate |= FB_ACTIVATE_FORCE;
fb_var.nonstd = task.output.format;
fb_var.bits_per_pixel = fmt_to_bpp(task.output.format);
ioctl(fd_fb, FBIOPUT_VSCREENINFO, &fb_var);
ioctl(fd_fb, FBIOGET_VSCREENINFO, &fb_var);
ioctl(fd_fb, FBIOGET_FSCREENINFO, &fb_fix);
task.output.paddr = fb_fix.smem_start;
blank = FB_BLANK_UNBLANK;
ioctl(fd_fb, FBIOBLANK, blank);
task.priority = IPU_TASK_PRIORITY_NORMAL;
task.task_id = IPU_TASK_ID_ANY;
task.timeout = 1000;
again:
ret = ioctl(fd, IPU_CHECK_TASK, &task);
if (ret != IPU_CHECK_OK) {
if (ret > IPU_CHECK_ERR_MIN) {
if (ret == IPU_CHECK_ERR_SPLIT_INPUTW_OVER) {
task.input.crop.w -= 8;
goto again;
}
if (ret == IPU_CHECK_ERR_SPLIT_INPUTH_OVER) {
task.input.crop.h -= 8;
goto again;
}
if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTW_OVER) {
task.output.crop.w -= 8;
goto again;
}
if (ret == IPU_CHECK_ERR_SPLIT_OUTPUTH_OVER) {
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Unit Test
task.output.crop.h -= 8;
goto again;
}
ret = -1;
return ret;
}
}
dump_ipu_task(&task);
while (--cnt > 0) {
fread(inbuf, 1, isize, file_in);
ioctl(fd, IPU_QUEUE_TASK, &task);
}
munmap(ovbuf, ovsize);
ioctl(fd, IPU_FREE, task.input.paddr);
ioctl(fd, IPU_FREE, task.overlay.paddr);
close(fd);
close(fd_fb);
fclose(file_in);
}
NOTE
The overlay width and height must be the same as those of the
output. For example, if the input is 240x320, and the output is
1024x768 which uses rotation of 90 degree, the overlay must be
the same as the output, that is, 1024x768.
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Chapter 7
MIPI DSI Driver
7.1 Introduction
The MIPI DSI driver for Linux is based on the IPU framebuffer driver.
This driver has two parts:
• MIPI DSI IP driver: low-level interface used to communicate with MIPI device
controller on the display panel.
• MIPI DSI display panel driver: provides an interface to configure the display panel
through MIPI DSI.
7.1.1 Overview of MIPI DSI IP Driver
The MIPI DSI IP driver is registered through the IPU framebuffer driver interface and it
is not exposed to the user space.
The driver enables the platform-related regulators and clocks. It requests OS related
system resources and registers framebuffer event notifier for blank/unblank operation.
Additionally, the driver initializes MIPI D-PHY and configures the MIPI DSI IP
according to the MIPI DSI display panel. The MIPI DSI driver supports the following
features:
• Compatibility with MIPI Alliance Specification for DSI, Version1.01.00.
• Compatibility with MIPI Alliance Specification for D-PHY, Version 1.00.00.
• Supports up to two D-PHY data lanes.
• Bidirectional Communication and Escape Mode Support through Data Lane 0.
• Programmable display resolutions, from 160x120 (QQVGA) to 1024x768 (XVGA).
• Video Mode Pixel Formats, 16bpp (565RGB),18bpp (666RGB) packed, 18bpp
(666RGB) loosely, 24bpp (888RGB).
• Supports the transmission of all generic commands.
• Supports ECC and checksum capabilities.
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Software Operation
• Supports End-of-Transmission Packet(EoTp).
• Supports ultra low power mode.
7.1.2 Overview of MIPI DSI Display Panel Driver
The MIPI DSI display panel driver is used to configure the MIPI DSI display panel.
It uses the APIs provided by the MIPI DSI IP driver to read/write the display module
registers. Usually, there is a MIPI DSI slave controller integrated on the display panel.
After being powered on and reset, the MIPI DSI display panel needs to be configured
through standard MIPI DCS command or MIPI DSI Generic command according to
manufacturer's specification.
7.1.3 Hardware Operation
The MIPI DSI module provides a high-speed serial interface between a host processor
and a display module.
It has higher performance, lower power, less EMI and fewer pins compared with legacy
parallel bus. It is designed to be compatible with the standard MIPI DSI protocol. MIPI
DSI is built on exisiting MIPI DPI-2, MIPI DBI-2 and MIPI DCS standards. It sends
pixels or commands to the peripheral and reads back status or pixel information from the
peripheral. MIPI DSI serializes all pixels data, commands and events, and contains two
basic modes: command mode and video mode. It uses command mode to read/write
register and memory to the display controller while reading display module status
information. On the other hand, it uses video mode to transmit a real-time pixel streams
from host to peripheral in high speed mode. It also generates an interrupt when an error
occurs.
7.2 Software Operation
The MIPI DSI driver for Linux has two parts: MIPI DSI IP driver and MIPI DSI display
panel driver.
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Chapter 7 MIPI DSI Driver
7.2.1 MIPI DSI IP Driver Software Operation
The MIPI DSI IP driver has a private structure called mipi_dsi_info. The IPU instance to
which the MIPI DSI IP is attached is described in the field int ipu_id while the DI
instance inside IPU is described in the field int disp_id
During startup, the MIPI DSI IP driver is registered with the IPU framebuffer driver
through the field struct mxc_dispdrv_entry when the driver is loaded. It also registers a
framebuffer event notifier with framebuffer core to perform the display panel blank/
unblank operation. The field struct fb_videomode *mode and struct mipi_lcd_config
*lcd_config are received from the display panel callback. The MIPI DSI IP needs this
infomation to configure the MIPI DSI hardware registers.
After initializing the MIPI DSI IP controller and the display module, the MIPI DSI IP
gets the pixel streams from IPU through DPI-2 interface and serializes pixel data and
video event through high speed data links for display. When there is an framebuffer
blank/unblank event, the registered notifier will be called to enter or leave low power
mode.
The MIPI DSI IP driver provides three APIs for MIPI DSI display panel driver to
configure the display module.
7.2.2 MIPI DSI Display Panel Driver Software Operation
The MIPI DSI Display Panel driver enables a particular display panel through the MIPI
DSI interface. The driver should provide struct fb_videomode configuration and struct
mipi_lcd_config data: some MIPI DSI parameters for the display panel such as maximum
D-PHY clock, numbers of data lanes and DPI-2 pixel format. Finally, the display driver
needs to set up display panel initialize routine by calling the APIs provided by MIPI DSI
IP drivers.
7.3 Driver Features
• MIPI DSI communication protocol
• MIPI DSI command mode and video mode
• MIPI DCS command operation
NOTE
The MIPI DSI driver does not support the DBI-2 mode, because
the DBI-2 and DPI-2 cannot be enabled at the same time on this
controller.
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Driver Features
7.3.1 Source Code Structure
<ltib_dir>/rpm/BUILD/linux/drivers/video/mxc.
Table 7-1. MIPI DSI Driver Files
File Description
mipi_dsi.c MIPI DSI IP driver source file
mipi_dsi.h MIPI DSI IP driver header file
mxcfb_hx8369_wvga.c MIPI DSI Display Panel driver source file
7.3.2 Menu Configuration Options
Device Drivers > Graphics support > MXC Framebuffer support > Synchronous Panel
Framebuffer > MXC MIPI_DSI
7.3.3 Programming Interface
The MIPI DSI Display Panel driver can use the API interface to read and write the
registers of the display panel device connected to MIPI DSI link.
For more information, see <ltib_dir>/rpm/BUILD/linux/driver/video/mxc/mipi_dsi.h.
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Chapter 8
Video for Linux Two (V4L2) Driver
8.1 Introduction
The Video for Linux Two (V4L2) drivers are plug-ins to the V4L2 framework that enable
support for camera and preprocessing functions, as well as video and post-processing
functions.
The V4L2 camera driver implements support for all camera related functions. The V4l2
capture device takes incoming video images, either from a camera or a stream, and
manipulates them. The output device takes video and manipulates it, and then sends it to
a display or similar device.
The features supported by the V4L2 driver are as follows:
• Direct preview and output to SDC foreground overlay plane (with synchronized to
LCD refresh)
• Direct preview to graphics frame buffer (without synchronized to LCD refresh)
• Color keying or alpha blending of frame buffer and overlay planes
• Streaming (queued) capture from IPU encoding channel
• Direct (raw Bayer) still capture (sensor dependent)
• Programmable pixel format, size, frame rate for preview and capture
• Programmable rotation and flipping using custom API
• RGB 16-bit, 24-bit, and 32-bit preview formats
• Raw Bayer (still only, sensor dependent), RGB 16, 24, and 32-bit, YUV 4:2:0 and
4:2:2 planar, YUV 4:2:2 interleaved, and JPEG formats for capture
• Control of sensor properties including exposure, white-balance, brightness, and
contrast
• Plug-in of different sensor drivers
• Link post-processing resize and CSC, rotation, and display IPU channels
• Streaming (queued) input buffer
• Double buffering of overlay and intermediate (rotation) buffers
• Configurable 3+ buffering of input buffers
• Programmable input and output pixel format and size
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V4L2 Capture Device
• Programmable scaling and frame rate
• RGB 16, 24, and 32-bit, YUV 4:2:0 and 4:2:2 planar, and YUV 4:2:2 interleaved
input formats
• TV output
The driver implements the standard V4L2 API for capture, output, and overlay devices.
The command modprobe mxc_v4l2_capture must be run before using these functions.
8.2 V4L2 Capture Device
• Capture interface-uses IPU pre-processing ENC channels to record the YCrCb video
stream
• Overlay interface-uses the IPU device driver to display the preview video to the SDC
foreground and background panel.
V4L2 capture support can be selected during kernel configuration. The driver includes
two layers. The top layer is the common Video for Linux driver, which contains chain
buffer management, stream API and other ioctl interfaces. The files for this device are
located in <ltib_dir>/rpm/BUILD/linux/drivers/media/video/mxc/capture/.
The V4L2 capture device driver is in the mxc_v4l2_capture.c file. The low level overlay
driver is in the ipu_fg_overlay_sdc.c, ipu_bg_overlay_sdc.c
This code (ipu_prp_enc.c) interfaces with the IPU ENC hardware, and ipu_still.c
interfaces with the IPU CSI hardware. Sensor frame rate control is handled by
VIDIOC_S_PARM ioctl. Before the frame rate is set, the sensor turns on the AE and
AWB turn on. The frame rate may change depending on light sensor samples.
Drivers for specific cameras can be found in <ltib_dir>/rpm/BUILD/linux/drivers/media/
video/mxc/capture/
8.2.1 V4L2 Capture IOCTLs
Currently, the memory map stream API is supported. Supported V4L2 IOCTLs include
the following:
• VIDIOC_QUERYCAP
• VIDIOC_G_FMT
• VIDIOC_S_FMT
• VIDIOC_REQBUFS
• VIDIOC_QUERYBUF
• VIDIOC_QBUF
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• VIDIOC_DQBUF
• VIDIOC_STREAMON
• VIDIOC_STREAMOFF
• VIDIOC_OVERLAY
• VIDIOC_G_FBUF
• VIDIOC_S_FBUF
• VIDIOC_G_CTRL
• VIDIOC_S_CTRL
• VIDIOC_CROPCAP
• VIDIOC_G_CROP
• VIDIOC_S_CROP
• VIDIOC_S_PARM
• VIDIOC_G_PARM
• VIDIOC_ENUMSTD
• VIDIOC_G_STD
• VIDIOC_S_STD
• VIDIOC_ENUMOUTPUT
• VIDIOC_G_OUTPUT
• VIDIOC_S_OUTPUT
Chapter 8 Video for Linux Two (V4L2) Driver
V4L2 control code has been extended to provide support for rotation. The ID is
V4L2_CID_PRIVATE_BASE. Supported values include:
• 0-Normal operation
• 1-Vertical flip
• 2-Horizontal flip
• 3-180° rotation
• 4-90° rotation clockwise
• 5-90° rotation clockwise and vertical flip
• 6-90° rotation clockwise and horizontal flip
• 7-90° rotation counter-clockwise
The following figure shows a block diagram of V4L2 Capture API interaction.
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V4L2 Capture Device
Figure 8-1. Video4Linux2 Capture API Interaction
8.2.2 Using the V4L2 Capture APIs
This section describes a sample V4L2 capture process. The application completes the
following steps:
1. Sets the capture pixel format and size by IOCTL VIDIOC_S_FMT.
2. Sets the control information by IOCTL VIDIOC_S_CTRL for rotation usage.
3. Requests a buffer by using IOCTL VIDIOC_REQBUFS. The common V4L2 driver
creates a chain of buffers (currently the maximum number of frames is 3).
4. Memory maps the buffer to its user space.
5. Queues buffers using the IOCTL command VIDIOC_QBUF.
6. Starts the stream by using the IOCTL VIDIOC_STREAMON. This IOCTL enables
the IPU tasks and the IDMA channels. When the processing is completed for a
frame, the driver switches to the buffer that is queued for the next frame. The driver
also signals the semaphore to indicate that a buffer is ready.
7. Takes the buffer from the queue by using the IOCTL VIDIOC_DQBUF. This
IOCTL blocks until it has been signaled by the ISR driver.
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Chapter 8 Video for Linux Two (V4L2) Driver
8. Stores the buffer to a YCrCb file.
9. Replaces the buffer in the queue of the V4L2 driver by executing VIDIOC_QBUF
again.
For the V4L2 still image capture process, the application completes the following steps:
1. Sets the capture pixel format and size by executing the IOCTL VIDIOC_S_FMT.
2. Reads one frame still image with YUV422.
For the V4L2 overlay support use case, the application completes the following steps:
1. Sets the overlay window by IOCTL VIDIOC_S_FMT.
2. Turns on overlay task by IOCTL VIDIOC_OVERLAY.
3. Turns off overlay task by IOCTL VIDIOC_OVERLAY.
8.3 V4L2 Output Device
The V4L2 output driver uses the IPU post-processing functions for video output.
The driver implements the standard V4L2 API for output devices. V4L2 output device
support can be selected during kernel configuration. The driver is available at <ltib_dir>/
rpm/BUILD/linux/drivers/media/video/mxc/output/mxc_vout.c.
8.3.1 V4L2 Output IOCTLs
Currently, the memory map stream API is supported. Supported V4L2 IOCTLs include
the following:
• VIDIOC_QUERYCAP
• VIDIOC_REQBUFS
• VIDIOC_G_FMT
• VIDIOC_S_FMT
• VIDIOC_QUERYBUF
• VIDIOC_QBUF
• VIDIOC_DQBUF
• VIDIOC_STREAMON
• VIDIOC_STREAMOFF
• VIDIOC_G_CTRL
• VIDIOC_S_CTRL
• VIDIOC_CROPCAP
• VIDIOC_G_CROP
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Source Code Structure
• VIDIOC_S_CROP
• VIDIOC_ENUM_FMT
The V4L2 control code has been extended to provide support for de-interlace motion. For
this purpose, the ID is V4L2_CID_MXC_MOTION. Supported values include the
following:
• 0-Medium motion
• 1-Low motion
• 2-High motion
8.3.2 Using the V4L2 Output APIs
This section describes a sample V4L2 output process that uses the V4L2 output APIs.
The application completes the following steps:
1. Sets the input pixel format and size by using IOCTL VIDIOC_S_FMT.
2. Sets the control information by using IOCTL VIDIOC_S_CTRL, for rotation and deinterlace motion (if need).
3. Sets the output information by using IOCTL VIDIOC_S_CROP.
4. Requests a buffer by using IOCTL VIDIOC_REQBUFS. The common V4L2 driver
creates a chain of buffers (not allocated yet).
5. Memory maps the buffer to its user space.
6. Executes IOCTL VIDIOC_QUERYBUF to query buffers.
7. Passes the data that requires post-processing to the buffer.
8. Queues the buffer by using the IOCTL command VIDIOC_QBUF.
9. Executes the IOCTL VIDIOC_DQBUF to dequeue buffers.
10. Starts the stream by executing IOCTL VIDIOC_STREAMON.
11. Stops the stream by excuting IOCTL VIDIOC_STREAMOFF.
8.4 Source Code Structure
The following table lists the source and header files associated with the V4L2 drivers.
These files are available in the following directory:
<ltib_dir>/rpm/BUILD/linux/drivers/media/video/mxc
Table 8-1. V2L2 Driver Files
File Description
capture/mxc_v4l2_capture.c V4L2 capture device driver
Table continues on the next page...
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Chapter 8 Video for Linux Two (V4L2) Driver
Table 8-1. V2L2 Driver Files (continued)
File Description
output/mxc_vout.c V4L2 output device driver
capture/mxc_v4l2_capture.h Header file for V4L2 capture device driver
capture/ipu_prp_enc.c Pre-processing encoder driver
capture/ipu_prp_vf_adc.c Pre-processing view finder (asynchronous) driver
capture/ipu_prp_vf_sdc.c Pre-processing view finder (synchronous foreground) driver
capture/ipu_prp_vf_sdc_bg.c Pre-processing view finder (synchronous background) driver
capture/ipu_fg_overlay_sdc.c synchronous forground driver
capture/ipu_bg_overlay_sdc.c synchronous background driver
capture/ipu_still.c Pre-processing still image capture driver
Drivers for specific cameras can be found in <ltib_dir>/rpm/BUILD/linux/drivers/media/
video/mxc/capture/
Drivers for specific output can be found in <ltib_dir>/rpm/BUILD/linux/drivers/media/
video/mxc/output/
8.4.1 Menu Configuration Options
The Linux kernel configuration options are provided in the chapter on the IPU module.
8.4.2 V4L2 Programming Interface
For more information, see the V4L2 Specification and the API Documents for the
programming interface.
The API Specification is available at LINUX MEDIA INFRASTRUCTURE API.
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Chapter 9
Electrophoretic Display Controller (EPDC) Frame
Buffer Driver
9.1 Introduction
The Electrophoretic Display Controller (EPDC) is a direct-drive active matrix EPD
controller designed to drive E Ink EPD panels supporting a wide variety of TFT
backplanes. The EPDC framebuffer driver acts as a standard Linux frame buffer device
while also supporting a set of custom API extensions, accessible from user space (via
IOCTL) or another kernel module (via direct function call) in order to provide the user
with access to EPD-specific functionality. The EPDC driver is abstracted from any
specific E Ink panel type, providing flexibility to work with a range of E Ink panel types
and specifications.
The EPDC driver supports the following features:
• Support for EPDC driver as a loadable or built-in module.
• Support for RGB565 and Y8 frame buffer formats.
• Support for full and partial EPD screen updates.
• Support for up to 256 panel-specific waveform modes.
• Support for automatic optimal waveform selection for a given update.
• Support for synchronization by waiting for a specific update request to complete.
• Support for screen updates from an alternate (overlay) buffer.
• Support for automated collision handling.
• Support for 64 simultaneous update regions.
• Support for pixel inversion in a Y8 frame buffer format.
• Support for 90, 180, and 270 degree HW-accelerated frame buffer rotation.
• Support for panning (y-direction only).
• Support for automated full and partial screen updates through the Linux
fb_deferred_io mechanism.
• Support for three EPDC driver display update schemes: Snapshot, Queue, and Queue
and Merge.
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• Support for setting the ambient temperature through either a one-time designated API
call or on a per-update basis.
• Support for user control of the delay between completing all updates and powering
down the EPDC.
9.2 Hardware Operation
The detailed hardware operation of the EPDC is discussed in the i.MX 6DualLite
Applications Processor Reference Manual.
9.3 Software Operation
The EPDC frame buffer driver is a self-contained driver module in the Linux kernel. It
consists of a standard frame buffer device API coupled with a custom EPD-specific API
extension, accessible through the IOCTL interface. This combined functionality provides
the user with a robust and familiar display interface while offering full control over the
contents and update mode of the E Ink display.
This section covers the software operation of the EPDC driver, both through the standard
frame buffer device architecture, and through the custom E Ink API extensions.
Additionally, panel intialization and framebuffer formats are discussed.
9.3.1 EPDC Frame Buffer Driver Overview
The frame buffer device provides an abstraction for the graphics hardware. It represents
the frame buffer video hardware and allows application software to access the graphics
hardware through a well-defined interface, so that the software is not required to know
anything about the low-level hardware registers. The EPDC driver supports this model
with one key caveat: the contents of the frame buffer are not automatically updated to the
E Ink display. Instead, a custom API function call is required to trigger an update to the E
Ink display. The details of this process are explained in the EPDC Frame Buffer Driver
Extensions.
The frame buffer driver is enabled by selecting the frame buffer option under the graphics
parameters in the kernel configuration. To supplement the frame buffer driver, the kernel
builder may also include support for fonts and a startup logo. The frame buffer device
depends on the virtual terminal (VT) console to switch from serial to graphics mode. The
device is accessed through special device nodes, located in the /dev directory, as /dev/fb*.
fb0 is generally the primary frame buffer.
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Chapter 9 Electrophoretic Display Controller (EPDC) Frame Buffer Driver
A frame buffer device is a memory device, such as /dev/mem, and it has features similar
to a memory device. Users can read it, write to it, seek to some location in it, and mmap()
it (the main use). The difference is that the memory that appears in the special file is not
the whole memory, but the frame buffer of some video hardware.
The EPDC frame buffer driver ( drivers/video/mxc/mxc_epdc_fb.c) interacts closely with
the generic Linux frame buffer driver (drivers/video/fbmem.c).
For additional details on the frame buffer device, please refer to documentation in the
Linux kernel found in Documentation/fb/framebuffer.txt.
9.3.2 EPDC Frame Buffer Driver Extensions
E Ink display technology, in conjunction with the EPDC, has several features that
distinguish it from standard LCD-based frame buffer devices. These differences
introduce the need for API extensions to the frame buffer interface. The EPDC refreshes
the E Ink display asynchronously and supports partial screen updates. Therefore, the
EPDC requires notification from the user when the frame buffer contents have been
modified and which region needs updating. Another unique characteristic of EPDC
updates to the E Ink display is the long screen update latencies (between 300-980ms),
which introduces the need for a mechanism to allow the user to wait for a given screen
update to complete.
The custom API extensions to the frame buffer device are accessible both from user
space applications and from within kernel space. The standard device IOCTL interface
provides access to the custom API for user space applications. The IOCTL extensions,
along with relevant data structures and definitions, can be found in include/linux/
mxcfb.h. A full description of these IOCTLs can be found in the Programming Interface
section Programming Interface.
For kernel mode access to the custom API extensions, the IOCTL interface should be
bypassed in favor of direct access to the underlying functions. These functions are
included in include/linux/mxcfb_epdc_kernel.h, and are documented in the Programming
Interface section Programming Interface.
9.3.3 EPDC Panel Configuration
The EPDC driver is designed to flexibly support E Ink panels with a variety of panel
resolutions, timing parameters, and waveform modes. The EPDC driver is kept panelagnostic through the use of an EPDC panel mode structure, mxc_epdc_fb_mode, which
can be found in arch/arm/plat-mxc/include/mach/epdc.h.
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Software Operation
struct mxc_epdc_fb_mode {
struct fb_videomode *vmode;
int vscan_holdoff;
int sdoed_width;
int sdoed_delay;
int sdoez_width;
int sdoez_delay;
int gdclk_hp_offs;
int gdsp_offs;
int gdoe_offs;
int gdclk_offs;
int num_ce;
};
The mxc_epdc_fb_mode structure consists of an fb_videomode structure and a set of
EPD timing parameters. The fb_videomode structure defines the panel resolution and the
basic timing parameters (pixel clock frequency, hsync and vsync margins) and the
additional timing parameters in mxc_epdc_fb_mode define EPD-specific timing
parameters, such as the source and gate driver timings. Please refer to the EPDC
programming model section within the iMX6SLDRM for details on how E Ink panel
timing parameters should be configured.
This EPDC panel mode is part of the mxc_epdc_fb_platform_data structure that is passed
to the EPDC driver during driver registration.
struct mxc_epdc_fb_platform_data {
struct mxc_epdc_fb_mode *epdc_mode;
int num_modes;
void (*get_pins) (void);
void (*put_pins) (void);
void (*enable_pins) (void);
void (*disable_pins) (void);
};
In addition to the EPDC panel mode data, functions may be passed to the EPDC driver to
define how to handle the EPDC pins when the EPDC driver is enabled or disabled. These
functions should disable the EPDC pins for purposes of power savings.
9.3.3.1 Boot Command Line Parameters
Additional configuration for the EPDC driver is provided through boot command line
parameters. The format of the command line option is as follows:
epdc video=mxcepdcfb:[panel_name],bpp=16
The EPDC driver parses these options and tries to match panel_name to the name of
video mode specified in the mxc_epdc_fb_mode panel mode structure. If no match is
found, then the first panel mode provided in the platform data is used by the EPDC
driver. The bpp setting from this command line sets the initial bits per pixel setting for
the frame buffer. A setting of 16 selects RGB565 pixel format, while a setting of 8 selects
8-bit grayscale (Y8) format.
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9.3.4 EPDC Waveform Loading
The EPDC driver requires a waveform file for proper operation. This waveform file
contains the waveform information needed to generate the waveforms that drive updates
to the E Ink panel. A pointer to the waveform file data is programmed into the EPDC
before the first update is performed.
There are two options for selecting a waveform file:
1. Select one of the default waveform files included in this BSP and built into the
kernel.
2. Use a new waveform file that is specific to the E Ink panel being used.
The waveform file is loaded by the EPDC driver using the Linux firmware APIs.
9.3.4.1 Using a Default Waveform File
The quickest and easiest way to get started using an E Ink panel and the EPDC driver is
to use one of the default waveform files provided in the Linux BSP. This should enable
updates to several different types of E Ink panel without a panel-specific waveform file.
The drawback is that optimal quality should not be expected. Typically, using a nonpanel-specific waveform file for an E Ink panel results in more ghosting artifacts and
overall poorer color quality.
The following default waveform files included in the BSP reside in firmware/imx/:
• epdc_E60_V110.fw - Default waveform for the 6.0 inch V110 E Ink panel.
• epdc_E60_V220.fw - Default waveform for the 6.0 inch V220 E Ink panel (supports
animation mode updates).
• epdc_E97_V110.fw - Default waveform for the 9.7 inch V110 E Ink panel.
• epdc_E060SCM.fw - Default waveform for the 6.0 inch Pearl E Ink panel (supports
animation mode updates).
The EPDC driver attempts to load a waveform file with the name "imx/
epdc_[panel_name].fw", where panel_name refers to the string specified in the
fb_videomode name field. This panel_name information should be provided to the EPDC
driver through the kernel command line parameters described in the preceding chapter.
For example, to load the epdc_E060SCM.fw default firmware file for a Pearl panel, set
the EPDC kernel command line paratmeter to the following:
video=mxcepdcfb:E060SCM,bpp=16
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9.3.4.2 Using a Custom Waveform File
To ensure the optimal E Ink display quality, use a waveform file specific to E Ink panel
being used. The raw waveform file type (.wbf) requires conversion to a format that can
be understood and read by the EPDC. This conversion script is not included as part of the
BSP, so please contact Freescale to acquire this conversion script.
Once the waveform conversion script has been run on the raw waveform file, the
converted waveform file should be renamed so that the EPDC driver can find it and load
it. The driver is going to search for a waveform file with the name "imx/
epdc_[panel_name].fw", where panel_name refers to the string specified in the
fb_videomode name field. For example, if the panel is named "E60_ABCD", then the
converted waveform file should be named epdc_E60_ABCD.fw.
The firmware script firmware.sh (lib/udev/firmware in the Linux root file system)
contains the search path used to locate the firmware file. The default search path for
firmware files is /lib/firmware;/usr/local/lib/firmware. A custom search path can be
specified by modifying firmware.sh. You’ll need to create an imx directory in one of
these paths and add your new epdc_[panel_name].fw file there.
NOTE
If the EPDC driver is searching for a firmware waveform file
that matches the names of one of the default waveform files
(see preceding chapter), it will choose the default firmware files
that are built into the BSP over any firmware file that has been
added in the firmware search path. Thus, if you leave the BSP
so that it builds those default firmware files into the OS image,
be sure to use a panel name other than those associated with the
default firmware files, since those default waveform files will
be preferred and selected over a new waveform file placed in
the firmware search path.
9.3.5 EPDC Panel Initialization
The framebuffer driver will not typically (see note below for exceptions) go through any
hardware initialization steps when the framebuffer driver module is loaded. Instead, a
subsequent user mode call must be made to request that the driver initialize itself for a
specific EPD panel. To initialize the EPDC hardware and E-ink panel, an
FBIOPUT_VSCREENINFO ioctl call must be made, with the xres and yres fields of the
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fb_var_screeninfo parameter set to match the X and Y resolution of a supported E-ink
panel type. To ensure that the EPDC driver receives the initialization request, the activate
field of the fb_var_screeninfo parameter should be set to FB_ACTIVATE_FORCE.
NOTE
The exception is when the FB Console driver is included in the
kernel. When the EPDC driver registers the framebuffer device,
the FB Console driver will subsequently make an
FBIOPUT_VSCREENINFO ioctl call. This will in turn
initialize the EPDC panel.
9.3.6 Grayscale Framebuffer Selection
The EPDC framebuffer driver supports the use of 8-bit grayscale (Y8) and 8-bit inverted
grayscale (Y8 inverted) pixel formats for the framebuffer (in addition to the more
common RGB565 pixel format). In order to configure the framebuffer format as 8-bit
grayscale, the application would call the FBIOPUT_VSCREENINFO framebuffer ioctl.
This ioctl takes an fb_var_screeninfo pointer as a parameter. This parameter specifies the
attributes of the framebuffer and allows the application to request changes to the
framebuffer format. There are two key members of the fb_var_screeninfo parameter that
must be set in order to request a change to 8-bit grayscale format: bits_per_pixel and
grayscale. bits_per_pixel must be set to 8 and grayscale must be set to one of the 2 valid
grayscale format values: GRAYSCALE_8BIT or GRAYSCALE_8BIT_INVERTED.
The following code snippet demonstrates a request to change the framebuffer to use the
Y8 pixel format:
fb_screen_info screen_info;
screen_info.bits_per_pixel = 8;
screen_info.grayscale = GRAYSCALE_8BIT;
retval = ioctl(fd_fb0, FBIOPUT_VSCREENINFO, &screen_info);
9.3.7 Enabling An EPDC Splash Screen
#define CONFIG_SPLASH_SCREEN
#define CONFIG_MXC_EPDC
Once this change has been made, rebuild the U-Boot image and flash it to your SD card.
Then perform the following steps to flash a waveform file to an SD card where U-Boot
can find it:
1. Identify the EPDC waveform file from the Linux kernel firmware directory that is
the best match for the panel you are using. For the DC2/DC3 boards, that would be
the waveform file /firmware/imx/epdc_E060SCM.fw.ihex.
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2. Convert the ihex firmware file to a stripped-down binary using the script
ihex2bin.py. Please contact Freescale to acquire this script.
python ihex2bin.py -I epdc_E060SCM.fw.ihex -o epdc_E060SCM_splash.bin
3. Write the firmware file to the SD card at an offset of 6MB where U-Boot will look
for it.
dd if=./epdc_E060SCM_splash.bin of=/dev/sdX bs=1024 seek=6144
9.4 Source Code Structure
Table below lists the source files associated with the EPDC driver. These files are
available in the following directory:
drivers/video/mxc
Table 9-1. EPDC Driver Files
File Description
mxc_epdc_fb.c The EPDC frame buffer driver.
epdc_regs.h Register definitions for the EPDC module.
Table below lists the global header files associated with the EPDC driver. These files are
available in the following directory:
include/linux/
Table 9-2. EPDC Global Header Files
File Description
mxcfb.h Header file for the MXC framebuffer drivers
mxcfb_epdc_kernel.h Header file for direct kernel access to the EPDC API extension
9.5 Menu Configuration Options
To get to the Linux kernel configuration options available for the EPDC module, use the
command ./ltib -c when located in the <ltib dir>. On the screen displayed, select
Configure the kernel and exit. When the next screen appears select the options to
configure. The following Linux kernel configuration options are provided for the EPDC
module:
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• CONFIG_MXC_EINK_PANEL includes support for the Electrophoretic Display
Controller. In menuconfig, this option is available under:
• Device Drivers > Graphics Support > E-Ink Panel Framebuffer
• CONFIG_MXC_EINK_AUTO_UPDATE_MODE enables support for auto-update
mode, which provides automated EPD updates through the deferred I/O framebuffer
driver. This option is dependent on the MXC_EINK_PANEL option. In menuconfig,
this option is available under:
• Device Drivers > Graphics Support > E-Ink Auto-update Mode Support
NOTE
This option only enables the use of auto-update mode.
Turning on auto-update mode requires an additional
IOCTL call using the
MXCFB_SET_AUTO_UPDATE_MODE IOCTL.
• CONFIG_FB to include frame buffer support in the Linux kernel. In menuconfig,
this option is available under:
• Device Drivers > Graphics support > Support for frame buffer devices
• By default, this option is Y for all architectures.
• CONFIG_FB_MXC is a configuration option for the MXC Frame buffer driver. This
option is dependent on the CONFIG_FB option. In menuconfig, this option is
available under:
• Device Drivers > Graphics support > MXC Framebuffer support
• By default, this option is Y for all architectures.
• CONFIG_MXC_PXP enables support for the PxP. The PxP is required by the EPDC
driver for processing (color space conversion, rotation, auto-waveform selection)
framebuffer update regions. This option must be selected for the EPDC framebuffer
driver to operate correctly. In menuconfig, this option is available under:
• Device Drivers > DMA Engine support > MXC PxP support
9.6 Programming Interface
9.6.1 IOCTLs/Functions
The EPDC Frame Buffer is accessible from user space and from kernel space. A single
set of functions describes the EPDC Frame Buffer driver extension. There are, however,
two modes for accessing these functions. For user space access the IOCTL interface
should be used. For kernel space access the functions should be called directly. For each
function below both the IOCTL code and the corresponding kernel function is listed.
MXCFB_SET_WAVEFORM_MODES / mxc_epdc_fb_set_waveform_modes()
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Description:
Defines a mapping for common waveform modes.
Parameters:
mxcfb_waveform_modes *modes
Pointer to a structure containing the waveform mode values for common waveform
modes. These values must be configured in order for automatic waveform mode selection
to function properly.
MXCFB_SET_TEMPERATURE / mxc_epdc_fb_set_temperature
Description:
Set the temperature to be used by the EPDC driver in subsequent panel updates.
Parameters:
int32_t temperature
Temperature value, in degrees Celsius. Note that this temperature setting may be
overridden by setting the temperature value parameter to anything other than
TEMP_USE_AMBIENT when using the MXCFB_SEND_UPDATE ioctl.
MXCFB_SET_AUTO_UPDATE_MODE / mxc_epdc_fb_set_auto_update
Description:
Select between automatic and region update mode.
Parameters:
__u32 mode
In region update mode, updates must be submitted via the MXCFB_SEND_UPDATE
IOCTL.
In automatic mode, updates are generated automatically by the driver by detecting pages
in frame buffer memory region that have been modified.
MXCFB_SET_UPDATE_SCHEME / mxc_epdc_fb_set_upd_scheme
Description:
Select a scheme that dictates how the flow of updates within the driver.
Parameters:
__u32 scheme
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Select of the following updates schemes:
UPDATE_SCHEME_SNAPSHOT - In the Snapshot update scheme, the contents of the
framebuffer are immediately processed and stored in a driver-internal memory buffer. By
the time the call to MXCFB_SEND_UPDATE has completed, the framebuffer region is
free and can be modified without affecting the integrity of the last update. If the update
frame submission is delayed due to other pending updates, the original buffer contents
will be displayed when the update is finally submitted to the EPDC hardware. If the
update results in a collision, the original update contents will be resubmitted when the
collision has cleared.
UPDATE_SCHEME_QUEUE - The Queue update scheme uses a work queue to
aynchronously handle the processing and submission of all updates. When an update is
submitted via MXCFB_SEND_UPDATE, the update is added to the queue and then
processed in order as EPDC hardware resources become available. As a result, the
framebuffer contents processed and updated are not guaranteed to reflect what was
present in the framebuffer when the update was sent to the driver.
UPDATE_SCHEME_QUEUE_AND_MERGE - The Queue and Merge scheme uses the
queueing concept from the Queue scheme, but adds a merging step. This means that,
before an update is processed in the work queue, it is first compared with other pending
updates. If any update matches the mode and flags of the current update and also overlaps
the update region of the current update, then that update will be merged with the current
update. After attempting to merge all pending updates, the final merged update will be
processed and submitted.
MXCFB_SEND_UPDATE / mxc_epdc_fb_send_update
Description:
Request a region of the frame buffer be updated to the display.
Parameters:
mxcfb_update_data *upd_data
Pointer to a structure defining the region of the frame buffer, waveform mode, and
collision mode for the current update. This structure also includes a flags field to select
from one of the following update options:
EPDC_FLAG_ENABLE_INVERSION - Enables inversion of all pixels in the update
region.
EPDC_FLAG_FORCE_MONOCHROME - Enables full black/white posterization of all
pixels in the update region.
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EPDC_FLAG_USE_ALT_BUFFER - Enables updating from an alternate (nonframebuffer) memory buffer.
If enabled, the final upd_data parameter includes detailed configuration information for
the alternate memory buffer.
MXCFB_WAIT_FOR_UPDATE_COMPLETE /
mxc_epdc_fb_wait_update_complete
Description:
Block and wait for a previous update request to complete.
Parameters:
mxfb_update_marker_data marker_data
The update_marker value used to identify a particular update (passed as a parameter in
MXCFB_SEND_UPDATE IOCTL call) should be re-used here to wait for the update to
complete. If the update was a collision test update, the collision_test variable will return
the result indicating whether a collision occurred.
MXCFB_SET_PWRDOWN_DELAY / mxc_epdc_fb_set_pwrdown_delay
Description:
Set the delay between the completion of all updates in the driver and when the driver
should power down the EPDC and the E Ink display power supplies.
Parameters:
int32_t delay
Input delay value in milliseconds. To disable EPDC power down altogether, use
FB_POWERDOWN_DISABLE (defined below).
MXCFB_GET_PWRDOWN_DELAY / mxc_epdc_fb_get_pwrdown_delay
Description:
Retrieve the driver's current power down delay value.
Parameters:
int32_t delay
Output delay value in milliseconds.
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9.6.2 Structures and Defines
#define GRAYSCALE_8BIT 0x1
#define GRAYSCALE_8BIT_INVERTED 0x2
#define AUTO_UPDATE_MODE_REGION_MODE 0
#define AUTO_UPDATE_MODE_AUTOMATIC_MODE 1
#define UPDATE_SCHEME_SNAPSHOT 0
#define UPDATE_SCHEME_QUEUE 1
#define UPDATE_SCHEME_QUEUE_AND_MERGE 2
#define UPDATE_MODE_PARTIAL 0x0
#define UPDATE_MODE_FULL 0x1
#define WAVEFORM_MODE_AUTO 257
#define TEMP_USE_AMBIENT 0x1000
#define EPDC_FLAG_ENABLE_INVERSION 0x01
#define EPDC_FLAG_FORCE_MONOCHROME 0x02
#define EPDC_FLAG_USE_ALT_BUFFER 0x100
#define EPDC_FLAG_TEST_COLLISION 0x200
#define FB_POWERDOWN_DISABLE -1
struct mxcfb_rect {
__u32 left; /* Starting X coordinate for update region */
__u32 top; /* Starting Y coordinate for update region */
__u32 width; /* Width of update region */
__u32 height; /* Height of update region */
};
struct mxcfb_waveform_modes {
int mode_init; /* INIT waveform mode */
int mode_du; /* DU waveform mode */
int mode_gc4; /* GC4 waveform mode */
int mode_gc8; /* GC8 waveform mode */
int mode_gc16; /* GC16 waveform mode */
int mode_gc32; /* GC32 waveform mode */
};
struct mxcfb_alt_buffer_data {
__u32 phys_addr; /* physical address of alternate image buffer */
__u32 width; /* width of entire buffer */
__u32 height; /* height of entire buffer */
struct mxcfb_rect alt_update_region; /* region within buffer to update */
};
struct mxcfb_update_data {
struct mxcfb_rect update_region; /* Rectangular update region bounds */
__u32 waveform_mode; /* Waveform mode for update */
__u32 update_mode; /* Update mode selection (partial/full) */
__u32 update_marker; /* Marker used when waiting for completion */
int temp; /* Temperature in Celsius */
uint flags; /* Select options for the current update */
struct mxcfb_alt_buffer_data alt_buffer_data; /* Alternate buffer data */
};
struct mxcfb_update_marker_data { __u32 update_marker; __u32 collision_test; };
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Chapter 10
Pixel Pipeline (PxP) DMA-ENGINE Driver
10.1 Introduction
The Pixel Pipeline (PxP) DMA-ENGINE driver provides a unique API, which are
implemented as a dmaengine client that smooths over the details of different hardware
offload engine implementations. Typically, the users of PxP DMA-ENGINE driver
include EPDC driver, V4L2 Output driver, and the PxP user-space library.
10.2 Hardware Operation
The PxP driver uses PxP registers to interact with the hardware. For detailed hardware
operation, please refer to the i.MX 6Solo/6DualLite Multimedia Applications Processor
Reference Manual.
10.3 Software Operation
10.3.1 Key Data Structs
The PxP DMA Engine driver implementation depends on the DMA Engine Framework.
There are three important structs in the DMA Engine Framework which are extended by
the PxP driver: struct dma_device, struct dma_chan, struct dma_async_tx_descriptor. The
PxP driver implements several callback functions which are called by the DMA Engine
Framework (or DMA slave) when a DMA slave (client) interacts with the DMA Engine.
The PxP driver implements the following callback functions in struct dma_device:
device_alloc_chan_resources /* allocate resources and descriptors */
device_free_chan_resources /* release DMA channel's resources */
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device_tx_status /* poll for transaction completion */
device_issue_pending /* push pending transactions to hardware */
and,
device_prep_slave_sg /* prepares a slave dma operation */
device_terminate_all /* manipulate all pending operations on a channel, returns zero or
error code */
The first four functions are used by the DMA Engine Framework, the last two are used
by the DMA slave (DMA client). Notably, device_issue_pending is used to trigger the
start of a PxP operation.
The PxP DMA driver also implements the interface tx_submit in struct
dma_async_tx_descriptor, which is used to prepare the descriptor(s) which will be
executed by the engine. When tasks are received in pxp_tx_submit, they are not
configured and executed immediately. Rather, they are added to a task queue and the
function call is allowed to return immediately.
10.3.2 Channel Management
Although ePxP does not have multiple channels in hardware, 16 virtual channels are
supported in the driver; this provides flexibility in the multiple instance/client design. At
any time, a user can call dma_request_channel() to get a free channel, and then configure
this channel with several descriptors (a descriptor is required for each input plane and for
the output plane). When the PxP is no longer being used, the channel should be released
by calling dma_release_channel(). Detailed elements of channel management are
handled by the driver and are transparent to the client.
10.3.3 Descriptor Management
The DMA Engine processes the task based on the descriptor. One DMA channel is
usually associated with several descriptors. Descriptors are recycled resources, under
control of the offload engine driver, to be reused as operations complete. The extended
TX descriptor packet (pxp_tx_desc), allows the user to pass PxP configuration
information to the driver. This includes everything that the PxP needs to execute a
processing task.
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10.3.4 Completion Notification
There are two ways for an application to receive notification that a PxP operation has
completed.
• Call dma_wait_for_async_tx(). This call causes the CPU to spin while it polls for the
completion of the operation.
• Specify a completion callback.
The latter method is recommended. After the PxP operation completes, the PxP output
buffer data can be retrieved.
For general information for DMA Engine Framework, please refer to Documentation/
dmaengine.txt in the Linux kernel source tree.
10.3.5 Limitations
• The driver currently does not support scatterlist objects in the way they are
traditionally used. Instead of using the scatterlist parameter object to provide a chain
of memory sources and destinations, the driver currently uses it to provide the input
and output buffers (and overlay buffers, if needed) for one transfer.
• The PxP driver may not properly execute a series of transfers that is queued in rapid
sequence. It is recommended to wait for each transfer to complete before submitting
a new one.
10.4 Menu Configuration Options
The following Linux kernel configuration option is provided for this module:
Device Drivers --->
DMA Engine support --->
[*] MXC PxP support
[*] MXC PxP Client Device
10.5 Source Code Structure
The PxP driver source code is located in drivers/dma/ and include/linux/.
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