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HCS12
Reference Manual
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Freescale Semiconductor HCS12 Reference Manual

S12CPUV2
Reference Manual
HCS12 Microcontrollers
S12CPUV2 Rev. 4.0 03/2006
freescale.com
S12CPUV2
Reference Manual
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://www.freescale.com
The following revision history table summarizes changes contained in this document.

Revision History

Revision
Number
3.0 April, 2002 Incorporated information covering HCS12 Family of 16-bit MCUs throughout the book.
4.0 March, 2006 Reformatted to Freescale publication standards.
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved.
Date Summary of Changes
Corrected mistake in ANDCC/TAP descriptions (Instruction Glossary). Corrected mistake in MEM description (Instruction Glossary).
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Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Section 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Section 2. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Section 3. Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Section 4. Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Section 5. Instruction Set Overview . . . . . . . . . . . . . . . . . . . . . . .55
Section 6. Instruction Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . .87

List of Sections

Section 7. Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . .311
Section 8. Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . .323
Section 9. Fuzzy Logic Support. . . . . . . . . . . . . . . . . . . . . . . . . .337
Appendix A. Instruction Reference. . . . . . . . . . . . . . . . . . . . . . .375
Appendix B. M68HC11 to CPU12 Upgrade Path. . . . . . . . . . . . .403
Appendix C. High-Level Language Support. . . . . . . . . . . . . . . .425
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433
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1.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
1.3 Symbols and Notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.1 Abbreviations for System Resources . . . . . . . . . . . . . . . . . . . . . . . . . .16
1.3.2 Memory and Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
1.3.3 Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
1.3.4 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.2.1 Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.2 Index Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.2.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2.2.5.1 S Control Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2.5.2 X Mask Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.3 H Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.4 I Mask Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.2.5.5 N Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.6 Z Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.7 V Status Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2.5.8 C Status Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Table of Contents

Section 1. Introduction
Section 2. Overview
2.3 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.5 Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
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Section 3. Addressing Modes
3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.2 Mode Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.3 Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.4 Inherent Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.5 Immediate Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
3.6 Direct Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
3.7 Extended Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.8 Relative Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
3.9 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.9.1 5-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . .37
3.9.2 9-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . .37
3.9.3 16-Bit Constant Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . .38
3.9.4 16-Bit Constant Indirect Indexed Addressing. . . . . . . . . . . . . . . . . . . .38
3.9.5 Auto Pre/Post Decrement/Increment Indexed Addressing. . . . . . . . . .39
3.9.6 Accumulator Offset Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . .40
3.9.7 Accumulator D Indirect Indexed Addressing . . . . . . . . . . . . . . . . . . . .41
3.10 Instructions Using Multiple Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10.1 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
3.10.2 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.11 Addressing More than 64 Kbytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Section 4. Instruction Queue
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2 Queue Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
4.2.1 Original M68HC12 Queue Implementation. . . . . . . . . . . . . . . . . . . . . .48
4.2.2 HCS12 Queue Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.3 Data Movement in the Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.3.1 No Movement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.2 Latch Data from Bus (Applies Only to the M68HC12 Queue) . . . . . . .49
4.3.3 Advance and Load from Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.3.4 Advance and Load from Buffer (Applies Only to M68HC12 Queue) . .49
4.4 Changes in Execution Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.4.1 Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.4.2 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
4.4.3 Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
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4.4.3.1 Short Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.4.3.2 Long Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
4.4.3.3 Bit Condition Branches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.4.3.4 Loop Primitives. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.4.4 Jumps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Section 5. Instruction Set Overview
5.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.2 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.3 Load and Store Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
5.4 Transfer and Exchange Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.5 Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
5.6 Addition and Subtraction Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.7 Binary-Coded Decimal Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
5.8 Decrement and Increment Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .61
5.9 Compare and Test Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
5.10 Boolean Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
5.11 Clear, Complement, and Negate Instructions. . . . . . . . . . . . . . . . . . . . . .63
5.12 Multiplication and Division Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.13 Bit Test and Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .65
5.14 Shift and Rotate Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.15 Fuzzy Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.15.1 Fuzzy Logic Membership Instruction . . . . . . . . . . . . . . . . . . . . . . . . . .67
5.15.2 Fuzzy Logic Rule Evaluation Instructions. . . . . . . . . . . . . . . . . . . . . . .67
5.15.3 Fuzzy Logic Weighted Average Instruction . . . . . . . . . . . . . . . . . . . . .68
5.16 Maximum and Minimum Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
5.17 Multiply and Accumulate Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.18 Table Interpolation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
5.19 Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
5.19.1 Short Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
5.19.2 Long Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
5.19.3 Bit Condition Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
5.20 Loop Primitive Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
5.21 Jump and Subroutine Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
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5.22 Interrupt Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.23 Index Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.24 Stacking Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.25 Pointer and Index Calculation Instructions . . . . . . . . . . . . . . . . . . . . . . . .83
5.26 Condition Code Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.27 Stop and Wait Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.28 Background Mode and Null Operations . . . . . . . . . . . . . . . . . . . . . . . . . .86
Section 6. Instruction Glossary
6.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.2 Glossary Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
6.3 Condition Code Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.4 Object Code Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.5 Source Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.6 Cycle-by-Cycle Execution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.7 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Section 7. Exception Processing
7.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
7.2 Types of Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
7.3 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
7.4 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313
7.4.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.3 COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.4.4 Clock Monitor Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
7.5 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
7.5.1 Non-Maskable Interrupt Request (
7.5.2 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .315
7.5.3 Interrupt Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316
7.5.4 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
7.5.5 Return-from-Interrupt Instruction (RTI). . . . . . . . . . . . . . . . . . . . . . . .317
XIRQ) . . . . . . . . . . . . . . . . . . . . . .315
7.6 Unimplemented Opcode Trap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317
7.7 Software Interrupt Instruction (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
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7.8 Exception Processing Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
7.8.1 Vector Fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .318
7.8.2 Reset Exception Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .320
7.8.3 Interrupt and Unimplemented Opcode Trap Exception Processing . .320
Section 8. Instruction Queue
8.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.2 External Reconstruction of the Queue . . . . . . . . . . . . . . . . . . . . . . . . . .323
8.3 Instruction Queue Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
8.3.1 HCS12 Timing Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .324
8.3.2 M68HC12 Timing Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325
8.3.3 Null (Code 0:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327
8.3.4 LAT — Latch Data from Bus (Code 0:1). . . . . . . . . . . . . . . . . . . . . . .327
8.3.5 ALD — Advance and Load from Data Bus (Code 1:0). . . . . . . . . . . .327
8.3.6 ALL — Advance and Load from Latch (Code 1:1) . . . . . . . . . . . . . . .327
8.3.7 INT — Interrupt Sequence Start (Code 0:1). . . . . . . . . . . . . . . . . . . .327
8.3.8 SEV — Start Instruction on Even Address (Code 1:0). . . . . . . . . . . .328
8.3.9 SOD — Start Instruction on Odd Address (Code 1:1) . . . . . . . . . . . .328
8.4 Queue Reconstruction (for HCS12) . . . . . . . . . . . . . . . . . . . . . . . . . . . .328
8.4.1 Queue Reconstruction Registers (for HCS12) . . . . . . . . . . . . . . . . . .329
8.4.1.1 fetch_add Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.2 st1_add, st1_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.3 st2_add, st2_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.1.4 st3_add, st3_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329
8.4.2 Reconstruction Algorithm (for HCS12). . . . . . . . . . . . . . . . . . . . . . . .330
8.5 Queue Reconstruction (for M68HC12) . . . . . . . . . . . . . . . . . . . . . . . . . .331
8.5.1 Queue Reconstruction Registers (for M68HC12). . . . . . . . . . . . . . . .331
8.5.1.1 in_add, in_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.2 fetch_add, fetch_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.3 st1_add, st1_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.1.4 st2_add, st2_dat Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332
8.5.2 Reconstruction Algorithm (for M68HC12). . . . . . . . . . . . . . . . . . . . . .332
8.5.2.1 LAT Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.5.2.2 ALD Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.5.2.3 ALL Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333
8.6 Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335
Section 9. Fuzzy Logic Support
Freescale Semiconductor 11
9.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .337
9.2 Fuzzy Logic Basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338
9.2.1 Fuzzification (MEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340
9.2.2 Rule Evaluation (REV and REVW). . . . . . . . . . . . . . . . . . . . . . . . . . .342
9.2.3 Defuzzification (WAV). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
9.3 Example Inference Kernel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345
9.4 MEM Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347
9.4.1 Membership Function Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . .347
9.4.2 Abnormal Membership Function Definitions. . . . . . . . . . . . . . . . . . . .349
9.4.2.1 Abnormal Membership Function Case 1 . . . . . . . . . . . . . . . . . . . .351
9.4.2.2 Abnormal Membership Function Case 2 . . . . . . . . . . . . . . . . . . . .352
9.4.2.3 Abnormal Membership Function Case 3 . . . . . . . . . . . . . . . . . . . .352
9.5 REV and REVW Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1 Unweighted Rule Evaluation (REV) . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1.1 Set Up Prior to Executing REV. . . . . . . . . . . . . . . . . . . . . . . . . . . .353
9.5.1.2 Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355
9.5.1.3 Cycle-by-Cycle Details for REV . . . . . . . . . . . . . . . . . . . . . . . . . . .355
9.5.2 Weighted Rule Evaluation (REVW) . . . . . . . . . . . . . . . . . . . . . . . . . .359
9.5.2.1 Set Up Prior to Executing REVW. . . . . . . . . . . . . . . . . . . . . . . . . .359
9.5.2.2 Interrupt Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .361
9.5.2.3 Cycle-by-Cycle Details for REVW . . . . . . . . . . . . . . . . . . . . . . . . .361
9.6 WAV Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
9.6.1 Set Up Prior to Executing WAV . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364
9.6.2 WAV Interrupt Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365
9.6.3 Cycle-by-Cycle Details for WAV and wavr . . . . . . . . . . . . . . . . . . . . .365
9.7 Custom Fuzzy Logic Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
9.7.1 Fuzzification Variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
9.7.2 Rule Evaluation Variations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372
9.7.3 Defuzzification Variations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
Appendix A. Instruction Reference
A.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375
A.2 Stack and Memory Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
A.3 Interrupt Vector Locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
A.4 Notation Used in Instruction Set Summary. . . . . . . . . . . . . . . . . . . . . . .377
A.5 Hexadecimal to Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .402
12 Freescale Semiconductor
A.6 Decimal to Hexadecimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . .402
Appendix B. M68HC11 to CPU12 Upgrade Path
B.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
B.2 CPU12 Design Goals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .403
B.3 Source Code Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .404
B.4 Programmer’s Model and Stacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5 True 16-Bit Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5.1 Bus Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407
B.5.2 Instruction Queue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408
B.5.3 Stack Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409
B.6 Improved Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410
B.6.1 Constant Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .412
B.6.2 Auto-Increment Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413
B.6.3 Accumulator Offset Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
B.6.4 Indirect Indexing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .414
B.7 Improved Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.1 Reduced Cycle Counts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.2 Fast Math . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .415
B.7.3 Code Size Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
B.8 Additional Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .417
B.8.1 Memory-to-Memory Moves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.2 Universal Transfer and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.3 Loop Construct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .420
B.8.4 Long Branches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
B.8.5 Minimum and Maximum Instructions . . . . . . . . . . . . . . . . . . . . . . . . .421
B.8.6 Fuzzy Logic Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
B.8.7 Table Lookup and Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422
B.8.8 Extended Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.9 Push and Pull D and CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.10 Compare SP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423
B.8.11 Support for Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
Appendix C. High-Level Language Support
C.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
C.2 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425
Freescale Semiconductor 13
C.3 Parameters and Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
C.3.1 Register Pushes and Pulls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426
C.3.2 Allocating and Deallocating Stack Space. . . . . . . . . . . . . . . . . . . . . .427
C.3.3 Frame Pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .427
C.4 Increment and Decrement Operators . . . . . . . . . . . . . . . . . . . . . . . . . . .428
C.5 Higher Math Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .428
C.6 Conditional If Constructs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.7 Case and Switch Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.8 Pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429
C.9 Function Calls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .430
C.10 Instruction Set Orthogonality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .431
14 Freescale Semiconductor
Reference Manual — S12CPUV2

1.1 Introduction

This manual describes the features and operation of the core (central processing unit, or CPU, and development support functions) used in all HCS12 microcontrollers. For reference, information is provided for the M68HC12.

1.2 Features

The CPU12 is a high-speed, 16-bit processing unit that has a programming model identical tothat of theindustry standard M68HC11central processor unit (CPU). The CPU12 instruction set is a proper superset of the M68HC11 instruction set, and M68HC11 source code is accepted by CPU12 assemblers with no changes.

Section 1. Introduction

• Full 16-bit data paths supports efficient arithmetic operation and high-speed math execution
• Supports instructions with odd byte counts, including many single-byte instructions. This allows much more efficient use of ROM space.
• An instruction queue buffers program information so the CPU has immediate access to at least three bytes of machine code at the start of every instruction.
• Extensive set of indexed addressing capabilities, including: – Using the stack pointer as an indexing register in all indexed
operations
– Using the program counter as an indexing register in all but auto
increment/decrement mode – Accumulator offsets using A, B, or D accumulators – Automatic index predecrement, preincrement, postdecrement,
and postincrement (by –8 to +8)
Freescale Semiconductor 15

1.3 Symbols and Notation

The symbols and notation shown here are used throughout the manual. More specialized notation that applies only to the instruction glossary or instruction set summary are described at the beginning of those sections.

1.3.1 Abbreviations for System Resources

A — Accumulator A B — Accumulator B D — Double accumulator D (A : B) X — Index register X Y — Index register Y SP — Stack pointer PC — Program counter CCR — Condition code register
S — STOP instruction control bit X — Non-maskable interrupt control bit H — Half-carry status bit I — Maskable interrupt control bit N — Negative status bit Z — Zero status bit V — Two’s complement overflow status bit C — Carry/Borrow status bit
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1.3.2 Memory and Addressing

M — 8-bit memory location pointed to by the effective
M : M+1 — 16-bit memory location. Consists of the contents of the
M~M+3 M
(Y)~M(Y+3)
M
(X)
M
(SP)
M
(Y+3)
PPAGE — Program overlay page (bank) number for extended
Page — Program overlay page X
H
X
L
( ) — Content of register or memory location $ — Hexadecimal value % — Binary value
address of the instruction
location pointed to by the effective address concatenated with the contents of the location at the nexthighermemoryaddress. The most significant byte is at location M.
— 32-bit memory location. Consists of the contents of the
effective address of the instruction concatenated with thecontentsofthenextthreehighermemorylocations. The most significant byte is at location M or M
(Y)
. — Memory locations pointed to by index register X — Memory locations pointed to by the stack pointer — Memory locations pointed to by index register Y plus 3
memory (>64 Kbytes).
— High-order byte — Low-order byte
Freescale Semiconductor 17

1.3.3 Operators

+ –
•
+
⊕
× ÷
M
⇒
⇔
—
Addition
—
Subtraction
—
Logical AND
—
Logical OR (inclusive)
—
Logical exclusive OR
—
Multiplication
—
Division
—
Negation. One’s complement (invert each bit of M)
—
:
Concatenate
Example: A : B means the 16-bit valueformedbyconcatenat­ing 8-bit accumulator A with 8-bit accumulator B. A is in the high-order position.
—
Transfer
Example: (A) ⇒ M means the content of accumulator A is transferred to memory location M.
—
Exchange
Example: D ⇔ X means exchange the contents of D with those of X.
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1.3.4 Definitions

Logic level 1 is the voltage that corresponds to the true (1) state. Logic level 0 is the voltage that corresponds to the false (0) state. Set refers specifically to establishing logic level 1 on a bit or bits. Cleared refers specifically to establishing logic level 0 on a bit or bits. Asserted means that a signal is in active logic state. An active low signal
changes from logic level 1 to logic level 0 when asserted, and an active high signal changes from logic level 0 to logic level 1.
Negated means that an asserted signal changes logic state. An active low
signal changes from logic level 0 to logic level 1 when negated, and an active high signal changes from logic level 1 to logic level 0.
ADDR is the mnemonic for address bus. DATA is the mnemonic for data bus. LSB means least significant bit or bits. MSB means most significant bit or bits. LSW means least significant word or words. MSW means most significant word or words. A specific bit location within a range is referred to by mnemonic and
number. For example, A7 is bit 7 of accumulator A.
A range of bit locations is referred to by mnemonic and the numbers that
definetherange. For example,DATA[15:8]formthehigh byte ofthedata bus.
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20 Freescale Semiconductor
Reference Manual — S12CPUV2

2.1 Introduction

This section describes the CPU12 programming model, register set, the data types used, and basic memory organization.

2.2 Programming Model

The CPU12 programming model, shown in Figure 2-1, is the same as that of the M68HC11 CPU. The CPU has two 8-bit general-purpose accumulators (A and B) that can be concatenated into a single 16-bit accumulator (D) for certain instructions. It also has:
• Two index registers (X and Y)

Section 2. Overview

• 16-bit stack pointer (SP)
• 16-bit program counter (PC)
• 8-bit condition code register (CCR)
7
15
15
15
15
15
AB
70
D
IX
IY
SP
PC
NSXH I ZVC
Figure 2-1. Programming Model
0
8-BIT ACCUMULATORS A AND B OR
0
16-BIT DOUBLE ACCUMULATOR D
0
INDEX REGISTER X
0
INDEX REGISTER Y
0
STACK POINTER
0
PROGRAM COUNTER
CONDITION CODE REGISTER
Freescale Semiconductor 21

2.2.1 Accumulators

General-purpose8-bitaccumulatorsAandBare used to hold operands and results of operations. Some instructions treat the combination of these two 8-bit accumulators (A : B) as a 16-bit double accumulator (D).
Most operations can use accumulator A or B interchangeably. However, there are a few exceptions. Add, subtract, and compare instructions involving both A and B (ABA, SBA, and CBA) only operate in one direction, so it is important to make certain the correct operand is in the correct accumulator. The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations. There is no equivalent instruction to adjust accumulator B.

2.2.2 Index Registers

16-bit index registers X and Y are used for indexed addressing. In the indexed addressing modes, the contents of an index register are added to 5-bit, 9-bit, or 16-bit constants or to the content of an accumulator to form the effective address of the instruction operand. The second index register is especially useful for moves and in cases where operands from two separate tables are used in a calculation.

2.2.3 Stack Pointer

TheCPU12supportsan automatic program stack.Thestackisused to save system context during subroutine calls and interrupts and can also be used for temporary data storage. The stack can be located anywhere in the standard 64-Kbyte address space and can grow to any size up to the total amount of memory available in the system.
The stack pointer (SP) holds the 16-bit address of the last stack location used. Normally, the SP is initialized by one of the first instructions in an application program. The stack grows downward from the address pointed to by the SP. Each time a byte is pushed onto the stack, the stack pointer is automatically decremented, and each time a byte is pulled from the stack, the stack pointer is automatically incremented.
When a subroutine is called, the address of the instruction following the calling instruction is automatically calculated and pushed onto the stack. Normally, a return-from-subroutine (RTS) or a return-from-call (RTC) instruction is executed at the end of a subroutine. The return instruction
22 Freescale Semiconductor
loads the program counter with the previously stacked return address and execution continues at that address.
When an interrupt occurs, the current instruction finishes execution. The address of the next instruction is calculated and pushed onto the stack, all the CPU registers are pushed onto the stack,theprogramcounter is loaded with the address pointed to by the interrupt vector, and execution continues at that address. The stacked registers are referred to as an interrupt stack frame. The CPU12 stack frame is the same as that of the M68HC11.
NOTE: These instructions can be interrupted, and they resume execution once the
interrupt has been serviced:

2.2.4 Program Counter

The program counter (PC) is a 16-bit register that holds the address of the nextinstructiontobeexecuted.Itisautomaticallyincrementedeachtimean instruction is fetched.
• REV (fuzzy logic rule evaluation)
• REVW (fuzzy logic rule evaluation (weighted))
• WAV (weighted average)

2.2.5 Condition Code Register

The condition code register (CCR), named for its five status indicators, contains:
• Five status indicators
• Two interrupt masking bits
• STOP instruction control bit
Freescale Semiconductor 23
The status bits reflect the results of CPU operation as it executes instructions. The five flags are:
• Half carry (H)
• Negative (N)
• Zero (Z)
• Overflow (V)
• Carry/borrow (C)
The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a previous operation.
In some architectures, only a few instructions affectconditioncodes,so that multiple instructions must be executed in order to load and test a variable. Since most CPU12 instructions automatically update condition codes, it is rarely necessary to execute an extra instruction for this purpose. The challenge in using the CPU12lies in finding instructions thatdo not alter the condition codes. The most important of these instructions arepushes,pulls, transfers, and exchanges.
2.2.5.1 S Control Bit
It is always a good idea to refer to an instruction set summary (see
Appendix A. Instruction Reference) to check which condition codes are
affected by a particular instruction. The following paragraphs describe normal uses of the condition codes.
There are other, more specialized uses. For instance, the C status bit is usedto enable weighted fuzzy logic rule evaluation. Specialized usages are described in the relevant portions of this manual and in Section 6.
Instruction Glossary.
Clearing the S bit enables the STOP instruction. Execution of a STOP instruction normally causes the on-chip oscillator to stop. This may be undesirableinsomeapplications.Ifthe CPU encounters a STOP instruction while the S bit is set, it is treated like a no-operation (NOP) instruction and continues to the next instruction. Reset sets the S bit.
24 Freescale Semiconductor
2.2.5.2 X Mask Bit
XIRQ input is an updated version of the NMI input found on earlier
The generations of MCUs. Non-maskable interrupts are typically used to deal with major system failures, such as loss of power. However, enabling non-maskableinterruptsbeforeasystemisfullypoweredandinitializedcan lead to spurious interrupts. The X bit provides a mechanism for enabling non-maskable interrupts after a system is stable.
By default, the Xbit is set to 1 during reset. As longas the X bitremains set, interrupt service requests made via the
XIRQ pin are not recognized. An instruction must clear the X bit to enable non-maskable interrupt service requests made via the
XIRQ pin. Once the X bit has been cleared to 0, software cannot reset it to 1 by writing to the CCR. The X bit is not affected by maskable interrupts.
2.2.5.3 H Status Bit
When an
XIRQ interrupt occurs after non-maskable interrupts are enabled, both the X bit and the I bit are set automatically to prevent other interrupts from being recognized during the interrupt service routine. The mask bits are set after the registers are stacked, but before the interrupt vector is fetched.
Normally, a return-from-interrupt (RTI) instruction at the end of the interrupt service routine restores register values that were present before the interrupt occurred. Since the CCR is stacked before the X bit is set, the RTI normally clears the X bit, and thus re-enables non-maskable interrupts. While it is possible to manipulate thestackedvalue of X so that X issetafter an RTI, there is no software method to reset X (and disable
XIRQ) once X
has been cleared.
The H bit indicates a carry from accumulator A bit 3 during an addition operation. The DAA instruction uses the value of the H bit to adjust a result in accumulator A to correct BCD format. H is updated only by the add accumulator A to accumulator B (ABA), add without carry (ADD), and add with carry (ADC) instructions.
2.2.5.4 I Mask Bit
The I bit enables and disables maskable interrupt sources. By default, the I bit is set to 1 during reset. An instruction must clear the I bit to enable maskable interrupts. While the I bit is set, maskable interrupts can become
Freescale Semiconductor 25
2.2.5.5 N Status Bit
pending and are remembered, but operation continues uninterrupted until the I bit is cleared.
When an interrupt occurs after interrupts are enabled, the I bit is automatically set to prevent other maskable interrupts during the interrupt service routine. The I bitis set after the registersare stacked, but before the first instruction in the interrupt service routine is executed.
Normally, an RTI instruction at the end of the interrupt service routine restores register values that were present before the interrupt occurred. Since the CCR is stacked before the I bit is set, the RTI normally clears the Ibit,andthusre-enables interrupts. Interrupts can bere-enabledbyclearing the I bit within the service routine.
TheNbitshowsthestateof the MSB of the result. N ismostcommonlyused in two’s complement arithmetic, where the MSB of a negative number is 1 and the MSB of a positive number is 0, but it has other uses. For instance, if the MSB ofa register or memory location is used as a status flag, the user can test status by loading an accumulator.
2.2.5.6 Z Status Bit
2.2.5.7 V Status Bit
2.2.5.8 C Status Bit
The Z bit is set when all the bits of the result are 0s. Compare instructions perform an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. The increment index register X (INX), decrement index register X (DEX), increment index register Y (INY), and decrement index register Y (DEY) instructions affect the Z bit and no other condition flags. These operations can only determine = (equal) and ≠ (not equal).
The V bit is set when two’s complement overflow occurs as a result of an operation.
The C bit is set when a carry occurs during addition or a borrow occurs duringsubtraction. The C bit also acts as an error flag for multiply and divide
26 Freescale Semiconductor

2.3 Data Types

operations.Shiftandrotate instructions operatethroughtheCbit to facilitate multiple-word shifts.
The CPU12 uses these types of data:
• Bits
• 5-bit signed integers
• 8-bit signed and unsigned integers
• 8-bit, 2-digit binary-coded decimal numbers
• 9-bit signed integers
• 16-bit signed and unsigned integers
• 16-bit effective addresses
• 32-bit signed and unsigned integers
Negative integers are represented in two’s complement form. Five-bit and 9-bit signed integers are used only as offsets for indexed
addressing modes. Sixteen-bit effective addresses are formed during addressing mode
computations. Thirty-two-bit integer dividends are used by extended division instructions.
Extended multiply and extended multiply-and-accumulate instructions produce 32-bit products.

2.4 Memory Organization

ThestandardCPU12addressspaceis64Kbytes.SomeM68HC12devices support a paged memory expansion scheme that increases the standard space by means of predefined windows in address space. The CPU12 has special instructions that support use of expanded memory.
Eight-bit values can be stored at any odd or even byte address in available memory.
Freescale Semiconductor 27
Sixteen-bit values are stored in memory as two consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary.
Thirty-two-bit values are stored in memory as four consecutive bytes; the high byte occupies the lowest address, but need not be aligned to an even boundary.
All input/output (I/O) and all on-chip peripherals are memory-mapped. No special instruction syntax is required to access these addresses. On-chip registers and memory typically are grouped in blocks which can be relocated within the standard 64-Kbyte address space. Refer to device documentation for specific information.

2.5 Instruction Queue

The CPU12 uses an instruction queue to buffer program information. The mechanism is called a queue rather than a pipeline because a typical pipelined CPU executes more than one instruction at the same time, while the CPU12 always finishes executing an instruction before beginning to execute another. Refer to Section 4. Instruction Queue for more information.
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Reference Manual — S12CPUV2

3.1 Introduction

Addressing modes determine how the central processor unit (CPU) accesses memory locations to be operated upon. This section discusses the various modes and how they are used.

3.2 Mode Summary

Addressing modes are an implicit part of CPU12 instructions. Refer to
Appendix A. Instruction Reference for the modes used by each
instruction. All CPU12 addressing modes are shown in Table 3-1. The CPU12 uses all M68HC11 modes as well as new forms of indexed
addressing. Differences between M68HC11and M68HC12 indexed modes are described in 3.9 Indexed Addressing Modes. Instructions that use more than one mode are discussed in 3.10 Instructions Using Multiple
Modes.

Section 3. Addressing Modes

3.3 Effective Address

Each addressing mode except inherent mode generates a 16-bit effective address which is used during the memory reference portion of the instruction. Effective address computations do not require extra execution cycles.
Freescale Semiconductor 29
Table 3-1. M68HC12 Addressing Mode Summary
Addressing Mode Source Format Abbreviation Description
INST
Inherent
(no externally
supplied operands)
INH Operands (if any) are in CPU registers
INST #opr8i
Immediate
Direct INST opr8a DIR
Extended INST opr16a EXT Operand is a 16-bit address
Relative
Indexed
(5-bit offset)
Indexed
(pre-decrement)
Indexed
(pre-increment)
Indexed
(post-decrement)
Indexed
(post-increment)
Indexed
(accumulator offset)
INST oprx5,xysp IDX
INST oprx3,–xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8
INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8
INST oprx3,xys– IDX Auto post-decrement x, y, or sp by 1 ~ 8
INST oprx3,xys+ IDX Auto post-increment x, y, or sp by 1 ~ 8
or
INST #opr16i
INST rel8
or
INST rel16
INST abd,xysp IDX
IMM
REL
Operand is included in instruction stream
8- or 16-bit size implied by context
Operand is the lower 8 bits of an address
in the range $0000–$00FF
An 8-bit or 16-bit relative offset from the current pc
is supplied in the instruction
5-bit signed constant offset
from X, Y, SP, or PC
Indexed with 8-bit (A or B) or 16-bit (D)
accumulator offset from X, Y, SP, or PC
Indexed
(9-bit offset)
Indexed
(16-bit offset)
Indexed-Indirect
(16-bit offset)
Indexed-Indirect
(D accumulator offset)
30 Freescale Semiconductor
INST oprx9,xysp IDX1
INST oprx16,xysp IDX2
INST [oprx16,xysp] [IDX2]
INST [D,xysp] [D,IDX]
9-bit signed constant offset from X, Y, SP, or PC
(lower 8 bits of offset in one extension byte)
16-bit constant offset from X, Y, SP, or PC
(16-bit offset in two extension bytes)
Pointer to operand is found at...
16-bit constant offset from X, Y, SP, or PC (16-bit offset in two extension bytes)
Pointer to operand is found at...
X, Y, SP, or PC plus the value in D
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