Freescale Semiconductor EETX4K User Manual
Freescale Semiconductor, Inc.
EETX4K
Block Guide
V00.04
DOCUMENT NUMBER
S12EETX4KV0
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Original Release Date: 7 JUL 2003
Revised: 30 OCT 2003
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its
products forany particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in
different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the
Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
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and reasonableattorney fees arising out of, directly or indirectly,any claim of personal injuryor death associated with such unintended or unauthorizeduse, even if such claim alleges
that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
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©Motorola, Inc., 2001
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Revision History
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Table of Contents
Section 1 Introduction
1.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1.1 Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Section 2 External Signal Description
2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Section 3 Memory Map and Registers
3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 ECLKDIV — EEPROM Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 RESERVED1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 RESERVED2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.4 ECNFG — EEPROM Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3.5 EPROT — EEPROM Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3.6 ESTAT — EEPROM Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3.7 ECMD — EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.8 RESERVED3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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3.3.9 EADDR — EEPROM Address Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3.10 EDATA — EEPROM Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Section 4 Functional Description
4.1 EEPROM Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1 Writing the ECLKDIV Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.2 Command Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.3 EEPROM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
4.1.4 Illegal EEPROM Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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4.4 Background Debug Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5 EEPROM Module Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.5.1 Unsecuring the MCU in Special Single Chip Mode via the BDM. . . . . . . . . . . . . 40
4.6 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6.1 EEPROM Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.6.2 Reset While EEPROM Command Active. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.7.1 Description of EEPROM Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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List of Figures
Figure 1-1 Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 3-1 EEPROM Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 3-2 EEPROM Clock Divider Register (ECLKDIV) . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-3 RESERVED1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 3-4 RESERVED2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3-5 EEPROM Configuration Register (ECNFG) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 3-6 EEPROM Protection Register (EPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3-7 EEPROM Status Register (ESTAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 3-8 EEPROM Command Register (ECMD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 3-9 RESERVED3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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Figure 3-10 EEPROM Address High Register (EADDRHI). . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3-11 EEPROM Address Low Register (EADDRLO) . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3-12 EEPROM Data High Register (EDATAHI). . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 3-13 EEPROM Data Low Register (EDATALO) . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 4-1 Determination Procedure for PRDIV8 and EDIV Bits . . . . . . . . . . . . . . . . . . 27
Figure 4-2 Example Erase Verify Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 4-3 Example Program Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 4-4 Example Sector Erase Command Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 4-5 Example Mass Erase Command Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 4-6 Example Sector Erase Abort Command Flow. . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 4-7 Example Sector Modify Command Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 4-8 EEPROM Interrupt Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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List of Tables
Table 3-1 EEPROM Configuration Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3-2 EEPROM Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 3-3 EEPROM Protection Address Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 3-4 Valid EEPROM Command List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4-1 EEPROM Command Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 4-2 EEPROM Interrupt Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Section 1 Introduction
1.1 Overview
This document describes the EETX4K module which includes a 4K byte EEPROM (Non-Volatile)
memory. The EEPROM memory may be read as either bytes, aligned words or misaligned words. Read
access time is one bus cycle for bytes and aligned words, and two bus cycles for misaligned words.
The EEPROM memory is ideal for data storage for single-supply applications allowing for field
reprogramming without requiring external voltage sources for program or erase. Program and erase
functions are controlled by a command driven interface. The EEPROM module supports both block erase
(all memory bytes) and sector erase (4 memory bytes). An erased bit reads ‘1’ and a programmed bit reads
‘0’. The high voltage required to program and erase the EEPROM memory isgenerated internally. Itis not
possible to read from the EEPROM block while it is being erased or programmed.
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NOTE:
An EEPROM word (2bytes) must beerased before being programmed. Cumulative
programming of bits within a word is not allowed.
1.1.1 Glossary
Command Write Sequence
A three-step MCU instruction sequence to execute built-in algorithms (including program and erase) on
the EEPROM memory.
1.2 Features
• 4K bytes of EEPROM memory divided into 1024 sectors of 4 bytes.
• Automated program and erase algorithm.
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• Interrupts on EEPROM command completion and command buffer empty.
• Fast sector erase and word program operation.
• 2-stage command pipeline.
• Sector erase abort feature for critical interrupt response.
• Flexible protection scheme to prevent accidental program or erase.
• Single power supply for all EEPROM operations including program and erase.
1.3 Modes of Operation
• Program, erase and erase verify operations (please refer to section 4.1 for details).
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1.4 Block Diagram
A block diagram of the EEPROM module is shown in Figure 1-1.
EETX4K
EEPROM
Interface
Command
Interrupt
Request
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Command Pipeline
cmd2
addr2
data2
Registers
cmd1
addr1
data1
EEPROM
2K * 16 Bits
sector 0
sector 1
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Oscillator
Clock
Protection
Clock
Divider
Figure 1-1 Module Block Diagram
EECLK
sector 1023
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Section 2 External Signal Description
2.1 Overview
The EEPROM module contains no signals that connect off-chip.
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Section 3 Memory Map and Registers
3.1 Overview
This section describes the memory map and registers for the EEPROM module.
3.2 Module Memory Map
A linear EEPROM memory map is shown in Figure 3-1. The HCS12X architecture actually places the
EEPROM memory addresses between logical addresses $0800 and $1000 with $0800 to $0BFF
representing 1K byte of paged EEPROM memory and $0C00 to $0FFF representing 1K byte of fixed
EEPROM memory. The EPROT register, described in section 3.3.5, can be set to protect the upper region
in the EEPROM memory from accidental program or erase. The EEPROM addresses covered by this
protectable region are shown in the EEPROM memory map. The default protection setting is stored in the
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EEPROM configuration field as described in Table 3-1.
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Table 3-1 EEPROM Configuration Field
EEPROM Memory
Address Offset
$_FFC
$_FFD
$_FFE - $_FFF
Size
(bytes)
1
1
2
Description
Reserved
EEPROM Protection byte
Refer to Section 3.3.5 EPROT —
EEPROM Protection Register
Reserved
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